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Digital-logic Design... Dream for many students… start learning front-end… Chip Designing for ASIC/ FPGA Design engineers and Students

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Binary subtraction Discussion proof of binary subt
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Binary numbers addition is straight forward process while binary subtractions involve three fundamentals. VHDL Test Benches
Generate VHDL models from timing diagrams or logic analyzer data. www.syncad.com Binary Numbers 1s_complement 2s_complement Binary Subtraction Binary Sub. Ex's Sign_magnitude SignM EX Gray Coding BCD coding Digital gates NAND NOR & XNOR Theorems Boolean Functions BFunc Examples Minterm Maxterm Sum of Minterms Prdt of Maxterms 2 var K-map 3 var K-map 4 var K-map 5 var K-map Prime Implicant PI example K-map Ex's KMap minimization

Binary Subtraction:
Suppose, M is Minuend and N is subtrahend Then, M – N can be done based on following three steps: Step 1: Take 2’s complement of N and add it to M. M – N = M + (2^n – N) Step 2: If M is greater than or equal to N then end carry is discarded from the result M –N = M + (2^n – N) – 2^n Step 3: If M is less than N then take 2’s complement of the result and append negative ‘-‘ sign in front M-N = (-) [2^n – (M + (2^n -1))] Example 1 : Perform binary subtraction of two binary numbers M = 10101010 and N = 00111000 M–N 10101010 - 00111000
End carry 1 01110010

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Verilog RTL code examples for front-end chip design. Digital Design Topics Half-adder, full-adder, Adder-sub tractor Stack Organization - LIFO, RPN Parity Generation and error checking Binary multiplier circuit. CMOS introduction Digital fundamentals RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle Pipeline vs. Parallel processing.

10101010 +11001000

Discard end carry from the subtraction Answer. Binary subtraction of M and N = 01110010 VHDL Test Benches
Generate VHDL models from timing diagrams or logic analyzer data. www.syncad.com Example 2 : Perform binary subtraction of two binary numbers N = 10101010 and M = 00111000 M–N 00111000 - 10101010 Result No end carry in result 2’s complement of result = 01110010 Answer. Binary subtraction of M and N = - (2’s complement of result) = -01110010 fullchipdesign.com/2scomex.htm 00111000 + 01010110 = 10001110

K-map - 2,3,4,5 var & Prime Implicant discussion

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Arithmetic, logical, shift micro-operations, Overflow Half-Adder, Full-Adder, Adder-Subtractor. Verilog code Half-Adder, Full-Adder GVIM Advance - regular expressions

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Digital Logic fundamentals topics @ fcd

Digital basics tutorial Binary number discussion, 1 and 2 complement discussion, Binary arithmetic, Signed Magnitude, overflow, examples Gray coding, Binary coded digital (BCD) coding, BCD addition Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates Discussion of Boolean Algebra with examples. Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms Sum of Minterms, Product of Maxterms or Canonical Forms, Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s Prime Implicant and Gate level minimization examples.

Verilog Tutorial Topics @ fullchipdesign.
Introduction to Verilog RTL Verilog Operators. Initial Statements in verilog. Clock and Reset generation. Blocking vs. Non-blocking Statements. Conditional Statements & ‘always’ block. Counter Implementation. File Operations - $fopen, $fclose, $fdisplay, $fscanf Read binary or hex format files - $readmemh, $readmemb. FOR Loop use in verilog code example Function declaration and call. Testbench structure. Random number generation. Shift micro-operations use in rtl. Memory - synchronous RAM implementation. Verilog generate for memory instances. Assertions in Verilog Introduction and few examples.

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