A 14-TRANSISTOR LOW POWER HIGH-SPEED

FULL ADDER CELL

Bhargav Repuri

200930023

K .Pradyumna reddy

200930021

Abstract—This paper describes ihe design of a high-speed low-power I-bit full adder cell. The main design objectives for this adder circuit are low power consumption and higher speed at low supply voltage. Using pseudo-NMOS together with two inverters this adder cell has been designed in 0.18-11CMOS process. Considering transistor chaining, grouping, and signal sequencing in our proposed adder layout which all have noticeable impacts on the circuit performance, shows substantial power saving and speed improvement at no area penalty. Inverters act as drivers. Therefore, each stage will not suffer degradation in its deriving capabilities. This saves power, area, and time.

Keywords-component; Full Adder, Low power, High-speed

Introduction (Heading 1)

To respond to the shifting high-performance digital signal processing (DSP) and central processing unit (CPU) chip to low-power demand high-speed and low-power arithmetic circuits such as adders and multipliers have been required. Adder as a main building block of the arithmetic logic unit (ALU) has been under extensive interest. Addition is also a crucial operation because it involves a carry propagation step. In order to achieve low-power performance for the adder structure with high-speed characteristic, different low-power techniques [I] and high-speed circuit design [2] have been introduced. Also high demand for smaller and more durable portable system has grown. This will add one more factor in design constraints, which is known as the area of the designed cell. Many full adder cells have been reported [4]. The transmission gate CMOS full adder cell using transmission gate logic realizes the complex function with the number of complementary inputs as the conventional CMOS full adder [5]. The transmission gate full adder cell exhibits better speed than the CMOS full adder at the same power consumption. Also complementary pass transistor logic (CPL) circuits, which have complementary inputs and outputs with NMOS transistor logic and CMOS inverter at the outputs, can he utilized to reduce the power consumption due to its low-swing internal nodes. The proposed full adder employs Pseudo-NMOS circuits using only PUN (Pull-Down Network) of a comparable CMOS circuit Not only does this save on area, but it also minimizes the gate-load capacitance due Lo the succeeding gates. The disadvantage associated with this dynamic circuit is usually low swing at both output nodes (output CMOS inverters compensate this degradation). In order to obtain higher speed in digital circuit, reducing propagation delay time in critical paths can be considered.

CIRCUIT DESIGN

a)Full Adder ( Block Diagram)

b) Schematic Diagram

1 Abbreviations and Acronyms

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The design of the proposed cell shown based on using pseudo NMOS logic. It has been claimed that [81 pseudo-NMOS logic is no faster than conventional CMOS logic due to lack of a PMOS logic tree. in the non-pipelined case where the system’s speed is determined by the average delays of the logic gates. Although fixed-biased pseudo-NMOS logic is truly faster than CMOS logic in non-pipelined cases, it does have some drawbacks such as low voltage swing of pseudo NMOS logic compare to that of the conventional CMOS. To overcome this issue, two CMOS inverters are added to output (Sum and Cout) of the circuit. The W L ratio between the pull-up PMOS and the NMOS’s in the logic tree have to be carefully chosen not to affect the rise time and hence the average delay and the magnitude of small-signal voltage gain of the circuit. In fact by carefully sizing and adjusting the PMOS load transistor (those transistors in the circles in Fig.1.) it will be guarantee first, the output voltage is low enough when N-logic tree is on and second, average gate delay has been optimized.
III. Layout Strategies
To enhance the performance of the proposed adder cell considering transistor chaining, grouping, and signal sequencing in our proposed adder layout, shows substantial power saving and speed improvement at no area penalty. The following tasks have been done to reduce parasitic effects:
1) Minimizing the use of diffusion as a routing layer to reduce the overall parasitic by using metal I1 layer.
2) Placing the transistors switched by the Cin signal close to the output.
3) Minimizing the capacitive load on the Cout signal by minimizing size of those transistors in the
Sum gate whose gate signals are connected to Cout.
4) Using matching transistor structure to reduce area. 5 ) Making the transistor connecting to Cin closer to the input of the circuit, results in reduced input capacitance .

1 SIMULATION RESULTS

The proposed full adder cell has been simulated and laid out in 0.18-p CMOS process. Delay of the critical path and power consumption of logic has been measured

The Above result is obtained when the W/L of the N- mos is more than thrice of that of the P- Mos.

The below are the results for different W/L ratios of N-Mos

The above result is obtained when the W/L ratio of the N Mos is equal to that of the P Mos.

The above result is obtained when the W/L ratio of the N Mos is twice that of the P mos.

1

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3 Conclusions:

This paper shows the experimental results for high speed and low power 1-hit full adder. An efficient

implementation of an adder in terms of area, speed and

power are targeted in this paper. Optimization to our

proposed adder has been done in various levels,

namely, circuit schematic level, transistor level, and

physical layout level. Pseudo NMOS configurations

are used to reduce the area. Current driven bulk

technique is used to speed up the addition operation

and compensate the speed degradation of this design

due to low voltage supply. Transistor grouping and

signal sequencing have been employed to reduce the

input and output capacitance while slightly increasing

the capacitance of some internal nodes.

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