A computer consists of a set of components or modules of three basic types * Processor * Memory * I/O These modules communicate with each other. In effect, a computer is a network of basic modules. Thus, there must be paths for connecting the modules. The collection of paths connecting the various modules is called the interconnection structure. The design of this structure will depend on the exchanges that must be made among modules.
First we describe the above mentioned modules briefly:
Memory: Typically, a memory module will consist of N words of equal length. Each word is assigned a unique numerical address (0, 1, . . . ,N – 1). A word of data can be read from or written into the memory. The nature of the operation is indicated by read/write control signals. The location for the operation is specified by an address.

I/O module: From an internal (to the computer system) point of view, I/O is functionally similar to memory. There are two operations, read and write. Further, I/O module may control more than one external device. We can refer to each of the interfaces to an external device as a port and give each a unique address (e.g., 0, 1, . . . ,M– 1). In addition, there are external data paths for the input and output of data with an external device. Finally, an I/O module may be able to send interrupt signals to the processor.

Processor: The processor reads in instructions and data, writes out data after processing, and uses control signals to control the overall operation of the system. It also receives interrupt signals.

The interconnection structure must support the following types of transfers:

Memory to processor: The processor reads an instruction or a unit of data from memory.
Processor to memory: The processor writes a unit of data to memory.
I/O to processor: The processor reads data from an I/O device via an I/O module.
Processor to I/O: The processor sends data to the I/O device.
I/O to/ from Memory: For these two cases, I/O module is allowed to exchange data directly with memory, without going through the processor, using Direct
Memory Access (DMA).

Interconnection Structures:
There are different possible interconnection structures out of which the most common are:
BUS INTERCONNECTION:
A bus is a communication pathway connecting two or more devices. A key characteristic of a bus is that it is a shared transmission medium. Multiple devices connect to the bus, and a signal transmitted by any one device is available for reception by all other devices attached to the bus. If two devices transmit during the same time period, their signals will overlap and become garbled. Thus, only one device at a time can successfully transmit.

System Bus:
Computers normally contain several buses. The bus that interconnects major components (processor, memory, I/O devices) is called the system bus. A system bus typically contains from 50 to several hundred lines which are grouped in data, address and control signals power lines may not be shown in bus diagram.

System bus
System bus

Bus Structure:
A system bus consists, typically, of from about 50 to hundreds of separate lines. Each line is assigned a particular meaning or function. Although there are many different bus designs, on any bus the lines can be classified into three functional groups (Figure above): data, address, and control lines. In addition, there may be power distribution lines that supply power to the attached modules.
The data lines provide a path for moving data among system modules. These lines, collectively, are called the data bus. The data bus may consist of 32, 64, 128, or even more separate lines, the number of lines being referred to as the width of the data bus. Because each line can carry only 1 bit at a time, the number of lines determines how many bits can be transferred at a time.
The address lines are used to designate the source or destination of the data on the data bus. For example, if the processor wishes to read a word (8, 16, or32 bits) of data from memory, it puts the address of the desired word on the address lines. Clearly, the width of the address bus determines the maximum possible memory capacity of the system. Furthermore, the address lines are generally also used to address I/O ports. Typically, the higher-order bits are used to select a particular module on the bus, and the lower-order bits select a memory location or I/O port within the module.
The control lines are used to control the access to and the use of the data and address lines. Because the data and address lines are shared by all components, there must be a means of controlling their use. Typical control lines include:

Memory write: Causes data on the bus to be written into the addressed location
Memory read: Causes data from the addressed location to be placed on the bus
I/O write: Causes data on the bus to be output to the addressed I/O port
I/O read: Causes data from the addressed I/O port to be placed on the bus
Transfer ACK: Indicates that data have been accepted from or placed on the bus
Bus request: Indicates that a module needs to gain control of the bus
Bus grant: Indicates that a requesting module has been granted control of the bus
Interrupt request: Indicates that an interrupt is pending
Interrupt ACK: Acknowledges that the pending interrupt has been recognized
Clock: Is used to synchronize operations
Reset: Initializes all modules

Bus Operation:
The operation of the bus is as follows. If one module wishes to send data to another, it must do two things: (1) obtain the use of the bus, and (2) transfer data via the bus. If one module wishes to request data from another module, it must (1) obtain the use of the bus, and (2) transfer a request to the other module over the appropriate control and address lines. It must then wait for that second module to send the data.

Elements of Bus Design:

Bus Types:
Dedicated - a line is permanently assigned either to one function or to a physical subset of computer components
Multiplexed - Time multiplexing - using the same lines for multiple purposes (different purposes at different times)
Method of Arbitration: determining who can use the bus at a particular time
Centralized - a single hardware device called the bus controller or arbiter allocates time on the bus.
Distributed - each module contains access control logic and the modules act together to share the bus
Timing: Timing refers to the way in which events are coordinated on the bus. Buses use either synchronous timing or asynchronous timing.
Synchronous Timing - the occurrence of events on the bus is determined by a clock. The bus includes a clock line upon which a clock transmits a regular sequence of alternating 1s and 0s of equal duration.
Asynchronous Timing - the occurrence of an event on a bus follows and depends on the occurrence of a previous event. It allows system to take advantage of advances in device performance by having a mixture of slow and fast devices, using older and newer technology, sharing the same bus.
Bus Width:
Data bus: wider = better performance
Address bus: wider = more locations can be referenced
Data Transfer Type:
All buses must support write (master to slave) and read (slave to master) transfers.

Combination operations:
Read-modify-write
a read followed immediately by a write to the same address. Address is only broadcast once, at the beginning of the operation Indivisible, to prevent access to the data element by other potential bus masters
Principle purpose is to protect shared memory in a multiprogramming system

Read-after-write - indivisible operation consisting of a write followed immediately by a read from the same address (for error checking purposes)

PERIPHERAL COMPONENT INTERCONNECTION:
The peripheral component interconnect (PCI) is a popular high-bandwidth, processor-independent bus that can function as a mezzanine or peripheral bus. Compared with other common bus specifications, PCI delivers better system performance for high-speed I/O subsystems (e.g., graphic display adapters, network interface controllers, disk controllers, and so on).The current standard allows the use of up to 64 data lines at 66 MHz, for a raw transfer rate of 528 MB/s, or 4.224 GB/s. But it is not just a high speed that makes PCI attractive. PCI is specifically designed to meet economically the I/O requirements of modern systems; it requires very few chips to implement and supports other buses attached to the PCI bus.

PCI Structure:

PCI may be configured as a 32- or 64-bit bus..These are divided into the following functional groups:
System pins: Include the clock and reset pins.
Address and data pins: Include 32 lines that are time multiplexed for addresses and data. The other lines in this group are used to interpret and validate the signal lines that carry the addresses and data.
Interface control pins: Control the timing of transactions and provide coordination among initiators and targets.
Interrupt pins: These are provided for PCI devices that must generate requests for service. As with the arbitration pins, these are not shared lines. Rather, each PCI device has its own interrupt line or lines to an interruptcontroller.
Cache support pins: These pins are needed to support a memory on PCI that can be cached in the processor or another device. These pins support snoopy cache protocols (see Chapter 18 for a discussion of such protocols).
64-bit bus extension pins: Include 32 lines that are time multiplexed for addresses and data and that are combined with the mandatory address/data lines to form a 64-bit address/data bus. Other lines in this group are used to interpret and validate the signal lines that carry the addresses and data. Finally, there are two lines that enable two PCI devices to agree to the use of the 64-bit capability.
JTAG/boundary scan pins: These signal lines support testing procedures defined in IEEE Standard 1149.1.

Data Transfer:

Every data transfer on the PCI bus is a single transaction consisting of one address phase and one or more data phases. In this discussion, we illustrate a typical read operation; a write operation proceeds similarly.
Bus Master gains control, asserts FRAME (begin transaction) signal. FRAME remains asserted until initiator ready to complete last data phase, Put start address on AD bus, Put read command on C/BE lines
Start of clock 2. Target will recognize its own address on AD
Initiator stops driving AD bus. A turnaround cycle is required on all signal lines that may be driven by > 1 device. Drop of AD prepares bus prepares bus for use by target. Initiator designates 1-4 bytes for transfer with C/BE lines. Initiator asserts IRDY
Selected target DEVSEL to indicate address recognized and device ready, Places data on AD lines, Asserts TRDY to indicate valid data on bus.
Initiator reads data at beginning of clock 4, Change Byte Enable in prep for next read
Example assumes slow target – needs time to prepare 2nd block of data
=> deassert TRDY to indicate that data will NOT be ready
=> initiator does NOT read data and BE remains unchanged
Block of data is read at start of clock 6.
During clock 6, target places item 3 on bus, but initiator has buffer full
=> deassert IRDY
=> Target maintains data on bus for extra clock Initiator knows third transfer is last => Deassert FRAME and assert IRDY to complete transfer
i. Initiator deasserts IRDY; bus -> idle state, target deasserts TRDY and DEVSEL