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CHAPTER

5

THE CMOS INVERTER
Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design

5.1 5.2 5.3

Exercises and Design Problems The Static CMOS Inverter — An Intuitive Perspective Evaluating the Robustness of the CMOS Inverter: The Static Behavior 5.3.1 5.3.2 5.3.3 Switching Threshold Noise Margins Robustness Revisited 5.5

5.4.2 5.4.3

Propagation Delay: First-Order Analysis Propagation Delay from a Design Perspective

Power, Energy, and Energy-Delay 5.5.1 5.5.2 5.5.3 5.5.4 Dynamic Power Consumption Static Consumption Putting It All Together Analyzing Power Consumption Using SPICE

5.4

Performance of CMOS Inverter: The Dynamic Behavior 5.4.1 Computing the Capacitances 5.6

Perspective: Technology Scaling and its Impact on the Inverter Metrics

180

Section 5.1

Exercises and Design Problems

181

5.1

Exercises and Design Problems
1. [M, SPICE, 3.3.2] The layout of a static CMOS inverter is given in Figure 5.1. (λ = 0.125 µm). a. Determine the sizes of the NMOS and PMOS transistors. Solution The sizes are wn=1.0µm, ln=0.25µm, wp=0.5µm, and lp=0.25 µm. b. Plot the VTC (using HSPICE) and derive its parameters (VOH, VOL, VM, VIH, and VIL). Solution The inverter VTC is shown below. For a static CMOS inverter with a supply voltage of 2.5 V, VOH =2.5 V and VOL=0 V. In order to calculate Vm , note from the VTC that the value is between 0.8 V and 0.9 V. Therefore, the NMOS is saturated and the PMOS is velocity saturated. Let Vin=Vout=Vm and set the currents equal to obtain the following equation:

(kn/2)(VGS-VTN)2(1+λVDS)=kpVDSAT[(VGS-VTP)-(VDSAT/2)](1+λVDS)
Substitute the appropriate values and solve numerically to find V m=0.883 V. Use the VTC data to solve for VIL and VIH numerically. The result is that VIH=0.97 V and VIL=0.56 V.
3

2.5

VIL

2

Output Voltage (V)

1.5

1

VM

0.5

0

VIH

−0.5

0

0.5

1

1.5 Input Voltage (V)

2

2.5

c. Is the VTC affected when the output of the gates is connected to the inputs of 4 similar gates? Solution No. CMOS gates are a purely capacitive load so the DC circuit characteristics are not affected.

182

THE CMOS INVERTER

Chapter 5

GND

Poly

In VDD = 2.5 V. Poly

2λ

NMOS Metal1 Out Metal1

PMOS

Figure 5.1

CMOS inverter layout.

2.

d. Resize the inverter to achieve a switching threshold of approximately 0.75 V. Do not layout the new inverter, use HSPICE for your simulations. How are the noise margins affected by this modification? Solution Changing the NMOS sizing to wn=2.0µm moves the switching threshold to 0.75 V. This increases N MH and decreases N ML. Figure 5.2 shows a piecewise linear approximation for the VTC. The transition region is approximated by a straight line with a slope equal to the inverter gain at VM. The intersection of this line with the VOH and the VOL lines defines VIH and VIL. a. The noise margins of a CMOS inverter are highly dependent on the sizing ratio, r = kp/kn, of the NMOS and PMOS transistors. Use HSPICE with VTn = |VTp| to determine the value of r that results in equal noise margins? Give a qualitative explanation. Solution The TSMC 0.25µm models were used for simulation and the threshold voltages of NMOS and PMOS devices are nearly equal in this process. A value near r=1 should result in equal noise margins, since the transistors will be closely matched. HSPICE showed that the resulting noise margins for this sizing were NMH=0.97 V and NML=1.1 V. The mismatch is due to the fact that the PMOS threshold voltage is actually slightly lower, so the PMOS is stronger and the upper noise margin is reduced. The actual value that results in equal noise margins is r=0.83. b. Section 5.3.2 of the text uses this piecewise linear approximation to derive simplified expressions for NMH and NML in terms of the inverter gain. The derivation of the gain is based on the assumption that both the NMOS and the PMOS devices are velocity saturated at VM . For what range of r is this assumption valid? What is the resulting range of VM ? Solution

Section 5.1

Exercises and Design Problems

183

Using the equations for finding the region of operation, it can be shown that the PMOS and NMOS are both velocity saturated only while the switching threshold is between 1.06 V and 1.10 V. Since this range may be considered inclusive, we can assume that both devices are velocity saturated and set the currents equal with V IN=V OUT=VM to find kp/kn . The result is that kp/kn must be between 0.34 and 0.41. This result can be checked by sizing the devices accordingly and testing the resulting V M in HSPICE. The result gives a range of 1.04 V to 1.09 V. This makes sense, because the NMOS must be much stronger than the PMOS to achieve a switching threshold near 1 V. c. Derive expressions for the inverter gain at VM for the cases when the sizing ratio is just above and just below the limits of the range where both devices are velocity saturated. What are the operating regions of the NMOS and the PMOS for each case? Consider the effect of channel-length modulation by using the following expression for the small-signal resistance in the saturation region: ro,sat = 1/(λID).
Vout VOH

VM

Vin VOL VIL VIH

Figure 5.2 A different approach to derive VIL and VIH.

Solution: When VM is slightly larger than 1.1 V, the NMOS is velocity saturated and the PMOS is saturated. When V‘ is slightly smaller than 1.06 V, the PMOS is velocity saturated and the NMOS is saturated. Section 5.3.2 of the text shows this derivation for the case when both devices are velocity saturated. These derivations can be completed by substituting the correct current equations and using the same method. The results are as follows: For the case when the NMOS is saturated and the PMOS is velocity saturated: k ( V – V )( 1 + λ V )+k V (1 + λ (V –V )) dV n in tn n out p DSATP p out DD out --------------- = – ----------------------------------------------------------------------------------------------------------------------------------------------------------------------V k λ dV 2 DSATP n n in ---------------------------------- ( V – V ) + k V in tn p DSATP λ p V i n – V D D – V tp – 2 2

Dropping the second order terms in the numerator, substituting Vm for Vin, and simplifying the denominator leads to the following expression for the gain: k (V – V ) + k V dV out n m tn p DSATP --------------- = – ---------------------------------------------------------------------dV in ID ( Vm) (λ n – λp )

For the case when the NMOS is velocity saturated and the PMOS is saturated: k V (1 + λ V ) + k (V – V – V ) (1 + λ (V –V )) dV n DSATN n out p in DD tp p out DD out --------------- = – -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------dV V k λ 2 in DSATN p p k n V DSATN λ n V i n – V t n – ----------------------- + ------------ ( V in – V DD – V t p ) 2 2
   

 

 

184

THE CMOS INVERTER

Chapter 5

Again, dropping the second order terms in the numerator, substituting Vm for Vin, and simplifying the denominator leads to the following expression for the gain: k V + k (V – V –V ) dV n DSATN p m DD tp out --------------- = – ----------------------------------------------------------------------------------------I ( V ) (λ – λ ) dV D m n p in

3.

[M, SPICE, 3.3.2] Figure 5.3 shows an NMOS inverter with a resistive load. a. Qualitatively discuss why this circuit behaves as an inverter. Solution For VIN VT, M1 is conducting and Vout=2.5V - (I*R). This in turn gives a low Vout and the input signal is inverted. b. Find VOH and VOL calculate VIH and VIL. Solution Assuming negligable leakage, when Vin> tpHL because RL=75kΩ is much larger than the effective linearized on-resistance of M1.

Section 5.1

Exercises and Design Problems

187

c. Compute the static and dynamic power dissipation assuming the gate is clocked as fast as possible. Solution Static Power: VIN=VOL gives Vout=VOH=2.5V, thus IVDD=0A so PVDD=0W. VIN=VOH gives Vout=VOL =46.3mV, which is in the linear region. Calculating the current through M1 gives IVDD=32.8mA --> PVDD =82mW Dynamic Power: Pdyn=CL∆V*Vdd*fmax=3pF*(2.5V-46.3mV)*2.5V*12.2MHz=0.225mW. The next figure shows two implementations of MOS inverters. The first inverter uses only NMOS transistors. a. Calculate VOH, VOL, VM for each case. VDD = 2.5V V = 2.5V
DD

5.

M2

W/L=0.375/0.25

M4 VOUT W/L=0.75/0.25 VIN M3
W/L=0.375/0.25

V OUT VIN

M1 W/L=0.75/0.25

A

B
Figure 5.4 Inverter Implementations

Solution Circuit A. VOH: We calculate VOH, when M1 is off. The threshold for M2 is:
V T = V T0 + γ ⋅ ( – 2φ F + V SB – – 2φ F ) , V SB = V OUT , –2φ F = 0.6V = 0,

and M2 will be off when: VGS – V T = V D D – V OUT – V T Substitute VT in the last equation and solve for VOUT.
V DD –V OU T –V T = 2.5 – V OU T – ( 0.43 + 0.4 ⋅ (

0.6 + V

O UT

–

0.6 ) ) = 0

We get VOUT=VOH=1.765V VOL: To calculate VOL, we set V IN=VDD=2.5V. We expect VOUT to be low, so we can make the assumption that M2 will be velocity saturated and M1 will be in the linear region. For M2:
I D2 2 W V 2 DSAT = k' ⋅ ------- ⋅ ( V –V )⋅V – ------------------ ⋅ ( 1 + λV ) n L GS T DSAT DS 2 2
       

and

188 for M1:
I
   

THE CMOS INVERTER
2 W V 1 DS = k' ⋅ ------- ⋅ ( V –V )⋅V – ----------D1 n L GS T0 DS 2 1
   

Chapter 5

Setting ID 1 = I D2 , we get an equation and we solve for V OUT. We get: VOUT=VOL=0.263V, so our assumption holds. VM: To calculate VM we set VM=VIN=VOUT. Assuming that both transistors are velocity saturated, then we have the next pair of equations:
2 V W D SAT 1 – ------------------ ⋅ ( 1 + λV ) = k' ⋅ ------- ⋅ ( V – V ) ⋅ V M T0 D SAT D1 n L M 2 1
       

I

I

2 V W DSAT 2 –V –V )⋅V – ------------------ ⋅ ( 1 + λ ( V = k' ⋅ ------- ⋅ ( V – V )) DD M T DSAT D2 n L DD M 2 2
       

Setting I D 1 = I D2 , we get for VM = 1.269V Circuit B. When VIN =0V, the NMOS transistor is off and the PMOS transistor in on and pulls VOUT up to VDD, so VOH=2.5. Similarly, when V IN=2.5V, the PMOS transistor is off and the NMOS transistor pulls V OUT all the way down to ground, so VOL=0V. To calculate VM we set V M=VIN =VOUT. We assume that both transistors are velocity saturated. We get the following pair of equations.
2 W V 4 DSATp I D4 = k'p ⋅ ------- ⋅ ( V M – V DD – V ) ⋅ VD SATp – ---------------------- ⋅ ( 1 + λ p V M ) L4 2 T0p 2 W V 3 DSATn I D3 = k'n ⋅ ------- ⋅ ( V M – V T0n ) ⋅ V DSATn – ---------------------- ⋅ ( 1 + λ n V M ) L3 2
               

Setting ID 3 + I D2 = 0 , we get for VM = 1.095V. So the assumption that both transistors were velocity saturated holds. b. Use HSPICE to obtain the two VTCs. You must assume certain values for the source/drain areas and perimeters since there is no layout. For our scalable CMOS process, λ = 0.125 µm, and the source/drain extensions are 5λ for the PMOS; for the NMOS the source/drain contact regions are 5λx5λ. Solution

Section 5.1

Exercises and Design Problems The two VTCs are shown below.
* problem 5
2.6 2.6

189

* problem 5

2.4

2.4

2.2

2.2

2

2

1.8

1.8

1.6

1.6

Voltages (lin)

1.2

Voltages (lin)

1.4

1.4

1.2

1

1

800m

800m

600m

600m

400m

400m

200m

200m

0

0

0

200m

400m

600m

800m

1

1.2 1.4 Voltage X (lin) (VOLTS)

1.6

1.8

2

2.2

2.4

2.6

0

200m

400m

600m

800m

1

1.2 1.4 Voltage X (lin) (VOLTS)

1.6

1.8

2

2.2

2.4

2.6

Depletion Load Inverter

CMOS Inverter

c. Find VIH , VIL, NM L and NMH for each inverter and comment on the results. How can you increase the noise margins and reduce the undefined region? Solution Circuit A VIL = 0.503V => VOUT1 = 1.65V, VIH = 1.35V => VOUT2 = 0.588V NMH = VOH - VOUT2 = 1.765 - 1.65 = 0.115V, NML = VOUT1 - VOL = 0.588- 0.23 = 0.358V Circuit B VIL = 0.861V => VOUT1 = 2.33V, VIH = 1.22V => VOUT2 = 0.219V NMH = VOH - VOUT2 = 2.5V - 1.22V = 1.28V, NML = VOUT1 - VOL = 0.861V- 0V = 0.861V We can increase the noise margins by moving VM closer to the middle of the output voltage swing. d. Comment on the differences in the VTCs, robustness and regeneration of each inverter. Solution It is clear from the two VTCs, that the CMOS inverter is more robust, since the low and high noise margins are higher than the first inverter. Also the regeneration in the second inverter is greater since it provides rail to rail output and the gain of the inverter is much greater. Consider the following NMOS inverter. Assume that the bulk terminals of all NMOS devices are connected to GND. Assume that the input IN has a 0V to 2.5V swing.

6.

VDD= 2.5V M3 x VDD= 2.5V M2 OUT IN M1

190

THE CMOS INVERTER a. Set up the equation(s) to compute the voltage on node x. Assume γ=0.5. Solution The voltage on node x is set to one threshold value VT below VDD. So: V X = V DD – V T V X = V DD – [ V T0 + γ ( V S B + – 2φ F – – 2φ F ) ]

Chapter 5

V X = 2.5 – [ 0.43 + 0.5 ( V X + 0.6 – 0.6 ) ] V X = 2.07 + 0.39 – 0.5 V X + 0.6 V X = 2.46 – 0.5 V X + 0.6 which gives VX=1.7014V. b. What are the modes of operation of device M2? Assume γ=0. Solution V X = V DD – V T V DS2 = V DD – V OUT V GS2 – V T = V DD – V T – V OUT – V T = V DD – V OUT – 2V T This means that V DS2 > V GS2 – V T , so M2 is either saturated (or vel. saturated) or cut off. c. What is the value on the output node OUT for the case when IN =0V?Assume γ=0. Solution When IN=0 then M1 is off and OUT will charge up to: V out ( max ) = V X – V T V out ( max ) = V DD – V T – V T V out ( max ) = V DD – 2V T d. Assuming γ=0, derive an expression for the switching threshold (VM) of the inverter. Recall that the switching threshold is the point where VIN= VOUT. Assume that the device sizes for M1, M2 and M3 are (W/L)1, (W/L)2, and (W/L)3 respectively. What are the limits on the switching threshold? For this, consider two cases: i) (W/L)1 >> (W/L)2 ii) (W/L)2 >> (W/L)1 Solution Assuming that both devises are velocity saturated we can equate the currents when VIN= VOUT=VM. This gives

Section 5.1

Exercises and Design Problems

191

1

2

1

2

( W ⁄ L )2 Solving for VM and substituting r = ------------------ we get: ( W ⁄ L )1
 

V DSAT V DSAT V M – V T – -------------- = r V DD – 2V T – V M – -------------2 2 V DSAT V DSAT r V DD – 2V T – -------------- + V T + -------------2 2 V M = ---------------------------------------------------------------------------------------1+r
       

To find the limits for VM we check the two cases: i) When (W/L)1 >> (W/L)2, VM = VT + V DSAT/2 = 0.43 + 0.63/2 = 0.745 ii) When (W/L)2 >> (W/L)1, V M = VDD - 2V T - VDSAT /2 = 1.325 For both cases the assumptions for M1 and M2 are valid. Consider the circuit in Figure 5.5. Device M1 is a standard NMOS device. Device M2 has all the same properties as M1, except that its device threshold voltage is negative and has a value of -0.4V. Assume that all the current equations and inequality equations (to determine the mode of operation) for the depletion device M2 are the same as a regular NMOS. Assume that the input IN has a 0V to 2.5V swing.

7.

VDD= 2.5 V M2 (2µm/1µm), VTn = -0.4V OUT IN M1 (4µm/1µm)
Figure 5.5 A depletion load NMOS inverter

a. Device M2 has its gate terminal connected to its source terminal. If VIN = 0V, what is the output voltage? In steady state, what is the mode of operation of device M2 for this input? Solution When VIN = 0V then M1 is off. M2 is on since VGS=0 > VTn2. Since there is no current through M2, the drain to source voltage of M2 is 0 (linear mode). This means that VOUT=2.5V. b. Compute the output voltage for VIN = 2.5V. You may assume that VOUT is small to simplify your calculation. In steady state, what is the mode of operation of device M2 for this input? Solution We assume that M1 is in the linear mode and M2 is velocity saturated. This means:

 

   

 

 

 

   

W ---L

V DSAT W V M – V T – -------------- = ---L 2

V DSAT V DD – V T – V M – V T – -------------2

 

   

 

 

   

W k' n ---L
   

V DSAT W V GS1 – V T – -------------- = k' n ---L 2

V DSAT V GS2 – V T – -------------2

192
2

THE CMOS INVERTER
2

Chapter 5

V ou V Dsat k n1 ( 2.5 – 0.4 )V ou t – ---------t = k n2 ( 0 – ( – 0.4 ) )V Dsat – -----------2 2 Since Vout is small we can neglect the V2out/2 term and the previous equation becomes k n2 0.05355 V out = ------ ------------------ , which gives V out ≅ 12mV k n1 2.1 So our assumptions are valid. c. Assuming Pr(IN =0)= 0.3, what is the static power dissipation of this circuit? Solution There is static power dissipation when both transistors are on. This happens when VIN=1. Then the static power dissipation is given by: P s tati c = P in = 1 V DD I D
    

115uA 2 0.63 -P sta tic = ( 1 – 0.3 )2.5 --------------- -- 0.4 ⋅ 0.63 – -----------2 1 2 V P stat ic = 21.55uW 8.
    

2

[M, None, 3.3.3] An NMOS transistor is used to charge a large capacitor, as shown in Figure 5.6. a. Determine the tpLH of this circuit, assuming an ideal step from 0 to 2.5V at the input node. Solutions To determine the rise time, an average current has to be calculated between the start of the transistion with VO=0V and midpoint of the transition. At the start of the transistion: V O=V OL=0V, M1 is velocity saturated and IDsat=1.46mA. To find the votlage swing, VOH must be calculated using the body effect: V gs = 2.5V – V OH = V t n + γ ( VOH=1.76V. The midpoint is thus, V OH – V OL ------------------------- = 0.88V 2 and the threshold voltage at the midpoint is: VT(Vsb=0.88V)=0.607V. Using this threshold voltage, V GT=1.013V, VDS=1.62V, and VDSat=0.63V, thus, the transistor M1 is still velocity saturated, giving IDSat=49.17mA. Finding the average current between V0= 0V and V 0= 0.88V gives: Iaverage=0.756mA. C L ∆V 5pF × 0.88V t p = ---------------- = ------------------------------ = 5.82n sec 0.756mA I aver age b. Assume that a resistor RS of 5 kΩ is used to discharge the capacitance to ground. Determine tpHL. Solution tpLH=0.69*RLCL=0.69*5kΩ∗5pF=17.25ns 0.6 + V OH – 0.6 )

Section 5.1

Exercises and Design Problems
VDD = 2.5V In 20 2 M1 Out CL = 5 pF Figure 5.6 Circuit diagram with annotated W/L ratios

193

9.

c. Determine how much energy is taken from the supply during the charging of the capacitor. How much of this is dissipated in M1. How much is dissipated in the pull-down resistance during discharge? How does this change when RS is reduced to 1 kΩ. Solution ∆QVDD=CL∆V=5pF*1.76V=8.8pC ∆EVDD =∆QVDD*Vdd=8.8pC*2.5V=22pC Half the energy is dissipated in the transistor M1, while the other half is dissipated in the restistor Rs. The energy dissipated is independent of R s. d. The NMOS transistor is replaced by a PMOS device, sized so that kp is equal to the kn of the original NMOS. Will the resulting structure be faster? Explain why or why not. Solution If a PMOS device replaces the NMOS device, body effect will not exist and the PMOS device will be faster. The circuit in Figure 5.7 is known as the source follower configuration. It achieves a DC level shift between the input and the output. The value of this shift is determined by the current I0. Assume xd=0, γ=0.4, 2|φf|=0.6V, VT0=0.43V, kn’=115µA/V2 and λ=0.

VDD = 2.5V

VDD = 2.5V

Io
Vi M1 1um/0.25um Vo Vbias= 0.55V M2 LD=1um Vi M1 1um/0.25um Vo

Io

(a)
Figure 5.7 NMOS source follower configuration

(b)

194

THE CMOS INVERTER

Chapter 5

a. Suppose we want the nominal level shift between Vi and Vo to be 0.6V in the circuit in Figure 5.7 (a). Neglecting the backgate effect, calculate the width of M2 to provide this level shift (Hint: first relate Vi to Vo in terms of Io). Solution The level shift of 0.6V tells us that V GS1=0.6V so VGT1=0.17V. This means that M1 must be in the saturation region (not velocity saturated). Thus,
W k' ⋅ ---n L 2 ---------------- ⋅ ( V –V ) = I , GS T D 2

and ID=6.647 µ A.

For M2, VGT=0.12, so M2 is also in the saturation region (not velocity saturated). Using the same equation as above and solving for W/L gives W/L = 8. b. Now assume that an ideal current source replaces M2 (Figure 5.7 (b)). The NMOS transistor M1 experiences a shift in VT due to the backgate effect. Find VT as a function of Vo for Vo ranging from 0 to 2.5V with 0.5V intervals. Plot VT vs. Vo Solution The threshold voltage equation provides the relation that we need:
V T = V T0 +γ⋅( 2φ F +V SB – 2φ ) = V + γ ⋅ ( F T0 2φ F +V – o 2φ ) F

.

See the graph at the end of this problem. c. Plot Vo vs. Vi as Vo varies from 0 to 2.5V with 0.5 V intervals. Plot two curves: one neglecting the body effect and one accounting for it. How does the body effect influence the operation of the level converter? Solution To plot Vo versus Vi, we need to relate Vo to Vi. We can do this by solving the current equation (M1 should remain in the same region to first order because VGT will remain roughly constant to maintain the correct drain current) for Vi:
2I DV = V + V + --------------- . i o T W k' ⋅ ---n L

d. At Vo(with body effect) = 2.5V, find Vo(ideal) and thus determine the maximum error introduced by the body effect. Solution The maximum error occurs at the highest VSB. At Vo = 2.5, the error is 3.49443.1=0.3944 V.

Section 5.1

Exercises and Design Problems

195

Backgate Effect: Vo versus VT 0.9
2.5 No backgate effect Backgate effect 2

Backgate Effect: V versus V o i

0.85

0.8

0.75

0.7
VT (V)

1.5
Vo (V)

0.65

0.6

1

0.55

0.5

0.5

0.45

0.4

0

0.5

1 V (V) o 1.5

2

2.5

0 0.5

1

1.5

2 Vi (V)

2.5

3

3.5

Figure for part (b)

Figure for part (c)

10.

For this problem assume: VDD = 2.5V, W P/L = 1.25/0.25, WN/L = 0.375/0.25, L=Leff =0.25µm (i.e. xd= 0µm), CL=Cinv2 2 -1 gate, kn’ = 115µA/V , kp’= -30µA/V , Vtn0 = | Vtp0 | = 0.4V, λ = 0V , γ = 0.4, 2|φf|=0.6V, and tox = 58A. Use the HSPICE model parameters for parasitic capacitance given below (i.e. Cgd0, Cj, Cjsw), and assume that VSB=0V for all problems except part (e). VDD = 2.5V

L = LP = LN = 0.25µm

VIN

VOUT CL = Cinv-gate
(Wp/Wn = 1.25/0.375)
+

VSB

Figure 5.8 CMOS inverter with capacitive

## Parasitic Capacitance Parameters (F/m)## NMOS: CGDO=3.11x10-10, CGSO=3.11x10-10, CJ=2.02x10-3, CJSW=2.75x10-10 PMOS: CGDO=2.68x10-10, CGSO=2.68x10-10, CJ=1.93x10-3, CJSW=2.23x10-10 a. What is the Vm for this inverter? Solution

196

THE CMOS INVERTER

Chapter 5

Assume that Vm is around midrail (1.25V). That means that the NMOS is velocity saturated and the PMOS is saturated. To find Vm, we set the sum of the currents at Vout equal to 0 using the correct equation for each device:
V 2 DSATn k ⋅V ⋅ V – V – ---------------------- + k ⋅ 0.5 ⋅ ( V – V –V ) = 0. n D SATn M Tn p M DD Tp 2
   

Plug in numbers:
172.5 ⋅ 0.6 ⋅ ( V M – 0.4 – 0.315 ) + ( –150 ) ⋅ 0.5 ⋅ ( VM – 2.5 – ( – 0.4 ) ) – 74 – – 75 ⋅ V
   

2

= 0

M

M

M

Solving this quadratic gives V M = 1.245 V. b. What is the effective load capacitance CLeff of this inverter? (Include parasitic capacitance, refer to the text for Keq and m.) Hint: You must assume certain values for the source/drain areas and perimeters since there is no layout. For our scalable CMOS process, λ = 0.125 µm, and the source/drain extensions are 5λ for the PMOS; for the NMOS the source/drain contact regions are 5λx5λ. Solution The calculation of the lumped load capacitance follows the format presented in the lecture notes. The only difference is the dimensions of the devices. CLeff = C L + Cparasitic = Cg3 + Cg4 + Cdb1 + Cdb2 + Cgd1 + Cgd2. Cg3 = (CGD0n + CGSOn)Wn + CoxWnL = 2(3.11e-10)(0.375e-6) + 6e-15(0.375)(0.25) = 0.796fF Cg4 = (C GD0p + CGSOp)Wp + C oxWpL = 2(2.68e-10)(1.25e-6) + 6e-15(1.25)(0.25) = 2.545fF Cdb1 = K eqn(ADn)C j + Keqswn(PD n)Cjsw. Need to do this calculation for both transitions and average the results. The Keq values are already calculated in the text. ADp=ASp=1.25um*0.625um=0.78125um2 and ADn=ASn=0.125*0.375+0.6252=0.4375um2. PDp=PSp=2*0.625um+1.25um=2.5um and PDn=PSn=5*0.125um*3+(2+1+1)*0.125um=2.375um. (0.57*0.4375*2 + 0.61*2.375*0.28) = 0.904fF for HL transition (0.79*0.4375*2 + 0.81*2.375*0.28) = 1.23fF for LH. Average Cdb1=1.067fF. Cdb2 = Keqp(ADp)Cj + Keqswp(PD p)Cjsw. (0.79*0.78125*1.9 + 0.86*2.5*0.22) = 1.65fF for HL transition (0.59*0.78125*1.9 + 0.7*2.5*0.22) = 1.26fF for LH. Average Cdb2=1.455fF. Cgd1 = 2CGD0nWn = 2*3.11e-10*0.375e-6 = 0.233fF. Cgd2 = 2CGD0pWp = 2*2.68e-10*1.25e-6 = 0.67fF. CL = sum = 6.767fF. Note - since the problem states that xd=0, it is ok if you neglected the last two parasitic capacitances. We intended for them to be included, though. c. Calculate tPHL, tPLH assuming the result of (b) is ‘CLeff = 6.5fF’. (Assume an ideal step input, i.e. trise=tfall=0. Do this part by computing the average current used to charge/discharge CLeff.) Solution We can estimate the propagation delay using the approximation ∆t = ∆Q/I, where ∆Q = CLeffVDD and I is the average current used to charge/discharge CLeff. During the high-to-low transition CLeff is discharged through the NMOS transistor so I = IavgN. During the low-to-high transition CLeff is charged through the PMOS transistor so I = IavgP. In summary:

 

103.5V

2

– 4.2V

+ 4.41

= 0.

Section 5.1

Exercises and Design Problems
V DD ⋅ CLef f t delay ≅ ------------------------------- , where 2 ⋅ I avg V V DD DD I (V = 0 ) + I V = -----------I (V = V )+I V = -----------ds o ds o ds o DD ds o 2 2 I = ----------------------------------------------------------------------------- , I = --------------------------------------------------------------------------------------avgN avgP 2 2

197

Table 1 shows corresponding values for IavgN, IavgP, tPLH, and tPHL. NOTE- This solution
Vo (V) 0 for tPLH 1.25 2.5 for tPHL 1.25 Operation Mode PMOS vel sat. PMOS vel sat NMOS vel sat. NMOS vel sat Ids (mA) 0.300 0.285 0.270 0.209 0.202 0.195 40.0 28.5 Iavg (mA) Prop Delay (ps)

Table 1: Average currents and propagation delays for Problem 4(c).

11.

included channel length modulation, but it is ok if your solution did not (see problem assumptions). d. Find (Wp/Wn) such that tPHL = tPLH. Solution One way to do this is to solve the current average equations for W p/Wn after setting the propagation delays equal to one another. A much easier method is to sweep the widths in HSPICE. The HSPICE sim shows that Wp/Wn =2.6 gives equal rise and fall times. e. Suppose we increase the width of the transistors to reduce the tPHL, tPLH. Do we get a proportional decrease in the delay times? Justify your answer. Solution The propagation delays DO NOT decrease in proportion to the widths because of selfloading effects. As the device size increases, its parasitic capacitances increase as well. In this problem, increasing device size increases both average current and C Leff. f. Suppose VSB = 1V, what is the value of Vtn, Vtp, Vm? How does this qualitatively affect CLeff? Solution Vtp = Vtp0 = -0.4V. Vtn = 0.4 + γ ⋅ ( 2φ F + 1 – 2φ F ) = 0.596 V. Using the equation for part a) and plugging in the new value of Vtn gives: VM = 1.35V The increased Vsb will increase the depletion region and lower the junction capacitance, lowering CLeff. Using Hspice answer the following questions. a. Simulate the circuit in Problem 10 and measure tP and the average power for input Vin: pulse(0 VDD 5n 0.1n 0.1n 9n 20n), as VDD varies from 1V - 2.5V with a 0.25V interval. [tP = (tPHL + tPLH ) / 2]. Using this data, plot ‘tP vs. VDD’, and ‘Power vs. VDD’. Specify AS, AD, PS, PD in your spice deck, and manually add CL = 6.5fF. Set VSB = 0V for this problem.

 

 

 

 

198 Solution

THE CMOS INVERTER

Chapter 5

*prob4g pset1
4u 230p 3.8u 220p 3.6u 210p 3.4u 200p 3.2u 190p 3u 180p 2.8u 170p 2.6u

*prob4g pset1

Outer Result (lin)

Measures (lin)
1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Outer Result (lin) (pvdd) 2 2.1 2.2 2.3 2.4 2.5

160p

2.4u

150p

2.2u

140p

2u

130p

1.8u

120p

1.6u

110p

1.4u

100p

1.2u

90p

1u

80p

800n

70p

600n

1

1.1

1.2

1.3

1.4

1.5

1.6 1.7 1.8 1.9 Outer Result (lin) (pvdd)

2

2.1

2.2

2.3

2.4

2.5

Delay vs VDD (part a)

Power vs VDD (part a)

b. For Vdd equal to 2.5V determine the maximum fan-out of identical inverters this gate can drive before its delay becomes larger than 2 ns. Solution The maximum number of identical inverters that this gate can drive before the propagation delay exceeds 2ns is 115 inverters. c. Simulate the same circuit for a set of ‘pulse’ inputs with rise and fall times of tin_rise,fall =1ns, 2ns, 5ns, 10ns, 20ns. For each input, measure (1) the rise and fall times tout_rise and tout_fall of the inverter output, (2) the total energy lost Etotal, and (3) the energy lost due to short circuit current Eshort. Using this data, prepare a plot of (1) (tout_rise+tout_fall)/2 vs. tin_rise,fall, (2) Etotal vs. tin_rise,fall, (3) Eshort vs. tin_rise,fall and (4) Eshort/Etotal vs. tin_rise,fall. Solution

Section 5.1

Exercises and Design Problems

199

(trise+tfall)/2 vs trfin 5 4
(trise+tfall)/2 (ns)

Etotal vs trfin 2

1.5
Etotal (pJ)

3 2 1 0

1

0.5

0

5

10 trfin (ns) Eshort vs trfin

15

20

0

0

5

10 trfin (ns)

15

20

Eshort/Etotal vs trfin 1

2

1.5
Eshort/Etotal Eshort (pJ)

0.9

1

0.8

0.5

0.7

0

0

5

10 trfin (ns)

15

20

0.6

0

5

10 trfin (ns)

15

20

d. Provide simple explanations for: (i) Why the slope for (1) is less than 1? (ii) Why Eshort increases with tin_rise,fall? (iii) Why Etotal increases with tin_rise,fall? Solution i) The slope is less than 1 because of the regenerative property of the inverter. The high gain around the switching point causes the output to change faster than the inputs. ii) The amount of time for which both devices are on simultaneously increases. iii) Total energy increases because the short circuit energy begins to dominate, and the short circuit increases as the rise/fall time increases.

200 12. Consider the low swing driver of Figure 5.9: VDD = 2.5 V

THE CMOS INVERTER

Chapter 5

W = 1.5 µm L n 0.25 µm W 3 µm = L p 0.25 µm

Vin 2.5V 0V

Vout
CL=100fF

Figure 5.9 Low Swing Driver

a. What is the voltage swing on the output node (Vout)? Assume γ=0. Solution The range will be from 0.4 V to 2.07 V, since the PMOS is a weak pull down device and the NMOS is a weak pull up device. b. Estimate (i) the energy drawn from the supply and (ii) energy dissipated for a 0V to 2.5V transition at the input. Assume that the rise and fall times at the input are 0. Repeat the analysis for a 2.5V to 0V transition at the input. Solution For a 0 V to 2.5 V transition on the input, the energy drawn from the power supply is: E SUPPLY = i DD V DD dt = V DD ∆Q = CV DD ( ( V DD – V tn ) – V t p )

The PMOS will be in cutoff and the energy dissipated in the NMOS will be: E DISSIPATED = E SUPPLY – ∆E CAP
       

E DISSIPATED = CV DD ( ( V DD – V tn ) – V t p ) – C

For a 2.5 V to 0 V transition on the input, the NMOS will be in cutoff and no energy will be drawn from the power supply. The energy dissipated in the PMOS device will be equal to:
       

c. Compute tpLH (i.e. the time to transition from VOL to (VOH + VOL) /2). Assume the input rise time to be 0. VOL is the output voltage with the input at 0V and VOH is the output voltage with the input at 2.5V. Solution When the input is high and the capacitor charges, the PMOS device is in cutoff and the NMOS is velocity saturated for the duration of the charging. The total voltage range is 0.4 V to 2.07 V, so the midpoint is 1.24 V. We can use the average current method to approximate tplh. For the velocity saturated NMOS:

∫

V DD – V t n ----------------------2

2

V tp – --------2

2

E = C

V DD – V t n ----------------------2

2

V tp – --------2

2

Section 5.1

Exercises and Design Problems V DSATN µn Co xW ------------------- V DSATN V GS – V t n – ----------------- ( 1 + λV DS ) L 2
     

201

Solving for the current at V=0.4 V and V=1.24 V and averaging yields an average current of 404 uA. Then: ( 100fF ) ( 1.24V – 0.4V ) C∆V t plh = ----------- = -------------------------------------------------------- = 208ps 404uA I avg d. Compute VOH taking into account body effect. Assume γ = 0.5V 1/2 for both the NMOS and the PMOS. Solution The PMOS will be deep in cutoff when Vout approaches VOH. Therefore, we consider only the NMOS. We can express the equation for threshold voltage numerically as follows: V t n = 0.43 + 0.5 ( ( 0.6 + 2.5 – V t n ) – 0.6 ) This is an equation in one variable, so it may be solved numerically to find that V tn=0.8 V. Consider the following low swing driver consisting of NMOS devices M1 and M2. Assume an NWELL implementation. Assume that the inputs IN and IN have a 0V to 2.5V swing and that VIN = 0V when VIN = 2.5V and vice-versa. Also assume that there is no skew between IN and IN (i.e., the inverter delay to derive IN from IN is zero). VLOW= 0.5V 25µm/0.25µm M2 Out M1 25µm/0.25µm CL=1pF
Figure 5.10 Low Swing Driver

13.

IN

IN

a. To what voltage is the bulk terminal of M2 connected? Solution In an NWELL process, the bulk terminal of an NMOS must be connected to ground. b. What is the voltage swing on the output node as the inputs swing from 0V to 2.5V. Show the low value and the high value. Solution Because the supply voltage is more than a threshold voltage lower than the gate drive voltage, the output range will not be limited. Therefore the low value is 0 V and the high value is 0.5 V. c. Assume that the inputs IN and IN have zero rise and fall times. Assume a zero skew between IN and IN. Determine the low to high propagation delay for charging the output node measured from the the 50% point of the input to the 50% point of the output. Assume that the total load capacitance is 1pF, including the transistor parasitics. Solution

 

I =

202

THE CMOS INVERTER

Chapter 5

The lower NMOS will be off during the low to high transition and the upper NMOS will be in the linear region throughout the transition from 0.0V to 0.25V. We will assume that the body effect is negligible, since the maximum value of VSB is 0.25V. Use the average current method to find tplh. Using the current equation for the linear region, the current when the capacitor is at 0V, is 10.8mA. When the capacitor reaches 0.25V, the current is 4.58mA. Threfore, the average current is 7.7mA. ( 1pF ) ( 0.25V ) C∆V tplh = ----------- = ---------------------------------- = 32.5ps 7.7mA I avg d. Assume that, instead of the 1pF load, the low swing driver drives a non-linear capacitor, whose capacitance vs. voltage is plotted below. Compute the energy drawn from the low supply for charging up the load capacitor. Ignore the parasitic capacitance of the driver circuit itself.
3

2

1

.5V 1V 1.5V 2V 2.5V 3V

Voltage, V

Solution The capacitor charges only from 0 V to 0.5 V, so only the first segment of the graph should be considered. The total energy drawn from the supply is: E = V DD I ( t ) dt = Q t otal V DD The total charge required to charge the capacitor is:
0.5 · 0.5

0

14.

Therefore, since the the E=QV, the total energy drawn from the supply is 0.375 pJ. The inverter below operates with VDD=0.4V and is composed of |V t| = 0.5V devices. The devices have identical I0 and n. a. Calculate the switching threshold (VM) of this inverter. Solution ( V G S – V t ) ⁄ ( nV T ) The subthreshold I-V relation is given by I D = Io e ( 1 + λV DS ) , assuming VDS > 50mV. To calculate the switching voltage, we need to find where Vin=Vout occurs. So equating the absolute values of the currents for the two transistors we get: Io' e
V in ⁄ ( nV T )

( 1 + λ n V o ut ) = I o' e

( V D D – V in ) ⁄ ( n VT )

∫

∫

Q =

C ( V ) dV = 1pF

∫

( 1 + 2V ) dV = 0.75pC

0

( 1 + λ p ( V DD – V out ) )

Section 5.1

Exercises and Design Problems Considering Vin=Vout and doing some cancellations we get: ln [ ( 1 + λ n V i n ) ⁄ ( 1 + λ p ( V i n – V DD ) ) ] = 1 ⁄ ( ( n ⋅ V T ) ( V DD – V i n – V i n ) ) after massaging the last equation we have: V DD ⁄ 2 – nV T ⁄ 2 ⋅ ln [ ( 1 + λ n V i n ) ⁄ ( 1 + λ p ( V DD – V in ) ) ] = V in

203

Iterating this expression with V DD=0.4V, V T=26mV, λn=0.06, λp=0.1 and n=1.5 we get Vin=0.2V. So we have a switching threshold of VDD/2=0.2V. b. Calculate VIL and VIH of the inverter.
VDD = 0.4V

VIN

VOUT

Figure 5.11 Inverter in Weak Inversion Regime

Solution To calculate the noise margins we need to calculate the slope of the VTC at VM=VDD /2. Equating the currents we get: Io' e
V in ⁄ ( nV T )

( 1 + λ n V o ut ) = I o' e

( V D D – V o u t ) ⁄ ( n VT )

( 1 + λ p ( V DD – V out ) )

and cancelling out Io‘ and differentiating both sides with respect to Vin we get:
V in ⁄ ( nV T ) ∂ ∂ ( V i n – V D D ) ⁄ ( nV T ) (e ( 1 + λ n V o ut ) ) = ( 1 + λ p ( V out – V DD ) ) e ∂ V in ∂ V in V in ⁄ ( nV T ) V in ⁄ ( nV T )

e

( 1 + λ n V out ) ⁄ nV T + e

λn

∂V ou t = ∂ V in
( V D D – V in ) ⁄ ( nV T )

= –e

( V D D – V in ) ⁄ ( nV T )

( 1 + λ p ( V DD – V out ) ) ⁄ nV T – e

λp

∂V out ∂Vin

manipulating this expression we get: (e
V i n ⁄ ( nV T ) ( V DD – V i n ) ⁄ ( nV T )

λp + e

V i n ⁄ ( nV T )

λn )

∂V out = ∂ Vi n ( 1 + λ p ( V DD – V o ut ) ) ⁄ nV T

= e

( 1 + λ n V out ) ⁄ nV T + e

( V DD – V in ) ⁄ ( nV T )

plugging in Vout=Vin=VDD/2 we reach:

204

THE CMOS INVERTER

Chapter 5

–e Finally:

( V DD ⁄ 2 ) ⁄ ( nV T )

( λp + λn )

( V D D ⁄ 2 ) ⁄ ( nV T ) ∂V ou t = e ( 2 + ( λ p + λ n )V DD ⁄ 2 ) ⁄ ( nV T ) ∂ V in

∂V out ∂ V in

Vin = Vout = V D D ⁄ 2

= – ( 2 + ( λp + λ n )V DD ⁄ 2 ) ⁄ ( nV T ) ⁄ ( λ p + λ n )

Using the values VDD=0.4V, V T=26mV, λn=0.06, λp=0.1 and n=1.5 we obtain: g = ∂V out = – 325.6 ∂ Vi n

15.

This value is much more that we would expect from an MOS inverter (which has g~-30). However we should keep in mind that in the subthreshold regime MOS devices behave essentially as bipolar devices and can yield such values of gain. We know that V IL=VM+(VDD-VM)/g and VIH =VM-VM/g from the text (eq 5.7). Using these equations and the results that we got we have: VIL=0.1994V and VIH =0.2006V. Also NMH=NML=0.1994V Sizing a chain of inverters. a. In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with input capacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown in Figure 5.12. Assume that the propagation delay of a minimum size inverter is 70 ps. Also assume that the input capacitance of a gate is proportional to its size. Determine the sizing of the two additional buffer stages that will minimize the propagation delay.
‘1’ is the minimum size inverter.
In
1 ? ?

OUT CL = 20pF

Ci = 10fF

Added Buffer Stage Figure 5.12 Buffer insertion for driving large loads.

Solution Minimum delay occurs when the delay through each buffer is the same. This can be achieved by sizing the buffer as f, f2, respectively where f = N F = 3 2000 = 12.6 , so (γ=0) t p = Nt p0 ( 1 + f ⁄ γ ) = 3 ⋅ 70ps ⋅ ( 1 + 12.6 ) = 2.8ns

b. If you could add any number of stages to achieve the minimum delay, how many stages would you insert? What is the propagation delay in this case? Solution

Section 5.1

Exercises and Design Problems From the text, we know that the minimum delay occurs when f = e. Therefore, ln ( 2000 ) N = --------------------- = 7.6 ln ( f ) ln ( 2000 ) --------------------7

205

f=e

= 2.96

t del ay = 7 × 3.96 × 70ps = 1.9ns c. Describe the advantages and disadvantages of the methods shown in (a) and (b). Solution Solution (b) is faster but it consumes much more area than (a). d. Determine a closed form expression for the power consumption in the circuit. Consider only gate capacitances in your analysis. What is the power consumption for a supply voltage of 2.5V and an activity factor of 1? Solution The power consumption is determined as follows
2 1 P = Ct ot V -- α dd T 3 2 1 C i V d d -- α

T

k=0

16.

[M, None, 3.3.5] Consider scaling a CMOS technology by S > 1. In order to maintain compatibility with existing system components, you decide to use constant voltage scaling. a. In traditional constant voltage scaling, transistor widths scale inversely with S, W∝1/S. To avoid the power increases associated with constant voltage scaling, however, you decide to change the scaling factor for W. What should this new scaling factor be to maintain approximately constant power. Assume long-channel devices (i.e., neglect velocity saturation). Solution I Dsat 1 2 We know that: P ∝ CV DD f and f ∝ --- ∝ ------------- , so t P CV DD W (W) 2 P ∝ I Dsat V ∝ k' ---- ( V – V t ) V ∝ ( s ) --------L 1 -s 1 To keep power constant we need to scale W ∝ --- . which means redesigning gates with 2 s W a factor of 1/s smaller. b. How does delay scale under this new methodology? Solution 1 1 1 ε ---- -- -------WL 2 s s 1⁄s tCV - ------------ ----------------------------------------- ∝ ∝ tp ∝ 2 W W 2 1 ⁄ sk' ---- V k' ---- V s ---------L L 1⁄s
         

   

 

 

∑

P =

f –1 k 2 1 f = C i V dd -- α -----------T f–1

4

1 = 136 -- pWatts T

206

THE CMOS INVERTER

Chapter 5

so tP ∝ 1 ⁄ s 2 .
c. Assuming short-channel devices (i.e., velocity saturation), how would transistor widths have to scale to maintain the constant power requirement? Solution 1 P ∝ I SAT V DD ∝ V DD WC ox ( V gs – V t )υ max ∝ W ( s ) , so W ∝ -- . s This means that no changes need to be made.

DESIGN PROBLEM
Using the 0.25 µm CMOS introduced in Chapter 2, design a static CMOS inverter that meets the following requirements: 1. Matched pull-up and pull-down times (i.e., tpHL = tpLH). 2. tp = 5 nsec (± 0.1 nsec). The load capacitance connected to the output is equal to 4 pF. Notice that this capacitance is substantially larger than the internal capacitances of the gate. Determine the W and L of the transistors. To reduce the parasitics, use minimal lengths (L = 0.25 µm) for all transistors. Verify and optimize the design using SPICE after proposing a first design using manual computations. Compute also the energy consumed per transition. If you have a layout editor (such as MAGIC) available, perform the physical design, extract the real circuit parameters, and compare the simulated results with the ones obtained earlier.

1

Chapter 6 Problem Set

Chapter 6 PROBLEMS
1. [E, None, 4.2] Implement the equation X = ((A + B) (C + D + E) + F) G using complementary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance? Solution Rewriting the output expression in the form X = ((A + B) (C + D + E) + F) G = ((AB + CDE)F) + G allows us to build the pulldown network by inspection (parallel devices implement an OR, and series devices implement an AND). The pullup network is the dual of the pulldown network.

A C

24 24 D G

B 24 E 12

24 24

F

12

X A B 8 8 C D E F 4 12 12 12 G 2

2.

The plot shows sizes that meet the requirement - in the worst case, the output resistance of the circuit matches the output resistance of an inverter with NMOS W/L=2 and PMOS W/L=6. The worst case pull-up resistance occurs whenever a single path exists from the output node to Vdd. Examples of vectors for the worst case are ABCDEFG=1111100 and 0101110. The best case pull-up resistance occurs when ABCDEFG=0000000. The worst case pull-down resistance occurs whenever a single path exists from the output node to GND. Examples of vectors for the worst case are ABCDEFG=0000001 and 0011110. The best case pull-down resistance occurs when ABCDEFG=1111111. Implement the following expression in a full static CMOS logic fashion using no more than 10 transistors: Y = (A ⋅ B) + (A ⋅ C ⋅ E) + (D ⋅ E) + (D ⋅ C ⋅ B) Solution

2 The circuit is given in the next figure.
VDD A C B

Chapter 6 Problem Set

D

E Y

A

C

D

B

E

3.

Consider the circuit of Figure 6.1.
VDD B

W/L=16
Cx1

W/L=8
D

W/L=8
C A

W/L=16
Y

B

W/L=12
C

A

W/L=12
Cx2

W/L=12 W/L=12
Cx3

D

Figure 6.1 CMOS combinational logic gate.

a. What is the logic function implemented by the CMOS transistor network? Size the NMOS and PMOS devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 4 and PMOS W/L = 8. Solution The logic function is : Y = ( A + B )CD . The transistor sizes are given in the figure above. b. What are the input patterns that give the worst case tpHL and tpLH. State clearly what are the initial input patterns and which input(s) has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes. Solution The worst case tpHL happens when the internal node capacitances (Cx2 and Cx3) are charged before the high to low transition. The initial states that can cause this are: ABCD=[1010, 1110, 0110]. The final state is one of: ABCD=[1011, 0111].

Digital Integrated Circuits - 2nd Ed

3

The worst case tpLH happens when Cx1 is charged before the low to high transition. The input pattern that can cause this is: ABCD=[0111] =>[0011]. c. Verify part (b) with SPICE. Assume all transistors have minimum gate length (0.25µm). Solution The two cases are shown below.

Figure 6.2 Best and worst tpHL.

Figure 6.3 Best and worst tpLH.

d. If P(A=1)=0.5, P(B=1)=0.2, P(C=1)=0.3 and P(D=1)=1, determine the power dissipation in the logic gate. Assume VDD=2.5V, Cout=30fF and fclk=250MHz. Solution Since D is always 1, the circuit implements the following function Y = ( A + B )C . P(A+B)=1 = PA=0.PB = 0 = 0.5*(1-0.2) = 0.4, P(A+B)=0 = 1 - 0.4 = 0.6, PY = 0 = P(A+B) = 1.PC = 1 = 0.6*0.3 = 0.18 PY = 1 = 1 - 0.18 = 0.82 PY = 0 =>1= 0.18*0.82 = 0.1476 So Pdyn = PY = 0 =>1CoutVDD2fclk = (0.1476)(30.10-15)(2.52)(250.106) = 6.92 µ W. 4. [M, None, 4.2] CMOS Logic a. Do the following two circuits (Figure 6.4) implement the same logic function? If yes, what is that logic function? If no, give Boolean expressions for both circuits.

4

Chapter 6 Problem Set Solution Yes, they implement the same logic function : F = (ABCD + E) = (A + B + C + D).E b. Will these two circuits’ output resistances always be equal to each other? Solution No c. Will these two circuits’ rise and fall times always be equal to each other? Why or why not? Solution No. Circuit B appears optimized for the case where the transistor with input E is on the critical path since it is closer to the output node than in circuit A. Therefore, if input E arrives later, circuit B will be faster than circuit A since the internal node will already be charged and only the output capacitance needs to be switched. Even if we assume, all inputs arrive at the same time, however, the two circuits rise and fall times will not be equal to each other. Consider an input combination where E,A,B,C,D are all low. Circuit A has only one bodyaffected device while circuit B has four. Since the associated rise in Vt and fall in output resistance affects only one resistor in circuit A, but four parallel resistors in circuit B, we expect a difference in the timing waveforms.
VDD E 6 A A 6 B 6 C 6 D 6 E F A B C D 4 4 4 4 E 1 A B C D 4 4 4 4 E 1 Figure 6.4 Two static CMOS gates. 6 F 6 B 6 C 6 D 6 VDD

Circuit A

Circuit B

5.

[E, None, 4.2] The transistors in the circuits of the preceding problem have been sized to give an output resistance of 13 kΩ for the worst-case input pattern. This output resistance can vary, however, if other patterns are applied. a. What input patterns (A–E) give the lowest output resistance when the output is low? What is the value of that resistance? Solution The lowest output resistance is obtained when all inputs (A, B, C, D and E) are equal to 1. In that case, the output resistance is the parallel of the resistance of a nMOS of width 1, with a series of four equal nMOS of width 4. Both combinations have the same resistance, equal to the worst-case output resistance, 13 k Ω . Then the output resistance, in this case, is half this value, 6.5 k Ω . b. What input patterns (A–E) give the lowest output resistance when the output is high? What is the value of that resistance?

Digital Integrated Circuits - 2nd Ed

5

6.

Solution The lowest output resistance is obtained when all inputs are equal to zero. Each of the pMOS have the same width, so all of them have the same resistance. The worst case resistance happens when only one of the inputs (A, B, C or D) is equal to 0 while all the rest are equal to 1. The output resistance in that case is the series of the resistance of two of the pMOS and it is equal to 13 k Ω . Then, each of the pMOS has an output resistance equal to 6.5 k Ω . The output resistance is equal to the series of one of these resistance with the parallel of four of the same resistnaces. Then, the minimum output resistance is 6.5 k Ω + 6.5 k Ω /4 = 8.125 k Ω . [E, None, 4.2] What is the logic function of circuits A and B in Figure 6.5? Which one is a dual network and which one is not? Is the nondual network still a valid static logic gate? Explain. List any advantages of one configuration over the other.
VDD A B B A B A F B A Circuit A A B B A VDD B A F B A Circuit B Figure 6.5 Two logic functions.

7.

Solution Both circuits A and B implement the XOR logic function. Circuit A is a dual network because the pull up network is dual with the pull down network. However, circuit B is still a valid static logic gate, because for any combination of the inputs, there is either a low resistance path from VDD or ground to the output. Circuit B has an extra advantage. The internal node capacitances are less compared to Circuit A, which make it faster than Circuit A. [E, None, 4.2] Compute the following for the pseudo-NMOS inverter shown in Figure 6.6: a. VOL and VOH Solution To find VOH, set Vin to 0, because VOL is likely to be below VT0 for the NMOS. If Vin=0, then M1 is off, so the PMOS pulls the output all the way to the rail. So, VOH=VDD=2.5V. To find VOL, set Vin = VOH = 2.5V. The NMOS is all the way on, but so is the PMOS. To find VOL, we can write a current balancing equation at the output node: IDP+IDN=0. First, we must determine the region of operation for each device. We can assume that VDS = VOL for the NMOS is less than VDSAT, so the NMOS is in the linear region. V DS for the PMOS will be more negative than VDSAT, and VGTp = -2.1, so the PMOS is velocity saturated. The equation is therefore: k' p ⋅ W ⋅ V DSAT ⋅ ( VGT – 0.5V DSAT ) ⋅ ( 1 + λVDS ) + k' n ⋅ W ⋅ V o ⋅ ( V GT – 0.5Vo ) ⋅ ( 1 + λV o ) = 0 ------L L

Plugging in numbers (process parameters such as VDSAT appear in tables in previous chapters) gives:

6

Chapter 6 Problem Set
– 30 ⋅ 2 ⋅ – 1 ⋅ ( – 1.6 ) ⋅ ( 1 – 0.1 ( V o – 2.5 ) ) + 115 ( 16 ) ⋅ V o ⋅ ( 2.07 – 0.5V o ) ⋅ ( 1 + 0.06V o ) = 0

Solving for Vo gives VOL = 31.6mV. b. NML and NMH Solution Rather than calculating the derivative of the current, we will estimate V IL and V IH from the simulated VTC. This approach estimates that the noise margin low is about 0.47Vand the noise margin high is about 1.67V. c. The power dissipation: (1) for Vin low, and (2) for Vin high Solution For Vin low, the NMOS is off, so the power dissipation is 0W. For Vin high, P=VI=2.5*IDP. We saw in part a) the equation for IDP. Plugging in the value for VOL, we get P=VI=2.5*120 µ A=300 µ W. d. For an output load of 1 pF, calculate tpLH, tpHL, and tp. Are the rising and falling delays equal? Why or why not?
2.5 V PMOS

M2 W/L = 0.5µm/0.25µm

Vout Vin M1 W/L = 4µm/0.25µm NMOS

Figure 6.6 Pseudo-NMOS inverter.

8.

Solution We cannot use the estimate of resistance from the I-V curve for the HL transition because the PMOS is still on. Therefore, we will use the average current method for estimating delay. The average current for the HL transition through the PMOS is 0.5(IVDD=2.5 + IVDD=1.25). IVDD=2.5 = 0. IVDD=1.25 = -30(2)(-1)(-2.1+0.5) *(1+0.1(1.25)) = 108uA. Thus, Iavg for the PMOS is 54uA. For the NMOS, IVDD=2.5 = 115(16)(0.63)(2.07-.63/2)(1+0.06*2.5)=2.4mA and IVDD=1.25 = 115 (16) (0.63) *(2.07-.63/2)(1+0.06*1.25) = 2.2mA. So, Iavg for the NMOS is 2.3mA. The average current discharging the capacitor is then 2.3mA-54uA = 2.25mA. Then tpHL = C*delV/Iavg = 556ps. For tpLH, the NMOS is off, so we can use equivalent resistance to find the transistion time. From the table of resistances in the text, we can calculate REQ = 31k Ω /(W/Lp) = 15.5k Ω . Then tpLH = 0.69*C*REQ. So tpLH = 10.7ns. tp = (tpLH + tpHL)/2 = 5.6ns. The rising delay is much longer because the PMOS is very weak relative to the NMOS. [M, SPICE, 4.2] Consider the circuit of Figure 6.7. a. What is the output voltage if only one input is high? If all four inputs are high? Solution

Digital Integrated Circuits - 2nd Ed
2  V W  min  ⋅ ( 1 + λ ⋅ V ) I = k′ ⋅ ---- ⋅ V ⋅V – ---------------- D DS L  GT min 2  

7

Consider a case when one input is high: A = VDD and B = C = D = 0 V. Assume that Vout is small enough that Vmin = VDSAT for the PMOS device, and Vmin = VDS = Vout for the NMOS devices. Solve for Vout by setting the drain currents in the PMOS and NMOS equal to each other, |IDP| = |IDN|, where the drain currents are functions of Vout, VDD, and the device parameters. Vout = 102 mV, and ID = 35.7 µA. Now verify that the assumptions for Vmin are correct. For the PMOS: VDS = -2.34 V, VDSAT = -1 V, VGT = -2.1 V, therefore Vmin = VDSAT. For the NMOS: VDS = 102mV, VDSAT = 630mV, VGT = 2.07 V, therefore Vmin = VDS. Consider the case when all inputs are high: A = B = C = D = VDD. For these hand calculations, this is numerically equivalent to a circuit with a single NMOS device with W/L = 4*1.5 and its gate tied to VDD. Now, the analysis used above for the case when one device is on can be reused, replacing W/L of the NMOS with 6, and using the same assumptions for Vmin. Vout = 25 mV, and ID = 35.9 µA. The assumptions for Vmin are correct. b. What is the average static power consumption if, at any time, each input turns on with an (independent) probability of 0.5? 0.1? Solution Notice in part a) that the drain current in the PMOS is 35.7 µA with one NMOS on and 35.9 µA with four NMOS devices on. The current in the PMOS can be approximated as 35.8 µA when any number of NMOS devices are on and 0 µA when all four are off. The probability that all four NMOS devices are off is (1−ρ)4 where ρ is the probability an input is high. Therefore,
4 4 P AVG = P OFF ⋅ ( 1 – ρ ) + P ON ⋅ 1 – ( 1 – ρ )

where POFF = 0 W, and PON = 89.5 µW. PAVG = 83.9 µW when ρ = 0.5 and PAVG = 30.7 µW when ρ = 0.5. c. Compare your analytically obtained results to a SPICE simulation. Solution From SPICE: Vout = 98.7 mV, and ID = 38.2 µA with one NMOS device on and Vout = 23.5 mV, and ID = 38.3 µA with all NMOS devices on.
VDD (W/L) = 0.6 F A B C D (W/L) = 1.5 Figure 6.7 Pseudo-NMOS gate.

9.

[M, None, 4.2] Implement F = ABC + ACD (and F) in DCVSL. Assume A, B, C, D, and their complements are available as inputs. Use the minimum number of transistors.

8 Solution
VDD

Chapter 6 Problem Set

F A B C A C D B A

F A C C C D

10.

[E, Layout, 4.2] A complex logic gate is shown in Figure 6.8. a. Write the Boolean equations for outputs F and G. What function does this circuit implement? Solution G=A(XOR)B F=A(XNOR)B b. What logic family does this circuit belong to? Solution It belongs to the DCVSL logic family. c. Assuming W/L = 0.5u/0.25u for all nmos transistors and W/L = 2u/0.25u for the pmos transistors, produce a layout of the gate using Magic. Your layout should conform to the following datapath style: (1) Inputs should enter the layout from the left in polysilicon; (2) The outputs should exit the layout at the right in polysilicon (since the outputs would probably be driving transistor gate inputs of the next cell to the right); (3) Power and ground lines should run vertically in metal 1.
VDD

F

G

A B

A

A B

A

Figure 6.8 Two-input complex logic gate.

d. Extract and netlist the layout. Load both outputs (F,G) with a 30fF capacitance and simulate the circuit. Does the gate function properly? If not, explain why and resize the transistors so that it does. Change the sizes (and areas and perimeters) in the HSPICE netlist. Solution The gate doesn’t function properly, because the PMOS devices are strong and the NMOS pull down network can not switch the output nodes .

Digital Integrated Circuits - 2nd Ed

9

11.

If you decrease the PMOS sizes to W=0.5um, then the logic gate will function properly. Design and simulate a circuit that generates an optimal differential signal as shown in Figure 6.9. Make sure the rise and fall times are equal.
A Y Y Y Y 50% of VDD A Y Y 0 0 1 1 1 0

Figure 6.9 Differential Buffer.

Solution The circuit is shown below.

A Y A

A

A Y

A

A

A

A

12.

If the inverters are sized for equal rise and fall times then you can achieve equal rise and fall times on the differential outputs, as long as the other FETs are sized symmetrically. What is the function of the circuit in Figure 6.10?
A Y B Y

Figure 6.10 Gate.

13.

Solution The circuit implements an S-R latch. Set is A and Reset is B. The invalid state is when both A and B are 0. Implement the function S = ABC + ABC + ABC + ABC, which gives the sum of two inputs with a carry bit, using NMOS pass transistor logic. Design a DCVSL gate which implements the same function. Assume A, B, C, and their complements are available as inputs. Solution

10 The two cases are shown in the figure below.
B A A A A Pass Gate Implementation VDD B C C

Chapter 6 Problem Set

S

S A A A

S A

B

B B

B B

B B

B

C

C

DCVSL Implementation

14.

Describe the logic function computed by the circuit in Figure 6.11. Note that all transistors (except for the middle inverters) are NMOS. Size and simulate the circuit so that it achieves a 100 ps delay (50-50) using 0.25µm devices, while driving a 100 fF load on both differential outputs. (VDD = 2.5V). Assume A, B and their complements are available as inputs.
Y A Y

M1 M2 M3 M4

A

M1 M2 M3 M4

M1 M2 M3 M4

A

M1 M2 M3 M4

A

B

B

B

B

A

A

A

A

B

B

B

B

Figure 6.11 Cascoded Logic Styles.

Digital Integrated Circuits - 2nd Ed

11

For the drain and source perimeters and areas you can use the following approximations: AS=AD=W*0.625u and PS=PD=W+1.25u. 15. Solution The circuit implements an XOR. The sizes of the transistors are M1: 28u/0.25u, M2: 28u/0.25u, M3: 10u/0.25u, M4: 10u/0.25u. MPinv: 4u/0.25, MNinv: 0.375u/10u [M, None. 4.2] Figure 6.12 contains a pass-gate logic network. a. Determine the truth table for the circuit. What logic function does it implement? Solution The truth table is shown below AB 00 01 10 11 Out 1 0 0 1

16.

The circuit implements an XNOR. b. Assuming 0 and 2.5 V inputs, size the PMOS transistor to achieve a VOL = 0.3 V. Solution The PMOS device will be velocity saturated and the NMOS passgate will be in the linear region. IDN+IDP=0, so k' p ⋅ W ⋅ V DSAT ⋅ ( V GT – 0.5V DSAT ) ⋅ ( 1 + λVDS ) + k' n ⋅ W ⋅ Vo ⋅ ( VGT – 0.5V o ) ⋅ ( 1 + λV o ) = 0 ------L L

We know that Vo=0.3V, so we can plug in numbers and solve for W/L for the PMOS is 7. Let the PMOS be 1.75/0.25. c. If the PMOS were removed, would the circuit still function correctly? Does the PMOS transistor serve any useful purpose?
A

1.5/.25

Out

B

Figure 6.12 Pass-gate network.

17.

Solution No. If the PMOS were removed, the output node could remain low when AB=00 because it would be floating. The PMOS device pulls the output node high when it would otherwise be in a high impedence state. [M, None, 4.2] This problem considers the effects of process scaling on pass-gate logic.

12

Chapter 6 Problem Set a. If a process has a tbuf of 0.4 ns, Req of 8 kΩ, and C of 12 fF, what is the optimal number of stages between buffers in a pass-gate chain? Solution m opt = 1.7 t p ⁄ ( R eq ⋅ C ) = 3.47 ≈ 3 gates between buffers. b. Suppose that, if the dimension of this process are shrunk by a factor S, Req scales as 1/S2, C scales as 1/S, and tbuf scales as 1/S2. What is the expression for the optimal number of buffers as a function of S? What is this value if S = 2? 2 Solution tp ⁄ S S ⋅ tp m opt = 1.7 -------------------------------- = 1.7 ---------------- = 4.9 ≈ 5 gates between buffers. -

R eq ⁄ S ⋅ C ⁄ S

2

R eq ⋅ C

18.

[C, None, 4.2] Consider the circuit of Figure 6.13. Let Cx = 50 fF, Mr has W/L = 0.375/0.375, Mn has W/Leff = 0.375/0.25. Assume the output inverter doesn’t switch until its input equals VDD/2. a. How long will it take Mn to pull down node x from 2.5 V to 1.25 V if In is at 0 V and B is at 2.5V? Solution To determine the time required for these transitions, we will find the average currents in the FETs Mr and Mn. The equivalent resistance method will not suffice since it does not account for both devices being on. For Mr, IVDD=2.5 = 0 since VDS = 0. For the other case, the PMOS device is velocity saturated, so: IVDD=1.25 = (-30)(1)(-1)(-2.1+0.5)(1+0.1*1.25) = -54uA. The average current in the PMOS is -27uA. Mn is in the velocity saturation region for both endpoints of the transition. The two currents are therefore: IVDD=2.5 = (115)(1.5)(0.63)(2.07-0.63/2)(1+0.06*2.5) = 219uA. IVDD=1.25 = (115)(1.5)(0.63)(2.07-0.63/2)(1+0.06*2.5) = 205uA. And the average current in the NMOS is 212uA. The total current DISCHARGING the capacitor is 211uA - 27uA = 185uA. The time for the transition is then t = C ⋅ ∆V = 50fF ⋅ 1.25V = 338ps . --------------------------------------------I avg 185µA b. How long will it take Mn to pull up node x from 0 V to 1.25 V if VIn is 2.5 V and VB is 2.5 V? Solution For the LH transition, the PMOS “keeper” is off. The NMOS Mn is the only FET that is on for this transition. We present both methods for finding the pull-up time. Equivalent Resistance: We need to perform a different sweep for this measurement than the regular ID vs VDS sweep. In this case, V DS is changing because the source node of the FET is rising. Since the source voltage is changing, VGS also is reducing as node x rises. This effectively “turns down” the current the NMOS can sustain. Performing the appropriate sweep and measuring REQ gives REQ = (11.3k Ω + 34.7k Ω ) / 2 = 23k Ω . Thus, t = 0.69*C*REQ = 0.69*50fF*23k Ω = 794ps. Average Current: When x = 0, the pass transistor has a VGS = 2.5 and a VDS = 2.5, so it is velocity saturated. Ix=0 = (115)(1.5)(0.63)(2.07-0.63/2)(1+0.06*2.5) = 219uA.

Digital Integrated Circuits - 2nd Ed

13

When x = 1.25, the pass transistor has VDS = 1.25 and VGS = 1.25. It is still velocity saturated, but notice that VGS has decreased. Thus, Ix=1.25 = (115)(1.5)(0.63)(1.25-0.43-0.63/2)(1+0.06*1.25) = 59uA. The average current is then Iavg = 139uA. C ⋅ ∆V 50fF ⋅ 1.25V t = --------------- = ------------------------------- = 450ps . I avg 139µA Clearly, the two solutions are not very close together. The actual simulated transition time is about 644ps. The Iavg approximation underestimates the solution because the true average current in this case is not close to the average of the endpoints. In a typical inverter (PMOS pullup and NMOS pulldown), VGS doesn’t change over the transition, so the current is reasonably linear with VDS. For that case, the average current is close to the average of the endpoints. In this problem, the pinch-off of VGS-VT in the pass transistor means the average is closer to the smaller value. Numerical calculation of the average current from an HSPICE sim gives Iavg = 93uA which would give a transition time of t = 672ps, which is much closer to the actual value. c. What is the minimum value of VB necessary to pull down Vx to 1.25 V when VIn = 0 V? Solution In order for Mn to pull node x low, the current in Mr must equal or exceed the current that charges up the capacitor at every point in the transition. The maximum current in Mr occurs when x = 1.25 V, and it is (from part a) IMr = -54uA. We can write a current equation for Mn at this point in the transition and solve for VB: Note that Mn is velocity saturated at this point: 54 = 115(1.5)(0.63)(VB-0.430.63/2)(1+0.06*1.25). Solving gives VB = 1.207V.
VDD VDD Mr B M2 In Mn x M1 Figure 6.13 Level restorer. Out

14 19. Pass Transistor Logic pass transistor network
B M2 A Mn1 B Mn2 x M1 Out VDD

Chapter 6 Problem Set

VDD = 2.5V (W/L)2 = 1.5um/0.25um (W/L)1 = 0.5um/0.25um (W/L)ni = 0.5um/0.25um kn’ = 115uA/V2, kp’ = -30uA/V2 VtN = 0.43V, VtP = -0.4V
Figure 6.14 Level restoring circuit.

Consider the circuit of Figure 6.14. Assume the inverter switches ideally at VDD/2, neglect body effect, channel length modulation and all parasitic capacitance throughout this problem. a. What is the logic function performed by this circuit? Solution The circuit is a NAND gate. b. Explain why this circuit has non-zero static dissipation. Solution When A=B= VDD, the voltage at node x is VX=VDD-VtN. This causes static power dissipation at the inverter the pass transistor network is driving. c. Using only just 1 transistor, design a fix so that there will not be any static power dissipation. Explain how you chose the size of the transistor. Solution The modified circuit is shown in the next figure.
VDD VDD Mr B M2 A Mn1 B Mn2 x M1 Out

The size of Mr should be chosen so that when one of the inputs A or B equals 0, either Mn1 or Mn2, would be able to pull node X to VDD/2 or less. d. Implement the same circuit using transmission gates. Solution

Digital Integrated Circuits - 2nd Ed The circuit is shown below.
B Out

15

A

B

e. Replace the pass-transistor network in Figure 6.14 with a pass transistor network that computes the following function: x = ABC at the node x. Assume you have the true and complementary versions of the three inputs A,B and C. Solution One possible implementation is shown.

B A

C

C C B B

ABC

20.

21.

[M, None, 4.3] Sketch the waveforms at x, y, and z for the given inputs (Figure 6.15). You may approximate the time scale, but be sure to compute the voltage levels. Assume that VT = 0.5 V when body effect is a factor. [E, None, 4.3] Consider the circuit of Figure 6.16. a. Give the logic function of x and y in terms of A, B, and C. Sketch the waveforms at x and y for the given inputs. Do x and y evaluate to the values you expected from their logic functions? Explain. Solution x = AB and y = ABC The circuit does not correctly implement the desired logic function. This stems from the fact that x is pre-charged high, and thus node y is discharged as soon as the evaluation phase starts. Although x is eventually discharged by the first stage, y cannot be charged high again since it is a dynamic node with no low-impedance path to Vdd (during evaluate). Common solutions to this problem areto either place an inverter between the two stages (thus allowing only 0-to-1 transitions on the inputs to each stage during evaluate) as in Domino logic or employing np-CMOS. The latter is presented in (b). b. Redesign the gates using np-CMOS to eliminate any race conditions. Sketch the waveforms at x and y for your new circuit. Solution

16

Chapter 6 Problem Set

2.5 V φ 0V 2.5 V A 0V 2.5 V B 0V A B φ φ

VDD Mp x Ma y Mb z Mn Cb = 10 fF Ca = 10 fF CL = 100 fF

2.5V x 0V 2.0V y 0V

Figure 6.15 Dynamic CMOS.

1.5V z 0V

22.

The modified circuit using np-CMOS is shown below together with the waveforms at x and y. The desired logic function is now correctly implemented [M, None, 4.3] Suppose we wish to implement the two logic functions given by F = A + B + C and G = A + B + C + D. Assume both true and complementary signals are available. a. Implement these functions in dynamic CMOS as cascaded φ stages so as to minimize the total transistor count. Solution Dynamic gates with NMOS pull-down networks cannot be directly cascaded. This solution uses a domino logic approach.

clk A B clk C F

clk G D clk

b. Design an np-CMOS implementation of the same logic functions. Solution

Digital Integrated Circuits - 2nd Ed
VDD φ A B φ x φ φ y C

17

2.5 V φ 0V 2.5 V A 2.5 V B C 0V (a) 2.5 V 0V 2.5 V 0V φ (b) np-CMOS A 2.5 V 0V 2.5 V 0V x B φ y

x

Figure 6.16 Cascaded dynamic gates.

VDD φ x

C φ y

y

The circuit is shown below

clk A B clk C F

clk D G clk

23. Consider a conventional 4-stage Domino logic circuit as shown in Figure 6.17 in which all precharge and evaluate devices are clocked using a common clock φ. For this entire problem, assume that the pulldown network is simply a single NMOS device, so that each Domino stage consists of a dynamic inverter followed by a static inverter. Assume that the precharge

18

Chapter 6 Problem Set time, evaluate time, and propagation delay of the static inverter are all T/2. Assume that the transitions are ideal (zero rise/fall times). φ φ φ φ

IN

Pulldown Network

Out1

Pulldown Network

Out2

Pulldown Network

Out3

Pulldown Network

Out4

φ

φ

φ

φ

Figure 6.17 Conventional DOMINO Dynamic Logic.

a. Complete the timing diagram for signals Out1, Out2, Out3 and Out4, when the IN signal goes high before the rising edge of the clock φ. Assume that the clock period is 10 T time units. Solution The timing diagram is shown below.
0 T 2T 3T 4T 5T 6T 7T 8T 9T 10T

CLK IN OUT1 OUT2 OUT3 OUT4

b. Suppose that there are no evaluate switches at the 3 latter stages. Assume that the clock φ is initially in the precharge state (φ=0 with all nodes settled to the correct precharge states), and the block enters the evaluate period (φ=1). Is there a problem during the evaluate period, or is there a benefit? Explain. Solution There is no problem during the evaluate stage. The precharged nodes remain charged until a signal propogates through the logic, activating the pull-down network and discharging the node. In fact, this topology improves the circuit’s robustness in terms of charge sharing affecting the output for any generic pull-down network, and reduces the body effect in the pull-down network. c. Assume that the clock φ is initially in the evaluate state (φ=1), and the block enters the precharge state (φ = 0). Is there a problem, or is there any benefit, if the last three evaluate switches are removed? Explain. Solution There is a problem during the precharge stage. If all precharged nodes are discharged during the evaluate stage, when the precharge FETs simultaneously turn on, the pull-down

Digital Integrated Circuits - 2nd Ed

19

24.

networks will initially remain on, creating a short circuit. This continues in each gate until the previous gate charges, disabling its pull-down network. [C, Spice, 4.3] Figure 6.18 shows a dynamic CMOS circuit in Domino logic. In determining source and drain areas and perimeters, you may use the following approximations: AD = AS = W × 0.625µm and PD = PS = W + 1.25µm. Assume 0.1 ns rise/fall times for all inputs, including the clock. Furthermore, you may assume that all the inputs and their complements are available, and that all inputs change during the precharge phase of the clock cycle. a. What Boolean functions are implemented at outputs F and G? If A and B are interpreted as two-bit binary words, A = A1A0 and B = B1B0, then what interpretation can be applied to output G? Solution F = A0B0 + A1B1, G = F(A0B0 + A1B1)

If A and B are interpreted as two-bit binary words, output G is high if A = B: a comparator
b. Which gate (1 or 2) has the highest potential for harmful charge sharing and why? What sequence of inputs (spanning two clock cycles) results in the worst-case charge-sharing scenario? Using SPICE, determine the extent to which charge sharing affects the circuit for this worst case.
2.5 V φ 2/0.25 1/0.25 B0 φ 1/0.25 2/0.25 A0 B0 2.5 V 1/0.25 F φ 2.5 V 2/0.25 1/0.25 A1 B1 φ GATE 1 Figure 6.18 DOMINO logic circuit. 2/0.25 2/0.25 2/0.25 GATE 2 A1 B1 2.5 V 1/0.25 0.5/0.25 G CL

0.5/0.25

Solution Gate 2 has the higher potential for harmful charge sharing because the capacitance that contributes to charge sharing is larger than in gate 1. The sequence of inputs resulting in the worst-case charge sharing is A 0 = B 0 and A 1 = B 1 for the first cycle. Then A 0 = B 0 and A 1 ≠ B 1 for the second cycle such that A1/A1 transistor that is on during the second cycle is the same as in the first cycle. For example, A0 = B0 = A1 = B1 = VDD in cycle 1 and A0 = B0 = A1 = VDD, B1 = 0 V in cycle 2. This

20

Chapter 6 Problem Set will cause the charge at the output of gate 2 to be shared with the total parasitic capacitance at the drains of the A1, A1, and B1 transistors.

25.

[M, Spice, 4.3] In this problem you will consider methods for eliminating charge sharing in the circuit of Figure 6.18. You will then determine the performance of the resulting circuit. a. In problem 24 you determined which gate (1 or 2) suffers the most from charge sharing. Add a single 2/0.25 PMOS precharge transistor (with its gate driven by the clock φ and its source connected to VDD) to one of the nodes in that gate to maximally reduce the chargesharing effect. What effect (if any) will this addition have on the gate delay? Use SPICE to demonstrate that the additional transistor has eliminated charge sharing for the previously determined worst-case sequence of inputs. Solution The additional precharge transistor should charge the node that is shared by the A1 and A1 transistor drains and the F transistor source. Assuming the gate delay is dominated by the precharge stage, this will reduce the gate delay by briefly aiding the precharging of gate 2. SPICE output with additional precharge transistor.

Digital Integrated Circuits - 2nd Ed

21

b. For the new circuit (including additional precharge transistor), find the sequence of inputs (spanning two clock cycles) that results in the worst-case delay through the circuit. Remember that precharging is another factor that limits the maximum clocking frequency of the circuit, so your input sequence should address the worst-case precharging delay. Solution The worst-case delay results from A = B for two consecutive cycles. This results in the maximum charging and discharging of the internal nodes c. Using SPICE on the new circuit and applying the sequence of inputs found in part (b), find the maximum clock frequency for correct operation of the circuit. Remember that the precharge cycle must be long enough to allow all precharged nodes to reach ~90% of their final values before evaluation begins. Also, recall that the inputs (A, B and their complements) should not begin changing until the clock signal has reached 0 V (precharge phase), and they should reach their final values before the circuit enters the evaluation phase. Solution The maximum clock frequency is ~4.4 GHz.

26.

[C, None, 4.2–3] For this problem, refer to the layout of Figure 6.19. a. Draw the schematic corresponding to the layout. Include transistor sizes. Solution

0.5/0.5 Out B A 1/0.25 C 1.5/0.25 1.5/0.25

22

Chapter 6 Problem Set b. What logic function does the circuit implement? To which logic family does the circuit belong? Solution The circuit implements Out = A+BC. It is in the pseudo NMOS family. c. Does the circuit have any advantages over fully complementary CMOS? Solution The circuit uses less area than a fully complementary CMOS implementation. d. Calculate the worst-case VOL and VOH. Solution VOH = VDD = 2.5V. To find VOL, assume that we can combine MB and MC into one NMOS with W/L = 0.75/0.25. Then the worst case VOL occurs when A=0 and the combined BC NMOS is on. Assume that VOL is less than VDSATn. Then the NMOS device is in the linear region. The PMOS device will be velocity saturated. Equating the currents at the output gives:
W W k' p ⋅ ---- ⋅ V DSAT ⋅ ( V GT – 0.5V DSAT ) ⋅ ( 1 + λV DS ) + k' n ⋅ ---- ⋅ V o ⋅ ( V GT – 0.5V o ) ⋅ ( 1 + λV o ) = 0 L L

The only unknown in this 3rd order polynomial is Vo. Solving for Vo gives VOL= 51.2mV e. Write the expresions for the area and perimeter of the drain and source for all of the FETs in terms of λ . Assume that the capacitance of shared diffuusions divides evenly between the sharing devices. Copy the layout into Magic, extract and simulate to find the worstcase tpHL time. For what input transition(s) does this occur? Name all of the parasitic capacitances that you would need to know to calculate this delay by habd (you do not need to perform the calculation).

Figure 6.19 Layout of complex gate.

Solution Call the PMOS device P, and name the other devices by their input signal. ADP = ASP = 19 λ 2. PDP = PSP = 15 λ . ASA = 40 λ 2. PSA = 18 λ .

Digital Integrated Circuits - 2nd Ed

23

27.

ADA = (3x8 + 3x12) λ 2 / 2 = 30 λ 2. PDA = 16 λ /2 = 8 λ . ADB= ADA. PDB = PDA. ASB = 36 λ 2/2 = 18 λ 2. PSB = 6 λ /2 = 3 λ . ADC = ASB. PDC = PSC. ASC = 60 λ 2. PSC = 22 λ . We can narrow the number of transitions to look at for determining the worst case tpHL. The worst case capacitance occurs when the internal node between MB and MC is charged up to VDD. Then the worst case delay will occur when either MA or the MB, MC pair discharges this capacitance. If the series devices are doing the discharging, we need to consider the case where MB is initially on and where MB is initially off. The simulation shows that the worst-case transition occurs over three cycles: ABC = 010 to 000 to 011 produces the worst-case tpHL. This is worse than when MA discharges the node (ABC = 010 to 110) or when MB is initially on (ABC = 010 to 011). We could calculate tpHL using either the equivalent resistance method or the average current method. In either case, CL would include the following parasitic capacitances: CGDPMOS + CDBPMOS + CGDA(no Miller effect b/c input not changing) + CDBA + CGDB + CDBB + CGSB + CGDC + CDBC. [E, None, 4.4] Derive the truth table, state transition graph, and output transition probabilities for a three-input XOR gate with independent, identically distributed, uniform white-noise inputs. Solution The truth table of a three-input XOR gate is: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 0 1 1 0 1 0 0 1

Table 1: Truth table As the inputs are independent, identically distribute, uniform white noise, each of the possible combinations of three input values, has a probability equal to 1/8. From the table, the probabiliy of having the output equal to 0 is p 0 = 0.5 . In the same way [C, None, 4.4] Figure 6.20 shows a two-input multiplexer. For this problem, assume independent, identically-distributed uniform white noise inputs. a. Does this schematic contain reconvergent fan-out? Explain your answer. Solution

28.

24

Chapter 6 Problem Set This schematic has reconvergent fan-out because both inputs of the or gate depend on the value of S. b. Find the exact signal (P1) and transition (P0 → 1) formulas for nodes X, Y, and Z for: (1) a static, fully complementary CMOS implementation, and (2) a dynamic CMOS implementation.
A S C Z C Y B C Figure 6.20 Two-input multiplexer X

29.

Solution Assuming a fully complementary CMOS implementation: X is the output of an AND gate with independent, identically-distributed uniform white noise inputs. As only when both inputs are equal to 1 the output is 1, P 1 = 0.25 . On the other hand P 0 → 1 = P 0 P 1 = 0.25 ( 1 – 0.25 ) = 0.1875 . Y is also the output of an AND gate with independent, identically distributed uniform white noise inputs. The analysis is the same as with X. If we represent the truth table of the schematic we will see that P 1 = 0.5 . Then P 0 → 1 = P 0 P 1 = 0.5 ( 1 – 0.5 ) = 0.25 . Assuming a dynamic CMOS implementation: In the same way as before, for X, P 1 = 0.25 . In order to obtain the transition probability, an n-tree dynamic gate will be assumed. In this case: P 0 → 1 = P 0 = 0.75 . The analisys for Y is equal to the analysis for X. For Z, using the truth table of the schematic we obtain, again , P 1 = 0.5 . For the transition probability, it will be assumed that a np-CMOS structure is used.. Then, Z is the P 0 → 1 = P 1 = 0.5 . output of a p-tree dynamic gate. Then: [M, None, 4.4] Compute the switching power consumed by the multiplexer of Figure 6.20, assuming that all significant capacitances have been lumped into the three capacitors shown in the figure, where C = 0.3 pF. Assume that VDD = 2.5 V and independent, identically-distributed uniform white noise inputs, with events occuring at a frequency of 100 MHz. Perform this calculation for the following: a. A static, fully-complementary CMOS implementation Solution Switching power is:
P SW = α ⋅ f ⋅ C ⋅ V DD 2 = ( α X0 → 1 + α Y0 → 1 + α Z0 → 1 ) ⋅ f ⋅ C ⋅ V DD 2

We calculated in Problem 27 the probabilities of a 0->1 transistion for each node: P 0 → 1 for X and Y is 0.1875 and P0 → 1 for Z is 0.25. Thus, PSW = (2*0.1875+0.25)*100MHz*0.3pF*2.52 = 117.2uW. b. A dynamic CMOS implementation Solution

Digital Integrated Circuits - 2nd Ed

25

30.

In Problem 27 for a dynamic np-CMOS gate, we calculated the probabilities: P 0 → 1 for X and Y is 0.75 and P 0 → 1 for Z is 0.5. Thus, PSW = (2*0.75+0.5)*100MHz*0.3pF*2.52 = 375uW. For the circuit shown Figure 6.21 ignore DIBL and S=100mV/decade. a. What is the logic function implemented by this circuit? Assume that all devices (M1-M6) are 0.5µm/0.25µm. Solution A(B+C) b. Let the drain current for each device (NMOS and PMOS) be 1µA for NMOS at VGS= VT and PMOS at VSG= VT. What input vectors cause the worst case leakage power for each output value? Explain (state all the vectors, but do not evaluate the leakage). Solution When the output is high, the worst-case leakage occurs when two transistors leak in parallel: ABC = 100.When the output is low, the worst-case leakage also occurs when two transistors leak in parallel: ABC = 110 or ABC = 101. c. Suppose the circuit is active for a fraction of time d and idle for (1-d). When the circuit is active, the inputs arrive at 100 MHz and are uniformly distributed (Pr(A =1) = 0.5, Pr(B=1) = 0.5, Pr(C=1) = 0.5) and independent. When the circuit is in the idle mode, the inputs are fixed to one you chose in part (b). What is the duty cycle d for which the active power is equal to the leakage power?
VDD = 2.5V B C
M4 M5

VDD = 2.5V A
M6

Out
M3

A

CL = 50fF

B

M1

C

M2

Figure 6.21 CMOS logic gate.

Solution d*Pactive = (1-d) Pleakage. Pactive = α 0->1*f*CL*VDD2 = (3/8 * 5/8)*(100*106)*(50*1015 – VT – 0.43 )*(2.52) = 7.3 µ W. --------------------S 0.1 Pleakage (ABC = 100) = VDD*2*IleakM1 = 5* I o 10 = 5* 1uA10 = 251pW. Plugging the power numbers into the activity equation and solving for d gives d = 3.4*10-8.

26

Chapter 6 Problem Set

DESIGN PROJECT Design, lay out, and simulate a CMOS four-input XOR gate in the standard 0.25 micron CMOS process. You can choose any logic circuit style, and you are free to choose how many stages of logic to use: you could use one large logic gate or a combination of smaller logic gates. The supply voltage is set at 2.5 V! Your circuit must drive an external 20 fF load in addition to whatever internal parasitics are present in your circuit. The primary design objective is to minimize the propagation delay of the worst-case transition for your circuit. The secondary objective is to minimize the area of the layout. At the very worst, your design must have a propagation delay of no more than 0.5 ns and occupy an area of no more than 500 square microns, but the faster and smaller your circuit, the better. Be aware that, when using dynamic logic, the precharge time should be made part of the delay. The design will be graded on the magnitude of A × tp2, the product of the area of your design and the square of the delay for the worst-case transition.

1

Chapter 10 Problem Set

Chapter 10 SOLUTIONS
1. [C, None, 9.2] For the circuit in Figure 0.1, assume a unit delay through the Register and Logic blocks (i.e., tR = tL = 1). Assume that the registers, which are positive edge-triggered, have a set-up time tS of 1. The delay through the multiplexer tM equals 2 tR. a. Determine the minimum clock period. Disregard clock skew. Solution The circuit and paths of interest has been reproduced for convenience in Figure 0.1 p2 Logic

Logic

Register

p4 Register t′θ

Logic

p1 Logic Logic Logic Logic tθ Θ p3 Logic

Figure 0.1

Sequential circuit.

Out of the 4 paths shown in the figure, p1 is the critical one and determines the lower bound on the clock period. Using T ≥ t reg + t log ic + tsetup – δ , we get Tmin = 1+7+1 = 9. b. Repeat part a, factoring in a nonzero clock skew: δ = t′θ – tθ = 1. Solution With finite clock skew, the time periods for different paths are as follows : Tmin(p1) = 9 - 1 = 8, Tmin(p2) = 6, Tmin(p3) = 7, Tmin(p4) = 7 - 1 = 6 (Note that the clock skew is 0 for paths p2 and p3). Therefore the minimum clock period is Tmin = 8. c. Repeat part a, factoring in a non-zero clock skew: δ = t′θ – tθ = 4. Solution As the clock skew increases, the most significant path changes. Repeating the calculations in part (b) we get : Tmin(p1) = 9 - 4 = 5, Tmin(p2) = 6, Tmin(p3) = 7, Tmin(p4) = 7 - 4 = 3(Note that the clock skew is 0 for paths p2 and p3). Therefore the minimum clock period is Tmin = 7.

2

Chapter 10 Problem Set d. Derive the maximum positive clock skew that can be tolerated before the circuit fails. Solution The maximum positive clock skew is determined by the inequality δ ≤ t cd ,reg + t cd ,log ic . Assuming that the contamination delay is same as the propagation delay, we get. δ max = 1 + 3 + 2 = 6. Note that p4 determines the maximum tolerable skew (the fastest path will produce the earliest contamination). Paths p3 and p2 do not matter since there is no skew involved. e. Derive the maximum negative clock skew that can be tolerated before the circuit fails. Solution The maximum positive negative skew has no bound since the clock period has no upper bound. 2. This problem examines sources of skew and jitter. a. A balanced clock distribution scheme is shown in Figure 0.2. For each source of variation, identify if it contributes to skew or jitter. Circle your answer in Table 0.1

4 Power Supply Noise 3 Interconnect Devices 2

5 Data Dependent Load

6 Static Temperature Gradient 1 Clock Generation

Figure 0.2

Sources of Skew and Jitter in Clock Distribution.

1) Uncertainty in the clock generation circuit 2) Process variation in devices 3) Interconnect variation 4) Power Supply Noise 5) Data Dependent Load Capacitance 6) Static Temperature Gradient
Table 0.1 Sources os Skew and Jitter

Skew Skew Skew Skew Skew Skew

Jitter Jitter Jitter Jitter Jitter Jitter

Digital Integrated Circuits - 2nd Ed

3

b. Consider a Gated Clock implementation where the clock to various logical modules can be individually turned off as shown in Figure 0.3. (i.e., Enable1,..., EnableN can take on difVDD
Input Clock Driver

VDD Enable Gated Clock Clk Enable Clk Gated Clock

Enable
Enable1

Clk

Clk

Enable2

Enable

Clk
EnableN Fine-grain Clock Gating

Gating Approach A
Figure 0.3 Jitter in clock gating

Gating Approach B

3.

ferent values on a cycle by cycle basis). Which approach (A or B) results in lower jitter at the output of the input clock driver? (hint: consider gate capacitance) Explain. Solution Approach A results in lower jitter. For Approach A, the capacitance seen by CLK is independent of data (the Enable signals) to first order. Figure 0.4 shows a latch based pipeline with two combinational logic units.

I
D Q

a

CL1 b 80ns

c
D Q

CL2 d 30ns

D Q

e

CLK

CLK
Figure 0.4 Latch Based Pipeline

CLK

Recall that the timing diagram of a combinational logic block and a latch can be drawn as follows, where the shaded region represents that the data is not ready yet.
IN CL OUT

IN

D Q

OUT

CLK
IN OUT tpd IN CLK OUT

Figure 0.5 Timing diagrams of combinational logic and latch

Assume that the contamination delay tcd of the combinational logic block is zero, and the tclk-q of the latch is zero too.

4

Chapter 10 Problem Set a. Assume the following timing for the input I. Draw the timing diagram for the signals a, b, c, d and e. Include the clock in your drawing.
CLK I T=100ns

Figure 0.6 Input timing

Solution
T=100ns

CLK I a b
T=80ns
slack

c d
T=30ns slack

e
b. State the deadline for the computation of the signal b and d, i.e. when is the latest time they can be computed, relative to the clock edges. In your diagram for part (a), label with a “” the “slack time” that the signals b and d are ready before the latest time they must be ready. Solution b should be ready before the rising edge of CLK for the negative latch to latch and hold its value. d should be ready before the falling edge of CLK for the second positive latch to latch and hold its value. c. Hence deduce how much the clock period can be reduced for this shortened pipeline. Draw the modified timing diagram for the signals a, b, c, d, and e. Include the clock in your drawing. Solution The clock can be reduced by 20 ns.

Digital Integrated Circuits - 2nd Ed

5

In general, it may be difficult to identify how much slack can be removed from the
T=80ns

CLK I a b
T=80ns
b is ready right before rising edge

c d
T=30ns
slack

e clock because it depends on the length of the pipeline too. 4. Consider the circuit shown in Figure 0.7.
Reg φ Reg

φ

Figure 0.7 Sequential Circuit

a. Use SPICE to measure tmax and tmin. Use a minimum-size NAND gate and inverter. Assume no skew and a zero rise/fall time. For the registers, use the following: • A TSPC Register. • A C2MOS Register. Solution From Figure 0.8 and Figure 0.9 we can see that for the TSPC Register: tr,max=175ps, tr,min=94ps, tand,max=90ps, tand,min=83ps. (Note that we don’t need the inverter to implement the logic when we use TSPC Registers). So T > tr,max + tand,max = 265ps. From Figure 0.10 and Figure 0.11we can see that for the C2MOS Register: tr,max=82ps, tr,min=49ps,tinv,max=40ps, tinv,min=33ps. So T > tr,max + tinv,max + tand,max = 212.

Reg φ

6

Chapter 10 Problem Set

* problem 4
2.6

* problem 4

2.6

2.4

2.4

2.2

2.2

2

2

1.8

1.8

1.6

1.6

Voltages (lin)

Voltages (lin)

1.4

1.4

1.2

1.2

1

1

800m

800m

600m

600m

400m

400m

200m

200m

0

0

45n

45.02n

45.04n

45.06n

45.08n

45.1n 45.12n Time (lin) (TIME)

45.14n

45.16n

45.18n

45.2n

45.22n

45.24n

24.98n

25n

25.02n

25.04n

25.06n

25.08n

25.1n

25.12n 25.14n Time (lin) (TIME)

25.16n

25.18n

25.2n

25.22n

25.24n

25.26n

Figure 0.8 tr,max and tr,min
* problem 4
2.8 2.8

* problem 4

2.6

2.6

2.4

2.4

2.2

2.2

2

2

1.8

1.8

1.6

1.6

Voltages (lin)

1.4

Voltages (lin)

1.4

1.2

1.2

1

1

800m

800m

600m

600m

400m

400m

200m 0

200m 0

-200m

-200m

24.88n 24.9n 24.92n4.94n4.96n4.98n 25n25.02n5.04n5.06n5.08n 2 2 2 2 2 2 25.1n 25.12n5.14n5.16n5.18n 2 2 2 25.2n 25.22n5.24n5.26n5.28n 2 2 2 25.3n 25.32n5.34n5.36n 2 2 24.86n 25.38n Time (lin) (TIME)

45.04n45.06n45.08n 45.1n 45.12n45.14n45.16n45.18n 45.2n 45.22n45.24n45.26n45.28n 45.3n 45.32n45.34n45.36n45.38n 45.4n 45.42n45.44n45.46n Time (lin) (TIME)

Figure 0.9 tand,max and tand,min
* problem 4
3

* problem 4

2.6

2.8

2.4

2.6

2.2

2.4

2

2.2

2
1.8

1.8
1.6

1.4

Voltages (lin)

Voltages (lin)

1.6

1.4

1.2

1.2
1

1
800m

800m
600m

600m

400m

400m

200m

200m 0

0

49.95n

50n

50.05n

50.1n

50.15n

50.2n 50.25n Time (lin) (TIME)

50.3n

50.35n

50.4n

50.45n

50.5n

50.55n

49.94n

49.96n 49.98n

50n

50.02n 50.04n 50.06n 50.08n

50.1n 50.12n 50.14n 50.16n 50.18n Time (lin) (TIME)

50.2n

50.22n 50.24n 50.26n

50.28n

Figure 0.10 tr,max and tr,min

Digital Integrated Circuits - 2nd Ed

7

* problem 4
3 3

* problem 4

2.8

2.8

2.6

2.6

2.4

2.4

2.2

2.2

2

2

1.8

1.8

1.6

1.6

Voltages (lin)

1.4

Voltages (lin)

1.4

1.2

1.2

1

1

800m

800m

600m

600m

400m

400m

200m 0

200m 0

-200m 49.75n 49.8n 49.85n 49.9n 49.95n 50n 50.05n 50.1n Time (lin) (TIME) 50.15n 50.2n 50.25n 50.3n 50.35n 50.4n

-200m 19.7n 19.75n 19.8n 19.85n 19.9n 19.95n 20n 20.05n 20.1n 20.15n 20.2n 20.25n 20.3n 20.35n 20.4n 20.45n 20.5n 20.55n 20.6n Time (lin) (TIME)

Figure 0.11 tinv,max and tinv,min

b. Introduce clock skew, both positive and negative. How much skew can the circuit tolerate and still function correctly? Solution We will examine the case with the TSPC Register. The maximum positive skew that the circuit can tolerate is 100ps. Figure 0.12 show the correct operation with no skew. The next two figures show the cases with skew of 100ps and 110ps. It is obvious that in the second case there is some corruption.
* problem 4
2.6 2.4

2.2

2

1.8

1.6

Voltages (lin)

1.4

1.2

1

800m

600m

400m

200m

0

-200m 29.8n 29.75n 29.85n 29.9n 29.95n 30n 30.05n 30.1n 30.15n 30.2n Time (lin) (TIME) 30.25n 30.3n 30.35n 30.4n 30.45n 30.5n 30.55n

Figure 0.12 No skew
* problem 4
2.6 2.6

* problem 4

2.4

2.4

2.2

2.2

2

2

1.8

1.8

1.6

1.6

Voltages (lin)

Voltages (lin)

1.4

1.4

1.2

1.2

1

1

800m

800m

600m

600m

400m

400m

200m

200m

0

0

-200m 29.8n 29.75n 29.85n 29.9n 29.95n 30n 30.05n 30.1n 30.15n 30.2n Time (lin) (TIME) 30.25n 30.3n 30.35n 30.4n 30.45n 30.5n 30.55n

-200m 29.8n 29.75n 29.85n 29.9n 29.95n 30n 30.05n 30.1n 30.15n 30.2n Time (lin) (TIME) 30.25n 30.3n 30.35n 30.4n 30.45n 30.5n 30.55n

Figure 0.13 100ps skew and 110ps skew

8

Chapter 10 Problem Set When the clock is routed in the opposite direction of the data (negative skew) the circuit operates correctly, with a negative impact on the circuit performance. c. Introduce finite rise and fall time to the clocks. Show what can occur and describe why. Solution As the rise and fall times of the clock increase, both chains of the C2MOS chains are on simultaneously. The first graph whow the correct operation of the register, while in the next two graphs rise and fall times of 2ns and 3ns respectively is introduced.
* problem 4
3.2 3 2.8 2.6 2.4 2.2 2 1.8

Voltages (lin)

1.6 1.4 1.2 1 800m 600m 400m 200m 0 -200m

0

5n

10n

15n

20n

25n

30n 35n Time (lin) (TIME)

40n

45n

50n

55n

60n

Figure 0.14 0ns rise and fall times

* problem 4
2.6 2.6

* problem 4

2.4

2.4

2.2

2.2

2

2

1.8

1.8

1.6

1.6

Voltages (lin)

1.4

Voltages (lin)

1.4

1.2

1.2

1

1

800m

800m

600m

600m

400m

400m

200m

200m

0

0

0

5n

10n

15n

20n

25n

30n 35n Time (lin) (TIME)

40n

45n

50n

55n

60n

0

5n

10n

15n

20n

25n

30n 35n Time (lin) (TIME)

40n

45n

50n

55n

60n

Figure 0.15 2ns and 3ns rise and fall times

5.

Consider the following latch based pipeline circuit shown in Figure 0.16. Assume that the input, IN, is valid (i.e., set up) 2ns before the falling edge of CLK and is held till the falling edge of CLK (there is no guarantee on the value of IN at other times). Determine the maximum positive and negative skew on CLK’ for correct functionality.

Digital Integrated Circuits - 2nd Ed

9

Combinational Logic Input

D

Q

Propagation Delay: 7ns Contamination Delay: 1ns

X

D Q

Output
Latch Parameters:

Wire Delay CLK tin,su=2ns CLK

tD-Q = 1ns (D to Q delay) thold=0 tsu=1ns CLK’
T= 20ns

IN

Figure 0.16 Latch based

Solution The positive and negative skew are given after the analysis below. tin,su=2ns CLK
T= 20ns

IN 2ns X 8ns 2ns 8ns

Latch 1 becomes transparent. Takes 1ns delay to get to combinational logic and 1ns to get contaminated by the combinational logic. 2ns

Correct computation of X.

1ns delay from IN to combinational logic and another 7ns for combinational logic propagation delay.

8ns X

X 1ns CLK’ CLK’ latest latch 2 can stop sampling earliest latch 2 can stop sampling Negative Skew – T δ MAX = 2 + -- + t p + t su = 3ns 2

Positive Skew + δ MAX = t D – Q + t CD = 2ns

10 6.

Chapter 10 Problem Set For the L1-L2 latch based system from Figure 0.17, with two overlapping clocks derive all the necessary constraints for proper operation of the logic. The latches have setup times TSU1 and TSU2, data-to-output delays TD-Q1 and TD-Q2, clock-to-output delays TClk-Q1 and TClk-Q2, and hold times TH1 and TH2, respectively. Relevant clock parameters are also illustrated in Figure 0.17. The constraints should relate the logic delays, clock period, overlap time TOV, pulse widths PW1 and PW2 to latch parameters and skews. φ1 φ2

L1 Latch

L2 Latch

φ1

PW1 TOV PW2

Tskr1

Tskl1 φ2 Logic Tskl2
Figure 0.17 Timing constraints

Tskr2

Solution Latest arrival of the D2 signal in the current clock cycle (“Setup 2”)
PW2 ≥ T ov +T sw2 –T sw1 +T D – Q1 +T skr2 –T skr1

PW1 + PW2 ≥ T ov + T sw2 + T C – Q1 + Tskl1 – T skr2

Latest arrival of the D1 signal in the next clock cycle (“Setup 1”)
P≥T D – Q1 +T D – Q2 +T gates

PW1 ≥ – P + T C – Q1 + TD – Q1 + T sw1 + T gates + T skl2 + Tskr2 P ≥ – T ov + T C – Q2 + Tsw1 + T gates + Tskl1 + T skl2

Earliest changes of D1 signal (“Hold 1”)
Td, log ic > Tov + T H1 + T skr1 + T skl2 – TC – Q2 T d, log ic > PW1 + T H1 + T skr1 + T skl1 – T D – Q1 – T C – Q2

Earliest changes of D2 signal (“Hold 2”)
PW2 < T H1 – T H2 + T D – Q1 + Tov + T skr1 – T skr2 PW1 + PW2 ≥ Tov + P + T C – Q1 – T H2 – T skr1 – Tskr2

7.

For the self-timed circuit shown in Figure 0.18, make the following assumptions. The propagation through the NAND gate can be 5 nsec, 10 nsec, or 20 nsec with equal probability. The logic in the succeeding stages is such that the second stage is always ready for data from the first. a. Calculate the average propagation delay with ths = 6 nsec.

Digital Integrated Circuits - 2nd Ed Solution t p 5 + 10 + 20 = --------------------------- + 6 = 17.67ns 3 f = 56.6MHz

11

b. Calculate the average propagation delay with ths =12 nsec. Solution t p 5 + 10 + 20 = --------------------------- + 12 = 23.67ns 3 f = 42.2MHz

c. If the handshaking circuitry is replaced by a synchronous clock, what is the smallest possible clock frequency?
Req HS Start Done Ack HS

Register

Register

2 INPUT NAND

LOGIC Figure 0.18 Self-timed circuit.

Solution In setting clock frequency, we account for the longest delay:
1 f = ----------- = 50MHz 20ns

8.

Note that the delay in the handshaking circuit can be a strong factor in choosing clocking strategies. Lisa and Marcus Allen have a luxurious symphony hall date. After pulling out of their driveway, they pull up to a four-way stop sign. They pulled up to the sign at the same time as a car on the cross-street. The other car, being on the right, had the right-of-way and proceeded first. On the way they also have to stop at traffic signals. There is so much traffic on the freeway, the metering lights are on. Metering lights regulate the flow of merging traffic by allowing only one lane of traffic to proceed at a time. With all the traffic, they arrive late for the symphony and miss the beginning. The usher does not allow them to enter until after the first movement. On this trip, Lisa and Marcus proceeded through both synchronizers and arbiters. Please list all and explain your answer. Solution At the stop sign, the law of “right of way” is the arbiter of two cars arriving at the same time. The stop light may also be considered an arbiter as it ensured that two cars don’t try to merge simultaneously, however it is more like a synchronizer as it allows traffic into an intersection only at specific times.

12

Chapter 10 Problem Set The metering lights are synchronizers as they allow cars to enter the freeway at distinct times. The user is a synchronizer making sure that people go in and out of the concert at the proper times. Design a self-timed FIFO. It should be six stages deep and have a two phase handshakin with the outside world. The black-box view of the FIFO is given in Figure 0.19.
In Req Ack Out Req Ack Figure 0.19 Overall structure of FIFO.

9.

Solution The block diagram of the FIFO is given in the next figure.
In R1 Done En Req Ack Ack C C En C R2 Done En C R3 Done En C R4 Done En C R5 Done Req En R6 Out

10.

The registers are dual-edge triggered on the enable signal, and Done is just a delayed version of enable. The FIFO is full if the Enable Signals alternate between 0’s and 1’s. On the other hand, the FIFo is empty if all enable signals are equal (either 0 or 1). System Design issues in self-timed logic One of the benefits of using self-timed logic is that it delivers average-case of performance rather than the worst-case performance that must be assumed when designing synchronous circuits. In some applications where the average and worst cases differ significantly you can have significant improvements in terms of performance. Here we consider the case of ripple carry addition. In a synchronous design the ripple carry adder is assumed to have a worst case performance which means a carry-propagation chain of length N for an N-bit adder. However, as we will prove during the course of this problem the average length of the carrypropagation chain assuming uniformly distributed input values is in fact O(log N)! a. Given that pn (v) = Pr(carry-chain of an n-bit addition is ≥ v bits), what is the probability that the carry chain is of length k for an n-bit addition? Solution The Pr(carry-chain = k bits) = Pr(carry-chain is ≥ k bits) - Pr(carry-chain is ≥ k+1 bits), which is:
Pk = p n ( v ) – pn ( v + 1 )

b. Given your answer to part (a), what is the average length of the carry chain (i.e., an)? Simplify your answer as much as possible. Now pn(v) can be decomposed into two mutually-exclusive events, A and B. Where A represents that a carry chain of length ≥ v occurs in the first n-1 bits, and B represents that a carry chain of length v ends on the nth bit Solution

Digital Integrated Circuits - 2nd Ed The average length of the carry chain is simply the expected value of Pk, which is: n a n = E[P ] = k

13

∑ i=0 i ⋅ ( p (i ) – p (i + 1 ) ) n n

= p ( 1 ) – p ( 2 ) + 2p ( 2 ) – 2p ( 3 ) + . . . n n n n

= p (1 ) + p (2 ) + . . . + p (n) n n n n =

∑ i=1 pn ( i )

c. Derive an expression for Pr(A). Solution Pr(A) is simply pn-1(v). d. Derive an expression for Pr(B). (HINT: a carry bit i is propagated only if ai ≠ bi, and a carry chain begins only if ai = bi = 1). Solution For B to occur a carry must be generated in bit (n - v) and then propagated all the way to bit n. In addition we must ensure that no carry chain of length v occurs in the initial (n - v) bits. The probability of a carry being generated is Pr(A = B = 1) = (1/2)2 = 1/4, and the probability of this carry being propagated until bit n is Pr(A ≠ B)v-1 = (1/2)v-1. The probability of a carry chain of length v not occurring in the first (n-v) bits is (1 - pn-v(v)). Hence the probability of event B occurring is:
1 – pn – v (v ) 1 1 Pr ( B ) = ( 1 – pn – v ( v ) ) ⋅ -- ⋅ -------------- = ------------------------------4 v–1 v+1 2 2

e. Combine your results from (c) and (d) to derive an expression for pn(v) - pn-1(v) and then bound this result from above to yield an expression in terms of only the length of the carry chain (i.e., v). Solution From the question we are given that:
1–p (v) n–v p n ( v ) = Pr ( A ) + PrB = p n – 1 ( v ) + ------------------------------v+1 2

So all we have to do is substitute in our values of Pr(A) and Pr(B) and then rearrange the equation to yield the required expression:
1 – pn – v ( v) p n ( v ) = p n – 1 ( v ) + ------------------------------v+1 2 1 – pn – v ( v ) ⇒ p n ( v ) – p n – 1 ( v ) = ------------------------------v+1 2

14

Chapter 10 Problem Set Since pn-v(v) is a probability it is non-negative and hence we can bound (1 - pn-v(v)) from above by 1, thus:
1 p (v) – p ( v ) ≤ -------------n n–1 v+1 2

f. Using what you’ve shown thus far, derive an upper bound for the expression: n ∑ i=v (p (v ) – p ( v) ) i i–1

Use this result, coupled with the fact that pn(v) is a probability (i.e., it’s bounded from above by 1), to determine a two-part upper bound for pn(v). Solution To derive the first upper bound we expand the given summation and collect terms: n ∑ i=v (p (v) – p ( v) ) = p (v ) – p (v ) + p (v ) – p ( v) + . . . + p ( v) – p v = p (v ) i i–1 v v–1 v+1 v n n–1 n

where pn(v) can be bounded from above by 1. The second upper bound is calculated using the expression that we derived in (e), and substituting it into the given summation. Note that the expression derived in (e) is independent of the summation variable and hence the result is simply (n - v + 1) times the bound given in (e): n ∑ i=v n–v+1 ( p n ( v ) – p n – 1 ( v ) ) ≤ -------------------v+1 2

Combining the two results we get the final, dual-valued upper bound on pn(v):
 n – v + 1 p n ( v ) ≤ min  1, --------------------  v+1   2

g. (The magic step!) Bound n by a clever choice of k such that 2k ≤ n ≤ 2k+1 and exploit the fact that log2 x is concave down on (0, ∞) to ultimately derive that an ≤ log2 n, which concludes your proof! Solution Go back to our original derivation of the average carry chain length (i.e., E[Pk]), and split the summation into two parts: those terms from 1 to (k-1), and those terms from k to n. k–1 E [ Pk ] = n pn ( v ) +

∑ i=1 ∑ k pn ( v )

Now utilize your two upper bounds from (f) to bound the above expression:

Digital Integrated Circuits - 2nd Ed k–1 E[P ] ≤ k 1+ n n–i+1 ------------------i+1 2

15

∑ ∑ i=1 i=k n

= ( k – 1) +

∑ i=k n–i+1 ------------------i+1 2

n ≤ ( k – 1) +

∑ i=k n ------------i+1 2

= n n ( k – 1 ) + -2

∑ i=k 2

i

n  1- 1- = ( k – 1 ) + --  ----- – -----  2 k n 2 2 

n ≤ ( k – 1 ) + ----k 2

which is a linear function of n. At the limits defined for n we have: k k 2 n = 2 → E [ P k ] = ( k – 1 ) + ----- = k = log n k 2 k+1 k+1 2 → E [ P ] = ( k – 1 ) + -------------- = k + 1 = log n k k 2

n = 2

16

Chapter 10 Problem Set Since log2n is concave down on (0,∞) we have that log2n is an upper bounds of the linear function of n (e.g., Figure 0.20) derived above. Hence E[Pk] ≤ log2n and we are finished.
6

5

log2n (upper bound)

4

3

linear function of n

2

1

0

16

32

48

64

n
Figure 0.20 Comparison of log2n and a Linear Function of n

h. Theoretically speaking, how much faster would a self-timed 64-bit ripple carry adder be than its synchronous counterpart? (You may assume that the overhead costs of using selftimed logic are negligible). Solution Given that a self-timed ripple-carry adder requires a delay on the order of log2n, while a synchronous version requires a delay on order n, then the improvement is:
Speed self – timed 1 ⁄ ( log 64 ) 64 32 Speedup = -------------------------------------------------- = ------------------------- = ------------- = ----Speed synchronous 1 ⁄ 64 log 64 3

11.

Figure 0.23 shows a simple synchronizer. Assume that the asynchronous input switches at a rate of approximately 10 MHz and that tr = 2 nsec, fφ = 50 MHz, VIH − VIL=0.5 V, and VDD = 2.5 V. a. If all NMOS devices are minimum-size, find (W/L)p required to achieve VMS = 1.25 V. Verify with SPICE. Solution Metastability occurs when both inputs to the cross coupled NANDs are high. One NAND of the cross-coupled pair is shown in Figure 0.21 a.
Vdd
W p -------L W p -------L

Out 2.5V
0.375u ---------------0.25u

Out

a

Out

0.375u ---------------0.5u

b

Out

Figure 0.21 a) Nand Gate, b) Simplified Gate

Digital Integrated Circuits - 2nd Ed

17

To solve for the metastable point, we can simplify it to the gate shown in Figure 0.21 b, where the NMOS device size has been modified accordingly. Setting Out = Out = 1.25V and assuming that both devises are velocity saturated, I have:
W V W V n DSATn p DSATp V V k ' --------V –V – ------------------------ + k ' --------V –V –V – ------------------------ = 0 n L DSATn  OUT TN  p L DSATp  OUT DD TP  2 2 115 × 10 – 6 0.375 0.63 ------------ 0.63  1.25 – 0.43 – ---------  + ( – 30  0.5 2  p ---------× 10–6 ) -------- ( – 1 )  1.25 – 2.5 – ( –0.4 ) – ( –1 )   L 2 W

= 0

which results in (W/L)p=2.6. Hspice simulation gives VM=1.23V. b. Use SPICE to find τ for the resulting circuit. Solution The time constants for the metasble point to Vdd and ground are measured in Figure 0.22 and the two vlaues are 237ps and 362ps.
* problem 4
2.6

2.4

2.2

2

1.8

1.6

Voltages (lin)

1.4

1.2

1

800m

600m

400m

200m

0

0

200p

400p Time (lin) (TIME)

600p

800p

1n

Figure 0.22 Measuring τ

c. What waiting time T is required to achieve a MTF of 10 years? Solution We can use the following equation, with the largest time constant, to find the waiting time T. ( V IH – V IL )e tr 1 ------------ = ---------------------------------------- -------------------------V SWING TSIGNAL T φ MTF ( 315360000s )
–1 –T ⁄ τ

( 0.5 )e 2ns = ------------------------------------ -------------------------------------------2.5 1 - -----------------1 ------------------ × 10MHz 50MHz
–1

– T ⁄ ( 362ps )

( 315360000s ) from which we get:

= 200 × 10 e

3 – T ⁄ ( 362ps )

T = 11.5ns d. Is it possible to achieve an MTF of 1000 years (where T > Tφ)? If so, how? Solution

18

Chapter 10 Problem Set

Vin

Vout 30 fF

30 fF φ
–1 3 – T ⁄ ( 362ps )

Figure 0.23 Simple synchronizer

12.

We have: ( 315360000s ) = 50 × 10 e , ( TΦ=5ns) Solving yields: T=9.42ns > TΦ. Explain how the phase-frequency comparator shown in Figure 0.24 works.

R X A

UP

RESET

B DN

V

Y

Figure 0.24 Phase-frequency comparator

The operation of the circuit is best explained with the timing diagrams below: R V A X B Y RESET UP DOWN If the VCO clock (V) leads the reference clock then the DOWN pulse is wider than the UP pulse. That will eventually shift V to the left so that the two clocks are locked.

Digital Integrated Circuits - 2nd Ed

19

The locked operation is shown in the next diagram. When the two clocks are locked R V A X B Y RESET UP DOWN then the UP and DOWN pulses have equal widths. The heart of any static latch is the cross-coupled structure shown in Figure 0.25 (part a). a. Assuming identical inverters with Wp/Wn =kn’/kp’, what is the metastable point of this circuit? Give an expression for the time trajectory of VQ, assuming a small initial Vd0 centered around the metastable point of the circuit, VM.

13.

Q

Q a) Latch

B

A

Q
Metastability Detector τ Latch
M⋅D M⋅D

Q

M D

b) Metastability Detector

c) Synchronizer

Figure 0.25

Simple synchronizer

Solution To find the metastability point of the circuit we just need to find the gate voltage of one inverter that gives the same voltage at the inverter output. Assuming that both devices are velocity saturated and neglecting channel length modulation, we can add the pmos and nmos currents. The equation looks like:

20

Chapter 10 Problem Set
W V W V n DSATn p DSATp V – V V – V k ' --------V – ------------------------ + k ' --------V –V – ------------------------ = 0 n L DSATn  M TN  p L DSATp  M DD TP  2 2

Solving for VM,
V V V DSATn DSATp DSATp V TN + ------------------------ + ------------------------  V DD + V TP + ------------------------   2 V 2 DSATn V = ------------------------------------------------------------------------------------------------------------------------------------------------M V DSATp 1 + -----------------------V DSATn

The time trajectory for the output can be modeled by: v ( t ) = V MS + ( V d0 – V MS )e t⁄τ b. The circuit in part b has been proposed to detect metastability. How does it work? How would you generate a signal M that is high when the latch is metastable? Solution If Q = Q, then NMOS are off, so the PMOS devices will pull A and B high. That means that, when M goes high, the latch goes into the metastble state.

B

A

A B

M

Q

Q

14.

c. Consider the circuit of part c. This circuit was designed in an attempt to defeat metastability in a synchronizer. Explain how the circuit works? What ís the function of the delay element? Solution If the latch becomes metastable, then M will go high and turn on the appropriate NMOS pulling the latch out of metastability. The time delay τ gives the Metastability detector and the latch time to pull out of metastability. An adjustable duty-cycle clock generator is shown in Figure 0.26. Assume the delay through the delay element matches the delay of the multiplexer. a. Describe the operation of this circuit Solution

Digital Integrated Circuits - 2nd Ed

21

The circuit works by using the overlap of two clocks from a ring oscillator to dictate the duty cycle. Longer overlap yields a greater duty cycle. 1 2 3 4 5 6 7 1 and 4 Clock signal from ANDing 1 + 4 gives 28.6% duty cycle. b. What is the range of duty-cycles that can be achieved with this circuit. Solution The range of duty cycles is: 7-50%. c. Using an inverter and an additional multiplexer, show how to make this circuit cover the full range of duty cycles.

Multiplexer Delay

CLOCK

Figure 0.26 generator.

Clock duty-cycle

Solution Inverting the output signal converts a 25% duty cycle to a 75% duty cycle.

22

Chapter 10 Problem Set

Multiplexer Delay

Multiplexer CLOCK

15.

The circuit style shown in Figure 0.27.a has been proposed by Acosta et. al. as a new selftimed logic style. This structure is known as a Switched Output Differential Structure1. a. Describe the operation of the SODS gate in terms of its behavior during the pre-charge phase, and how a valid completion signal can be generated from its outputs. Solution Pre-charging is active low, and the inputs must become valid prior to the rising edge of Φ. During pre-charge the outputs are shorted together and at some point one of the pull-down networks will provide a path to ground. This path to ground will turn on one of the two pullup PMOS transistors, connecting the two outputs to Vdd. Hence the outputs are high during the pre-charge phase. During the evaluate phase the outputs will become complimentary so you can use a NAND gate to signal completion when it’s output goes high. b. What are the advantages of using this logic style in comparison to the DCVSL logic style given in the notes? Solution The advantage of using SODS is that the delay of the gate is independent of the topology of the pull-down networks, and the gate will be faster due to reduced output capacitance of the switching nodes. c. What are the disadvantages of using this style in comparison to DCVSL? Solution The disadvantage is that it requires the inputs to become valid before the pre-charge phase has ended, the outputs also exhibit reduced noise margins due to the problem discussed in (d). In addition, there can be significant static power dissipation during the evaluate phase if the gate is not designed carefully. d. Figure 0.27.b shows a 2-input AND gate implemented using a SODS style. Simulate the given circuit using Hspice. Do you notice any problems? Explain the cause of any problems that you may observe and propose a fix. Re-simulate your corrected circuit and verify that you have in fact fixed the problem(s).

1

A.J. Acosta, M. Valencia, M.J. Bellido, J.L. Huertas, “SODS: A New CMOS Differential-type Structure,” IEEE Journal of Solid State Circuits, vol. 30, no. 7, July 1995, pp. 835-838

Digital Integrated Circuits - 2nd Ed

23

Vdd Φ out Φ inputs PDN

Vdd

Vdd = 2.5V

Vdd
24/2

Vdd
24/2

Φ out Φ PDN out
3/2

out
3/2 3/2

Φ

Φ

B A

4/2 4/2

8/2 8/2

B A

Figure 0.27 a - SODS Logic Style

Figure 0.27 b - 2-input And Gate in SODS Style

Solution Using an input of A=B = 0, followed by A = B = 1 yields the outputs shown in the next graph. Note that there is a reduced noise margin in the outputs as they cannot be pulled to ground.
* problem 11
2.6

2.4

2.2

2

1.8

1.6

Voltages (lin)

1.4

1.2

1

800m

600m

400m

out clk
0 500p 1n 1.5n 2n 2.5n Time (lin) (TIME) 3n 3.5n 4n 4.5n 5n

200m

0

The reduced noise margins are caused by the fact that during the evaluate phase either node A or B will be pulled up to Vdd through an NMOS pass gate (Figure 8). For example: suppose that during the pre-charge phase node A is pulled low by its PDN and B is left to float, while nodes C and D are pre-charged to Vdd. When Φ goes high the outputs are connected to A and B via the M3 and M4. Since A is connected to ground it will discharge C, pulling out low as well. Node D will remain pulled up to Vdd via M2 and hence B will be pulled up to (Vdd - VtN) through M4. This leaves the gate of M1 at (Vdd - VtN) as well, which will turn on M1

24

Chapter 10 Problem Set

to some degree (as determined by the ratio of VtP to VtN), causing some static current to flow through M3, generating some voltage at out given by IleakageRon(M3).
Vdd Vdd Φ

M1 C out Φ inputs

M2 D out Φ

M3 A
PDN

M4 B
PDN

To reduce the problems the designer can either minimize the width of M1-2 (to reduce Ileakage), or increase the width of M3-4 (to reduce Ron). Figure 9 shows the effects of having

the size of M1-2, while doubling the size of M3-4.
16. Voltage Control Ring Oscillator. In this problem, we will explore a voltage controlled-oscillator that is based upon John G. Maneatis’ paper in Nov. 1996, entitled “Low Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” appeared in the Journal of Solid-State Circuits. We will focus on a critical component of the PLL design: the voltage-controlled ring oscillator. Figure 0.28 shows the block diagram of a voltage controlled ring oscillator:
Vctl Bias Generator Vctlp Vctlp Vctln

Vin+

Voutdelay delay delay delay

Vin-

Vout+

Vctln

Figure 0.28 Voltage Controlled Ring Oscillator

The control voltage, Vctl, is sent to a bias generator that generates two voltages used to properly bias each delay cell equally, so that equal delay (assuming no process variations) appear across each delay cell. The delay cells are simple, “low-gain” fully differential input and output operational amplifiers that are connected in such a way that oscillations will occur at any one of the outputs with a frequency of 1/(4*delay). Each delay is modeled as an RC time constant; C comes from parasitic capacitances at the output nodes of the delay element,

Digital Integrated Circuits - 2nd Ed

25

and R comes from the variable resistor that is the load for the delay cell. Below is a circuit schematic of a typical delay cell.

24/2

24/2 Vctlp

24/2

24/2

VoutVin+ 36/2 36/2

Vout+ Vin-

Vctln

48/2

Figure 0.29 One delay Cell

As mentioned before, the value of R is set by a variable resistor. How can one make a variable resistor? The object in the delay cell that is surrounded by a dotted line is called a “symmetric load,” and provides the answer to a voltage-controlled variable resistor. R should be linear so that the differential structure cancels power supply noise. We will begin our analysis with the symmetric load. a. In Hspice, input the circuit below and plot Vres on the X axis and Ires on the Y axis, for the following values of Vctlp: 0.5, 0.75, 1.0, 1.25, 1.5, 1.75, and 2.0 volts, by varying Vtest from Vctlp to Vdd, all on the same graph. For each curve, plot Vres from 0 volts to Vdd-Vctlp. When specifying the Hspice file, be sure to estimate area and perimeter of drains/sources.
+ Vres 24/2 24/2 Vctlp Ires + Vtest

Figure 0.30 :Symmetric Load Test Circuit

After you have plotted the data and printed it out, use a straight edge to connect the end points for each curve. What do you notice about intersection points between the line you drew over each curve, and the curves themselves? Describe any symmetries you see. Solution The lines intersect curves at the “point of inflection” of the curves. At these points, the point of symmetry is x-y symmetric, if we take the drawn line as the x axis, and the y axis as a line drawn perpendicular to the x axis and intersecting the “point of inflection.” Ideally, for symmetric loads, we should notice that the “point of inflection” should occur at 1/2 the voltage sweep range and 1/2 the current output range; but due to non-linear effects, the “point of inflection” is shifted towards the power rail.

26

Chapter 10 Problem Set

Wave D0:A0:i(vtest) D1:A0:i(vvtest) D2:A0:i(vvtest) D3:A0:i(vvtest) D4:A0:i(vvtest) D5:A0:i(vvtest) D6:A0:i(vvtest)

Symbol 1.3m 1.25m 1.2m 1.15m 1.1m 1.05m 1m 950u 900u 850u 800u 750u 700u

* problem set 6 a

Currents (lin)

650u 600u 550u 500u 450u 400u 350u 300u 250u 200u 150u 100u 50u 0 -50u 600m 800m 1 1.2 1.4 1.6 Voltage X (lin) (VOLTS) 1.8 2 2.2 2.4

400m

2.6

b. For each Vctlp curve that you obtained in a), extract the points of symmetries (Vres, Ires), and find the slope of the line around these points of symmetry. These are the effective resistances of the resistors. Also, for each Vctl curve, state the maximum amplitude the output swing can be, without running into asymmetries. Put all of this data in an worksheet format. Solution Although the problem did not ask for 1/gm of the symmetric load when Vres=Vctl, it is good to look at them, because it is good to compare which ‘effective resistance’ to use as an estimation: the slope at the “point of inflection”, or the effective resistance the symmetric load offers when it is in the lowest impedance state (when Vres=Vctl... that gives the lowest gm). gm=W/L*k’*(Vdd-Vctl-Vt) where W=sum of both transistor widths in a symmetric load k’=30e-6 W=48 L=2 Vt=.4 (Vctl, Vres, Ires, Slopes, 1/gm of the symmetric load when Vres=Vctl) (.5, 1.0, 500u, 2.26K, 868) (.75, 0.7, 300u, 3K, 1.028K) (1, 0.6, 200u, 4.76K, 1.262K) (1.25, 0.5, 120u, 9K, 1.633K) (1.5, 0.4, 80u, 22.3K, 2.314K) (1.75, 0.25, 25u, 69K, 3.968K) (2, 0.22, 0.6u, 2.2M, 13.888K) For each symmetric load Vctl setting, the theoretical upper swing limit is Vdd, and lower swing limit is Vctl. Thus, the total swing is Vdd-Vctl. We will be using the bias generator to “set” the Vctln for a given Vctl (Vctlp is essentially Vctl) such that half the current runs through each of the delay cell legs. This theoretically biases the delay cell common mode outputs to Vdd-Vctl/2, which is supposed to be the point of inflection for a given Vctl voltage; however, since the symmetric loads are not perfectly symmetric, we will analyze and see how well the assumption holds. A way to correct this so that the symmetry point occurs

Digital Integrated Circuits - 2nd Ed

27

where we expect it to, would be relative sizing between the symmetric load transistors; but keep in mind that this actually invalidates the symmetry altogether, for certain ranges of bias currents (try it, you will see). c. Using the estimations you made for area and perimeter of drain and source that you put in your Hspice file, calculate the effective capacitance. (Just multiply area and perimeter by CJ and CJSW from the spice deck). Since we are placing these delay elements in a cascaded fashion, remember to INCLUDE THE GATE CAPACITANCE of the following stage. Each delay element is identical to one another. Now, calculate the delay in each cell, according to each setting of Vctlp that you found in a): delay=0.69*R*C. Then, write a general equation, in terms of R and C, for the frequency value that will appear at each delay output. Why is it necessary to cross the feedback lines for the ring oscillator in the first figure? Finally, draw a timing/transient analysis of each output node of the delay lines. How many phases of the base frequency are there? Solution Capacitance Estimations: (lambda is .125e-6) Area of drain/source pmos in symmetric: 24*lambda*.625e-6=1.875e-12 Perimiter of drain/source pmos in symmetric: 24*lambda+1.5e-6=4.5e-6 Area of drain/source nmos input: 36*lambda*.625e-6=2.8125e-12 Perimeter of drain/source nmos input: 36*lambda+1.5e-6=6e-6 Cgdon 3.1e-10 Cgdop=2.7e-10 Cjn=2e-3 Cjp=1.9e-3 Cjswn=2.75e-10 Cjswp=2.232e-10 Cox=6e-3 diode connected pmos contributes: Cgp=Cgdop*Wp+Cox*Wp*Lp=2.7e-10*24*lambda+6e-3*24*2*lambda^2=5.31e-15 Cdb=Cjp*ADp+Cjswp*PDp=1.9e-3*1.875e-12+2.232e-10*4.5e-6=4.566e-15 current source pmos contributes: Cgd=Cgdop*Wp=2.7e-10*24*lambda=8.1e-16 Cdb=Cjp*ADp+Cjswp*PDp=1.9e-3*1.875e-12+2.232e-10*4.5e-6=4.566e-15 Input gate transistor contributes: Cgd=Cgdon*Wn=3.1e-10*36*lambda=1.395e-15 Cdb=Cjn*ADn+Cjswn*PDn=2e-3*2.8125e-12+2.75e-10*6e-6=7.275e-15 load capacitance presented by gate capacitance of following stage: Cg=(2*Cgdon+Cgson)*Wn+Cox*Wn*Ln=(3*3.1e-10)*36*lambda+ +6e-3*lambda^2*36*2 = 10.9e-15 Total load capacitance: 34.817e-15 farads In spice, the actual capacitance is 27.379e-15 farads. Pretty good estimation! Here, we are also adding the analysis of Rgm (1/gm of symmetric load when Vctl=Vres of symmetric load) on delay: (vctl, 0.69*Rslope*C, 0.69*Rgm*C) (.5, 5.457e-11, 1.79e-11)

28 (.75, 7.24e-11, (1, 1.1e-10, (1.25, 2.17e-10, (1.5, 5.38e-10, (1.75, 1.666e-9, (2, 5.3e-8, 2.127e-11) 2.61e-11) 3.38e-11) 4.78e-11) 8.2e-11) 2.87e-10)

Chapter 10 Problem Set

delay=0.69*R*C The frequency will be 1/(2*4*delay), because a “high” and “low” level output on the ring oscillator will be valid for 4 delay times, equivalently. Thus, it will take two times the four delay blocks to form 1 frequency. It’s necessary to cross the lines so we can get an odd number of inversions, while exceeding the “hold time” of the “first” delay block when we feedback the inverted signal. Basically you will have 4 phases of a clock, and for each phase, you will also have the inverted phase. 8 signals total. Some of them are overlapping one another. d. Now, we will look at the bias generator. The circuit for the bias generator is as follows:

24/2 Vctl

24/2

24/2

24/2 Vctlp

72/2 + _ A 48/2

72/2

48/2 Vctln

Figure 0.31 :Bias Generator

Implement this circuit in Hspice, and use the ideal voltage controlled voltage source for your amplifier. Use a value of 20 for A. This circuit automatically sets the Vctln and Vctlp voltages to the buffer delays to set the DC operating points of the delay cells such that the symmetric load is swinging reflected around its point of symmetry for a given Vctl voltage. Also, it is important to note that Vctl is the same as Vctlp. It must go through this business to obtain Vctln (which sets the bias current to the correct value, which sets the DC operating point of the buffer). Do a transient run in Hspice to verify that Vctlp is indeed very close to Vctl over a range of inputs for Vctl. Show a Spice transient simulation that goes for 1uS, and switches Vctl in a pwl waveform across a range of inputs between 0.5V and 2.0V. For extra points, explain how this circuit works. Solution See the following figure.

Digital Integrated Circuits - 2nd Ed

29

Wave D0:A0:v(vctl) D0:A0:v(vctlp) D0:A0:v(vctln) D0:A0:v(v1)

Symbol 2.6

* biasgen

2.4

2.2

2

1.8

1.6

1.4

Voltages (lin)

1.2

1

800m

600m

400m

200m

0

0

200n

400n

600n

800n 1u Time (lin) (TIME)

1.2u

1.4u

1.6u

1.8u

We will refer the two legs of current that contain 1 symmetric load in each leg of the bias generator to be “delay cell replicas.” These replicas serve the purpose so that we can put one of them in a feedback loop such that we can set Vctlp equal to Vctl (thereby setting the symmetric load to the lowest swing point for the given Vctl voltage). Through this process, it also generates the correct Vctln, which gives rise to a certain current ‘I’, will produce the desired voltage for Vres such that Vres=Vctl. Note the sizes of the transistors; the lowest NMOS device has the same width as an actual delay cell’s NMOS current sink device. Thus, both the delay cell replica and actual delay cell’s NMOS current source sink the same current. However, since there are two incoming current legs to the NMOS current sink of the delay cell, the current that the symmetric loads in the delay cell each see I/2, this automatically biasing the dc operating point of the delay cell to the symmetric load’s point of symmetry (theoretically). e. Now, hook up the bias generator you just built with 4 delay cells, as shown in the first figure. For each control voltageVctlp from part c), verify your hand calculations with spice simulations. Show a spreadsheet of obtained frequencies vs. hand-calculation predictions, and in a separate column, calculate % error. Give a brief analysis of what you see. Print out all of the phases (4) of the clock, for a Vctl value of your choice. Solution The spreadsheet is given here.
(Vctl, measured, calculated w/Rslope, calculated w/Rgm, % error from Rslope, % err from Rgm) (2, 3.95MHz, 2.3MHz, 435MHz, 41%, 11000%) (1.75, 384MHz, 75MHz, 1.5GHz, 80%, 390%) (1.5, 1.6GHz, 232MHz, 2.6GHz, 85%, 162.5%) (1.25, 2GHz, 576MHz, 3.6GHz, 72%, 180%) (1, 2.5GHz, 1.13GHz, 4.7GHz, 54%, 188%) (.75, 3.7GHz, 1.72GHz, 5.8GHz, 53%, 156%) (.5, 4.2GHz, 2.29GHz, 6.9GHz, 45%, 164%)

See the following figures.

30

Chapter 10 Problem Set

Wave D0:A0:v(vctl) D0:A0:v(vctlp) D0:A0:v(vctln) D0:A0:v(v1)

Symbol 2.2

* biasgen

2

1.8

1.6

1.4

Voltages (lin)

1.2

1

800m

600m

400m

1.7106u

1.7108u

1.711u

1.7112u 1.7114u Time (lin) (TIME)

1.7116u

1.7118u

1.712u

Wave D0:A0:v(vctl) D0:A0:v(vctlp) D0:A0:v(vctln) D0:A0:v(v1)

Symbol

* biasgen

2.2

2

1.8

Voltages (lin)

1.6

1.4

1.2

1

1.3404u 1.3406u 1.3408u 1.341u 1.3412u 1.3414u 1.3416u 1.3418u 1.342u 1.3422u 1.3424u 1.3426u 1.3428u 1.343u 1.3432u 1.3402u 1.3434u Time (lin) (TIME)

Wave D0:A0:v(vctl) D0:A0:v(vctlp) D0:A0:v(vctln) D0:A0:v(v1)

Symbol 2.4

* biasgen

2.2

2

Voltages (lin)

1.8

1.6

1.4

1.2

1.234u

1.2345u

1.235u

1.2355u 1.236u Time (lin) (TIME)

1.2365u

1.237u

1.2375u

Digital Integrated Circuits - 2nd Ed

31

Wave D0:A0:v(vctl) D0:A0:v(vctlp) D0:A0:v(vctln) D0:A0:v(v1)

Symbol

* biasgen

2.4

2.2

2

Voltages (lin)
1.8 1.6 1.4 1.139u 1.14u 1.141u 1.142u 1.143u Time (lin) (TIME) 1.144u 1.145u 1.146u

Wave D0:A0:v(vctl) D0:A0:v(vctlp) D0:A0:v(vctln) D0:A0:v(v1)

Symbol

* biasgen

2.4

2.2

Voltages (lin)

2

1.8

1.6

1.025u

1.03u

1.035u

1.04u 1.045u Time (lin) (TIME)

1.05u

1.055u

1.06u

Wave D0:A0:v(vctl) D0:A0:v(vctlp) D0:A0:v(vctln) D0:A0:v(v1)

Symbol

* biasgen

2.4

Voltages (lin)

2.2

2

Time (lin) (TIME)

32 This begs the question: why are these OFF by so much?

Chapter 10 Problem Set

The delay equation of 0.69*R*C is what we used. However, in Maneatis’ paper, he calculates delay using just R*C, where R is Rgm that we have included in this problem set solution. If we go back and calculate our estimations using Maneatis’ estimation of delay, we come up with less % error in the % err from Rgm column. However, it still does not explain the still glaringly large %error. If we look again at the figure in part (d), we can see that the lower swing limit of the buffers never reach the lowest point, Vctlp. This is due to the fact that we are not putting in enough delay elements so that the overall frequency is slow enough, so that the delay cells can input and output the full swing range. Thus, our estimation of R using the slope and 1/gm is innaccurate. The overall delay only allows “limited swinging.” Another effect that may be appearing, is the much degraded gds output resistance of short channel devices. if gds begins to appear in the range of gm, then we will see a reduction in measured frequency vs. calculated frequency. In any case, the VCO does not need to be characterized in an absolute voltage to frequency relation; only that the transfer from voltage to frequency is linear, or at least the slope of the voltage to frequency curve has the same polarity at all times. When placed in a feedback loop, the non-linearities of the voltage to frequency curve of the VCO will be compensated for.

Wave D0:A0:v(v1) D0:A0:v(v2) D0:A0:v(v3) D0:A0:v(v4)

Symbol

* biasgen

2.4

2.3

2.2

Voltages (lin)

2.1

2

1.9

1.8

1.7

1.037u

1.038u

1.039u 1.04u Time (lin) (TIME)

1.041u

1.042u

1.043u