Free Essay

Computer Architecture

In:

Submitted By bolajiabey
Words 2037
Pages 9
NAME: BOLAJI ABIODUN FOLORUNSO
COURSE: COMPUTER ARCHITECTURE.

INTRODUCTION
As computer architectures become increasingly complex, more sophisticated analysis methods and optimization tools are required to harness their full performance. Technologies such as event-based sampling and expert systems are now augmenting traditional methods of performance analysis based upon profile and call graph tools. Understanding the basics of performance analysis, as well as the current state- of-the-art software optimization technologies, enables developers to pinpoint and implement solutions to application performance issues.
One sophisticated processor, the Intel® Pentium® M processor, is growing in embedded application usage due to its high performance and low power utilization. The Intel Pentium M processor features Intel MMX™ and Streaming SIMD Extensions (SSE, SSE2) that enable higher performance through parallel computation. Getting the most out of the processor, however, requires that developers take full advantage of these built-in performance enhancements.
Software optimization technology offered by advanced compilers utilizes the enhancements in Intel Pentium M processors in a fashion conducive to embedded development. Compiler technology provides access to these extensions with low development investment while maintaining backward compatibility and minimal code size, two critical challenges in embedded software development. The key to focusing the optimization process, however, is to perform performance analysis.
Performance analysis is the study of application performance on hardware with the end goal of understanding issues and recommending enhancements. Amdahl’s L aw states that performance improvement is limited by the frequency of execution of the improved region and serves as motivation for the following two key insights of performance analysis:
Optimize the most frequently executed regions - the best return on investment for performance enhancement is the optimization of these regions.
Know when to stop - calculating the limit on overall performance gain balances tradeoffs between meeting performance goals and effort to optimize.
For example, if an application comprises two phases that execute in the same amount of time, optimization efforts aimed at only one phase will inevitably return less than two times overall application speedup. If greater performance is desired, optimization efforts should also target the second phase.
Finding the most frequently executed regions of application code commonly employs profiling and typically involves some kind of runtime monitoring of the application. Traditional profiles return metrics such as the amount of time spent in individual functions and the number of times each function is called. The Intel Pentium M processor features a set of built-in performance monitoring counters that can generate profiles based upon processor events such as instructions retired, branch mis-predictions, and cache misses. To collect these event-based profiles:
The user specifies events to monitor and an interval at which to collect an event sample during the application execution.
The processor executes the application. The application may be the fully optimized build, but mapping events to individual lines of source code requires a build with debug information.
While the application runs, performance monitoring counters on the Intel Pentium M processor keep a running total of the specified events as they occur.
When the performance monitoring counter reaches a predetermined number, it posts an interrupt that the operating system will service.
The performance monitoring interrupt handler records the specified event and instruction pointer’s location when the interrupt occurred.
After the profiling of the application has ended, the counters can display their data.
The Pentium M brand refers to a family of mobile single-core x86 microprocessors (with the modified Intel P6 microarchitecture) introduced in March 2003 (during the heyday of the Pentium 4 desktop CPUs), and forming a part of the Intel Carmel notebook platform under the then new Centrino brand. The Pentium M processors had a maximum thermal design power (TDP) of 5–27 W depending on the model, and were intended for use in laptops (thus the "M" suffix standing for mobile). They evolved from the core of the last Pentium III–branded CPU by adding the front-side bus (FSB) interface of Pentium 4, an improved instruction decoding and issuing front end, improved branch prediction, SSE2 support, and a much larger cache. The first Pentium M–branded CPU, code-named Banias, was followed by Dothan. The Pentium M-branded processors were succeeded by the Core-branded dual-core mobile Yonah CPU with a modified microarchitecture. The Pentium M represented a new and radical departure for Intel, as it was not a low-power version of the desktop-oriented Pentium 4, but instead a heavily modified version of the Pentium III Tualatin design (itself based on the Pentium Pro core design). It is optimised for power efficiency, a vital characteristic for extending notebook computer battery life. Running with very low average power consumption and much lower heat output than desktop processors, the Pentium M runs at a lower clock speed than the laptop version of the Pentium 4 (The Pentium 4-Mobile, or P4-M), but with similar performance - a 1.6 GHz Pentium M can typically attain or even surpass the performance of a 2.4 GHz Pentium 4-M. The Pentium M 740 has been tested to perform up to approximately 7,400 MIPS and 3.9 GFLOPS (using SSE2).
The Pentium M coupled the execution core of the Pentium III with a Pentium 4 compatible bus interface, an improved instruction decoding/issuing front end, improved branch prediction, SSE2 support, and a much larger cache. The usually power-hungry secondary cache uses an access method which only switches on the portion being accessed. The main intention behind the large cache was to keep a decent-sized portion of it still available to the processor even when most of the L2 cache was switched off, but its size led to a welcome improvement in performance.
Other power saving methods include dynamically variable clock frequency and core voltage, allowing the Pentium M to throttle clock speed when the system is idle in order to conserve energy, using the SpeedStep 3 technology (which has more sleep stages than previous versions of SpeedStep). With this technology, a 1.6 GHz Pentium M can effectively throttle to clock speeds of 200 MHz, 400 MHz, 600 MHz, 800 MHz, 1000 MHz, 1200 MHz, 1400 MHz and 1600 MHz; these intermediate clock states allow the CPU to better throttle clock speed to suit conditions. The power requirements of the Pentium M varies from 5 watts when idle to 27 watts at full load. This is useful to notebook manufacturers as it allows them to include the Pentium M into smaller notebooks.
Although Intel has marketed the Pentium M exclusively as a mobile product, motherboard manufacturers such as AOpen, DFI and MSI have been shipping Pentium M compatible boards designed for enthusiast, HTPC, workstation and server applications. An adapter, the CT-479, has also been developed by ASUS to allow the use of Pentium M processors in selected ASUS motherboards designed for Socket 478 Pentium 4 processors. Shuttle Inc. offers packaged Pentium M desktops, marketed for low energy consumption and minimal cooling system noise. Pentium M processors are also of interest to embedded systems' manufacturers because the low power consumption of the Pentium M allows the design of fanless and miniaturized embedded PCs. Banias
As the M line was originally designed in Israel, the first Pentium M was identified by the codename Banias, named after an ancient site in the Golan Heights. The Intel Haifa Israel team had previously been working on the memory controller for Timna, which was based on earlier P6 memory controller designs giving them detailed knowledge of P6 architecture which they used when Intel gave them a crash project to create a backup mobile CPU. Given the product code 80535, it initially had no model number suffix, but was later identified as the Pentium M 705. It was manufactured on a 130 nm process, was released at frequencies from 900 MHz to 1.7 GHz using a 400 MT/s FSB, and had 1 megabyte (MB) of Level 2 cache. The core average TDP (Thermal Design Power) is 24.5 watts.
The CPUID signature for a Banias is 0x69X.
Dothan
Intel launched its improved Pentium M, formerly known as Dothan, named after another ancient town in Israel, on May 10, 2004. Dothan Pentium M processors (product code 80536, CPUID 0x6DX) are among the first Intel processors to be identified using a "processor number" rather than a clockspeed rating, and the mainstream versions are known as Pentium M 710 (1.4 GHz), 715 (1.5 GHz), 725 (1.6 GHz), 735 (1.7 GHz), 740 (1.73 GHz), 745 (1.8 GHz), 750 (1.86 GHz), 755 (2.0 GHz), and 765 (2.1 GHz).
These 700 series Pentium M processors retain the same basic design as the original Pentium M, but are manufactured on a 90 nm process, with twice the secondary cache. Die size, at 84 mm2, remains in the same neighborhood as the original Pentium M, even though the 700 series contains approximately 140 million transistors, most of which make up the 2 MB cache. TDP is also down to 21 watts (from 24.5 watts in Banias), though power use at lower clockspeeds has increased slightly. However, tests conducted by third party hardware review sites show that Banias and Dothan equipped notebooks have roughly equivalent battery life.[citation needed] Additionally third party hardware review sites have benchmarked the Dothan at approx 10-20% better performance than the Banias in most situations.
Revisions of the Dothan core were released in the first quarter of 2005 with the Sonoma chipsets and supported a 533 MT/s FSB and XD (Intel's name for the NX bit) (and PAE support required for it was enabled, unlike earlier Pentium Ms that had it disabled). These processors include the 730 (1.6 GHz), 740 (1.73 GHz), 750 (1.86 GHz), 760 (2.0 GHz) and 770 (2.13 GHz). These models all have a TDP of 27 W and a 2 MB L2 cache.
In July 2005, Intel released the 780 (2.26 GHz) and the low-voltage 778 (1.60 GHz).
The processor line has models running at clock speeds from 1.0 GHz to 2.26 GHz as of July 2005. The models with lower frequencies were either low voltage or ultra-low voltage CPUs designed for even better battery life and reduced heat output. The 718 (1.3 GHz), 738 (1.4 GHz), and 758 (1.5 GHz) models are low-voltage (1.116 V) with a TDP of 10 W, while the 723 (1.0 GHz), 733 (1.1 GHz), and 753 (1.2 GHz) models are ultra-low voltage (0.940 V) with a TDP of 5 W.
CONCLUSION
The Intel Pentium M processor is Intel.s first microprocessor designed specifically for the requirements of tomorrow’s mobile PCs. It provides uncompromised performance while observing the thermal and energy requirements and limitations of the mobile platform. Performance-enhancement features were included only if proved to be power-efficient. The processor features many novel power-aware performance mechanisms such as advanced branch prediction, micro-operation fusion, a dedicated stack engine, and the optimized Pentium M bus. It also features the Enhanced Intel SpeedStep technology to reduce energy consumption. These unique features enable the Pentium M processor to deliver breakthrough performance and enable extended battery life thereby providing users with a superior mobile experience.

REFERENCES

1 R. Ronen, A. Mendelson, K. Lai, S.L. Lu, F. Pollack, and J.P. Shen, .Coming Challenges in Microarchitecture and Architecture,. In Proceedings of the IEEE, Vol. 89, No. 3, March 2001, pp. 325-340.
2 IA-32 Intel Architecture Software Developer’s Manual Volume 1: Basic Architecture at ] http://developer.intel.com/design/pentium4/manuals/245 470.htm
3 D. M. Brooks et al., .Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors,. IEEE Micro, Vol. 20, Issue: 6, Dec. 2000, pp. 26-44.
4 D.B. Papworth, .Tuning the Pentium® Pro microarchitecture,. IEEE Micro, Vol. 16-2, April 1996, p. 8.
5 C. Mead and L. Conway, Introduction to VLSI systems, Addison-Wesley Publishing Company,
Boston, Dec. 1980.
6 G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel, .The Microarchitecture of the Pentium 4 Processor,. Intel Technology Journal, Issue 1, 2001, article 2.

Similar Documents

Free Essay

Computer Architecture

...Solution* for Chapter 1 Exercise* Solutions for Chapter 1 Exercises 1.1 5, CPU 1.2 1, abstraction 1.3 3, bit 1.4 8, computer family 1.5 19, memory 1.6 10, datapath 1.7 9, control 1.8 11, desktop (personal computer) 1.9 15, embedded system 1.10 22, server 1.11 18, LAN 1.12 27, WAN 1.13 23, supercomputer 1.14 14, DRAM 1.15 13, defect 1.16 6, chip 1.17 24, transistor 1.18 12, DVD 1.19 28, yield 1.20 2, assembler 1.21 20, operating system 1.22 7, compiler 1.23 25, VLSI 1.24 16, instruction 1.25 4, cache • 1.26 17, instruction set architecture Solutions for Chapter 1 Exercises 1.27 21, semiconductor 1.28 26, wafer 1.29 i 1.30 b 1.31 e 1.32 i 1.33 h 1.34 d 1.35 f 1.36 b 1.37 c 1.38 f 1.39 d 1.40 a 1.41 c 1.42 i 1.43 e 1.44 g 1.45 a 1.46 Magnetic disk: Time for 1/2 revolution =1/2 rev x 1/7200 minutes/rev X 60 seconds/ minutes 3 4.17 ms Time for 1/2 revolution = 1/2 rev x 1/10,000 minutes/rev X 60 seconds/ minutes = 3 ms Bytes on center circle = 1.35 MB/seconds X 1/1600 minutes/rev x 60 seconds/minutes = 50.6 KB Bytes on outside circle = 1.35 MB/seconds X 1/570 minutes/rev X 60 seconds/minutes = 142.1 KB 1.48 Total requests bandwidth = 30 requests/sec X 512 Kbit/request = 15,360 Kbit/sec < 100 Mbit/sec. Therefore, a 100 Mbit Ethernet link will be sufficient. Solution* for Chapter X Exarclsm 1.49 Possible solutions: Ethernet, IEEE 802.3, twisted pair cable, 10/100 Mbit Wireless Ethernet, IEEE 802.1 lb, no medium...

Words: 3285 - Pages: 14

Free Essay

Computer Architecture

...Cache Memory [pic] – Study of large program reveal that most of the execution time is spend, in the execution of a few routines (sub-sections). When the execution is localized within these routines, a number of instructions are executed repeatedly, This property of programs is known as LOCALITY OF REFERENCE. – Thus while some localized area of the program are executed repeatedly, the other areas are executed less frequently. – To reduce the execution time these most repeated segments may be placed in a fast memory known as CACHE (or Buffer) Memory. – The memory control circuitry is designed to take advantage of the property of LOCALITY OF REFERENCE. – If a word in a block of memory is read, that block is transferred to one of the slots of the cache. Cache Operation: – CPU requests contents of memory location – Check cache for this data – If present, get from cache (fast) – If not present, read required block from main memory to cache – Then deliver from cache to CPU – Cache includes tags to identify which block of main memory is in each cache slot [pic] [pic] [pic] Fig: Cache Organization Elements of Cache Design: Cache Size Write Policy Replacement Algorithm Mapping Function Block Size / Line Size CACHE SIZE: – Size of cache should be small enough so that average cost per bit is close to that of main memory and large enough so that average access time...

Words: 314 - Pages: 2

Premium Essay

Computer Architecture

...Computer Architecture Student’s name Professor Intro to Information Technology February 2, 2014 Computer Architecture John von Neumann published the Von Neumann architecture on June 30, 1945. The central processing unit (CPU), the memory, and the input/output devices (I/O) are the main three building blocks of the Von Neumann computer systems connected using the system bus. The components of the model are composed of memory, arithmetic logic unit (ALU), input/output, and the control unit. The memory is where all the data information is stored, in present computers it is call the RAM. The ALU is where the calculation and processing of information take place. The input gets information into the computer like the keyboard, and the mouse. The output gets information out of the computer like the monitor and the printer. The control unit makes sure that all other parts are doing their job correctly and on time. Modern computers still follow the idea of Von Neumann architecture. The CPU chip holds the control unit and the ALU and the memory in the form of RAM located on the motherboard. Von Neumann architecture is important in the present day. All modern computers are based on the same basic design. The central processing unit does the calculations, a memory to hold the data, and an interface that allows the input/output to change the information in memory. The architecture is simple and can be easily reduced to a smaller size and capacity needed. Back in 2012 at the University...

Words: 1605 - Pages: 7

Free Essay

Computer Architecture

...2/3/2014 Week 4 Assignment 1 Computer Architecture John von Neumann was a mathematician and polymath who was born on December 28 1903 and while he made major contributions to a number of fields the one we care about in the IT field is von Neumann Architecture. In 1946 he co wrote a paper with Arthur W. Burks and Hermann H. Goldstine and out lined what would be need for a general purpose electronic computer. The title of the paper was “Preliminary Discussion of the Logical Design of an Electronic Computing Instrument” ( von Neumann , 2000) and the idea of the paper would have far reaching impacts on the field of computer science and would lead the design and building of the first computer call Manchester Mark I witch ran its first program in 1948. While the history lesson of the man is all well and good the question we need to ask ourselves is how the von Neumann architecture works and what goes into the process. Von Neumann believe that computing machines contained four parts the arithmetic logic unit this part of the architecture is solely involved with carrying out calculations upon the data such as adding subtracting multiplying and division the control unit will manage the process of moving data and program into and out of the memory and also deal with carrying out program instructions the memory that can hold data and also the program processing that data in modern computers this RAM and the input-output devices which allows for the idea that a person needs to interact...

Words: 1344 - Pages: 6

Free Essay

Computer Architecture

...CSC 213 ARCHITECTURE ASSIGNMENT QUESTION 1 2.1. What is a stored program computer?   A stored program computer is a computer to use a stored-program concept. A stored-program concept is the programming process could be facilitated if the program could be represented in a form suitable for storing in memory alongside the data. Then, a computer could get its instructions by reading them from memory, and a program could be set or altered by setting the values of a portion of memory.     2.2. The four main components of any general-purpose computer *      Main memory (M) *       I/O module (I, O) *       Arithmetic-logic unit (CA) *       Program control unit (CC)   2.3. The three principal constituents of a computer system at an intergreted circuit level *       Transistors *      Resistors *      Capacitors  2.4. Explain Moore’s law The famous Moore’s law, which was propounded by Gordon Moore, cofounder of Intel, in 1965. Moore observed that the number of transistors that could be put on a single chip was doubling every year and correctly predicted that this pace would continue into the near future. To the surprise of many, including Moore, the pace continued year after year and decade after decade. The pace slowed to a doubling every 18 months in the 1970s, but has sustained that rate ever since.   2.5. The key characteristics of a computer family * Similar or identical instruction set: In many cases, the exact...

Words: 1531 - Pages: 7

Free Essay

Computer Architecture

...1(a) F(w,x,y,z) = wʹxʹyʹzʹ + wʹxʹyzʹ + wxʹyʹzʹ + wʹxyʹzʹ + wʹxyz + wʹxyzʹ + wxʹyzʹ | | | | | | | | | | | | | | | | Minimal sum of products form: F(w,x,y,z) = x’z’ + w’z’ + w’xy (b) F (w,x,y,z) = xz’ + w’z’ + w’xy (using Only NAND Gates) F F (c) (i) | | | | | | | | S (p,q,r) = p | | | | | | | | T (p,q,r) = pq’ + p’q = p XOR q | | | | | | | | U (p,q,r) = q’r + qr’ = p XOR r (ii) (d)(i) Multiplexer How it works: * A multiplexer is a combinational circuit which connects multiple input lines to a single output, allowing only a single selected input signal to be passed to the output line at a time. * An Input signal is selected to be passed to output based on selection code which is implemented as two select lines. Typical Inputs and Outputs: * Consider a 4 -to -1 Multiplexer, typical inputs include four input lines labelled C0, C1, C2 and C3, along with two select lines labelled S0 and S1. * Output include single output line labelled F. Labelled diagram of 4-to-1 Multiplexer: (ii) Jk Flip Flop How it works: * A JK flip-flop is a sequential circuit which has two inputs that are similar to that of an S-R flip-flop, however all possible combinations of input values are valid...

Words: 1667 - Pages: 7

Premium Essay

Computer Architecture

...Assignment 1: Computer Architecture Joseph Henry Strayer University CIS 106 Prof. Shaun Gray November 03, 2013 Assignment 1: Computer Architecture Von Neumann architecture is named after the late John Von Neumann, who was part of a team that created the EDVAC in 1944. This machine was the follow up to the ENIAC, simply because the ENIAC could not modify the program’s contents and could only hold 20 10-digit numbers at a time, needing to be programmed manually (Anderson, Ferro, & Hilton, 2011, p. 11) The concept of Von Neumann architecture is that of a stored program computer, where both binary instructions and data are stored on the main memory. Basically, a program is loaded into memory, and that program could modify itself and be written to perform other functions. Binary instructions are fetched at the same time that data operations occur since they share the same bus. From the computer’s memory, instructions are processed in order and executed by the central processing unit (CPU). The focal point is the CPU, which contains an arithmetic login unit (ALU), control unit (CU), and registers (small storage areas). The ALU performs mathematical functions, especially addition. The CU controls the data traffic in and out of the CPU. The registers are small high-speed units that store instructions and data for the CPU. The CPU accepts input and provides output to external devices. A crystal clock, known as the System Clock times each step in the fetch-execute cycle that...

Words: 1203 - Pages: 5

Free Essay

Computer Architectures

...Have you ever wondered how using a computer actually accomplishes tedious tasks? Tasks including connection to the internet, moving a file from one location to another, or having the ability to use a video application that helps interact with family in remote locations. If the needs of a computer were adequate enough to produce one specific function, such as typing, than the technologies we have now would not exist. The computers of today need to perform expeditious data processing for extensive data tasks. That’s approximately three billion calculates per second on just your average household computer. (Tymann 2008). This is all accomplished by programmable chip sets known as central processing units. Programmable codes within the central processing units are known as complex instruction set computing and reduced instruction set computing. Technologies in the present and the future depend on these architectures for expedited growth, without them society will halt in technological advances. These computing architectures provide the foundations of computer processing, although each having their specific advantages, disadvantages, pros, and cons. Information technology is rapidly growing, providing users and businesses a means to share digital data. Businesses gear towards investing money in all aspects of information technology systems to provide services for their customers. Users use computers as a means to communicate with family or watch the latest movie over the internet...

Words: 2285 - Pages: 10

Premium Essay

Computer Organization and Architecture

...Management Information Systems Program | MIS 545: Computer Organization and Architecture | Paper Systems Project My technology project will describe my personal computer systems that I currently use to complete projects for a variety of business acumens. Since the early1990’s I have provided various business services to small business and individuals including but not limited to financial and tax advice and preparation, data gathering and analysis and reporting, documentation services and notary services. I have twenty plus years of experience in Financial Services and Business Analysis focusing on Asset Management domain with strong skills in facilitating discussions regarding documenting methods and business procedures involving key stakeholders from both business side and IT sides to elicit high level requirements and estimate project feasibility, with these types of projects, usually for major banks I require a system that a) works, b) is secure and c) is compatible with client software and programs. That has perhaps been my most challenging feat in keeping up with technology. The basic hardware and software components Because I am one person, occasionally hiring out portions of larger projects, my equipment has been somewhat limited to that available to retail consumers. This business currently has four laptops, (only 3 being utilized) and three printer, scanner fax combination machines. I also have an external hard drive to which I can connect from anywhere...

Words: 1007 - Pages: 5

Premium Essay

Computer Architecture- Von Neumann Architecture

...Abstract Computer architecture and its history are important to understanding how a computer works. The Von Neumann architecture is the basic building block to the modern day computer. There are different types of functions within the Von Neumann architecture that have helped create an efficient design and allow computers to perform multiple functions rather than being used for one specific purpose. The Von Neumann model uses memory, system buses, and Boolean operators to communicate programs and perform functions. Computer Architecture- Von Neumann Architecture Explained A computer is an electronic device that operates under the control of instructions that are stored in memory. The concept of storing memory or instructions within the computer came from John Von Neumann. Von Neumann architecture can be best described as a stored program design. A stored programmed design means that the program that operates the computer and the instructions that carry out the program are stored on the computer in one location, memory. By having a stored program design, the computer doesn’t have to go through a rigorous process to be reprogrammed, or to perform multiple functions. The basic design of today’s computers is founded on the architecture of Von Neumann, which can be referred to as the “fetch-execute cycle”. The Von Neumann model consists of five major components that work together to make the computer perform. There is an area for memory to be held and processed; today we know...

Words: 1392 - Pages: 6

Premium Essay

Assignment 1: Computer Architecture

...Assignment 1: Computer Architecture Noel E Baez Professor Ali Abedin Introduction to Information Technology July 25, 2013 Abstract This paper will describe the Von Neumann Architecture and explain why it is important. It will describe and explain what a system bus is, and why it is needed in the computer system. A summary of the Boolean operators and the use in computers calculations will be included as well. Finally, a short list of various types of computer storage and memory will be included, and a definition of computer storage. Keywords: Neumann, Boolean, Memory, Storage, System, Bus John Von Neumann was born in 1903 in Budapest. He studied mathematics and graduated from the Pázmány Péter University in Budapest with a Ph.D. In 1930 he was invited to the University of Princeton to teach mathematics in the Institute for Advance Study of Princeton. Von Neumann possessed an extraordinary memory, he was a gifted man that made multiple contributions to the math world, and the computer world, but perhaps his biggest contribution is the creation of the Von Neumann Architecture. The Von Neumann architecture stated that a computer was able to have an uncomplicated, established structure, able to execute any calculation when given the proper command. The Model of this architecture is comprised of the following components, the memory, the control unit, the arithmetic logic unit (ALU). The memory was used to store the information from the ALU or processing unit. This...

Words: 1474 - Pages: 6

Premium Essay

Evolution of Computer Applications & Architecture

...Evolution of Computer Applications and Architecture By Ken Jacobi, Computer Architecture (IT-501) In discussing the evolution of computer architecture, we find that there are many angles on how people tend to view things. Some will take consideration in how things have changed over the last few years. Others will take a stronger look at the direction of where they believe technology is going. A third focus is in regards to the unexpected mistakes that people have made. In conjunction with the past, how can these mistakes be avoided in the coming future and evolution of technology; both for equal and competitive reasons. In part with this, we can turn to the very basic view about what makes a good design. Many architectural topics once began with the idea that if you build something and develop it correctly, change is not something one should expect. If it’s developed right the first time then you don’t have to change it. In this successful strive, people have come to the underlying conclusion that this is a very unrealistic position to be. A very good place to stress the relevance here is by dating back to the start of an exciting architectural turn of events that have gotten us to where we now are: the birth of modern computing. Many will say that this “landmark” of progress has lead to an evolutional launch that we constantly live within. It’s safe to say that these embarking events once began somewhere amongst the early 1970s. Coming out of the...

Words: 3634 - Pages: 15

Free Essay

Computer Architecture

...INTRODUCTION As computer architectures become increasingly complex, more sophisticated analysis methods and optimization tools are required to harness their full performance. Technologies such as event-based sampling and expert systems are now augmenting traditional methods of performance analysis based upon profile and call graph tools. Understanding the basics of performance analysis, as well as the current state- of-the-art software optimization technologies, enables developers to pinpoint and implement solutions to application performance issues. One sophisticated processor, the Intel® Pentium® M processor, is growing in embedded application usage due to its high performance and low power utilization. The Intel Pentium M processor features Intel MMX™ and Streaming SIMD Extensions (SSE, SSE2) that enable higher performance through parallel computation. Getting the most out of the processor, however, requires that developers take full advantage of these built-in performance enhancements. Software optimization technology offered by advanced compilers utilizes the enhancements in Intel Pentium M processors in a fashion conducive to embedded development. Compiler technology provides access to these extensions with low development investment while maintaining backward compatibility and minimal code size, two critical challenges in embedded software development. The key to focusing the optimization process, however, is to perform performance analysis. Performance analysis is...

Words: 267 - Pages: 2

Free Essay

Arm Processer for Computer Architecture

...Subject: The use of the ARM processor as an instruction tool for Computer Architecture Class Journal Article Title: Arms for the Poor: Selecting a Processor for Teaching Computer Architecture Author: Alan Clements Site: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5673541 When an individual chooses to become a teacher, professor, or some sort of instructor, he or she will become subject to one of the most primitive questions ever asked in the history of civilization: “Why?” However, generally speaking when a student asks the question “Why?” it is not for a genuine thirst for knowledge or explanation. It is not like a child who wants to know why the sky is blue, or why dogs can’t talk. A students real interpretation of the question why is more like: “Why is this important?”, or “Why do we have to learn this?”, or the big one (according to Algebra teachers), “Will I ever use this again in the real world?” A computer architecture professor is different from other professor (besides obviously being smarter ;) ), when having to answer this question. Unlike Algebra, which is pretty well established and unlikely to change operations in the next 10 years, Computer Architecture is a rapidly evolving industry and has the very good possibility to look completely different in the year 2022. So a computer architecture professor is faced with a difficult answer to the question. One answer could be “Yes you have to learn it, because it appears on the final and I will...

Words: 1463 - Pages: 6

Premium Essay

Computer Organization and Architecture Designing for Performance 8th Edition

...COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE EIGHTH EDITION William Stallings Prentice Hall Upper Saddle River, NJ 07458 Library of Congress Cataloging-in-Publication Data On File Vice President and Editorial Director: Marcia J. Horton Editor-in-Chief: Michael Hirsch Executive Editor: Tracy Dunkelberger Associate Editor: Melinda Haggerty Marketing Manager: Erin Davis Senior Managing Editor: Scott Disanno Production Editor: Rose Kernan Operations Specialist: Lisa McDowell Art Director: Kenny Beck Cover Design: Kristine Carney Director, Image Resource Center: Melinda Patelli Manager, Rights and Permissions: Zina Arabia Manager, Visual Research: Beth Brenzel Manager, Cover Visual Research & Permissions: Karen Sanatar Composition: Rakesh Poddar, Aptara®, Inc. Cover Image: Picturegarden /Image Bank /Getty Images, Inc. Copyright © 2010, 2006 by Pearson Education, Inc., Upper Saddle River, New Jersey, 07458. Pearson Prentice Hall. All rights reserved. Printed in the United States of America. This publication is protected by Copyright and permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise. For information regarding permission(s), write to: Rights and Permissions Department. Pearson Prentice Hall™ is a trademark of Pearson Education, Inc. Pearson® is a registered trademark of...

Words: 239771 - Pages: 960