CSC 213
ARCHITECTURE ASSIGNMENT

QUESTION 1

2.1. What is a stored program computer? A stored program computer is a computer to use a stored-program concept. A stored-program concept is the programming process could be facilitated if the program could be represented in a form suitable for storing in memory alongside the data. Then, a computer could get its instructions by reading them from memory, and a program could be set or altered by setting the values of a portion of memory.

2.2. The four main components of any general-purpose computer * Main memory (M) * I/O module (I, O) * Arithmetic-logic unit (CA) * Program control unit (CC)

2.3. The three principal constituents of a computer system at an intergreted circuit level * Transistors * Resistors * Capacitors 2.4. Explain Moore’s law
The famous Moore’s law, which was propounded by Gordon Moore, cofounder of Intel, in 1965. Moore observed that the number of transistors that could be put on a single chip was doubling every year and correctly predicted that this pace would continue into the near future. To the surprise of many, including Moore, the pace continued year after year and decade after decade. The pace slowed to a doubling every 18 months in the 1970s, but has sustained that rate ever since. 2.5. The key characteristics of a computer family * Similar or identical instruction set: In many cases, the exact same set of machine is instructions are supported on all members of the family. Thus, a program that executes on one machine will also execute on any other. In some cases, the lower end of the family has an instruction set that is a subset of that of the top end of the family. This means that programs can move up but not down. * Similar or identical operation system: The same basic operating system is available for all family members. In some cases, additional features are added is the higher-end members. * Increasing speed: The rate of instruction execution increases in going from lower to higher family members. * Increasing number of I/O ports: In going from lower to higher family members. * Increasing memory size: In going from lower to higher family members. * Increasing cost: In going from lower to higher family members. 2.6. The key distinguishing feature of a microprocessor. * Clock speeds * Bus width * Number of transistors (microns) * Addressable memory * Virtual memory QUESTION 2. 3.1. General categories of functions that are specified by computer instructions * Instruction fetch * Instruction execution.
3.2. List and briefly define possible states that define an instruction execution. i. Instruction address calculation-determine the address of the next instruction to be executed. ii. instruction fetch-read instruction from its memory location into the processor iii. Instruction operation decoding-analyze instructions to determine type of operation to be performed and operand to be used. iv. Operand addresses calculation-if operations involve reference to an operand in the memory or available via input/output, then determine the address of the operand. v. operand fetch-fetch the operand from memory or read it in from input output vi. Data operation-perform the operation indicated in the instruction vii. operand store-write the result in the memory or out to input/output.

3.3. Two approaches to dealing with multiple interrupts * The First approach is to disable interrupts while an interrupt is being processed. * The Second approach is to define priorities for interrupts and to allow an interrupt to higher priority to cause a lower-priority interrupt handler to be itself interrupted. 3.4. The interconnection structure must support the following types of transfers: * Memory to processor: The processor reads an instruction or a unit of data from memory. * Processor to memory: The processor writes a unit of data to memory. * I/O to processor: The processor reads data from an I/O device via an I/O module. * Processor to I/O: The processor sends data to the I/O device. * I/O to or from memory: For these two cases, an I/O module is allowed to exchange data directly with memory, without doing through the processor, using direct memory access (DMA). 3.5. What is the benefit of using a multiple-bus architecture compared to single bus architecture?

* Compared to single-bus architecture, the using of multiple-bus architecture has a great advantage in speed and of course, will affect performance also. Using multiple-bus architecture will make each device to connect to own bus, which means that each device will have its own bus. This way, it will be faster to transfer data of each device, so the data transfer doesn't have to queue like in the single-bus architecture where many devices are connected to a single-bus that will eventually reach the capacity of the bus and thus will make the data "queue". It will cost more to have multiple bus, but the cost will not match the need of faster speed, compared to the one of that single-bus architecture. * 3.6. List and briefly describe functional groups of signal lines for PCI. i. System pins -include clock and reset pins. ii. Address and data pins-include 32 lines which are time multiplexed for addresses and data. The other lines in the groups are used to validate and interpret the signal lines that carry the addresses and data. iii. Interface control pins-control the timing of transactions and provide coordination among the initiators and the target. iv. Arbitration pins-they are non-shared lines which act as arbiters. v. Error reporting lines-used to report parity and other errors.

QUESTION 3.

3. Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus.
a. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”?

The Maximum memory address space = 2^16 = 64 Kbytes.

b. What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory”?

The Maximum memory address space = 2^16 = 64 Kbytes.
Therefore, in (a) and (b), the microprocessor is to access 64K bytes, but the difference thing between them is that the access of 8-bit memory will transfer a 8 bits and the access of 16-bit memory may transfer 8 bits or 16 bits word.

c. What architectural features will allow this microprocessor to access a separate “I/O space”?

Separate I/O instructions are needed because during its execution will generate separate its own signals I/O signals. That signals will be different from the memory signals which is generated during the execution for memory instructions. Therefore, one more output pin will be needed to carry I/O signals.

d. If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain

With an 8-bit I/O port number the microprocessor can support 2^8 = 256 8-bit input ports,
And 2^8 = 256 8-bit output ports.
With an 8-bit I/O port number the microprocessor can support 2^8 = 256 16-bit input ports,
And 2^8 = 256 16-bit output ports.
Thus, the size of the I/O port will not change the number of I/O ports since the number of I/O ports depends on the number of bits which is used to represent the I/O port number (equals to 8 bits in both cases).

4. Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain, in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the external clock frequency supplied to the microprocessor? State any other assumptions you make, and explain. Hint: Determine the number of bytes that can be transferred per bus cycle.
Answer:
Since minimum bus cycle duration = 4 clock cycles and bus clock = 8 MHz Then, maximum bus cycle rate = 8 M / 4 = 2 M/s
Data transferred per bus cycle = 16 bit = 2 bytes
Data transfer rate per second = bus cycle rate * data per bus cycle = 2 M * 2 = 4 Mbytes/sec.
To increase its performance: * By doubling the frequency, it may mean adopting a new chip manufacturing technology (assuming each instruction will have the same number of clock cycles); * By doubling the external data bus, that means wider (may be newer) on-chip data bus drivers/latches and modifications to the bus control logic.

Therefore, in the first situation the speed of the memory chips will need to double, not to slow down the microprocessor. Regarding the second situation, the word length of the memory will must double to be able to send/receive 32-bit quantities.