PHYSICS HOMEWORK
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Introduction
The homework is composed of discussions of the capacitor - voltage relationship (C-V characteristics) in MOS capacitors. Transistors are also part of the homework. The capacitor-voltage analysis is a technique that is widely used to determine wide range parameters of MOS capacitors. These parameters involve flat-band voltage, threshold voltage, substrate doping concentration and the thickness of the gate oxides.
The MOS capacitance is characterized by its capacitance, Cox. It has two capacitors that are connected in series at the depletion layer. These two capacitors are depletion layer and oxide capacitors that is, Cdep and Coxrespectively. When the MOS-capacitor is supplied by AC voltage, the gap width increase and contracts with respect to the AC frequency (Huff, 2005, pg. 219).
To maintain the reliability and the quality of MOS structures is a vital practice among the MOS capacitors. The C-V measurements are employed mostly to determine the details and quality of gate oxides. On the MOS capacitor, measurements are done at the absence of the drain and source. The test operations provide the process information and at the same time ensuring efficient devices. The interface charges and bulk charges are also part of the parameters that are determined.
The capacitor voltage measurements are carried out using tools like the Keithley model. The Keithley model makes use of 4200-SCS apparatus. Parameters like capacitance, voltage and current are taken. Analysis of the obtained results can be done mathematically, graphically or by use of software. When software is used, a wide range of formulas are used so as to extract the basic C-V parameters.
The MOS capacitor is a device fabricated by placing an oxide between a metal and a semiconductor. Poly-silicon can also be used in the place of the metal gate. The oxide serves the purpose of a dielectric material. The capacitor is as a result of the area of the metal gate. The MOS capacitor capacitance is dependent on the DC voltage (Montoro, 2007, pg. 312).
Discussion
Question one
The MOS capacitor with a p-type polysilicon gate is depended on the applied voltage at the gate. Unlike the metal gate, the polysilicon MOS capacitor has three operation regimes. Two voltages, VT and VFB separates the three operation regimes. See figure 1 for more description. The three regimes are accumulation, depletion and inversion. In the case of the accumulation regime, the same type carriers accumulate at the surface of the body. With depletion operation regime, the surface is occupied by the depletion layer only. In other words, the surface becomes devoid of carries.
In the third operation regime, there is an aggregate of all the opposite type carriers at the surface and, therefore, inverting the conductivity type. The flat band voltage VFB is responsible for separating the depletion regime from the accumulation regime. The threshold voltage VT demarcates the inversion regime from the depletion regime.

Cmos Cmax = Cox CQs Cmax

CHF Cmin = Cmos(VT) VG VT VFB
Figure 1: MOS capacitance; graph of capacitance against Gate voltage
The threshold voltage of a p-type poly-silicon gate MOS capacitance has a negative value unlike that of a metal gate. Considering a positive flat-band voltage that is lesser than the gate voltage. Negative charges are induced on the semiconductor. Take note that for a metal gate positive charges are induced. Electrons being the only negative charges they accumulate at the surface of the semiconductor. The electron accumulation process is referred to as surface accumulation (Nicollian, 2006, pg. 89).
The flat band voltage is the voltage that appears on the surface when there are no charges at the surface. At this instance and across the oxide there appears no electric field. CMOS, accumulation = Cmax = Cox = ε ox tox as the capacitance when the slope of the graph is linear at the accumulation operation regime (Montoro, 2007, pg. 67).
Question two tox = 10 nm, ox = 3.9 and
T = 300K
K = 1.38 * 10-23
To find the slope before the stress choose two points along the before stress curve
Let;
P1 = (0, 10-12) and P2 = (0.5, 10-8)
Slope = ΔyΔx = ΔIΔV
Slope = 10-8 - 10-120.5-0 = 1.9998 *10-8
Therefore, the slope before the stress = 1.9998 *10-8
Slope after the stress can be calculated using the same formula as that before the stress (Kapoor, 2013, pg. 37)
Let;
P1 = (0.3, 10-12) and P2 = (0.5, 10-10)
Slope = ΔyΔx = ΔIΔV
Slope = 10-10 - 10-120.5-0.3 = 4.95 * 10-10
Cox = ε ox tox = 3.9 10 = 0.93
Cox = 0.93
∆Dit = Cox2.3kT(1slope before - 1slope after)
∆Dit = 0.932.3* 1.38 * 10-23 * 300(11.9998 *10-8 - 14.95 * 10-10)
∆Dit = 1.92 * 1029 cm-2eV-1
Question three
At the inversion operation regime, the high frequency (1 MHz) and low frequency (<1 MHz) C-V curves vary differs. The differences in the MOS capacitance curve crops in due to different signal frequencies. The measurement frequency is dependent on the MOS capacitor capacitance. At quasi-static or low frequencies there is holes generation at the surface of the depleted silicon. The holes generation is relatively fast and, therefore, making them be swept to the thin layer. The thin layer is made up of the Si/Si (Marinella, 2008, pg. 372). A layer of charges is created at the Si/Si interface. At this point and under quasi-static conditions, the capacitance per unit area is given by
CMOS, inversion, Qs = ε ox tox = Cmaximm
The holes generation rate at high frequency is always not fast enough. The slow holes generation rate denies the formation of the charges. Therefore, at the Si/Si interface there will be no holes charge density. This is opposed to the case of the low-frequency signal. With the high-frequency signal, the thickness of the surface depletion layer remains unchanged. Or in other words, its thickness remains at maximum value (Johnstone, 2012, pg. 97). The capacitance per unit area for the high-frequency inversion can be calculated by;
CMOS, inversion, HF = Cminimum = Cdepletion, min Cox CDminCox - CDmin
Take note that with the case of a p-MOSFET, the inversion layer capacitance does not change. The capacitance values remain the same irrespective of the frequency value. The value at the quasi-static conditions is maintained all through. The behavior appears due to enough supply of holes. The p-type drain/source regions generate the holes (Huff, 2005, pg. 312).
Question four
Transfer characteristics
VD = 2V
W/L = 10:1 a) Threshold voltage can be calculated as; (Boltsmann, 2010, pg. 123)
Vt = VFB + 2∅B + qNaεs2∅BCox where;
Vt = threshold voltage εs = substrate material permittivity
Cox = capacitance of the oxide
VFB = 30 V (voltage of the flat-band) q = 1.60219 * 10-19 C (electron charge)
Na = 1016 cm-3
Ni = 1.45 * 1010 cm-3 k = 1.3807 * 10-23 J/k
∅B = -kTq * ln (NaNi )
∅B = -1.3807 * 10-23*3001.60219 * 10-19 * ln (10161.45 * 1010 )
∅B = 0.348
Therefore, the threshold voltage can be given as;
Vt = 30 + 2*0.348 + 1.60219 * 10-19* 1016*3.9 * 2 * 0.3480.93
Vt = 30 + 0.696 + 0.0709 = 30.7669 V
Therefore, the threshold voltage is equal to 30.7669 volts. At this voltage, twice the bulk potential will be equal to the surface potential (Broderson, 2011, pg. 97). This voltage indicates the start of a strong inversion process. The threshold voltage corresponds to the MOSFET device starts to conduct. The threshold voltage value for the MOSFET device is always slightly different from that of MOS-capacitor. b) Field effect mobility μFE = LW * 1VdCox * gm gm = trans-conductance. Let the value of gm be 100. Then; gμFE = 110 * 12*0.93 * 100 = 5.38
Conclusion
The aims of the homework were achieved. Several calculations were done. The MOS capacitance C-V characteristic curve for the p-type poly-silicon gate was found to have a negative threshold voltage. This was opposed to the metal gate MOS capacitor. The polysilicon MOS capacitor was seen to have three operation regimes separated by VT and VFB. The three regimes are known as accumulation, depletion and inversion (Bhattacharyya, 2009, pg. 39). The value of the threshold voltage was found to be 30.7669 volts. ∆Dit was found to be 1.92 * 1029 cm-2eV-1. The value of field mobility was found to be 5.38.

Reference
Bhattacharyya, A. 2009. Compact MOSFET models for VLSI design. Singapore: John Wiley &
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Broderson, R., & Gray, P. 2011. MOS switched capacitor filters. Berkeley: Electronics Research Laboratory, College of Engineering, University of California.
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Kapoor, A. 2013. Polysilicon emitter bipolar transistors. New York: IEEE Press.
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Montoro, C., & Schneider, M. 2007. MOSFET modeling for circuit analysis and design. Singapore: World Scientific.
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