Ece Book

Foundations of Analog and Digital Electronic Circuits

Solutions to Exercises and Problems

Anant Agarwal and Jeffrey H. Lang Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology

c 1998 Anant Agarwal and Jeffrey H. Lang

July 3, 2005

Chapter 1 The Circuit Abstraction
Exercises
Exercise 1.1 Quartz heaters are rated according to the average power drawn from a 120 volt AC 60 Hz voltage source. Estimate the resistance (when operating) a 1200 watt quartz heater. NOTE: The voltage waveform for a 120 volt AC 60 Hz waveform is

The factor of in the peak amplitude cancels when the average power is computed. One result is that the peak amplitude of the voltage from a 120 volt wall outlet is about 170 volts. Solution: Power watts

; where

is average value of sinusoidal voltage,

Average value of a sinusoidally oscillating signal is the peak value divided by Therefore

Therefore

1

©

¥£ $ ¡ ! 3 © § ¥£¡ ¦QPIHG00F E¨¦¤¢

¥£ & $ ¡ ! ¦%('%#" ¨¦¤¢ © § ¥£¡ (0 7 0 T § 02@ CA § @ 3 71 § 3 1 ¦D B29865)42§ § S@ § 0)R © (0)§ C D B(0 A §
.

2 ANS::

CHAPTER 1. THE CIRCUIT ABSTRACTION

Exercise 1.2 a) The battery on your car has a rating stated in ampere-hours which permits you to estimate the length of time a fully charged battery could deliver any particular current before discharge. Approximately how much energy is stored by a 50 ampere-hour 12 volt battery? b) Assuming 100% efﬁcient energy conversion, how much water stored behind a 30 meter high hydroelectric dam would be required to charge the battery? Solution: a)

b) Potential Energy b & a p) (S§ ¢3 ¦B) A & 3 ) V 9(B§ A C u ! s p& y x vus b & a wtc) ( § )

Electrical Energy; assume

efﬁciency

, height of water, assuming that there is enough water in the dam such that the height does not change as some of the water is taken out
¥ ££ 4 ¡ & ¦(IR6( q§

ANS:: (a)

Joules, (b) 7200 kg, or about 8 tons.
Y§

and

Solution: But

(Ohm’s Law), so

D

ANS::

Y

@

Exercise 1.3 In the circuit in Figure 1.1, R is a linear resistor and (DC) voltage. What is the power dissipated in the resistor, in terms of

@ £ ¥ £ 7 ) 4 PI¦D8HG((&

! £E C e d Q¢4f9)

§ ¥! E ¡¥! ¥ C R¦£ F" PH(D¢

b & a § ¥ C A ` X c) (2GDF S¢! Y$

i H()

7

D

@

A @ £ ¥ £ 7 ) 4 2 B%9¦86503¡

§ R)3

£! & V ! E H)WG(0(¢3 ¦£ F

@

§ ¥£ ¡ F¦F

!! 4 "1)

! £E C e d rQFQq9)

! E @ ¥ C ¦£ I" RQ¢ A §5¥£101 £ ¡ 3 91 § (¢¦£ %# ) 3 ' & ¥ $ ! " © § § 3 ¦ ¨R)41 F¦¤¢ § ¥£ ¡

@ ¥ C A @ £ ¥ £ 7 ) 4 RDF UT9¦D8HS0(&

g h@

d

)

T § 0ES@ b a p (

a constant ?

@ ` 0(2§ 1 '1 F¦¤¢ 3 § ¥£ ¡ d eC

3

+ v Figure 1.1: Exercise 1.4 In the circuit of the previous exercise (Figure 1.1), soidal (AC) voltage with peak amplitude and frequency , in radians/sec. a) What is the average power dissipated in R? b) What is the relationship between and power in is the same for both waveforms? Solution:
¡ h
¢

R

in Figure 1.1 when the average

v V DC V AC = 2V DC = peak t

Figure 1.2: a) If peak voltage is
¡

, then
D

where

is the average amplitude of the voltage signal.

b) If peak voltage is

, then
D

where

is the average amplitude of the voltage signal.

£ £H ¢ ! 7 @ 0

¡

¡

§

7 ( © ¥

§

, a sinu-

` ¡ 0¡

@

§

7

D

@

© §

© §

§

7¥

¡
¥

¡

¡

@

A

¥ ¦0¡

§

¥ £ ¡ ¦¤¢ (S9¦e ¤ £ & 4 ¥ £

¡

Q

Q

@

4 ANS:: (a) (b)
¡

CHAPTER 1. THE CIRCUIT ABSTRACTION
D E

Problems
Problem 1.1 Determine the resistance of a cube with sides of length cms and resistivity Ohm-cms, when a pair of opposite surfaces are chosen as the terminals. Problem 1.2 Sketch the resistance of 10 Ohms.

characteristic of a battery rated at 10V with an internal

Problem 1.3 A battery rated at 7.2V and 10000 joules is connected across a lightbulb. Assume that the internal resistance of the battery is zero. Further assume that the resistance of the lightbulb is . 1. Draw the circuit containing the battery and the lightbulb and label the terminal variables for the battery and the lightbulb according to the associated variables discipline. 2. What is the power into the lightbulb? 3. Determine the power into the battery. 4. Show that the sum of the power into the battery and the power into the bulb is zero. 5. How long will the battery last in the circuit? Problem 1.4 A sinusoidal voltage source

is connected across a 1k resistor. 1. Make a sketch of

, the instantaneous power supplied by the source.

2. Determine the average power supplied by the source. 3. Now, suppose that a square wave generator is used as the source. If the square wave signal has a peak-to-peak of 20V and a zero average value, determine the average power supplied by the source. 4. Next, if the square wave signal has a peak-to-peak of 20V and a 10V average value, determine the average power supplied by the source.

£

¢ $

1 ! ) R §

© §

1 @ 2

T ((

¥ ¦£ ¡

7

@ 0(` 7 ¡

)

Chapter 2 Resistive Networks
Exercises
Exercise 2.1 Find the equivalent resistance from the indicated terminal pair of the networks in Figure 2.1.

1Ω 4Ω (a) R

2Ω 3Ω

2Ω

1Ω 2Ω 2Ω

(b) R R R

2R

2R

2R

R

(c)
Figure 2.1: Solution: 5

6 a)

CHAPTER 2. RESISTIVE NETWORKS

b)

c)

Therefore

ANS:: (a)

(b)

(c)

+ -

6 vA vS vB

Figure 2.2: Solution: KVL: (1)

2§

@ ¡

¥ 0&

¡

Exercise 2.2 Determine the voltages in Figure 2.2.

T § ¢¢ § ¥ ¢¢ ) §£S¨0H§© ¨ §£ § ¡§ @ ¥ ¡ ¢¢

and

(in terms of

+ + -

3 vA

+ -

+ 2 vA -

vA

+ -

T a 02 (S§ @ §
2

@ § SS@ @ § ¡§ @ ¥

2 F3 2

@ ( § @ ¢¢ @ S §0 7 ( @

¥ ¦2

§
2

¢¢ ¤£2 § ¡§ @

@ 0
) for the network shown

T )

T a 02 (

7
¡

(2)

Exercise 2.3 Find the equivalent resistance between the indicated terminals (all resistances in ohms) in Figure 2.3.

Solution: a)

T § ¢ ()G) §¢ ¦2 § ¡§ @ ¥

¡

ANS::

,

5Ω 10 Ω 2Ω 3Ω 6Ω

10 Ω (a)

4Ω 2Ω (c)

2Ω 1Ω

Figure 2.3:

2§
¡

¡

@ ¡

0& ¥ 2§

¥ 0& 2§
¡ § @ ¡ 0V

%S§ & § ¡ 2§ ¡ 0&

¡

@ ¡

0&
@

§ 0e6§ & `

(b)

4Ω 3Ω 2Ω (d) Difﬁcult

2Ω 1Ω

! E ¦£ F"& § %FBS42§ 3 V § @3 1

Exercise 2.4 Determine the indicated branch voltage or branch current in each network in Figure 2.5.

T 0 T 0S§
§

T

T )

T ()

@ 2§

1

§

@

@ s

¥

7 ¡ ¥ ¥

¤¡

¥ 1

V

@ ¤ V @

§ 7
V

V

§

s

§

¥7 ¥s

¡

¥ 7 ¥ @ s ¤¡

¥ 7 ¥ @ ¡

§

7 ¡ ¥ ¥s

@ ¤

¡

¥ s ¥ @ ¡

£§¥ ¨¨¦£ £§¥£ ¨¨¦¤ A

§ ¡§ @

T § ¥ #¡ ¤¢ ( r¡ § ¡§ @ ¥ ¢ ¥ ¥ T § ¢ ¡ ¢¢ ) G& §¢ ¢V §¡ § ¡§ @

8

d) Apply test voltage:

b)

a) c)

Solution: ANS:: (a) Substitute these expressions into the equation below: (b)

v test

(c)

+ –

(d)

Figure 2.4:

i test

v1
4

CHAPTER 2. RESISTIVE NETWORKS

2 3

2

v2

1

¢ S0 ¤¢ H0

¥ S) § ¡§ @

© § ¥D ¨¦§
u w

1

¤

¤£E§ 1

! E 1 § ¦£ F"GS§ )3 (( (0SE ) 7 ) 4 EE ¤ ¦§ 8H1 r1 ) § 1 § 2¨¥ 0( 0 ¥ (( )P¡ 1 @ (V !
Figure 2.5:
7 ) 4 V 8H%@

§

¢ 7 ¡§ 1 d 1 µA

3A

d)

b)

c) KVL:

e)

s

(a)

(d)

2 MΩ

; current follows path of “short circuit”

v -

+

2Ω

i

+ 30V –

30 V

6V -

+

i1

+ -

10 kΩ

i

10KΩ

Figure 2.6:

(b)

(e)

20 kΩ

20KΩ i2 2Ω i i

20 kΩ

1 µA

30 V

20KΩ + 10 kΩ (f) (c) 2 MΩ V + i 20 kΩ 2 MΩ
9

¥7 @ ¥ s 7 @

s

@ #¡

¥¥ @ ¥

@

§ ¥ 7 @s @ s ¥

@ ¥ 7 @ §¢ ¢ s @ § ¡§ @
b)

@ ¥ 7 @ ¥

@ 2§
§

@
a)

Exercise 2.5 Find the equivalent resistance at the indicated terminal pair for each of the networks shown in Figure 2.8.
¤

£

¤

¤£

§
Figure 2.7:

¤ ¥

£ ¢ 7 ¥ ¢ 7
¤
¦ ¥

u

¤ ¥

u

¥
¤

¤£

) 2 ¢a ¤ FS£(2§
¤

) 2a F"SE§ @

1% § s 1 § 71

§ ((( ¡ 1 ¥
@

71 § 1 ¥ (( 0 ¡ 7 1 s ) 2a ¤ I"9§ 1 T H0 § ¡ @

10

f) KCL:

ANS:: (a) 6V (b) -3A (c) 20V (d)

2a "( @
¦ ¥

¦ ¥7 ¤ § § u § 1 £ F" § s £ E

¢

Solution: This implies KCL: KVL: (right loop)

1µA

e1

(e) .75mA (f) -.5

2MΩ i

CHAPTER 2. RESISTIVE NETWORKS

2MΩ

1 1 s 1
@

1

¤

£
S2

B§

1

§ R 1 C £ §¢ § D ¢¢ ¤D ¨C D ¢¢ ¤¤ D D ©D ¥ D D ¥ £ @
ANS:: (a)

7 @

@

C D ¢ ©D ¥ C C D ¢¤ ¤ D £ § ©D ¢ ¢ C D ¢ ¤¤ D ©D £ £ D D D £ ¤D D ¥ D ¡@ ¥ @ ¥ 7 @ ¥ s @ ¥ H¡@ ¥ #H¥ 7 @ ¥ s #¡ @¡ @
(d)

¥

C § ¨C ¢ ¤ D ¢ ¤ D ¢ C D D ¦¤D ¥£ § H¡@ ¥ ¥

¥

¥
@ @

¡@ ¥ ¡@ ¥

¥

7 @ ¥ s @ § 7 @s @

¥

@ ¥ 7 @ ¥ s @ § ¥ @ ¥ 7 @¡ s @

¥

Exercise 2.6 In the circuit in Figure 2.9, , , and

s

D¤ D

¥ ¥

@ ¡ §¢ ¥ 7 @ ¥ ¢ s ¡@ §¢¢

@ ¥ 7 @ §¢ ¢ s @ § ¡§ @
d)

¥

@ ¥ 7 @ ¤¢ ¢ s @ 2§ ¡§ @
c)

(a)

e)

R1

R3

(d)

R2

R1

R3

, (b)

(b)

R4

R2

Figure 2.8:

R1

R2

(e)

R3

(c)

are known. Find

R1

R2

(c)

R1

R3

R4

.

¥

@ ¥ 7 2¥ @ s R2

R3

(e) 11

@¡ §
§

@

12

CHAPTER 2. RESISTIVE NETWORKS i + v Figure 2.9:

R1

R2

Solution:

ANS:: 750 k

Exercise 2.7 In the circuit in Figure 2.10, , , . Which of the resistors if any, are dissipating less than 1/4 watt?

, and

vo

+ -

R1 R2 R3

Figure 2.10: Solution:

i1 6V + –

100Ω e 1 25Ω i2
Figure 2.11:

50Ω i3

§

¥

s

£

T(2 @ ¤#¡

T 2 0S ¥ s ¥ £ @ #¡

T (() ¥ s ¥ £ @ H#¡ &

KCL:

§

¥

@

T 2 S § 7 @

T 0() §

§

s

@

H&

U@

T HS¢ § 7 @ 2 s 7 @ @

§ ¡

¥

U@

KCL:

T H¢§ 2 s @
¥ ¡1

T

T (02

¥

@

7 @

a

!¦£ £ ! ¦£ £ ! ¦£ £

4 ¡ ¢

¥

` IW

¥

@

7 @

4 ¡ 9£ a 4 ¡ & 90 a

¦ a 0F3 7 2¨¥ 03¡ § 2 1 § 2 GS%3 7 7 2¨(S#¡ § 2 1 § ¥ 2

¢¢ ¢¢

() 3 7 s 6¨¥ () ¡ ¢ ¢ ¢ § 1 § ¥ () ¡ ¢ ¢ ¢ § T (0)
Power in resistor

¤ q
¢

a 2§ 2§

§ 1
£

¥

V ¤ ¡I9S a
V 2 ¤ S¦ H a

s £
¢

T (2 s @ £ T029 s
@

§ 71 § s1

§

T ((
@ s

H&

! E ¦£ F"
13

&

§

£

+

v -

Exercise 2.8 Sketch the i-v characteristics for the networks in Figure 2.12. Label intercepts and slopes.

i

(a)

ANS::

Solution: and

+ 10 Ω v -

and

dissipate less than

i

(b)

+ v -

i

+ -

Figure 2.12: watt of power

5V

(e) 4Ω + v 5Ω i (c) 5Ω 2A + 2V + v i 4Ω (d) 6Ω

14 a) See Figure 2.13

CHAPTER 2. RESISTIVE NETWORKS

i + v (a) 10Ω
3 2 1 -9 -6 -3 -1 -2 -3 3 6 9
1 ------

Figure 2.13: b) See Figure 2.14
2

i + v (b)
-3 -2 -1 -1 -2 -3

+ -

5V

Figure 2.14: c) See Figure 2.15

¡2 5 ¥ 1 §

) § 1 ¥ ) ¡ 65 1 § i 10 v

§ R

i

3 2 1 v 1 2 3

4

5

15

i + v (c)

5Ω + 3/5

2V

-4 -3

-2

-1 -1/5 -2/5 -3/5

Figure 2.15: d) See Figure 2.16

i + v -

4Ω
3 2

6Ω (d)
-9 -6

-3 -1 -2 -3

Figure 2.16: e) See Figure 2.17

¥ ¥ 2 ` ¡ ¥ ` ¡ 0 ¦S( 2¥ II( § 1

¥

2
i 2/5 1/5 v 1 2 3 4
1 --

) § 1 1 § ) 5

@ %

0

2

§ 1 § 1

5

i

1 3 6 9

1 ------

10

v

16

CHAPTER 2. RESISTIVE NETWORKS i i + v 4Ω

5Ω
3 2

9 20

-----

2A
-40/9

1 v -20/9 -1 -2 -3 20/9 40/9

(e)

Figure 2.17: Exercise 2.9 a) Assign branch voltages and branch current variables to each element in the network in Figure 2.18. Use associated reference directions.

iA vA + A

B

C

D

E
Figure 2.18: b) How many linearly independent KVL equations can be written for this network? c) How many linearly independent KCL equations can be written for this network? d) Formulate a set of KVL and KCL equations for the network. e) Assign non-zero numbers to each branch current such that your KCL equations are satisﬁed f) Assign non-zero numbers to each branch voltage such that your KVL equations are satisﬁed. g) As a check on your result, you can draw on the fact that power is conserved in a network that obeys KVL and KCL. Therefore calculate the quantity . It should be zero.
© ©

1

17 Solution: a) See Figure 2.19.

iB – vA + – A B vB + – C vC + iC + E – iE vE
Figure 2.19: b) 2 c) 3 d) KVL: (1)

+ – vD D + iD –

iA

(2)

KCL: (1)

(2)

(3)

e) Satisfy KCL: ¤ ¡a

2§
@

2§

§

2§

2§
01 1 §

§ 1

¥ Q ¥ § ¥
@ QUD

1 ¥ ¡1

@ 1

@ ¡

@

1

¤

@

E§

1

¡

01

¤ a

§
§

1 2§ 1 §
¡

1

18 f) Satisfy KVL:
S @ ¢

CHAPTER 2. RESISTIVE NETWORKS

g) Power conservation:

Check:
§ ¥ @ H290 ¡

so, correct

ANS:: (b) 2 (c) 3 (d) (Depending on your assignment of branch variables, your answer may be different). KVL: , KCL: , , (e) (f) , , , , Exercise 2.10 A portion of a larger network is shown in Figure 2.20. Show that the algebraic sum of the currents into this portion of the network must be zero. Solution: Use KCL at node A (
¡

is a fraction of
¡

§

1

¥

§

¡

@ TP¡

01

¥ 1 ¥

w1

¥

1 ¥

¡

1

1

¡

¥ 1

¡

Prove:

that ﬂows to the left at node B):

§

¤ ¡a

@ § 01 @ 1 c1 @

1

¥

§

¤

¡

a

§

¡ ¥ 0 ¡ @ ¥ @

D 1

§

1

¢@

D

¥ D01 ¥ 1 ¥

@ D

§

b

¡

¤ a

¢ § ¡ SS§ § §1 § 1 § ¡1 § ©Q ¥ § ¥

¥ b ¨ p a ¥ ¡ p ( ¥ p ( ¥ @ b a b a

H

§

¡ ¡

1 ¥

§

§

¥

§

§

¡

S §

§ 1

§ ¡
01 @ §

D

§ 1 ¥

¥ 1 ¥

9 @ Q

2§

¡

¢@

1

S @ ©

S @

§ D S§ 1 @

1

§ § §
©

1

D §
¡

¡

1

19

iA

iB

iC
Figure 2.20:

iA

A

i B + xi C

B xi C

( 1 – x )i C

iB
Figure 2.21:

iC

20

CHAPTER 2. RESISTIVE NETWORKS

Problems
Problem 2.1 A pictorial diagram for a ﬂashlight is shown in Figure 2.22. The two batteries are identical, and each has an open-circuit voltage of 1.5 volts. The lamp has a resistance of when lit. With the switch closed, 2.5 volts is measured across the lamp. What is the internal resistance of each battery?

Battery

Battery

Solution: Redraw circuit:

RI 1.5V RI 1.5V + Figure 2.23: Use a voltage divider relation to ﬁnd

¡@

T 02

+ + -

Switch

Lamp

Figure 2.22:

+ lamp

3V

+ -

2RI
5Ω 2.5V

:

21

ANS::

0.4 A

Solution: The circuit simpliﬁes to 2 in parallel with 2 . The current divides into 0.2A for each branch. On the right branch, the current divides evenly again among the 2 resistors. So . ANS:: 0.1A

Problem 2.3 Find the resistance between nodes A and B in Figure 2.25. All resistors equal . Solution: One possible way to solve this problem is by using vertical symmetry. The current going in and out of the radial branches must be equal in magnitude. In fact, the radial resistors may be detached from the middle node completely. The circuit simpliﬁes to , , and all in parallel. Resulting resistance is . See example 4 in section 1.5 for an alternative approach also using symmetry.

¥

ANS::

T

¤

¥

T

T

¥

§

T

u

Problem 2.2 Determine the current tors in series and parallel.

in the circuit in Figure 2.24 by working with resis-

2Ω i0 2Ω
Figure 2.24:

a § V S2 (SEH¢3 a S2 (2§

T 2 "a 2§

V S¢3

¢ @0 ¥ £! ¥ ¡@ ¢ £! ¥ ¡@

@ @ ¥ ¦2 1 T T

2

T 02 a
1Ω 2Ω

T 0

¤ a

T )

§ u1 T

¤

¥

22

CHAPTER 2. RESISTIVE NETWORKS
A

B
Figure 2.25: s Problem 2.4 For the circuit in Figure 2.26, ﬁnd values of lowing conditions: a) v = 3 V b) v = 0 V c) i = 3 A s d) The power dissipated in

is 12 watts.

3Ω i + 12 V + v R1 -

Figure 2.26: Solution:
¤

¤

c) Solve s D ¢7 s

¢ ¥ § ¤£¥ 7 D

s

§

V ¤ t§

s

b)

. Since the current is not 0, the resistance must be zero.

¤

D

¢¥

a) Voltage divider. Solve

@

to satisfy each of the fol-

HV

§

D

¡S

@

@

T )§ T)§ 1 §

1 ¢2§ s s

@ @ @

C

¢ ¢ ¢¤ D C D ¢ D£¤D C£©DD ¢ DD ¤ D ¢D ©D ¤ £ ¥ ¤¦ £ ¥ s¢ C ¥ ¤¦ ¤

§ ¤@ ¢
¢ ¤@ ¢ ¤@ ¢ ¤@

¤

£

C D D

C £©D ¢ C D s @ £¤D D ¥ 2§ C £©D ¢ D C ¢ ¤ D £ D ¤ D ¢ §C¤ D § ¦D ¢ £s ¥ ¤ ¥ §
¤¥

C

§ ¤@ ¢ § ¤@ ¢ @ 2§ ¤@ ¢
b)

¢ CD ¤ D ¢ D ¤ D £©£ D D ¤ C D £ ¤ ¥ ¢ ¤s ¥ ¢ ¤ ¤ ¥
@ ¥ 7 @ ¥ s ¥
Figure 2.27:

¢ £@

T V (t§
¤

@

T )E§

@

§

@ s T )E§

@

7 ¢s

§ 1

D

§ ¡SE5

1 ¢2§

¡

§

@

d) Power dissipated in

where

and

D

¥

¤ ¤

D

¢¥

ANS:: (a)

(b)

(c)

(d)

s

Problem 2.5 Find the equivalent resistance networks in Figure 2.27.

s

s

s

T (V §

s

@

d)

e) c) a)

¥

¢ D § ¤@

Solution:

R3 (a)

R1

R2

R1

(b)

R2

R3

(e) R1 R2 at the indicated terminals for each of the

R3

R4 (c) R1 R2 R3 R1 R2 (d)
.

R3
23

C C £©D D ¢ ©C£ D ¤ A D ¢ D ¤ D @ § ¥ 1 D C C £ ©D D ¢ ©C£ D ¤ A D ¢ D ¤ D @ § ¥ 1 D C £ ¤D C ¢ D ¢ 1 @ § ¥ 1 C C D £©D D § ¢ £©D ¤ C D ¢ A D ¤ D § ¢D § ¢ 1 ¡A £ D ¢ D¥ C £ D ¢ C D ¥ s 2§ ¤@ @ ¢ £ ©D D
Figure 2.29:

¥1

¤

2§ s 1 92 R § § s1
.
¤

¥

V ¤ R@

s

@ § ¤@ ¢

C £ ©D ¢ D C ¢ ¤ D £ ©D ¤ D ¢ D ¤ D

§ ¤@ ¢

C C D ¢ C©D ¢ D ¤ ¢ ¤ D ¤ £ C C £ £ £ ¤D D ¢ ¤C D ¤ ¤ D ¢ D D ¤ D D ¢ ¤D ¤D @ ¢ D D ¥ ¢ @ ¤D ¥ £ § ¢ £ ©D D D
(b)

C £ ©D ¢ C D ¢ D 7 § ¤s @ £ ¤D D ¥ @ ¥ § ¤@ @ ¢
(e)

+

-

Problem 2.7 For the circuit in Figure 2.29, determine the current all circuit parameters.

V ¤ @

2 § St5

§ s 1 92 § 7 HV § s s 7 V ¤ V@ § 1 92 § Ht§ § s 1 S2 5 §
¤

T )

§ s1

2 § StES

Problem 2.6 In each network in Figure 2.28, ﬁnd the numerical values of the indicated variables (Units are Amperes, Volts and Ohms).

24

Bottom ﬁgure, since 5V is in parallel across the the resistor.

¥ HB§ 7 V

V HB§

W @

6t§

ANS:: (a)

Top ﬁgure,

s

ANS:: Top:

Top:

s

ANS::

Solution: Solution:

1A +

4V

1V

v1

v + -

+ -4Ai1 R1
,

2V

, Bottom:

Figure 2.28:

v2

+

, Bottom:

CHAPTER 2. RESISTIVE NETWORKS

R2 + R3
,

resistor, all 5A of

I3 = 5 A

V3 = 5 V

(c)

i3 explicitly in terms of .

+ -

i1

go through

1Ω
(d)

+ v -

25 Problem 2.8 Determine explicitly the voltage

I R4

R1

Figure 2.30: Solution:

Voltage across current source is not zero. Using voltage divider,
§¥¦ C
¤ ¥ ¥¤ ¥

Problem 2.9 Calculate the power dissipated in the resistor R in Figure 2.31.

3V

+ -

Solution: The equivalent resistance is , so of current is split between the resistors. Therefore, current goes through . and

T

T 0

@

¤

¥7

D

ANS::

4Ω

2Ω=R 1Ω 2Ω

Figure 2.31:

C ¤ £ © ¥ ¤D D ¤ ¢ D ¢ D C ¢ D ¤ D D ¥ £

C £ £ ©D ¤¢ D D ¡ ¡@ G

§ ¢

££ ¥¥¤

¥
¥

in the circuit in Figure 2.30.

R2

R3 v3 +

¦ C¡ D ¦

C £D¢ £ ¤D

¢ ¤@

T 0

C £ D ¢ DC ¢ ¤ D £ ©D C¤ D ¢ D ¤ D C @ £ ¤D ¢ D ¤D ¤ ¢ ¢ D C ¢ ¤ ¤ D £ £ ©D D D D

§

£ ¤ ¥D

@

£

C £ ©D ¤ ¢ ¢ D C ¢ ¤ ¤ D D D D D
¤

§

¥

@ ¡2§

¥

@

§

¢ ¤@

¥

26 Power ¡S§

CHAPTER 2. RESISTIVE NETWORKS

ANS:: Power

Problem 2.10 Design a resistor attenuator to make , using the circuit conﬁguration given in Figure 2.32, and resistor values available in your lab. This problem is underconstrained so has many answers.

R1 + -

R3 + vo -

vi

R2

Figure 2.32: Solution: Here is one possibility with the resistors available in lab kits. ANS::

Problem 2.11 Consider the network in Figure 2.33 in which a non-ideal battery drives a load resistor . The battery is modeled as a voltage source in series with a resistor . The following are some proofs about power transfer.

a) Prove that for when .

b) Prove that for ﬁxed and variable, the power dissipated in when (“matched resistances”).

T(0(2§ ¡@ 0) ¥ ((St§ ((9V § @ ((0t§ 7 @ T H0( § s @ T T V V T T & 2 T (0(S§ ¡@ ( ¥ ((SB§ ( It§ @ ((02 § 7 @ T H0(2§ T T V V T V T &

,

,

,

,

RS vS + Source network
Figure 2.33: variable and ﬁxed, the power dissipated in

£@

£@

(()"` §
R4
,

RL

Load

¥

¢@

¡@

¥

@

@

¡

¡@

§ @

§

§ @

¡@

s

@
@

,

in maximum is maximum

¥ @ #¡

7 ¡@ ¥ ¡@ 7
:

§ ¨¥

¡@ ¡

¡@

§ @

¥

£@

¥
§ ¥ ¦¥

@ ¥ #¡ #¡ ¥ @

¡@ 7 S § 7 ¥ ¡@ ¥ @ ¡ 7 ¥ ¡@ #¡ ¥ ¡@ ¥ @ ¡ ¥ @ 7 @ 7 S § ¥ @¡ ¥ 7 0¡ 7 ¥ @ ¥ #¡ @ ¥ ¡@ ¡@ 7
7¥ @
3¡ @

¡ ¡@ " ¢ 7
§

@

¢@

§

§ @

£@
) 01 E

¥ @¡

7 ¡@ ¥ ¡@ 7 §

¨ £ ©§

D

7

@

¥ #¡

7 ¡@ ¥ ¡7 @ @ 7¥

§ §

u

¥ £ ¦¤

D¢

¡@

¥ @ #¡

7

¡ ¡@ " ¢ 7
§

¢@

c) Prove that for ﬁxed and variable, the condition that maximizes the power delivered to the load requires that an equal amount of power be dissipated in the source resistance .

¢@

¢@

@

@

b)

a) Power dissipated in resistor

c) Maximum power in circuit is dissipated when

¡@

¥ @ #¡

¢@

7

§

Solution:

Maximize with respect to

So, power dissipated in decreases as increases.

when this holds power maximized in : maximum when :

¡

@ R @ § g §

@
X X

. Otherwise power in

27

28

CHAPTER 2. RESISTIVE NETWORKS

Problem 2.12 Sketch the v-i characteristics for the networks in Figure 2.34. Label intercepts and slopes.

i + v i + v 3A 3Ω + v -

Solution: a) See Figure 2.35

b) See Figure 2.36

c) See Figure 2.37

¥ £ §D ©§D ¤ @ @ 0 @ @ ¡@ ¥ @ ¦ ¥£ ¢ § D § @ § @ 7 7 7 G 7 G 7 ¡ £ §D ¥ ¡D @ ¢ R D § @ § ¥ ¨" @ R¡#¡ § @ i 4Ω 2A + v i 4Ω + 3Ω v 4Ω 3Ω i 4Ω + 8V i + v Figure 2.34:

7¥ 7

¡@
@

7

¥ ¥ ( ¡1 ¡

¥ @¡

§ 1 1 § 0V R

§

¥ @ ¡ ¥ 1 § ¡(B5

@

V

§ 1

§

§ 5

"

¡ ¢

§ 1

29

i

i + v 3Ω
3 2 1 -3 -2 -1 -1 -2 -3 1 2 3
1 -3

v

Figure 2.35:

i

i + v 4Ω 2A
3 2 1 v -8 -6 -4 -2 -1 -2 -3 2 4
1 -4

6

8

Figure 2.36:

30

CHAPTER 2. RESISTIVE NETWORKS

i

i + v 4Ω
3

+ 8V -8 -6 -4 -2

2 1 v 2 -1 -2 -3 4
1 -4

6

8

Figure 2.37:

i

i + v 3A
-3 -2

3 2 1 v -1 -1 -2 -3 amps -3 1 2 3

Figure 2.38:

31 i i + v -

4Ω

3

3Ω
-8 -6 -4 -2

2 1 2 -1 -2 -3 4 6 8
1----7

v

Figure 2.39: d) See Figure 2.38 e) See Figure 2.39

Problem 2.13 a) Find , , and in the network in Figure 2.41. (Note that standard convention for current direction). b) Show that energy is conserved in this network. Solution: a) An easy way to do this problem is by superposition. s ¥1

¥

@s @ ¥ 7 4 @ @

1 does not obey the

¢

§ )3 1

¥

¥ @@

§ 1 ¢ 7 @ ¥ s @ § 7 @ s @ 5 7 @ ¥ 7 @s @ § s1 ¥ 7 @ ¡
¡

f) See Figure 2.40

§ 1 1 § ¢ R
¢

¥1

71

1

32

CHAPTER 2. RESISTIVE NETWORKS

i 12 9
7 ----12

i + v 4Ω 3Ω
-8 -6 -4

6 3 v -2 -3 -6 -9 2 4 6 8

Figure 2.40:

i1 vA + -

R1 + v1 + v2 -

R3 i2 + v3 R2

i3 + v - B

Figure 2.41:

33

b) KVL and KCL imply:

We wish to show that

substitute (3) for

Note: Power and, more generally, any sum of products of currents and voltages will always be zero. Note that we did not use any information other than KVL and KCL. The currents and voltages don’t even have to belong to the same network. This powerful theorem is known as Tellegen’s Theorem.
¤

ANS:: (a)

,

,

Problem 2.14 Assume that you have an arbitrary network of passive two-terminal resistive elements in which the i-v characteristic of each element does not touch either the v-axis or the i-axis, except that each i-v characteristic passes through the origin. Prove that all branch currents and branch voltages in the network are zero. Solution: Assume that there is a voltage across any element. Therefore, since the v-i characteristic is such that it intersects the axes at only the origin, there is a current through that element. The element thus consumes power. Due to the conservation of power rule, some element must be producing that power. This contradicts the assumption that all the elements are passive. Therefore there cannot be any voltage across any element, and consequently no current through any element either.

C C £C £ £ ¥ ©D ¤ §AD ¢ ¤ ¤D ¤AD ¢¢ C D D

D ¤¥ D D ¤A § 1

¥

C C £ ©D ¤ ¤ D ¢ ¦¤A£¥ D ¢ D ¢ §A D ¤ D £ ¤D £

s

¡

¢

substitute (1) and (2)
¡

s

s

D § 7 1 ©D ¤ ¦D A £C ¥ D

rearrange s ¥ ' ¥ 1 2§ ¥ 4 ¥ 1 1 1 ¥ 1 ¥ ¥ ¥ 7 2¥ P1¥ 7 ¥ ¡ § ¥ 4 ¥ ¡ 1 ¥ ¥ 1 ¥ 7 P ¥ ¥ 1 ¥ ¤1¡ ¥ 1 § ¥ 4 ¥ 1

¥ ¥1

¥ ¥
(2.1) (2.2) (2.3)

@s @ ¥ 7 @ ¡ @ s s

@s @ ¥ @7 @ ¥ 7 @s @ § 71 @ ' ¥ @ ¡
¥ 7 7 1 ¥ s s 2 § 4 ¥ s 1 ¡ 1 1 s ¥ ¥

7 2§ 1 ¥ 1 2§ 2§ s

¡

@7 @ ¥ 7 @s @ § 1 @ ' ¥ 7 ' @ s s

¥

¥

¥

¥

s 1 ¥ 7 ¥ 7 s
¡

¥

s

1 ¡ 1 ¡
¡

£ ¢ ¤DD C DA ¢¢ CC DD £ ©

£ ¤

¡

71

£ ¤

AD § s 1

34

CHAPTER 2. RESISTIVE NETWORKS

Problem 2.15 Solve for the voltage across resistor in the circuit in Figure 2.42 by assigning voltage and current variables for each resistor.

R1 v + R2

R3 R4 I

Figure 2.42: Solution: Label currents and voltages (see Figure 2.43).

i1 R1 + v -

R3 i3 i4 + v4 I

+ v1 - i2 - v3 + + R2 v2 R4 Figure 2.43:

From KCL: 1) 2)

From KVL: 3) 4)

From Ohm’s Law: s s

5) 6) 7) 8)

@

2§ 7 ¥ @ 2§ 7 ¥ s ¥ @

¥1

1 ¥ 2§ 1 ¥ s 2§ 7 1 1
@ 1 § 7 @71 § 7

¥ ¥ ¥

¡@ 1

@s1 §

¥

§

¥

35 Solving for , the voltage across

ANS::

A 150 Ω B 150 Ω 20 Ω 100 Ω 100 Ω 2 A E 20 Ω C

25 Ω

50 Ω

D
Figure 2.44: Solution:

D

A 150 i5 B i8 25 20 i6 D
Figure 2.45:

i3 150 i1 E 20 i7 i2 2A 100

100 i4 C i9 50

D

¡

Problem 2.16 Find the potential difference between each of the lettered nodes ( , and ) in Figure 2.44 and ground. All resistances are in ohms.
¢

¤

¡@ 7 ¡@ ¥ @ 7
, ,

D CC D ¢ ©D C £ D ¤D D ¢ D £ @ ¥ @ 7 @ ¥ ¡@ s @ ¥ @ s @ ¥ ¡@ @ s @ ¥ ¡@ 7 @ s

¥

¥

¥

@

C D ¢ D ¤ D ¢ ©D ¤ D ¢ D ¤ CD A £C £ ¤D ¤ D ¢ D D ¤ D ¢ D D B§ @ ¥ 7 @s @ § @ ¥ @ 7 " @

:

2 § SS2EH()

T 2 0S

¥ T0HV ¥ ( 2 T T (

§

I

S a X

§

S02

§

9

2 SSS§

D

H()E§ §

¡

H0)

££%¥¢ ¢9HW(¢P£ ! 1 I¥ (0A £ £ $ 1 ! S § A ! £ ¥ 4 ! ¥ !£ T £ H2 § ¤002 § I 1 2 9SS§ ¤ S2§ D 1 2 § ¥ 2 ¨ ¡ S ¥ ¥ ¡ 0¢§ ¤ 9 ¥ ¥ 0¢ § 2 1 2 1 2

¡

E§ ¤1 § ¤ 1
4)

§ ¤1 ¢
,

§ d1

¤ s

§ ¥1

¤ s

§ 5 1
,

§ 1

¥

¤ s

§ 71

¤ s

§ s1
@
¡

§ 7 0() 1

1 2 00U@

§ () 1 § ¥ 0¢ 1 2

¤ 129 ¥ s 00W 1 2 7 0( 1
@ @ @ s

1 2 00W
¢ £

§ d 00 1

1 0

d ¢£1 ¥ 2§ 1 ¤ ¥ 7 2§ ¡1 1

1 ¥1

¥ s 2§ ¤ 1 1

¥

¥1
CHAPTER 2. RESISTIVE NETWORKS

¥ 1 ¥ 2§ 1 1 ¥ 7 1 ¥ s 2§ ¤ 1

36

1)

1)

3)

2)

5)

4)

3)

2)

From KCL:

Solve for currents: ,

From KVL:

Redraw circuit (see Figure 2.45)

,

,

,

7

7

7

7

ANS::

Find voltages relative to ground (D):

,

,

,

§

Problem 2.17 Find the voltage between node resistances are in ohms.
¡

Since the network to the right of the resistor is not grounded, there is no loop for current to ﬂow through it. Therefore, apply a voltage divider to the left loop:

T 2 0S

Solution: and the ground node in Figure 2.46. All , ,

37

85 Ω i1 100 V + 35 Ω C 40 Ω D + 200 V 25 Ω i2 i3

A 15 Ω 20 Ω B 5Ω

2A

Grounded node
Figure 2.46: Note that node D is at
I H(0

:
2 § 2 9S(SESS

ANS::

¥ H(02§ I ¥ I2§ 9
¡

H(02§

2 S9(

§

9

38

CHAPTER 2. RESISTIVE NETWORKS

Chapter 3 Network Theorems
Exercises
Exercise 3.1 Write node equations for the network in Figure 3.1. Solve for the node voltages, and use these voltages to ﬁnd the branch current . To minimize errors and facilitate answer-checking, it is helpful to obtain literal expressions before substituting numerical values for the parameters. s volts

+ V -

R1 R2

R5 i

R3 R4

Figure 3.1: Solution: Node equations:

39

T )§

¥

@

T

1

¥ @ ¡@ @ § 7 ¥ 7 ¥ 7 s £ @ £ £ @ £ @ s 7 @ ¥ @ @ ¥ s ¥ s £ @ £ @

§

§ 7 @ s £ @

T § 7
£

¡@

T 0S§

¥

@

T (V §

¥

@

§ SE

40

CHAPTER 3. NETWORK THEOREMS

V

+ -

R1 e1 R2

R5 i

R3 e2 R4

Figure 3.2: Solving the above two equations,
¤ I
¢

ANS:: 8/53 A Exercise 3.2 Find the Norton equivalent at the indicated terminals for each network in Figure 3.3.

i 3Ω 5V + 2Ω + v Figure 3.3: Solution: Left network: when
2

source is made a short circuit.

2 0¢ a § 7

V W(
¤

V a 0 ¦ S §
V 92

a

2§ 7 § 1
£

¥

@

@

s s £

£ £

§ 1 T a § ¢ G SF §¢
V t§ ¤@ ¢

R2

R1

i +

+ Vo -

Is

v -

41 when the indicated terminals are connected with a wire (“shorted”) since then no current ﬂows through the resistor. Right network: circuit. u V ` ¤ 992

, when the

source is shorted and the

by superposition

Exercise 3.3 Find the Th´ venin Equivalent for each network in Figure 3.4. e

R1

i +

R2

Is

v -

Solution: Left network: when since no current ﬂows through when

is made an open circuit. s current source is made an open circuit.

@

s

ANS:: Left:

, Right:

Figure 3.4:

C C ¦ D §¢ ¤ D ¥ D C ¢ ¤ D 7 @ ¥ D

,

Is

in the open circuit case.

u

£ ¤¡ ¥

current divider for

contribution from when

7¦ @ ¤ ¥ £

u

s ¢

@

¥ 3

@

T F

£ ¡ ¤¢u

¦7 ¤ £ ¢ @

7 @

V ` T a ¤ 992 ¤0 S

¥ s @

¥7 @ ¥

7 S¥ @ § s 7 " § D© @ ¨ 7 @ ¥ s 2§ ¤@ @ ¢

@ ¢ #¡ §¢

s

¥

@

@ 2§ ¤@ ¢

§ ¤@ ¢

§

source is made an open

R1

i +

R2

R3

v -

42 Since (current through

CHAPTER 3. NETWORK THEOREMS

current divider relation for fraction of that will ﬂow through and

4 kΩ 1 kΩ 6A

Solution:

(a): 1. Set voltage source to zero (short circuit):

§

u

u

Exercise 3.4 Find

in (a) and (b) by superposition in Figure 3.5.

31 A 2 kΩ + 3 kΩ 10 V + vo Figure 3.5:

3Ω 2Ω + 62 V -

2Ω

vo 3 Ω
-

+

i1 3 31 A 2 2 i2 – 3 vo +

Figure 3.6:

D

s

ANS:: Left:

, Right:

§ ¢ ¤@

C £ ¤D ¢ C D ¢ ¤ £ ¤D D £

§

¨ D©

¥ @3 ¥¦

@ ¥ 7 @ ¥ 7 @3

¥

7 E¥ @

¤ ¥£

s

s ¢

¥

¥
@

@

@

§ ¢ @ 7 I @

§

¨ D©

§ ¨ D©

3

¥

@ 2§

¥7 @ ¥

¨ D©

) by Ohm’s Law,

s

@ ¢ #¡ ¤¢

¥

@

43 2. Set current source to zero (open circuit):

voltage divider

[superposition]

(b): 1. Set current source to zero (open circuit):
¤ ¥£ ¤ ¤ ¡ ¡ ¡

since

voltage divider

2. Set voltage source to zero (short circuit):
¤ £ ¤ ¤

current divider

[superposition]

ANS:: (a) 6V (b) 0V Exercise 3.5 Use superposition to ﬁnd the voltage Solution:

in the network in Figure 3.7.

SE§ a

¤ t§

V

¢¢ ¤£

s

1 )3

©

¤

¥

) §

V

¦

(( ¦((0V ¥ 3 (((V ! E ¦£ I
§ ¨ ¤ ¦

§ 71

¦

¥ V ¤¢£ ¥ ¢

§ EE

¤£

! E ¦£ F

! E ¦£ F

§

¤ ¥£

¢

& 2§

& 2§

¥ @¡ ¥ (2¦ §

! E ¦£ F

u

H&

3 &

u u V

¢

% @

¡ ¡ ¡ ¡ ¢

) §
¤ ¤ ¦

¥ 2§ u

¤

¦

V

u

¥ ¥ V §£ ¢¢

V t§

§ ¨¥ 7 1 "FV § @ ¡ 3
V ¢ F¤¢

¤ ¥£ u s

1

¢

¡ ¡ ¢

§ u u

44

CHAPTER 3. NETWORK THEOREMS
1Ω 1Ω + v Figure 3.7:

1Ω 2Ω 1Ω 1A

1Ω

2Ω

1A

+ -

1V

from left current source

from voltage source

from right current source

ANS:: 1/3V Exercise 3.6 Determine (and label carefully) the Th´ venin equivalent for the network in e Figure 3.8.

(in mA)

i + v -

R1 R2 i0

Figure 3.8: Solution: , when current source set to zero (open circuit) s [volts] since no current ﬂows through u in the open-circuit case.

ANS::

volts, and

Exercise 3.7 Determine and label carefully the Norton equivalent for the network in Figure 3.9.

! E ¦£ F

V

@

§
¦

¢ £

¤ ¥£

T

@ H

%V

¡¥
¢

£

§ ¤@ ¢

¢

¦ ¥ ¢ ¤£

¨ ¤ ©§¦¥V

1

¥

§ u1

¦ ¥£ ¢ ¤

V

£

T ¢§ 7 @

T

¢

%V

¨ ¤ ©§¦¥V

§ E § 7 @ ¥ £
¢

¨¦¤ V ©t§

§

¨ D©

T SS§ s s

@ 2§ ¤@ ¢

¨ D©

@

45

a

5 kΩ

2 kΩ b 1 kΩ
Figure 3.9: Solution:

4 mA

current divider

, when current source is “open-circuited”

ANS::

, and

Exercise 3.8 Find the Th´ venin equivalent for the circuit at the terminals e ure 3.10.

2 kΩ + 10 V -

1 kΩ

A

2 kΩ A’

Figure 3.10: Solution: , by voltage divider since no current ﬂows through and

when voltage source is short-circuited.

resistor in the

open-circuit case. ANS::

Exercise 3.9 The resistive network shown in Figure 3.11 is excited by two voltage sources and .

¤ ¥

¤ ¤

T ¢

) ¤ RE§

) ¤ H3

¦ ¢ £ 6¥
¢

! E ¦£ I

S2 S

¤ ¥£

T

%

T

¥ S

! E ¦£ IP2 § D© ¨ T SS§ T S§¢ T S ¥ T ¢ § ¤@ ¢ ¢

2 t§ D¨

§ ¤@ ¢

¡§
¢

§

¢6¥ 9
¤ )

F

¥£ ¦¤¡ 7

T S2§ ¤@ ¢

¥ S2 § ¤@ ¢

§

F

in Fig-

¥£ ¦¤¡ s

46

CHAPTER 3. NETWORK THEOREMS
2Ω i(t) v1(t) + 1Ω + - v2(t) 2Ω

Figure 3.11: a) Express the current through the resistor as a function of and a b) Determine the total energy dissipated in the from time to time .

resistor due to both

and

c) Derive the constraint between and such that the value for b) can be computed by adding the energies dissipated when each source acts alone (i.e. by superposition). Solution: a)

b) Energy c)

For superposition to apply,

[orthogonal]

§ ¨§

Exercise 3.10 Find the Norton equivalent at the terminals marked Figure 3.12.

in the circuit in

s

ANS:: (a)

(b) Energy

(c)

3

¥£ ¦¤¡ 7

¤ ¤ C ¢

¥£ ¦¤¡ 7
¢

¥ ¦£ ¡ s

¤ ¤ ¥d s £ X 7 ¦¦¤¡ 7 ¥ ¦¤¡ s ¤¡ C ¢ s ¥¥£ ¥£ ¢

¥ ¦£ ¡ s

¥ ¦¤¡ 7 ¥ ¦£ ¡ s ¡ ¥£ ¥

¤ & ) £ X 7 ¥ ¦£ ¡ 7 ¥ ¦¤¡ s ¤¡ C ¢ ¥ ¥£ ¢ ¡

¤ ¢ S££ X 3 7 )3 s C ¢ ¢ ¡

§ ¥ ¦£ ¡ 7 ¥ ¦¤¡ s ¡ ¥ ¥£

¥£ ¦¤¡ 7

T ) §

T )

¥£ ¦¤¡ s

¢

§

¥¥£ ¦¦¤¡ 7 ¥ ¦¤¡ s ¤¡ ¥£

¦§¢ ¥ ¢ ¢ §¢

7

¥£ ¦¤¡ 1

§ ¥ 9¦£ ¡ 1

s

§ ¦£ ¡ 1 ¥

s

¢ S¦£ X 3 7

47

x

2Ω 1Ω

4Ω + - Vo = 5 V

x

Io = 3 A

2Ω

Figure 3.12: Solution:

when voltage source shut off

when current source shut off

ANS::

and

Exercise 3.11 Find the Th´ venin equivalent for the circuit in Figure 3.13 at the terminals e .

6 Ω 12 V + 3 Ω

Figure 3.13: Solution:

Find

by superposition:

¤

E§

¦ ¤£ ¢

T § ¢ 0SG§¢
¤

¥

§ E§

! E ¦£ F

¦ ¥£ ¢ ¤

U¥ F

&2§E% ¥ PB§ D© ¨ T 2§ F¤¢ 2§ ¤@ V ¢ & ¢

¢ I¤¢ 2§ ¤@ ¢ §
F

when both sources are “shut off” , by superposition

T 02§ ¤@ ¢

D¨

¤

¤ ¤

A 1A A’

48

CHAPTER 3. NETWORK THEOREMS
6 3 + A V oc – A'
Figure 3.14: When current source is off:

12V

+ -

voltage divider

i2 6 i1 3 1A +

A V oc

– A'
Figure 3.15: When voltage source is off:
¤

current divider

ANS::

and

Exercise 3.12 In the network in Figure 3.16, ﬁnd an expression for Solution: By superposition,

voltagedivider

currentdivider

7

7 I3 @

! E ¦£ F
.

¦ 7 ¥£ ¤ @ ¥

¢

PB§

! E ¦£ I

s

V

@

s

§

S§

¢ ¦ 7 @ ¥ ¥¢

¤

3

3
¦ ¦

T (V 3

¢&

¢&

¤ ¥£

! E ¦£ I

&

¥ V

@ ¥ 7 @

s

¤ ¥£

V

1 6§

¥ V
¤ ¥£ s

¢

%&

¢

D¨

@

¢ 3 ¥ 2§

§ s1

§

§

¨ D©

Q¨

7

T 2§ ¤@ ¢

49

R1

v3 - + I3
+

R2 v2
-

Figure 3.16:

ANS::

Exercise 3.13 The networks in Figure 3.17 are equivalent (i.e. have the same v-i relation) at terminals . Find and .

I3

Solution: Right network is Th´ venin Equivalent of left network. e , by superposition. s since no current ﬂows through

when

ANS::

and

Exercise 3.14 For each of the circuits in Figure 3.18 give the number of independent node variables needed for a solution of the problem by the node method. Solution: a) 3 node variables b) 3 node variables

¥

¢ ¢ 7 @ 3 £C D ¤ ¢ ¤ D ¥ £C D C ¢ ¤ D ¡3 2§ 7 D D
R1 v3 - + R2

@

¥

¥ 7 @ 3 § ¢

¢ ¤@

¥

¥

¥

¥ 7 @ 3 § Q¨ § ¢ 7 2§ ¤@ @ ¢

¢

7 @ § ¤@ ¢

¤

¥

¤

@

¤

i
+

RT A v
-

i
+

A v
-

vT A’

+ -

A’

Figure 3.17:

is shut off.

50

CHAPTER 3. NETWORK THEOREMS
I1 R2 R3 R4 R5 R2
Figure 3.18: ANS:: (a) 3 (b) 3

R1 R4 v
+ -

I R5 R3 R4

R1

I2

Exercise 3.15 For the circuit shown in Figure 3.19, write a complete set of node equations for the voltages , and . Use conductance instead of resistance. Simplify the equations by collecting terms and arranging them in the “standard” form for n linear equations in n unknowns. Do not solve the equations.

v

+ -

Solution: (1) (2) (3) ANS:: (1) , (3)
@ ¥ 3 s &

, (2)

§ ( 3

& @ ¡

¥ H

& ¥ r¡ &

¥

¤3

¥¥ 3 & @

7

§

& B§

¥

§ F ¥ ¡ 3 3

9 3

3 ¥

&

d

7 & d ¤3 B§ 3 ¥ & ¥ & ¥ s 3 B§ 3 ¥ ¡"3 S¥ & & @ ¥ & ¥ 7 r2¥ ¢ 9 & &¡ 3

&

@ ¢

¥ H

&

¥

&

¥ &¡ ¥ ¥ 3

@ ¥

¥

¥

¥

&

¥

¥ & ¥ s &¡

¥

¥

¡

7 & ¡ ¥ ¡ 3 ¥ ¥ & ¥ ¥ &

& @

@ ¥

F 3

¥

R1 va R3 R5 vb

I

R2 R4 R6 vc

Figure 3.19:

¥

s

& &

¡

F 3

51 Exercise 3.16 For the circuit shown in Figure 3.20, use superposition to ﬁnd of the ’s and source amplitudes.

v1 R3
+ +

R1

v2

-

+

R2 v
-

I

Figure 3.20: Solution: Redraw:
+ +

V2

V1 R1

R3

I

–

V R2

+

Figure 3.21: Superposition: 1. since no current through

2.

voltage divider

3.

7 e3

¦ ¤ ¥£ ¢ @ §¢ s @ ¥ 7 @ ¢ @ E § 7 @

¥

s

on;

and

off:

7 @

s

,

off;

on:

in terms

§ 7

@

7

52

CHAPTER 3. NETWORK THEOREMS

R1 I – V + R2
Figure 3.22:

R3

V2

+

R1 V + – R2

R3

Figure 3.23:

V1

+

R3 R2 R1

– V +

Figure 3.24:

53

Superposition:
@

Exercise 3.17 Find the Th´ venin equivalent of the circuit in Figure 3.25 at the terminals e indicated.

R1 v
+ -

R2 I

Figure 3.25: Solution:

R1 R2

Figure 3.26: To ﬁnd
¢ @

, shut off 2 sources:

To ﬁnd

, use superposition:

¥

@ ¥ 7 @ ¥ s @ § ¨¥ @ ¥ 7 #¡ ¤¢ @ ¢ ¥ @ ¥ 7 #¡ s @ @

¥

£ ©D

¡

¥

¢C

s

@ 2§ ¤@ ¢

£ ©D

¡

C

DC

¢¤

s

ANS::

i
+

R3 v
-

R3

¥

@%¤¢ s @ ¥ 7 @ 7 ¢ 3 7 @

s

3

¥

@ ¤¢ 7 @ ¥ ¢ @ §¢ 7 @ ¢

¥

C¤ D D

¥

@ ¥%¤¢¢ %§¢¢ @ 7 ¥ @ @

D 3 7

s

7

@

§
U@ s

@

3

£ ©D

s

¡

§ E

D

D 3

¨ D©

§ E

7

on; s

and

off:

54

CHAPTER 3. NETWORK THEOREMS i1 V oc – + R3 i2 R1

I

R2

Figure 3.27: 1.

2.

V

+ -

R1

R2 R3

+ V oc –

Figure 3.28:
3

Exercise 3.18 In the circuit shown in Figure 3.29 there are 5 nodes, only 3 of which are independent. Take node as a reference node, and treat nodes , , and as the independent nodes. s ¡
¡

a) Write an expression for

, the voltage on node

, in terms of

,

,

, and

¢

9

¤

ANS::

,

¥

¥

@ ¥ 7 @ ¥ s @ § @ ¥ 7 #2¥ 3 7 @ s @ @¡

¥

¥

@ ¥ 7 @ ¥ s @ ¥ @ ¥ 7 #¡ @

C £ § ©D ¢ C ¢ D ¢ ¢ ¤ x D C £ ¤D D ¥

¥

Shut off :

¥
.

@ ¥ 7 @ ¥

3 7 @s @

3

¥

@ ¥ 7 @ ¥ s @

7 @

Shut off

§

s

@ 3 s 2§ 1

s

D¤ D §

§

@

Q¨

§ s1
9 Q¨ ¨ D© ¨ D© #

£ § ¤D ¢ ¢ C D ¢ ¤¤ £ ©D D ¥

C

D ¢ D § ¤@

:

55

R1 R2
A B

R3

V1
C

+ -

D

R4

R5
E

R6

Figure 3.29: b) Write a complete set of node equations which can be solved to ﬁnd the unknown voltages in the circuit. Do not solve the set of equations but do group them neatly. Solution: s a) b)

Exercise 3.19 Consider the circuit in Figure 3.30.

50 Ω 100 Ω

25 V
+ -

i A’ + v A’

0.5 A

300 Ω

Figure 3.30: a) Find a Norton equivalent circuit for this circuit at terminals

.

s

¤

¤

d

@

¤

¡

s

,

¡

¥

¥

¥

¥

3

7

& @

s

¥

s

ANS:: (A)

(b)

,

¥

F3 7

&B§ I 3 & T@ S§

& ¥ & s I & @

¤

¥ s & ¡ ¥ & @ F3 7 & @ ¡ F3 ¥

s

s

¥

&

¥

§ I 3 ¥ d & ¥ & ¥ s r¡ ¥ & @ ¡ 3 s & 7 &¡ 7 &B§ 9 & @ ¥ ¥ & ¥ & ¥ r2¥ ¡ 3 2§ I s & @ ¤ 3 7 & @ ¡ 3 H & ¥ 7 & ¥ ¥
& U¥

¥

&

¥ s r¡ &

¥

7 & & § 9 & @ ¥ ¥ & ¥ & ¥ r¡ ¥ I § 9

¥

¥

¥

¥ 96§ I s & T@ & T@

¥

&

¡

56

CHAPTER 3. NETWORK THEOREMS
b) Find the Th´ venin equivalent circuit corresponding to your answer in Part a). e Solution: a)

Current divider:
2 SF3

From this, one can ﬁnd the short-circuit current:

b) The open-circuit voltage was found in the previous part.

Exercise 3.20 Measurements made on terminals of a linear circuit in Figure 3.31(i), which is known to be made up only of independent voltage sources and current sources, and resistors, yield the current-voltage characteristics shown in Figure 3.31(ii). a) Find the Th´ venin equivalent of this circuit. e b) Over what portions, if any, of the i-v characteristic does this circuit absorb power. Solution:

¤

@

¥

ANS::

,

Volts,

Amperes

¥
¦

2a ¤ "(#¡

!£ ¥£ 7 I¦D8)

3

¢ 02

! E ¦£ I

¢ (0V
¤

& ` 0W§

¤ ¥£

¥¦0) ¦(0V ¥ V (0@

& ` 0W§

V

¥¦02 ¥ 0) ()

& ) §

I

Q¨

¢ ¤@

¨ D©

T § V ¢ ¥ G( ((F§¢ (02 ¥ () ¡ § ¤@ ¢ §

¢

¥ V ¦((63

F

& 7 ) §

§

Q¨ ¨ D©

T G()E§ ¤@ ¢

57

i (mA)
40 30

V

+ -

i I
+ -

20

B B’

-4 -3 -2 -1

v

10 1 2 3 -10 -20

4 5

v (V)

R (i)
Figure 3.31: a) (voltage when current,

-30

(ii)

We ﬁnd

b) In quadrants 1 and 3, the product within this range. ANS:: (a) Exercise 3.21
V R@

is positive. Thus, the circuit absorbs power

Volts,

, (b) In quadrants 1 and 3

a) Write in standard form the minimum number of node equations needed to analyze the circuit in Figure 3.32.

R2 v + R1 R3 i4

R5 R4 I

Figure 3.32:

T 2 ¢§
¤

§ 1
V

a

§

T 2 G0¢E§ ¤@ ¢

3 1

£ E 7 ¤W!

§ ¤@ ¢ 42§ 3 1
¥ £ ¡ ¦¤¢

! E ¦£ F §

@ V ¨ D©

§

D¨

)

¥

¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¡ ¥ & &

& @

§ 1
£ @

§ ¥

s

7 ¡ £

¥

& & ¥ & 7& ¥ & 7& ¥¦¥ & ¥ 7 & ¡ 3 ¥ & 3 7 & 3 0R3 ¡ & & ¥ & 7& ¥ & 7& ¥ ¥ & ¥ 7 r¡ 3 ¥ ¥ & 3 7 TE3¡ @ & & 3 ¥H & & ¥ 7 & & ¥ 7 & r¡ 9 & & 3 7 7 ¥ & ¥ &r¡ ¥ U@ ¡ & @ H & & ¥ & ¥ ¥ 7 & & ¥ 7 & & §
& &

7

¥

¥

¥
&

¥ 7 &

¨¥ & @ §

¥

& @ T¡ £

7

¥ T3 s £ &
¡

§

¥7
£

¡@
@ s

£ ¡

¥ @

¥
£

¥7

@ 7 & @

§

&

7
£

¥ ¥ & @ 7 & ¡ s £ @
¡

2§ ¥

s £

¡@ 7 3¡ ¥ ¥ ¥ £
@ s

¥

s £

¡@
@

£

£

7 3¡ £

§ 1
a)

58

b) Determine explicitly the current .

1

Solution:

Thus we need to ﬁnd

V

+ -

,

s

7

b) We ﬁnd that:

@

7

&

7
£

& r¡

§

s £

@
@

#¡ 7
:
£ s

£ @ £
¤

7 @
:

s

(2) At
0¡

(1) At

, etc.

Node equations:
.

R1

Figure 3.33:

R3

R2

CHAPTER 3. NETWORK THEOREMS

e2

e1

R4

i4

R5

Standard form:
I

D § s &

59

Exercise 3.22 a) Find the Th´ venin equivalent of the circuit in Figure 3.34. e

R3

I

R7 A

R1

+ v -

R4

R6 A’

R2

R5
Figure 3.34:

R8

b) Find the Norton equivalent of the circuit in Figure 3.35.

R1

R2

1 R4 1

I

+ -

v

R3
Figure 3.35: Solution:
¢

s

b)

, since no current ﬂows through

@

C £©D ¢ D § I ¥ @ ¥ 7 @ ¡ ¢§©¡2§ ¤@ ¢ @ ¢ @ )3 § D¨

¥

d

d

a)

, since the current source cuts off the subcircuit to its left, for the purpose of determining the Thevenin resistance.

7

7

ANS:: (a)

, and

§ ¥ & @

¥

& ¡ £ @

¥ & 3 s £

@ 7 & @

§

&

£

C §§ C £ ¢ £ C ¢ £ ¢ ¥ x ¢ £ x x ¥ ¥ & @ 7 T¡ s £ & @

, (b)

¤

@ ¥

@ ¥

@ § ¤@ ¢

C

¥x

§ 1

60
¢

CHAPTER 3. NETWORK THEOREMS d d

ANS:: (a)
`

and

, (b)

Exercise 3.23

a) Find the Norton equivalent of the circuit in Figure 3.36.

I

R4

R6 1

R1

R2

R3

v

+ -

R5 1 R7

Figure 3.36: b) Find the Th´ venin equivalent of the circuit in Figure 3.37. e

I

R4 A

v

+ -

R1

R2

R3 A’

Figure 3.37: Solution:
¢

b)

¢

d

¢

d

ANS:: (a)

,

, (b)

,

§

¨ D©

@ 6¥ ¥

¥

@ §¢ 7 @ ¡ ¢

§ ¤@ ¢

¥

@ ¥

@ #¡

`

§

@ ¥

¥ %¤¢ 7 #¡ § D¨ @ ¢ @ @ ¥ ¥ %¤¢ 7 @ ¡ § ¤@ @ ¢ ¢

¥¢ @ ¥

¥

@ § ¢ @

¥

d

d

a)

¥ @ ¥ 7 @ ¢§¢ ¡ ¢

¥

@ ¡§

¢ ¤@

@ 53 §

¨ D©

¤

@ ¥

@ ¥

¥ @ ¥ 7 #¡ @ @ § ¤@ ¢

, and

¥

@ ¥

@#¡ ` § @ 2§ ¤@ ¢

¥

¥

@ ¢ %¤¢ 7 @ ¡

§

F

61 Exercise 3.24 Find the Th´ venin equivalent circuit as seen from the terminals e Figure 3.38.

10 kΩ a 10 mA 10 kΩ b 2V

+

Figure 3.38: Solution: By superposition,

ANS::

,

Volts
#

Exercise 3.25 Find the node potential

in Figure 3.39.

8 kΩ

1V E + -

5V

+ -

8 kΩ

0.4 kΩ

2.5 mA

Figure 3.39: Solution: ANS:: 2.4 Volts
a H (

, by superposition.

¡@
4

in

! E ¦£ F

H

§

£ ¤S)

H

¥ H)

¢
¥

@ S ¡

¥ ¡ T H)I§¢ T H) ¥ ¢

B§ Q¨

§

T

92 S a

¥

§ T H)I§¢ T H) § ¤@ ¢ ¢
) ¤ 9) H¡a

T

2 St§ ¤@ ¢

¡ § ¥

Q¨ H¡a

§

#

62

CHAPTER 3. NETWORK THEOREMS

Exercise 3.26 For the circuit in Figure 3.40, write the node equations. Do not solve, but write in matrix form: source terms on the left, unknown variables on the right.

R1 R3

V + -

R2

R2

Figure 3.40: Solution:

+ R1 R3

V – va R4 vb R2 I

Figure 3.41: (1) (2)

ANS::

, and

Solution: Superposition: 1.

2.

¥ s §¢ 7 @ ¡ 3 § @ ¢

off,

on

s

Exercise 3.27 Find

by superposition for the circuit in Figure 3.42.

¥

&

¥ r¡ ¢ ¥ ¥ T¥ ¥ § @ Y3 & & @¡ &

¥

¥

¥ & ¥ & ¡ ¢ ¥ ¥ T¥ ¥ § @ TS & @ ¡ & 3 ¥ 7 & ¥ s rF¥ 2§ s TS &¡ & 3

& @ ¥ Y3 ¢56H &

& R3 ¢

¥

@

¥

&

¥ 7 & ¥ s & G¥ 2§ s Y3 ¡ &

¥

63

v1 R2 I R3

R1

+ -

V

Figure 3.42:

vi I R3 R2

R1

Figure 3.43:

vi R2

R1

I

R3
Figure 3.44:

vi I R3 R2

R1 + V

Figure 3.45:

64

CHAPTER 3. NETWORK THEOREMS
R1 + R3 vi R2

V

Figure 3.46:

Problems
Problem 3.1 A fuse is a wire with a positive temperature coefﬁcient of resistance (in other words, its resistance increases with temperature). When a current is passed through the fuse, power is dissipated in the fuse, which raises its temperature.

I0

Figure 3.47: Use the following data to determine the current at which the fuse (in Figure 3.47) will blow (i.e., its temperature goes up without limit). u ¢C

DC

¢¤

¢C

CD

ANS::

Fuse

¢

7 @ ¥ 7 @

s

@

7 @ ¥ 7 @ 3 S ¥ s @

¢

7 @ ¥ s @ 7 @ s @

D

§ D S ¥ 3

3 §

¢¤ D § D ¤ D 3

on,

off

65 Fuse Resistance:
£ $ 1

Temperature rise: £W!¢Ch 1 ! ¥£ ¡ 7 $ 1 X ££(4D7 )!81 X ¦¢ ¤7 ¢7 U§ s § ! £ ¦£ (4 ¡` £W9¥e&q£ ! £ X §
¡

Solution:

ANS:: 15 amps Problem 3.2 a) Prove, if possible, each of the following statements. If a proof is not possible, illustrate the failure with a counter-example and restate the theorem with a suitable restriction so it can be proved. i) In a network containing only linear resistors, every branch voltage and branch current must be zero. ii) The equivalent of a one-port network containing only linear resistors is a linear resistor. b) To demonstrate that you understand superposition, construct an example which shows explicitly that a network containing a nonlinear resistor will not obey superposition. You may select any nonlinear element (provided you show that it is not linear) and any simple network containing that element. Solution: a) i) This is true. Assume that there is a nonzero branch voltage. That must cause a nonzero branch current, due to the relationship of a linear resistor.

1

@ 1

£

) H4

£ ¢ C

4R£¢!81¥ 9D(I¦D8¦£ § £ ¥ C£ 4 ¥ £ 7 ) !£WIeq£ ` T £ ¥ & § X T) ( a R4 U¨S@ ) A 4 ¥ §

!

¡

u 2¦ § 7 ¥4 T ¢ @ C s ! A ¨s§ ¥ ) § S@ u )A @ 7 ¥U¨S@ ¢4 ¥ § ¢4 ¥ § ¦ ¥U¨S@

!

!

) A

¡
!

7 ) 2 8H4 ¢§

¥

¤

¢ £

u

¢

66

CHAPTER 3. NETWORK THEOREMS
Therefore the resistor consumes power. Something must be producing this power, but linear resistors cannot produce power, so our hypothesis falls apart. Therefore there are no nonzero branch voltages or branch currents. ii) This is true. This is the mathematical deﬁnition of linearity.

i

i = Kv3 v Figure 3.48: b) Consider the nonlinear resistor with the relation shown in Figure 3.48, which is given by . Let a voltage be applied across the resistor. A current ﬂows through the resistor. Similarly, a voltage produces a current . Suppose a voltage is applied. The relation tells us the resultant is . However, superposition tells us is , which in general is not equal to what the relation says. in Figure 3.49. Solve by (1) Node Method, (2) Superposition. All Problem 3.3 Find resistances are in Ohms. u 2Ω 8V + 4Ω 6A

2Ω + 6Ω V0 Figure 3.49:

Solution:

¥1

@

@ h1

1

7

¥ 7 ¥ s 7 ¥ s §

¥

@

1

s

7 ¥ ¥ ¥ ¥¥ ¥ ¤§ 7 1 ¥ 1 ¤¡ ¢§ ¥ 1 ¥ ¥7 £§ 7 1 ¥ ¢§ 1 s s s s

¥ ¡§

1

67 (1) Node Method Label the nodes
£ s

2Ω

8V

+ -

4Ω

By the node method, we obtain the following two equations:

Thus,

(2) Superposition Find the voltage due to each source independently, as shown in Figure 3.51 and Figure 3.52.

2Ω

8V

+ -

4Ω

Figure 3.51:
V %H a V

ANS:: 8.57 V

¦ (2 a

§

§ ¥ ¨!

¤ ! C ¨

§

) A

! !

7

7

and

¨

¨ d¤

¥

¢ 2 a & #¡ ! ! ¨ ! ¨ !

£

as shown in Figure 3.50.

e1

2Ω

e2 +

6A

6Ω

Vo
-

Figure 3.50:

¢ 2 a

¤

§ & ¥

¨ £ £ ¡¡ ¥ ¢ 7 ¨ £

§ 7

£ ¢ ¤ H¥ ¡

§ 7 t§ u £ 7 ! C ¨ d @ C ! ¤ ¨ ! ¤ © ¨ @ ¤ ! ¨ 7 u

¥ s u t§ & #¡ § 7

%

¤

¡ §

s u

u

u

¤

2Ω + 6Ω Vo1 -

8Ω

8 -- Ω 3

68

CHAPTER 3. NETWORK THEOREMS
4 -- Ω 3 2Ω 2Ω + 4Ω 6A 6Ω 8Ω

Vo2
-

Figure 3.52: Problem 3.4 Consider the ﬁgure you used for the previous problem (Figure 3.49). Find the Norton equivalent of the network as seen at the terminals on the right. Solution: Remove the sources to ﬁnd

The Norton equivalent is shown in Figure 3.54. ANS:: 2.14 Ohms and 4 A Problem 3.5

!

) A

a ¦ e

¡¢ @
2Ω 4 -- Ω 3

, as shown in Figure 3.53.

2Ω + 4Ω 6Ω Vo -

Figure 3.53:

§

§

!

¤ t§

¨ £ ¢ 7 ¥

£ ¢ 7 §¢ d

¥d ¡ ¨ ©¢A D §

!

¥ § ¦¡ ¡ A D § ¤1 £ ¥ ¦

§ ¢¤@ ¢ ¨ d¥

69

+ 4A 2.14Ω Vo Figure 3.54: a) Find , the equivalent resistance “looking into” the terminals on the right, of the circuit in Figure 3.55.

b) Find the Th´ venin equivalent, looking into the terminals on the right of the circuit e in the ﬁgure in Figure 3.56.

1A

Solution: a) See Figure 3.57.

2 %9 a

§

! ¨ !

¢7 ¨ 7

¥

! ¨ !

¤ ¤

¢7 ¨ 7

! ¨ !

¤

£¨ s ¢

b) Check out Figure 3.58. s C

¥

¤

¡¥ PH%!

) A

#¡ §

) A

Q¨

E§ ¢¤@ ¢

§ ¢¢

@ 2§

@

R

R

R

R

2R

2R

2R

Req = ?

Figure 3.55:

1Ω 2Ω

1Ω 2Ω

1Ω
+

1Ω

2Ω

Vo
-

Figure 3.56:

¡

@

70

CHAPTER 3. NETWORK THEOREMS

R

R

R
+

R

2R

2R

2R

Vo
-

2R

R

2R
Figure 3.57:

R

2R

R

1Ω

1Ω

1Ω +

1A

1Ω

2Ω

2Ω

2Ω

Vo
-

2.05R

1.05R

2.2R

1.17R

3R

Figure 3.58:

71

Problem 3.6 Find for amps, volts in Figure 3.59. Strategy: to avoid numerical errors, derive expressions in literal form ﬁrst, then check dimensions.

I

2Ω
+

3Ω 2Ω

vi
-

2Ω

Figure 3.59: Solution: Use the node method. Label the nodes as shown in Figure 3.60.

I e3 2Ω
+

3Ω e2 2Ω

e1 2Ω

vi
-

Figure 3.60:

& 02

@

§

s

£

Solving with

and

:

T T 0 ¥ § ¥ ¥ T 0V T (V T 0 §9¥ ¡ £ @ ¥ ¥ T0 7 £ @ ¥

@

¥

§

T(V T 0V 7 ¡ U¥ £ £ @ T T ¥ ¡ 7£ ¥ ¥ ¡ T0 T 0 s ¥ ¡ £

Node equations:

§

¥

§ SSE

V

§

s

V ¤ B§

£ R@

ANS:: (a)

(b)

2Ω

2Ω

) A
+ -

E§

¡¢ @ 9S a § ¢¢ 2

8@

§

@

V

+ -

V

72

CHAPTER 3. NETWORK THEOREMS

ANS:: -2.95 V Problem 3.7 For the circuits in Figures 3.61(i) and (ii): s a) Find b) Find

for for

.

A A R1 V
+ +

R vo
-

R1 V
+ -

R
+

vo

R B

R B

R (ii)
Figure 3.61:

(i)

Solution: a) By symmetry,

in both cases.

b) For (i), we can use two voltage dividers: Note that the

case reduces to part a.

For (ii), we must use the node method (See Figure 3.62).

c) Find the Th´ venin equivalent for the network to the right of points e .

¤

2 a 9H e

@

& 02

Thus,
@

§

§ 7

¥

£ £

§ s £

§ § ¨ @2§ 7 ¥s @ § @ § s @

@

s
¤

D ¢ D¡ D

@ @

, assuming

@ §

§ ¨

s

@

R
-

R

73

A R1 V
+ -

R R
+ -

e1 R B

vo

e2 R

Figure 3.62: s 7 D¥ ¢ D £ D D ¥ § £ @ t§ ¨ ¤ § C D ¥ § D C ¥ D C ¤ ¤ ¤ ¤ § ¥D ¥ C D ¥ ¥ D ¥

So,

c) By symmetry, no current ﬂows across the middle resistor for (ii), so we can replace it with an open circuit. Therefore, cases (i) and (ii) are identical. The equivalent resistance of the four resistors can be easily found, so in both cases, and .

Problem 3.8

a) Determine the equation relating to

i + v -

1Ω 2Ω

Figure 3.63: b) Plot the i-v characteristic of the network. c) Draw the Th´ venin equivalent circuit. e d) Draw the Norton equivalent circuit.

D

¥

1

7

¤

ANS:: (a)

b) i)

ii)

c)

.

in Figure 3.63.

4Ω 2A 3Ω

@ S§ ¡¢ @

2§ ¢¢

82§ @

¢ ¢¤@

§ ¤¤ D ¥ ¢

D D¥

¥ s

§ ¤¤

@

¥

D ¢ D¡ D

2§ ¢¢

74 Solution: a) See Figure 3.64.

CHAPTER 3. NETWORK THEOREMS

+ v 2Ω 2A 7Ω

i

2Ω

2A

7Ω

Figure 3.64:

Hence, by linearity, b) See Figure 3.65.

-3.11V

29"a(#¡ 2 s

In (ii),

, so

¤ ¢ ¨ ¤

In (i),

, so

i

1.22A

Figure 3.65:

V R( a R@

R( a V 1 %! A @ ¥ ) ! ¨ a ¤ ( S§ ! ! §¨ ¢ ¢ 7 ! ¨ ¢¥ !

§

¨ 7¥ ¥
¥
¤

¤

#¡
@

§ R

#¡ § 1

§ 5

§ 25

2§ 1

.

.

v

75 c) See Figure 3.66.

2.56Ω +

i +

3.11V

v
-

Figure 3.66: d) See Figure 3.67.

i + 1.22A 2.56Ω v
Figure 3.67: ANS:: (a)
¢( a V @ 1

Problem 3.9 In Figure 3.68, ﬁnd

1Ω + 6Ω

Ao V

Solution: a) See Figure 3.69. Find the voltage due to each source. So,

¡

¥ !

) A

S2 ( 5 2 a ¡ §

via (a) superposition, (b) the node method.

2Ω 4Ω

i + vo -

8A

Figure 3.68:

76

CHAPTER 3. NETWORK THEOREMS

1Ω

2Ω

i +

3Ω

AoV

+ -

6Ω

4Ω

vo1 -

6Ω

1Ω

2Ω

i +

6Ω

8A

4Ω

vo2
-

6 -- Ω 7
Figure 3.69:

6Ω

Problem 3.10 Use the following three different methods to ﬁnd in Figure 3.71:

1

§
¤

!

s
¡

¨¦

¦7 ! E ¦£ F" @ ¡ § 7 t§ ¨ £ 7 ¨ ¤¨ § ! C © @ C ! § d 7 @ ¤ ! C ¨ ¥ !¤ ¨ @ ¤

! E ¦£ F" ! E ¦£ F
77

¦7

@
¡

§

¦7 ! E ¦£ F" @ ¡ § 7 ¨ ¥ s ¨ § v d § ¥ ) ¨! A R¡ ! ¨ ¢ ¥ ¤ § 7 @ ¡ ! ¨ v s ! © ¢ 7 ! ¨ ¢ s ¥! E u ¡ ! ¨ © ¨ ! ¨ ¦£ I" ¤ §

¥¥

b) See Figure 3.70.

1) Node Method

3) Alternate Th´ venin/Norton Transformations e 2) Superposition
@
¡

ANS::

AoV

+ -

6Ω

volts

1Ω

- +

3V

6Ω

6Ω

i

Figure 3.71: Figure 3.70:

3Ω e1 8A 2Ω 4Ω e2 i

3Ω

2A

¦7

Vo
+

-

¨ ¨ ¨

78

CHAPTER 3. NETWORK THEOREMS
3V e1 - 3V - + i 6Ω 6Ω 3Ω 2A e1 e2

3Ω

Figure 3.72: Solution: 1) See Figure 3.72. From the node diagram, we get:

2) See Figure 3.73. From each source, we get:

So,

3) See Figure 3.74. “Nortonize” the parts of the circuits on either side of the wire whose current we are ﬁnding, and simplify: So,

ANS:: .5 amps

Problem 3.11 A student is given an unknown resistive network as illustrated in Figure 3.75. She wishes to determine whether the network is linear, and if it is, what its Th´ venin equivalent is. e The only equipment available to the student is a voltmeter (assumed ideal), 100 k and 1 M test resistors that can be placed across the terminals during a measurement (Figure 3.76).

T

!

7 ) 4 8H%2 a

§ !

) A

!

7 ) 4 V V 8H%9SV a

& ¥

!

V ) ¢! A

7 ) 864

§

! 78)H42 a ! ¨ d ¢d ! ! ¨ d ! !

¢

& a §

V

4 ¥ ¥ I9QS` !

d ¢ ¨ ¥ ¤ ! ¨ d d ¨ d¢ !

§ 1 ¥ s 16§ 1 #¡ § 7 1

7 ) 4 a ¡ 8H92 SP§

¨

¥¥

d

So,

2§

¤ ¥

¤ ! 78)H4 "a § ! ¥ ¨ § 1 2 § C ! ¨ ¤¥ ¥ ! C ¨ @ ¤ d ¤ ¤ ¥ ! § ¨ @ ¥! C ¨

¨ ¥
! d

¥

¥

¥¨

1

T

¥

§ s1

79

3Ω 3V - + i 6Ω 6Ω 3Ω

6Ω

3Ω

3Ω i 6Ω 6Ω 3Ω 2A

3Ω

6Ω
Figure 3.73:

80

CHAPTER 3. NETWORK THEOREMS

3V - + i 6Ω 6Ω 3Ω 2A 3Ω

i .5A 6Ω 6Ω 6Ω 1A

i 1.5A 3Ω 6Ω

Figure 3.74:

Resistive network

Unknown network
Figure 3.75:

81

Resistive network

+ V R Test resistor V Voltmeter

Unknown network
Figure 3.76: The following data were recorded: Test Resistor Voltmeter Reading Absent

What should the student conclude about the network from these results? Support your conclusion with plots of the network v-i characteristics. Solution: Let us assume that the network is linear and that the Th´ venin equivalent voltage of e the network be denoted and resistance . Without the test resistor, the measured voltage of 1.5V is the open circuit voltage. Thus . With a 100k resistor, the voltage measured across the test resistor is

Thus

. ¡6¥ S(02 a ¡5S2 S

With a 1M resistor, the voltage measured across the test resistor is
¢§

This is corroborated by our measurement. Thus, the network is a linear network, and can be represented by and . Problem 3.12 a) Devise an electrical circuit of voltage sources and resistors that will “calculate” the balance point (center of mass) of the massless bar shown in Figure 3.77, for 3

¡¢ @ ¥ H( 2a S() 9"S

¢ ¡¤@

§ 2 a GS (

¢ ¢¤@

¢¢

a S 2 9 a a 2 S

¢¢

H(2

a S2 S

§ ¢¤@ ¢

§ ¢¢

T ¡ T H()

82

CHAPTER 3. NETWORK THEOREMS arbitrary masses hung at 3 arbitrary places along the bar. We want the circuit to generate a voltage which is proportional to the position of the balance point. Write the equation for your network, and show that it performs the required calculation. (Work with conductances and superposition for a simple solution.)

Mass A

Mass B
Figure 3.77:

Mass C

b) Extend your result in part a) to two dimensions, that is, devise a new network (which will have more voltage sources and more resistors than above) that can ﬁnd the center of mass of a triangle with arbitrary weights handing from its three corners. The network will now have to give you two voltages, one representing the x coordinate and the other the y coordinate of the center of mass. This system is a barycentric coordinate calculator, and can be used as the input for video games, or to simulate trichromatic color vision in the human eye. Solution: a) See Figure 3.78.

+

G1

G2

G3 vo

v1

+ -

v2

+ -

v3

+ -

Figure 3.78: The center of mass of the bar is given by the equation , where and are the mass and position of the hanging object, respectively. Analogously, in Figure 3.78, the conductances represent the masses, and the voltages represent the positions. Thus, , as needed.
!

¥ ! C¢ C C ! ¢ ¤ ! £ ¥ ! ¢ ! ¢ ¤ ¡¤

!

§

§

£

¥¥

¢

¢

¢C

1

¢ C C ¢ ¢ ¤ ¤ ¢ ¤ ¢ ¢

¢

§ ¨

§

)

83 b) See Figure 3.79.

+ G1 vox v1y Figure 3.79: Similar reasoning as in part a. Problem 3.13 . a) Find the Th´ venin equivalent for the network in Figure 3.80 at the terminals e The current source is a controlled source. The current ﬂowing through the current source is , where is some constant. (We will discuss controlled sources in more detail in the later chapters.) ¡

+

G2

G3

G1

G2

G3 voy

+ -

v2y

+ -

v3y

+ -

v1x

+ -

v2x

+ -

v3x

+ -

Vs + -

b) Now suppose you connect a load resistor across the output of your equivalent circuit as shown in Figure 3.81. Find the value of which will provide the maximum power transfer to the load. Solution: a)

¡s u )@ ¨¥ ! ¨ §

¢

£@

£

¢

@ ¡

¥ !

) A

¢

%( P¡

!

) A

H()E§

s

§

¢

I1 10 kΩ

+

C

βI1

100 kΩ B

Figure 3.80:

D¨

6§ ¢

¢ ¢¤@

84

CHAPTER 3. NETWORK THEOREMS
RT VT + B
Figure 3.81: b)

C RL

ANS:: (a)

,

(b)

Problem 3.14 You have been hired by the MITDAC Corporation to write a product description for a new 4-bit digital-to-analog-converter resistance ladder. Because of mask tolerances in VLSI chips, each resistor shown in Figure 3.82 is guaranteed to be only within 3% of its nominal value. That is, if is the nominal design resistance, then each resistance labeled R can have a resistance anywhere in the range and each resistance labeled 2R can have a resistance anywhere in the range . You are to write an honest description of the accuracy of this product. Remember that if you overstate the accuracy, your company will have many returns from dissatisﬁed customers, whereas if you understate the accuracy, your company won’t have any customers. NOTE: Part of this PROBLEM is to describe what the problem is: How should accuracy be speciﬁed? Is there an error level that is clearly unacceptable? Does your product avoid that error level? Is there an obvious “worst case” that can be easily analyzed? Have fun. And remember, common sense is an important ingredient of sound engineering. Solution: There are several approaches to this problem. This approach analyzed the circuit piece by piece to determine the effective error we can expect from the circuit.
¢

Accuracy of

: high:

, low:

.

So the error for 2

resistors in parallel is 3%.

u

Given: 3% tolerance, implies that

,

.

u

u

@ & a ¦¥ 0 t¢#¡ @ V P¥ S a ¡P¡

@ & ¦¥ 0 a

a 2§I aS §¢ I S ¢ a V a § & a ¢ & a S SF( ( §¢ 0 ( § @ S u P¥ S a £P¡ § @ @ V

¢#¡

§ 2¢¡

¢ @ ¤2§

¥ ¥ ¡@ ¡@

¥ ¢ #¡ @

u

¡ )@ § ¢

@

¢

@ ¡0
@

7 ¥

To maximize , we write to equal to zero. So,

as a function of

7 ¥

£@

¡@

¡ ¡ @ § ¥ ¤@ 4¡@ 7 ¢ § 7 ¥ D ¡ ¢ ¢D Q 2S@ 7 § ¢ ¡

and set its derivative with respect

¡@

T H()§ ¢¤@ ¢

¢ ¤@ § ¥ ¤#¡ 7 ¢ t§ ¥ ¢ @

@ @ ¢ @ 0 ¤¢ 0

¡@ ¡@ ¡ ¡@

¤

¡

85

R
2R 2R + -

R
2R + -

R + 2R 2R + -

2R v1 v2 v4

v8

+ -

vA
-

Figure 3.82:
¢

So the error for 2

resistors in series is 6%.

R

R

R 2R + 2R vA -

2R

2R

2R

2R

+ -

(a)

2R
(6%)

+ + v8 (b)
Figure 3.83:

R
(3%)

vA -

First, consider the highest-order bit ( ) in isolation (see Figure 3.83(a)). We can simplify this circuit, keeping track of the effective errors incurred by taking the resistances in parallel and in series. The resulting simpliﬁed circuit is shown in Figure 3.83(b), with the effective errors of each resistor parenthesized.
¡

We can now ﬁnd the following voltage divider for cases (high/low) in resistance values:
VS a ¥¨ ¦0 a ¥ & ¨ ¥ V 9 a

, considering the extreme error

Va

2§

V S a V S a

¢

Accuracy of

: high:

, low:

v8

a I SE§

a

¥

a

@ V § ¨ ¥

& a ( (2§

¤

V a ¥ V a S S6¦S S

¤ @¤ § ¡¡

@

@ ¥ @

.

s

¥

(V a (S ¥ 2

¥

(#¡ a

§ s ¥
£ £

£

7 s £

3 7 3 £ 3 7 3 £ s £ s £ £

s s £ 3 ¡ § ¡¡ s s £ 3 ¡¡ § ¡

Va

(¢ ¥ 2

¥

2a

#¡ §

¥
¤

¥

£

7

86

Now consider the lowest-order-bit ( ) in isolation (see Figure 3.84. Again, we ﬁnd voltage-divider relations:

We can now ﬁnd the bit-conversion accuracies of the lowest-order bit:

¤ ¡¡
§ 7 s £ ¡¡

£ £

¥
§ s ¥

¥
£

¥
7 7

£ £ £ £

s

£

¥

§ 7 §

£ s £ £

§ ¡¡ § ¡
And by symmetry: s £

2 H a 2 ¢ 2 a

2§

s £ § § ¡ V9 a T @ s £ § ¡¡ ¥ V S a

s

Va

§

V S a V S a

¤ ¥¦V § ¡
@ T

Noting the similarity at

2R

e3

+ -

2R

v1

R

to Figure 3.83(b):

e2

Figure 3.84:

2R R e1

CHAPTER 3. NETWORK THEOREMS

2R R

R

+ vA

87 Generalizing to a bit of order :
© $

Now consider the circuit as a whole. The worst case error-wise will be when all bits are “on”. In this case:

Problem 3.15 You have a 6 volt battery (assumed ideal) and a 1.5 volt ﬂashlight bulb, which is known to draw 0.5 amps when the bulb voltage is 1.5 volts (in Figure 3.85). Design a network of resistors to go between the battery and the bulb to give volts when the bulb is connected, yet insures that does not rise above 2 volts when the bulb is disconnected.
2 S§ a

+ 6V ?

+ vs -

Figure 3.85: Solution: See Figure 3.86.

i W a

& §

2 S & a

2S(& a @ ¢

2a

Error low:

i 2 9"a

& §

2 S & a

29 & ( a @ ¤

(¢ a

Error high:

¤

¡

As a point of comparison, the error-free case is:

.

F3

F3

¢

¢ 0£a §

2a "(

§

2 F3 S & a

2¢ 2 a 2 ¢ 2 a

2H a 2 H a

2§

@f F3 @ T

@T 3 FF(V a @ T

¥

Va

©

§

§ 2¨¥

§ ¥

¥ ¥

¥ 2 (W ¥ 2 (S

2a ¡ 3 "(#"F V a (#"3 a ¡

¥

¥

2 ¢ 2 a

2 H a

¥ 7 ¢ 2

¥ 7

Va

7 § ¡ 7 2§ ¡
2 H a 2a

¥

¦H ¥ 2

2 2 ¢""a a

¨P"3 ¥ ¡ ¥ P"3 ¡

3 ¢F V a F3

(V a 2§ ¡

§ ¡

88

CHAPTER 3. NETWORK THEOREMS

6V

+ 2.25Ω

1Ω

3Ω

Figure 3.86: The resistance of the bulb is When the bulb is connected,

Note: This scheme is not very practical, but it is simple.

¡

When the bulb is disconnected,

7¤ 7 s 2H S§ ! ! ¨ ¥ s ¢ ¥ #R a &¡ § ¨ § ¦£¤§ £ ¦ ¤ ¥ § ¥ ¥ ¤§ ¤ ¢ ! ¨ ¥ 7 ¤ 7 ¥ %#¡ § £ %"aSE§ § ¦£¤§ £ ¢ §¨¦¥¦¤§ ¢ ¦ ¤ 2 & § £ § § ¦¤§ § ¥ £ ¥£ £ ¢ ¨£ ¦¤§ ¤ ¢ ! A t§ § ¡ ) V
.

@

Chapter 4 Analysis of Nonlinear Circuits
Exercises
Exercise 4.1 Consider a two-terminal nonlinear device (Figure 4.1) whose v-i characteristic is given by:

+

vA
-

Figure 4.1:
¡

Solution: 89

¥

(Hint: Substitute and Taylor Series, ignore second order and higher terms in and small signal terms.)
¡ ¡

¡ ¡

Show that the incremental change in the current ( in the voltage ( ) at the DC operating point
¡ ¡ ¡

) for an incremental change is given by:

in Equation 4.1, expand using , and equate corresponding DC

¥

1 2§

¥

¥

S¥

1

£

¡

¥ ¡ ¡
¥

£ ¤

A

¡

¡

§

¡ ¥ ¡ ¡

§
X
¡

X

1 § ¥1
¥

(4.1)

iA

1 S¥

§

¥

§
¡

1

¡

90

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

Taylor series expansion (at
X

): a a B¥ a

with:

, and ignoring high-order terms:
¥

Equating DC and small-signal components, we have: DC:

Exercise 4.2 Suppose the two-terminal nonlinear device from the previous exercise (Figure 4.1) has the following v-i characteristic:
£ ! ¡ ¥ £ W81 F¦DA

b) Find the incremental change in the current age at the operating point . c) By what fraction does
¡

change for a

percent change in
¡

d) Suppose the nonlinear device is biased at instead of , where is percent greater than . Find the incremental change in the current ( ) for an incremental change in the voltage ( ) at this new bias point. By what fraction is different from the calculated in part (b). e) Find the incremental change in the current for an incremental change in the parameter (given by ) from its nominal value of , assuming the operating point v-i values are .
¡ ¥

§

¥ ' '

¡

§¡

t§ ¡

1

¡

Hint: Observe that if

depends on the parameters

and

, in other words,

'

¤1

¤

¡

¥

¡

¥

¤1

'

¥

¥

1

¤

¡

¥

1

'

¡ ¡

¡ ¡

¡

a) Find the operating point current
¥

for an operating point voltage

, where

for an incremental change in the volt.

¡

£ )2§ ¥ ¡ ¤¡

¡

X $ 4 (

¥

£

¡

¥

£ ¤

A

¡

¡

¡

¡

¥ F¢

¡

X

Small-signal:
X

7¥

¡ U@ ¡

¤¡

¥
£

¥
¥

£ ¤

A 7¡

¡

¡

¡

¡

¡
£

7 X

¥

£ X ¤

§
£ ¤

A

¡

¡

¡

¡

¡

¡

¢¥

X

¥

¥ ¥

X

¡ 0¡

1 ¥
¥ ¥
¡

¡ U@ ¡

¡ 0¡ t§ ¥

§ ¡ 1 ¡¥ ¡ ¡ § ¡ 1

§

¡

¡
© ¨

§ ¥1

£

§

¡ ¡

¥

¥

¥ ¡

1 ¥

£ ¤

¡

A

¡ ¡ ¡ ¡

§ '¨ ¥ 7 ¡ ¦2§ ¥ ¡ ¡ ¥

¥

¡ ¥

¡

1

X

1

¥ ¥

¡ 3¡
¥ ¡

¡ U@ ¡ ¥

§ ¥1 ¥ 1

2§ §
¥

¡

¡

1

.

¤

¥1 ¥ ¨§ ¥1 ¥ ¡ ¡ § ¡ ¥ ¡ ¡ ¡ ¥ ¥¡ § ¥ P¡F¡0 ¥ ¡ ¥1

§

¥ ¦0 ¥ ¦0

¥ ¨ ¥ §
¡

¥

()
'

¤

¡ ¦0 0¥ ¥ ¡

§ ¥1

¤

¥ ¡ §

¤

¡

¥ ¥ ¡

§ ¥1

(
'

¥ ¨§

¥

§ P¥ ¡ ¥
¡ ¡ §

¡ f¦0 ¥

¡ H¥

(
'
¥

¥ ¥

£

¡

0 3
,
¥

P¥
¥

¡ ¨ §
¡

¡
¥

)3
¥

£

£

A
¥

T¥¦0 3 ¥ § ¥ 1 0 §

¡ ¡ §
£ ¤

A

¡

¡

¡

¥

¡

¡

©
¡

¡ §
¡

¥ 7 ¡ f¥
¡

¥

¡ 3¡

§
¡

§
a)

¥

¥
¥

¡ ¡ ¡ ¡ ¡

'

§

'
' ¡

¥ '

§¡

§ ¡¨
¡

¥

1

'

1

b)

X

d) Incremental change at new bias point:

¥ ¥

¤1

1
¥ ¡ ¨P§ ¥ 1
¥ ¥

¤ § ¤1
¡

¤

uu ws

¥ ¨ ¡ §

¢ ¤ £
¥

X

§ ¥1

c) For a y% change in

Solution:

Different from part (b):
¥

§ ¨ ¥ ¡ ¦0 ¥ uu ws ¥ ¡ ¡ ¦0 ¥ ¥ ¡ ¥ ¡ § uws u ¥ ¤¡ ¥ ¡ ¦0 2¥ ¥ ¥ ¡ § ¡ ¥ ¡ uu ws § ¨ ¥ ¡ ¥ ¥ )3 ¥ ¨ ¥ ¡ § § )3 ¥ ¨ ¥ ¡

¥

¤

¡

§

¥

¤1

1

then the incremental change in

so
¡

also changes by y%. This is expected since

for an incremental change in

is linear. is given by 91

¢a £(2

§

9

a B§
¢

1

a 2 S¢ (t§
¤

I 1

) a I¢ B§

@ 1
¢

¤

§

)9 a )6¥ 9 3 S@ § 1 a 3 01 @ H) I @

T 0) § @

9

1

1

@ 8

¥

¤

¡ f¦0 0¥ ¥ ¡

Exercise 4.3 The nonlinear device (NLD) in the circuit in Figure 4.2 has the acteristics shown. Find the operating point and for .

7¥ 3

¡ 0I3 ¡ ¥

¥ ¦2§ ©
¡

¥

1

B§ ¥ 1

¤

¡ ¡ §

¥

¡ ¡ ¥ ¡ 3"3 ¡

¥

¡ §
¡

¥ 7 ¡ ¡ ¥

7¥

¥ ¡2§ ¥ ¦

¥

1
At operating point:

¡ 7 ¥ ¡ "3
¥ ¦3
¡ ¡

§ §

¡ ¥ £

¡ 7¡

¡ ¥ ¢
¡ ¡ ¡ ¡

¥ ¦3

92

e)

¥ ¨ ©

¨ ¤¦#¡ § ¥

¥ ¡

§

¥

1

ANS:: (a)

(e)

Intersection of it and

©¦ § ¢ ¦ ¤ ¢

£

§ ¨

¥

£

¡ £ ¡ £

7

7 ¥ E§
¦

ANS:: KVL:

Draw this load line on graph.

Solution:

10 V

R

mA,

+ NLD vD -

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

iD

V (b) plot is operating point. Figure 4.2:

iD(mA)

10

5

0
¤¦ ¥

(c) y% (d)

5

10

vD (V) char-

¥ ¡ §

93 Exercise 4.4 a) Plot the vs. characteristics for the nonlinear network shown in Figure 4.3. Assume the diode is ideal.
¡

iA
+

vA
-

b) The nonlinear network from part (a) is connected as shown in Figure 4.4. Draw the load line on your characteristic from part (a), and ﬁnd .

1 kΩ 3.5 V
+ -

+ NLD -

iT

vT

Figure 4.4: Solution:

i A ( mA )
2 oper. point

1 slope = -------500 ad lo

1

1 slope = – ----------1000
4

1 slope = ----------1000

0.5

1

2

3

3.5V

Figure 4.5:

¢1

@ 1

¡

1

1 kΩ 1 kΩ 1V

NLD
Figure 4.3:

e lin

v A ( volts )

94

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

b) Load line: KVL:

Operating point occurs at intersection, and we ﬁnd that
) ¤ IS§

ANS:: (b)

mA

Exercise 4.5 Consider two identical semiconductor diodes, each of which has an relation:

(4.2)

a) Find the relation of to for the pair connected in parallel as shown in Figure 4.6a.

(a)
Figure 4.6: b) Find the relation of to Solution:

(b)

for the pair connected in series as shown in Figure 4.6b.

@

1

§ ¢

¥ )

¢ ¤2 a V @

@

(()

(()

@ ¦¡ ¥

¥ 0()P¡ ¢ 1

¡

: Diode off

¢ (0))§¢ (0)

¡

¢ £ A 3£¡

§

§ ¢1

¢1

¡

1

§
@
¡

§ 01

1
S2 a V

1

1

2§ ¢ 1

¡¡

¡

a)

: Diode on

95 a) The currents add, so the i-v graphs may be vertically added - so if the two devices are identical, the output is merely twice the output of each individual device, since we would replace the vertical coordinate with .

b) Here, the two devices are in series, so the voltages add. Since the two devices are identical, the horizontal addition is the same as replacing the original coordinate with .

Exercise 4.6 For the circuit in Figure 4.7, ﬁnd the input characteristic, versus , and the transfer characteristic versus . is ﬁxed and positive. Express your results in graphs, labeling all slopes, intercepts, and coordinates of any break points.
+

i i2 v R1 R2 I

-

Figure 4.7: Solution: Note: when diode is on,

as graph shows.
¤

C

D

C

D

ANS::

7 @ ¥ s @ s @ 3 7 @ s @ ¥ 7 @ ¥ s @¡ s @ ¥ 7 @ ¥ s @¡ 7 @ s ¥7 @ ¥ s

@ @ #¡

7 @ ¥ § 71 7 @ ¥ s @ ¥ s § 71 @ 3

But

1

¢

7 @ ¥

s

@

s

@

¥ 81 ¥ ¡ § 7 1

¢

§ 1

ANS:: (a)

, (b)

¢

@ @

¢

¢

7¢

¡

¢

¢

x £

x £ @

7

¢

3 F § 7 01 ¥ s 1 § 1

7 £ ¢

1

§ 1

x £

§ 1

@

¢

¡

¢ £ x

£

3 S§ 1

D

¢x¤

71

D ¥

§ 71

7

A

96

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS i2 ON

i
ON

I
OFF

slope = 0 1 slope = ---------------------( R 1 || R 2 ) I ⋅ R1 -----------------R1 + R2

1 slope = ----R2

V
1 slope = ----R 1
O FF

V
IR 2

IR 2
Intercept at

v = ( R 1 || R 2 ) ⋅ I

I
Figure 4.8: Exercise 4.7 For the circuit in Figure 4.9 and the values shown below, sketch the waveform of . On your sketch, show when the ideal diode is on and when it is off.

+

i

vi + Figure 4.9: Solution: Diode on: Diode off:

@ ` ¥

92

§ ¥£ 29¦¤¡ 1

¥ ¦¤¡ s 0§ ¦¤¡ 1 ¥£ ¡ ¥£

T § )2@
R Vo

S2

§ u

£

¢ £¡

¨

§ ¥£ ¦¤¡ 1

97

V 1 (+)
10 ON

t
-5 -10 OFF

Figure 4.10:

i (+)
15 5 -5 -10 ON OFF ON OFF

t

Figure 4.11:

98 ANS:: Diode on:

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS
; Diode off:

Problems

Problem 4.1 Consider the circuit containing a nonlinear element ure 4.12. The i-v relation for is given by:

R vI + N

iA + vA -

Figure 4.12:

b) Find the operating point values of the nonlinear element’s voltage and current for , where is positive.
¡

c) Find the incremental change in (given by ).

(given by

) for an incremental change in

d) Determine the incremental change in the voltage across the resistor mental change in the input (given by ).
¡

for an incre.

e) Find the incremental change in f) Find the incremental change in , .

for a 2% increase in the value of
¡

for an incremental change in

at the bias point

g) Suppose we replace the source with a DC voltage in series with a small time varying voltage . Determine the time varying component of .
¡

1

@

@

¥

1

1

¡

1

1

£ £0 § ¢ !

¡

¡

a) Solve for

and

using the analytical method.

£ W!

1

¡ ¥ £ F¦A

£ §

¥£ 2§ ¦¤¡ 1 as shown in Fig¡

1

X Y$ 4

¡

@ 0` ¥

¥ ¢

S2 u

¥ ¦£ ¡ s § ¦¤¡ ¤¡ ¥ ¥£ 1

¥

¡ s

¥ 7¡ 7 § 1
¡

1

t§
¡

¡

¤

! §

$ ¢ #!

¦

C

¦
¤

¥¢ ¥ C§¤ ¦A

! " # £

¥

¥¢ ©
£

¤

¢ s

¢
§

C 7

D § s

£ £

¥

A ©©

¢ D § ¥1 ¥£A ¡ § ¦¥ £
©

£ ¥

@

¤¡ s D

@ B¥ § s

¢¤

¤

¤¤

¤

£ ¤A ¡ s ¥ ¡ 7 0S§ £ © C C 7 § ¥ § s ¢ ¤ § ¢ A ¦ D C D¥ D¥ D C s ¢ ¤ D¥ © § C 7u s § ¢ ¦ C D 7 u sC ¥ 7 § ¡1 ¨ @ ¤¡ D s § D 7 u s ¥ £A D 7 u s ¥ D ¤ u C s ¢¤ D 7u s¥ © C C ¦ § ¢ ¥ £A ¥ £A D ¢ C D ¢ C s ¢ ¤ D ¥ © @ T § ¥ ¤ 52§ §A ¤ ¤ ¡ @ s ¦ ¦ ¤ @ H¥ 1 § C C ¦ § ¢ ¥ D ¢ C D ¢ C s ¢ ¤ D ¥ © T ¡ s D § £A ¤ ¥ @ s ¦ ¤ C § ¦ C § C D7 s ¢¤ ¢¢C 7 § ¡ ¢ D ¥ D C s ¢ ¤ D ¥ © D D C § s ¢ ¤ § ¢ ¦ D C 7 C § s ¢ ¤ © § ¡ D¥ D¥ D D¥ C C 7 § ¦ C 2§ ¡ % u F@ 1 C § s ¢ ¤ DD ¥ © s ¢ ¤ D ¢ ¢ A C D 7 § ¡ 1 ¢ A D ¥ D C t§ ¡ u F@ § s ¢ ¤ D ¥ § £A ¦ D ¥ D C 7 D C § s ¢ ¤ D ¥ © § ¡ ¢ C § £A ¦ C C § s ¢ D ¤ 7 © ¡ § s ¢ ¤ § ¡ ¢ D¥ D D¥ D¥ ¨¥H @ u F@#¡ ¥ ¡ ¥ s F#¡ ¥ I 7 F@ § ¥ @ 7¡ ¥ u ¥ ¡ s ¥ 7 ¡ 7 5@ @ § ¡ ¡ @ ¡1 @ § ¡

¥ ¥

1 1

@ ¡ 2§ ¥ 1 1

1
¡ ¡ ¥

( § ¥ § 1 ¥ ¡ § ¡1 volts. ).
¥

1 1

§

§

§

)§

¥

t§

h) Suppose we now replace

i) Find the bias point DC current

¡

iii) Find the value of

iv) Find the value of

ii) Find the value of

v) Now, ﬁnd the exact value of the

corresponding to

using the analytical method for

using small signal analysis. (Use

, where

corresponding to

using

¡

g) Incremental model of N is a resistor

¤

d)

b)

e)

¤

c)

a)

f)

Solution:

vi) What is the error in the value of

;

for

computed using the small signal method?

for

volt using small signal analysis.

;

volts and

.

otherwise volt. volts. 99

otherwise

Problem 4.2 The circuit shown in Figure 4.13 contains two nonlinear devices and a current source. The characteristics of the two devices are given. Determine the voltage, , for (a) amp, (b) amps, (c) (in amperes).

£ R 1 ! §

R 1 §

¤

¤¤

¤

¤

C § s ¦ C C § s ¢ ¤ © ¢ § wCs s D 7 ¦ C C § s ¢ ¤ © C 7 u D¥ D D¥ D¥ D D¥ D ¦ ¦ C ¦ ¤ ! § ¤ ! ¥¢ ¥ ! C§ ¤ ¤ ¥¢ © C C 7 D ¦ ¢D ¥ § ¦ @ s u s D ¥ C D C § s ¢ ¤ D ¥ © ¢ § ws D ¥ C D C § s ¢ ¤ D ¥ © C D 7 s ¦ ¦ C ! C ¤ ! § ¤ ! §¤ ¦ ¤ ¥¢ © ¥ ¢ ¥ C ¢D ¥ s § ws ¦ C § C D7 s § ¥1 s D ¥ D C s ¢ ¤ D ¥ © ¢ ¤ D ¢ C D 7 7 § ! ¡¦ 1 ! ¦ C ! C ¦ ¤ ¤ § ¤ §¤ © ¥ ¢ ¥ ¥ ¢ C C 7 D ¢ D § ¥1 ¥ s ¥ § ¦ § ¡1 u s D ¥ C D C § s ¢ ¤ D ¥ © s ¢ ¤ D ¢ C D u 7 ¦ C !C ¦¤ $ ¤ ! § ¢ #! §¤ © ¥ ¢ ¥ ¥ ¢ C £ ¦ ¢ D § ¥1 ¥ § s ¦ C C § s ¢ ¤ C D 7 © s ¢ ¤ ¢ C u 7 § ¡ A u D D D¥ © CD ¥ D C C 7 ¤ £ §A ¢ £ 7 § s § ¦¥ £ ¡ s ¥ ¡ 7 0 § £ © ¥ § s ¢ ¤ § £A ¦ D C D¥ ¢ D¥ D C s ¢ ¤ D¥ © C§ 7u s C 7 7u s § ¡1 ¨ @ ¡ D s @ ¡ sD @ ¥ § s ¤ 7 u s § £A ¦ D C ¥ § ¢ D 7 u s ¥ D ¤ u C s ¢ ¦ ¤ D 7 u s ¥ © C C ¦ §¢ D ¥ C C § ¢ ¢ ¥ £A D ¢ C D ¢ C s ¢ ¤ D ¥ © D ¢ C D ¢ C s ¢ ¤ D ¥ © s @ ¥ s D § ¦ ¤¤ C C 7 @ P¡ s C §¢ ¦ C § C D7 § § ¡ § s ¢ ¤ § ¦ DC § ¡ D¥ D C s ¢ ¤ D¥ © s ¢ ¤ D ¢ ¢ D 7 D¥ C¢ D¥ D C s ¢ ¤ D¥ © § s ¢ ¤ § £A ¦ D C 7 § § ¡ u F@ § ¡ ¢ D¥ D C s ¢ ¤ D¥ © CD ¥ § £A ¦ C § C D7 C § ¡ 1 u F@ § ¡1 ¢ ¢ D ¥ D C s ¢ ¤ D ¥ © s ¢ ¤ D ¢ £A D 7 C § s ¦ C C § s ¢ ¤ © ¢ § wCs s D 7 ¦ C C § s ¢ ¤ © C 7 u D D¥ D D¥ D¥ D D¥ ¦ ¦ C ¦ ¤ ! § ¤ ! ¥ ¢ #¥ ! C § ¤ ¤ ¥ ¢ © ¢D ¥ s @ C C 7 D ¦ § ¦ u s D ¥ C D C § s ¢ ¤ D ¥ © ¢ § sws D ¥ C D C § s ¢ ¤ D ¥ © C D 7 § ¥ 1 C § ws ¦ C C § s ¢ ¤ C D 7 © s ¢ ¤ ¢ C 7 7 § ¡ 1 s D¥ D D¥ D D ¦ ¦ C ¦ ¤ ! § ¤ ! ¥¢ ¥ ! C§ ¤ ¤ ¥¢ © ¢ D ¥ § us ¦ C C § s C C D 7 ¥ s D ¥ D ¢ ¤ D¥ © s ¢ ¤ D ¢ C D u 7 ¡ ¡1 § ¥1 ¥ ¦ ¦ C § ! C§¤ ¦ ¤ ¤ ! § ¤ ! © ¥ ¢ #¥ ¥ ¢ ¢ D § ¥1 ¥ s C C D7 © s ¢¤ D ¢C Du7 § ¡

§ s ¦ u

D¥

C

D

C§

s

¢¤ D¥

100

h)

i)

iii)

(e)

¤

(ii)

(b) (c)

erwise,

ANS:: (a)

Solution:

(See Figure 4.14)

§ 1

vi) error

iv)

ii)

v)

(iv) is:

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

(f)

(h) (i)

(iii)

,

for

(d)

(vi) ;

for

(g)

(v)

otherwise

oth-

,

101

i1 (A) i1 iS N1 N2 i2 + v -1 1 -1
Figure 4.13:

i2 (A) 1 v (V) -1

1

1 v (V) 2

i1+i2

1

-2

-1

1

2

v

-1

Figure 4.14:

102 a) 2 b) 11

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

i s ( t ) = cos t

1

–2 π -1 v(t ) 2

2π

t

–2 π

2π

t

-2

Figure 4.15: c) See Figure 4.15. ANS:: (a) 2 (b) 11 Problem 4.3 A plot (hypothetical) of the v-i characteristics, (terminal voltage as a function of the current drawn out, and NOT its associated variables) for a battery is shown in Figure 4.16(a). a) If a 2 ohm resistor is connected across the battery terminals, ﬁnd the terminal voltage of the battery and the current through the resistor. b) A light bulb is a nonlinear resistance because of self-heating effects. A hypothetical i-v plot is shown in Figure 4.16(b). Find the bulb current and bulb voltage if the lamp is connected to the battery.

103

V (V) 3 2

I (A) 2 1

1 0 1 2 3 (a)
Figure 4.16: c) Devise a piecewise-linear model for the battery which is reasonably accurate over the current range 0-2 amp. d) Use this piecewise-linear battery model to ﬁnd the battery voltage and bulb current if the bulb and 2 ohm resistor are connected in series to the battery. Solution: ¡

4

5 I (A)

0

1

2 3 (b)

4

5 V (V)

a) b)

amps; amps;

c) see Figure 4.17. d) amp;
V p

volts;

volts volts (b) amps; volts (d)

¡

ANS:: (a) volts
V

amps;

1

(Ep a

S a

T ) a § ¢¤@ ¢

1

a (c

V B§

(c a

a (c

¢¢

S a

1

S a

S a

1 1 1

volts volts
R TH

i a Vth = 3 V Rth = 0.1 ohms 0 ≤ i ≤ 2 amps a’

Vth

+ -

Figure 4.17:

amp;

p

104 Problem 4.4

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

a) Assuming the diode can be modeled as an ideal diode, and , plot the waveform for the circuit in Figure 4.18, assuming a triangle wave input. Write an expression for in terms of and . b) If the triangle wave has a peak amplitude of only 2 volts, and , a more accurate diode model must be used. Plot and write an expression for assuming that the diode is modeled using an ideal diode in series with a 0.6 volt source. Draw the transfer curve versus . s

vi vi t
+ -

R1 R2

Figure 4.18: Solution:

1 R th = -- R 1 2 vi
+

vo t

1 v th = -- v i 2

+ -

Figure 4.19:

7

7

ANS:: (a)

for

and

otherwise (b)

for

9 a

@

s

§

S§

(

7

b) See Figure 4.20.
s

for

, and

&a

@

§

S@ a

§ ¡ s

7

a) see Figure 4.19.

for

and

otherwise otherwise , and

7 @

7 @

§

§

s

@

@

7 @

§

s

@

s

¥ ¡ ¦£

§ ¡

¥£¡ ¦¤)

+

vo
-

vo
-

§

&a
@

§

105

2

vi vo 1 -- v i 2
+ -

1 -- R 1 2
+
0.6 V

+ -

-0.6 -2

t

vo
-

vo
2

-1
-0.6 -2

4

vi

Figure 4.20:

+

iZ vZ
8 -4 -2 4

iZ (mA)

R1 = 1 kΩ
+

∆v + 50 mV AC vZ (V)
2

-

vo
+ V - 10 V DC -

-4 -8
Figure 4.21:

106

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

Problem 4.5 Figure 4.21 is an illustration of a crude Zener-diode regulator circuit. a) Using incremental analysis, estimate from the graph an analytical expression for in terms of and .

b) Calculate the amount of DC and the amount of AC in the output voltage using the Zener diode characteristic to ﬁnd model values. Numbers, please. c) What is the The´ venin output resistance of the power supply, that is, the Th´ venin e e resistance seen looking in at the terminals. Solution: Assume 20mA/V for forward bias, 40mA/V for reverse breakdown. a) ¡

b) DC: c)

V AC:

mV

ANS:: (a)

(b) DC:

V AC:

mV (c)

Problem 4.6 The terminal voltage-current characteristic of a single solar cell is shown in Figure 4.22a. Note that this is a sketch of the terminal voltage as a function of current drawn out (i.e. not the associated variable convention). An array is made by connecting a total of 100 such cells as follows: Ten solar cells are connected in series. Ten sets of these are made. These ten series strips are then connected in parallel (see Figure 4.22b). If a 3 ohm resistor is connected across this new two-terminal element (the 100 cell array), determine the terminal voltage across and the current through the resistor. Solution: The act of combining 10 in series causes the graph to stretch vertically by a factor of 10, and the act of combining 10 in parallel stretches it horizontally by 10. So one intersects this new graph with a line of slope 3, and gets the approximate intersection point of
¢

ANS::

volts;

Problem 4.7 The junction ﬁeld-effect transistor (JFET) with the speciﬁc connection shown in Figure 4.23a (gate and source shorted together) behaves as a two-terminal device. The characteristics of the resulting two-terminal device shown in Figure 4.23b saturates at current for greater than a voltage , called the pinch-off voltage. In the two-terminal conﬁguration shown, the JFET characteristic is

9

a S§

¢

volts;

amps amps

T 2 0S

9 a

2 a

¨

a SE§

I a

S a

§

1

(2 a

¨

¥ a e2

I a @

§E (t a 2 §

2 a 9

a (¢ SP¡

§ T 2 09

107

terminal voltage of single cell

V 0.6 V 0.5 V non-linear region 0.25 V linear region I 0.1 A 0.2 A 0.25 A 0.3 A current drawn out (a)
Figure 4.22:

1

2

9

10

+

linear region

1 2 3 4

V

9 10

-

(b)

and

As illustrated in Figure 4.23c, this two-terminal device can be used to make a wellbehaved dc current source, even starting with a ripple-containing power supply (depicted as ), as would be obtained from ordinary rectiﬁer circuits. Suppose the voltage source has an average value and a 60 Hz “ripple component”, as shown in Figure 4.23d. a) First assume that there is no ripple ( ). Find the current through the resistor as a function of for a value of . At what value of does the current stabilize at ? How would this value change if were doubled in value? Explain. b) Now assume and . Make reasonable approximations to ﬁnd the current waveform when , and . Determine in each case the average value of the current and the magnitude and frequency of the largest sinusoidal component of the current. Solution:
2 9¢

£

¢

¨¦ ©¤

4

1

§ ¡

§

@

H)

T ¢

for

for

B

¤ ¥9

¢ £7 ¥

I

1 §

S` I

§

@ §

S2

T ¢

¡
4 @

§ 1

¥ §

§

S` I

@

¡ ¡ §
¡
W a

§

4

01

@

108

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

iD + iD vD IDSS

0 (a) vS VS i vP (b)

2vP

vD

+ -

a vS
R

0 (c)
Figure 4.23:

2π ----ω (d)

4π ----ω

t

109
£ £ £
$

Problem 4.8 The current-voltage characteristic of a photovoltaic energy converter (solar cell) can be approximated by

i + R v Sunlight

Figure 4.24: s Assume

and assume light exposure such that

a) Plot the i-v characteristic of the solar cell. Be sure to note the values of open-circuit voltage and short-circuit current. (Note, however, that the characteristic is clearly nonlinear. Therefore, Th´ venin or Norton equivalents do not apply.) e

¤

¥ )§ 7

7

where the ﬁrst term characterizes the diode in the dark and light intensity.

is a term that depends on

3

7

@

¥

@ ¦¡ ¥

,

,

.

¥

A¥1

2 9¢§

) ¤ F2

§

¥

A¥1 7

¢ A 3£¡ s

§ H)ER¡

§ 1

) V ¤ ¦ a t§

. (a)
¥

for

) ¤ I2 § @ ¥

¡

£ £

£

$

§ ¢ C $¥ C

ANS::

Assume
¡

) ¤ I2

§

7

¢

£ £

¢ C $ ¥

D § ¥ ¢

7

¢

£ £

When

) ¤ F2

§

) I 3 A ¤

¢ C $ ¥¥

¥

A ¥ S¢§ ¡ 1 2 ( a

When magnitude

,

, largest sinusoidal component has frequency , no sinusoidal component present

and (b)

¢

) 2 ¤ It§

¥

¥

1

£

H)

7

)§

§ 1

When magnitude

,

largest sinusoidal component has frequency , ,

¢

¤ ¦ (V ) a

§

) & 2 90H a 3 A¤ ¥ ¥1 S2

b)

,

stabilizes at
¤

when
S2

@ ¥

¡ 7 D

a)

for

@ ¥

¡

§ ¢ C $ ¥ C

7

¢
£

£ ¢ ¥ C $ ¥

¡

¢§

§

7

¢

£ £

¢ C $ ¥

3

§ 5¡

§ ¡

¥
) I2

£

A

§
¥ 1 S2 S2

7

§ 1

The current

§

§

110

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

b) If it is desired to maximize the power that the solar cell can deliver to a resistive load, determine the optimum value of the resistor. How much power can this cell deliver? Solution:

i i = I 1(e v ⁄ V TH

– 1) – I2

I2 v oc = V TH ln  ---- + 1  I1

v
I sc = – I 2

Figure 4.25:

Problem 4.9 a) A nonlinear device has i-v characteristics shown in Figure 4.26. Assuming that is an ideal voltage source, which connection, (i), (ii) or (iii) consumes most power? What if is an ideal current source? b) Another crazy device, , with v-i characteristics as shown in Figure 4.27, is introduced. If device and device are connected in series across an ideal voltage source of 6 volts, what is the current ﬂow in the circuit? (You can either solve it analytically or graphically.) Solution: a) ii) consumes the most power. If S is a current source, i) consumes the most power.
¡ ¡

¢

¦

¤

¦

ANS:: (b)

ohms; Maximum power =

9& ( ) a

(V §

¢

¨ @

¦

¢

¦

b)

ohms; Maximum power = 2.6 mW

7

a) See Figure 4.25.

;

¤ ¥ ¥ C Q£¡¢¢ ¡ ¢

§

Q¨

@

§

I

(V §

¢

¨ @

111

vA = K iA2 iA + vA A iA vA = 0

for i A ≥ 0 for i A < 0

where K = 1.0 V/A2

vA

I + V S A (i) n A’s in series A + V S

I + A A V S (ii) n A’s in parallel
Figure 4.26:

I

B

B

B

(iii) n B’s in parallel, each B is n A’s in series

iC (A)
4

+ vC C -

iC
2

5

10

15

vC (V)

Figure 4.27:

112 b) 1 Ampere

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

ANS:: (a) ii; if S current source, i (b)
¤

i + v1 v2
+

v -

 ---------  V TH – 1 i = I 1e   I1 = 10-9A

+

-

Figure 4.28: a) Find the current if only the out). b) Find the current if only the source is connected (i.e., with the s source is connected.

c) Find the current if both sources are connected as shown. Is superposition obeyed? Explain. d) Based on your answer in c) discuss the dependence of the amplitude of the sinusoidal component of the current on the amplitude . How big can be before signiﬁcant generation of harmonics will occur? HINT: Taylor’s theorem is relevant to this problem. Solution:
¤ ¢ ¥£¡

a) b) c)

d) The dependence of the sinusoidal component of the current on the amplitude is nonlinear. However, for sufﬁciently small the relationship approximates a linear dependence. When , harmonics make up approximately 2% of the sinusoidal component.

7

¤

7

¤

7

7

¤

7

¤

s

Problem 4.10 In the circuit in Figure 4.28, assume . Assume further that mV.
2 9S§

and

v

source shorted

£
¢

¨¦ ©¤ 7
¤

§ 7

S2 a

2§

£ ¥ £ 7 I¦D8) ¤

( a

, where

¥ )

¢¢

§ 7

@

¥ )

7

¥

§

¤

@

¥

¥

£

§

¥ )

s¥¦¡ wu u ¢ u u £¦ ¡ ¥ s wu u u

¥

@

¤ ¥¤

¥ ¥ ¦¡ u ¡ ¥

1

1

¤

1

¤

¡

¡

¤ ¢ ¥£¡

¤ ¢ ¥£¡

¡

¡

¡

W

)E§ 1

)E§ 1

)E§ 1

( a

§ 7

©

©

£

¢

§

¥

) ¤ 9¡a

§

1 H& a

§

9

s

§

¨ D©y¤T S2 a

§

¢ ¢¤@

£
¢

¨ ©§¦¤

b 2 2a 8S"e¢
¤ £ ¢

§ §

©

T

)

b c9 a

§ ¥ ¨¥ ¦ ¡ ¡

¥ ¦¡

¥

a (2§ ¨ D©

1

&a §

I

s
§
©

T

2 "a

§ ¢¤@ ¢

£
¢

¨¦¤ ©¥9( a
B§ s

¥ B§

¥£ ¦¤¡

§ 1
113

¥ )
@

Problem 4.11 This problem concerns the circuit illustrated in Figure 4.29:

b) Assume that for bias point determination the diode can be modeled by an ideal diode and a 0.6 volt battery. What are and when volts?

1

S

2 SS§

¢¢

¤

T ¢E§

)

b %

§ R T

¡@

2a S"(2§

¥

§

¥

¥ u ¦¡ s wu u ¡

¤

¡

)

§ 1

£ ¦¡ ¥ 0 a 2§ 7 ¥ s wu u @ ¥ § ¥ ¤ ¥ @ ¥¥ ¤¥ ©¡ u ¡ ¥¢ ¡¡ § 1 ¤

¤

ANS:: (a)

(b)

£

¤ ¥¢

d) Use your model of part c) to ﬁnd

¥

@

¥ @ ¦¡ ¢ A ¢ § 1 s £¡ ¥ T H S§ 7 @ T H S§ a a
¢

¢

s

@

¤ u ¢ ¥¤ u ¡

¤ ¥¢ ¡

¡

b)

c)

£

d)

a)

c) Find a linear equivalent model for this diode valid for small signal incremental operation about the bias point determined from part b.

a) Find the Th´ venin equivalent circuit for the circuit connected to the diode. e

ANS:: (a)
©

For

Solution:

vI

V,

k

+ -

mA

(d)

R1

with

Figure 4.29:

R2

if

(b)

¨¦ ©¤ )

b 2 a 8S2 (¢

§

T

b 9 a

¥ § ¥ ¦ ¡ ¡

¤ ¥¢

¥ ¦¡

£

(d)

R3

D1

and

iD

vD

+

-

volts.

R4

mV.

(c)

)

(c)

114

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

Problem 4.12 Consider the circuit in Figure 4.30. The voltage source and the current source are the sum of a dc-level and an ac-perturbation:

such that

(dc),

(dc),

(ac),

v
+

R2 i0
+

i

R1

Z0

v0
-

Figure 4.30: s The resistors have the following values: has the characteristic: u ohm. The nonlinear element

Remark: You can assume in your analysis that the nonlinear element is behaving as a passive element, i.e., is consuming power. Solution: DC component: AC component from current source: ANS:: DC:
S2 S S 0 a ( a 0 a S2

AC component from voltage source: , AC from current:

, AC from voltage:

Problem 4.13 The circuit shown in Figure 4.31 contains a nonlinear element with the following properties:
£ A $ ¤¡ £ 7£ $ A ¡

u

Find, by incremental analysis, the DC and AC components of the output voltage

) ¤ 92

S

§ 1

( a

` (¢ § 7 2§ @

90) )

£

£

u u 7 ¥ § 1

u

1
(ac). .

§ 5

H

@

¥ § 1 ¥ 5 §

)

¤

)E§ § §

£¤1 £ ¤1

H(V

§ E

115

iN vi VB
+

+

vN

-

+ -

+

R vOUT
-

Figure 4.31: where is in amps, and

The output voltage,

is a dc voltage produced by Where duced by the incremental voltage source . Assuming that operates with Solution: (note: must label resistor value)

and

volts and is such that the nonlinear element volts, determine the incremental output voltage .
¡

ANS::

Problem 4.14 Consider the diode network shown below. For purposes of this problem, the accurately represented as
! 9 @ 1

characteristics of all of the diodes can be

where

Do not use a piecewise-linear model.

b) Now assume that is non zero, but small enough so that incremental analysis can be used to determine and . What is the ratio ?

7

`

s

7

7

and

s

s

1

a) First assume that values of voltages

. (Thus ?

). What are the operating-point

¥7

£ 9` ¤ q§ )

¡

§ 7

¡

¥ ¢ ¡© ¨

¡

§

§

¡¢

£

¢ ¥ 7 £ A ¥

¡¨

¢

¥ ¡ ¢ ¦£ ¢ Q£¡

$

1!

£ 6

§ 1

¥ )

¨ ¥ ) wuu ¥ D ¢ D

¥ ¡ ¢ ¦£ ¢ 4£

¢ ¡¨

£

§

1

§

¨ ¥ ) wuu ¥ D ¢ D

) § £

§

¢ ¡© ¨

¡

§

£ ¤1

is in volts. , may be written approximately as the sum of the two terms: (4.3) is the incremental voltage pro-

¡

116

CHAPTER 4. ANALYSIS OF NONLINEAR CIRCUITS

+

∆i 1 mA 1 mA

+

V2 + ∆v2
-

V1 + ∆v1
-

Figure 4.32: Solution: b)

¥

7

s

ANS:: (a)

, (b) .

s

2 a SS SE§

FS ) 2

7

& §

s s

a)

;

2 a SS SE§

IS ) 2

& §

¥

Chapter 5 The Digital Abstraction
Exercises
Exercise 5.1 Write a Boolean expression for the following statement: “ is TRUE if either or is FALSE, otherwise is FALSE”. Write a truth table for this expression. Solution: ¡

0 0 1 1
¡

0 1 0 1

ANS::

Exercise 5.2 Write a Boolean expression for the following statement: “ is FALSE if either or is FALSE, otherwise is TRUE”. Write a truth table for this expression. Solution: ¡

¡

ANS::

117

¡

§

¥ ¥ ¡ ¡

¥

§ §
¡ ¡

1 1 1 0

§

¥

§ §

118
¡

CHAPTER 5. THE DIGITAL ABSTRACTION

0 0 1 1

0 1 0 1

0 0 0 1

Exercise 5.3 Write a Boolean expression for the following statement: “ more than two of , , and are TRUE, otherwise is FALSE”. Solution: In this case, “no more than 2” = “not all 3”, so: ¡ ¡

is TRUE if no

a) Write a Boolean expression for the above statement. b) Write a truth table for the function . c) Implement using only AND, OR, and NOT gates. The inputs , , and are available. Each gate may have an arbitrary number of inputs. (Hint: A sum-ofproducts representation of the Boolean expression will facilitate this implementation.) d) Implement using only AND, OR, and NOT gates. Each gate may have no more than two inputs. As before, the inputs , , and are available. e) Implement using only NAND and NOR gates. (Hint: a NAND gate or a NOR gate with its inputs tied together behaves like an inverter). f) Implement g) Implement ¡ ¡

using only NAND gates. (Hint: Use De Morgan’s laws.) using only NOR gates. (Hint: Use De Morgan’s laws.)

h) Repeat part (d) and attempt to minimize the number of gates used. i) Repeat part (d) and attempt to minimize the number of gates used, assuming that the inputs are available both in their true and complement forms. In other words, assume that in addition to , , and , the inputs , , and , are also available. ¡

¡

Exercise 5.4 Consider the statement: “ TRUE, otherwise is FALSE”.

is TRUE if at least two of

,

, and

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are

119 Solution: a) ¡

0 0 0 0 1 1 1 1 b) c) See Figure 5.1 for logic diagram.

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

W

X Z

Y
Figure 5.1:

d) See Figure 5.2 for logic diagram. e) See Figure 5.3 for logic diagram. f) Only NAND:

See Figure 5.4 for logic diagram.

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120

CHAPTER 5. THE DIGITAL ABSTRACTION

W

X Y

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Figure 5.2:

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X Z

Y
Figure 5.3:

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Figure 5.4:

121 g) Only NOR:

See Figure 5.5 for logic diagram.

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X Z

Y
Figure 5.5: h) ¡

See Figure 5.6 for logic diagram.

W Z

X Y
Figure 5.6: i) Solution: same as (h)
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122

CHAPTER 5. THE DIGITAL ABSTRACTION

Exercise 5.5 Represent the decimal number 4 as an unsigned, three-bit binary number and as an unsigned, four-bit binary number. Unsigned numbers do not include a sign bit. For example, 11110 is the unsigned, binary representation of the decimal number 30. Solution: Unsigned 3-bit: Unsigned 4-bit: ANS::

,

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 0 0 1 1 0 1

0 0 0 1 0 1 1 1

Table 5.1: Truth table for Exercise 5.6

Solution: a)
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e) Repeat parts b) through d) for the function

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with logic gates. using only 2-input gates. using only 2-input NAND gates. Hint: Use De Morgan’s .

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a) Write a logic expression corresponding to the functions .

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Exercise 5.6 Consider the functions table given in Table 5.1.
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and

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123 If we simplify F, combining the ﬁrst pair and the second pair,

We can combine the ﬁrst and last terms,

b) See Figure 5.7 for logic diagram.

A F

B C
Figure 5.7: c) Same as part (b)

d) Using our simpliﬁed version of , De Morgan’s laws, and the fact that a NAND gate with logical signal tied into both inputs produces ,
¡

See Figure 5.8
B B C C A C F

Figure 5.8:

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124

CHAPTER 5. THE DIGITAL ABSTRACTION

A

G B C

Figure 5.9:

A G B C

Figure 5.10:

125
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e) Implement Implement Implement

See Figure 5.11

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B C

Figure 5.11:

Exercise 5.7 Consider the four logic expressions below. 1. 2. 3. 4.
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a) Give an implementation using gates for each of the logic expressions above. b) Write the truth table for each of the four expressions. c) Suppose you know that

. Simplify the four expressions under this constraint.

d) Simplify the four expressions assuming that

and

are related as

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with logic gates. See Figure 5.9 using only 2-input gates. See Figure 5.10 using only 2-input NAND gates.

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126 Solution: a)

CHAPTER 5. THE DIGITAL ABSTRACTION

1. A simpliﬁcation of the expression would be

See Figure 5.12(1)
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2. Using De Morgan’s laws, the fact that X the distributive law,

= 0, the fact that X X = X, and
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See Figure 5.12(2) 3. Using the fact that X + X Y = X and De Morgan’s,
¢

See Figure 5.12(3)
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4. Using the fact that

+X Y=

+ Y and De Morgan’s,
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See Figure 5.12(4)

b) See Table 5.2

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127

B 1) A D D B A A B D C A 4) A C D B F C F

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Figure 5.12:

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1

0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0

1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1

0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Table 5.2:

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128 3)

CHAPTER 5. THE DIGITAL ABSTRACTION

Exercise 5.8 A logic gate obeys a static discipline with the following voltage levels: , , and . (a) What range of voltages will be treated as invalid under this discipline? (b) What are its noise margins? Solution: (a) Devices must produce output voltages within the following ranges: Valid range for low outputs:
H a

Valid range for high outputs:

Devices must interpret correctly input voltages within the following ranges: Valid range for low inputs:

Valid range for high inputs:

(b)

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, “1” outputs:

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129 Exercise 5.9 Consider a family of logic gates which operates under the static discipline with the following voltage thresholds: V, V, V, and V. a) Graph an input-output voltage transfer function of a buffer satisfying the voltage thresholds given above. b) Graph an input-output voltage transfer function of an inverter satisfying the voltage thresholds given above. c) What is the highest voltage that can be output by an inverter for a logical 0 output? d) What is the lowest voltage that can be output by an inverter for a logical 1 output? e) What is the highest voltage that must be interpreted by a receiver as a logical 0? f) What is the lowest voltage that must be interpreted by a receiver as a logical 1? g) Does this choice of voltage thresholds offer any immunity to noise? If so, determine the noise margins. Solution: a) See Figure 5.13
2 "a V

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CHAPTER 5. THE DIGITAL ABSTRACTION vout 4.4

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Figure 5.14: d) e) f)
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g) Yes. The noise margins are given by:
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Exercise 5.10 Consider a family of logic gates which operates under the static discipline with the following voltage thresholds: V and V. a) Graph an input-output voltage transfer function of a buffer satisfying the voltage thresholds given above. b) Graph an input-output voltage transfer function of an inverter satisfying the voltage thresholds given above. c) What is the highest voltage that can be output by an inverter for a logical 0 output? d) What is the lowest voltage that can be output by an inverter for a logical 1 output? e) What is the highest voltage that must be interpreted by a receiver as a logical 0?

¨ © §

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131 f) What is the lowest voltage that must be interpreted by a receiver as a logical 1? g) Does this choice of voltage thresholds offer any immunity to noise? Solution: a) See Figure 5.15

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Figure 5.16: c) d)
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132 e) f)
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CHAPTER 5. THE DIGITAL ABSTRACTION

g) No. ANS:: (c) 0.5V (d) 4.4V (e) 0.5V (f) 4.4V (g) No

Problems
Problem 5.1 Derive a truth table and a Boolean expression that describes the operation of each digital circuit shown in Figure 5.17. Solution: For truth tables, see Table 5.1 (parts a-b), and Table 5.1 (parts c-f).

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1

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133

A B C D (a) Z

A B C D (b) Z

A B C (c) Z B

A Z C (d)

A B C (e)
Figure 5.17:

A Z B C (f) Z

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 1 1 0 1

1 1 0 1 1 1 0 1

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134 c) d) e) f)
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CHAPTER 5. THE DIGITAL ABSTRACTION

1

Problem 5.2 Draw an output voltage waveform for the circuit in Figure 5.17c in response to the input voltage waveforms shown in Figure 5.18. Assume that the gates in the circuit obey the static discipline with V, V, V, and V.

5V 4V 3V 2V 1V 0
Figure 5.18: Solution: For Circuit 5.17c, the output is given by

A

t

C B

There are 7 different states, where a state transition occurs when one of the three inputs changes by itself. For example, the ﬁrst state is when and are low and is high, the second state is when and are high, and is low, and so on. The output in the ﬁrst, second and ﬁfth states is low (below 1V), while the output in the remaining states is high (above 4V). ¡

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135 Problem 5.3 The truth table for a “ones count” circuit is given in Table 5.3. This circuit has four inputs: , , , and , and three outputs , , and . Together, the signals , , and represent a 3-bit positive integer . The output integer reﬂects the number of ones in the input. Using only NAND, NOR and NOT gates, design an implementation for the circuit. Each gate may have an arbitrary number of inputs. 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 u Table 5.3: Solution: See Figure 5.19 for logic diagram. Using sum-of-products,
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Problem 5.4 A four-input multiplexer module is shown in Figure 5.20. The multiplexer

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136

CHAPTER 5. THE DIGITAL ABSTRACTION

A B C D

Out 2

A C D B C D A B C D A B C D

Out 1

B C D A B C

A B C D A B C D

A B C D A B C D A B C D A B C D

Out 0

A B C D A B C D

Figure 5.19:

137 has two select signals and . The value on the select signals determines which of the inputs A, B, C, and D appears at the output. As illustrated in the ﬁgure, A is selected if is 00, B if is 01, C if is 10, and D if is 11. Write a boolean expression for Z in terms of , A, B, C, and D. Implement the multiplexer using only NAND gates. u A B C D

00 01 10 11 2 S1S0 Z

Figure 5.20: A four-input multiplexer module. The “2” beside the wire corresponding to the select signals is a short-hand notation indicating there are two wires present. Solution: Boolean expression: u See Figure 5.21 for logic diagram. u Problem 5.5 A four-input demultiplexer module is shown in Figure 5.22. The demultiplexer has two select signals and . The select signals determines on which of the outputs (OUT0, OUT1, OUT2, or OUT3) the input IN appears. As illustrated in the ﬁgure, IN appears at output OUT0 if is 00, at OUT1 if is 01, at OUT2 if is 10, and at OUT3 if is 11. An output is 0 if it is not selected. Write a boolean expression for each of the outputs in terms of and IN. Implement the demultiplexer using only NAND gates. Solution: See Figure 5.23 for logic diagrams. Boolean expressions: u ¢s ¢

u

¢s ¢

7 ¢ 3

¢s ¢

s

u

¢3

¢s ¢

¢

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138
A S1 S0 B S1 S0 C S1 S0 D S1 S0

CHAPTER 5. THE DIGITAL ABSTRACTION

Z

Figure 5.21:

00 01 IN 10 11 2 S1S0
Figure 5.22:
IN S1 S0 IN S1 S0 IN S1 S0 IN

OUT0 OUT1 OUT2 OUT3

OUT0

OUT2

OUT1

S1 S0

OUT3

Figure 5.23:

139

Problem 5.6 Implement the “greater-than” circuit depicted in Figure 5.24 using NAND gates. A and B represent one-bit positive integers. The output Z is 1 if A is greater than B, otherwise Z is 0.

A B

>
Figure 5.24:

Z

Solution: Z is 1 only if A is 1 and B is 0. The resulting expression is then:

See Figure 5.25 for logic diagram.
A B

Z
Figure 5.25:

Problem 5.7 Implement the 4-input “odd” or “odd parity” circuit depicted in Figure 5.26 using NOR gates. In this circuit, the output Z is high if an odd number of the inputs are high, otherwise the output Z is low. How would you use the 4-input “odd” circuit module shown in Figure 5.26 to implement a 3-input “odd” circuit. If this cannot be done, discuss why not.

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140

CHAPTER 5. THE DIGITAL ABSTRACTION

A0 A1 A2 A3

ODD

Z

Figure 5.26:

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

141 Solution: Boolean expression:

This circuit can be implemented in the same way as the previous problems, using sum of products and NAND gates. This same circuit module can be used to implement a 3input “odd” circuit by tying one of the A inputs to ground. Incidentally, you could also make a 3-input “even” circuit by tying one of the A inputs to hi.

Problem 5.8 Figure 5.27 depicts a 4-input majority circuit module. The output Z of this circuit module is high if a majority of the inputs are high. Write a boolean expression for Z in terms of A0, A1, A2, and A3. How would you use the 4-input majority circuit module shown in Figure 5.27 to implement a 3-input majority circuit and a 2-input majority circuit. If either of these cannot be done, discuss why not.

A0 A1 A2 A3

Majority

Z

Figure 5.27: Solution: Boolean expression:
V ¤

Use NAND gates and sum-of-products to implement the Boolean expression. A 3input majority circuit can be implemented by tying one input to HI. A 2-input majority circuit can be implemented by tying one input to ground and another input to HI. ANS::
V ¤

Problem 5.9 Figure 5.28 illustrates a two-bit grey code converter. Its outputs OUT0, OUT1, are equal to the inputs when the IN0, IN1 are 00 or 01. However, when the inputs IN0, IN1 are 10 and 11 the outputs OUT0, OUT1 are 11 and 10 respectively. Implement the grey code converter using 2-input NAND gates.

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142

CHAPTER 5. THE DIGITAL ABSTRACTION

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

IN 0 IN 1

Figure 5.28:

0 0 1 1

0 1 0 1

0 0 1 1

0 1 1 0

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0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1

OUT 0 OUT 1

143 Solution: Boolean expressions:

Problem 5.10 Figure 5.29 illustrates input-output voltage transfer functions for several one-input one-output devices. For the voltage thresholds , , , and as shown, which of the devices can serve as valid inverters?

VOUT

5V

VOH E VOL D 0 VIL VIH
Figure 5.29: Solution: Only C is valid according to the static discipline. Problem 5.11 Suppose we wish to build a two-bit adder circuit (Figure 5.30) that takes as input a pair of two-bit positive integers and and produces a two-bit sum output and a carry out bit . Write a truth table and a boolean expression for the carry out bit in terms of the inputs. Now, suppose we wish to build a two-bit adder circuit (Figure 5.31) that takes as input a pair of two-bit positive integers and , and a carry-in bit , and produces a two-bit sum output and a carry out bit . Write a truth table and a boolean expression for the carry out bit in terms of the inputs. Solution: u ¡

B C A F

5V VIN

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u

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CHAPTER 5. THE DIGITAL ABSTRACTION
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CHAPTER 5. THE DIGITAL ABSTRACTION

Problem 5.12 Suppose we have two logic families named NTL and YTL. The NTL family of logic gates operates under the static discipline with the following voltage threshV, V, V, and V. The YTL family, on olds: the other hand, is characterized by the voltage thresholds: V, V, V, and V. Will a YTL inverter driving the input of an NTL inverter operate correctly? Explain. Will a NTL inverter driving the input of an YTL inverter operate correctly? Explain. Solution: A YTL inverter driving an NTL inverter will operate correctly because all valid outputs of the YTL are valid inputs for the NTL. On the other hand, an NTL inverter driving a YTL inverter will not operate correctly since a valid low output of the NTL between 0.8V - 1V would fall into the forbidden region (0.8V - 3V) of the YTL. Problem 5.13 Consider a family of logic gates which operates under the static discipline with the following voltage thresholds: V, V, V and V. a) Graph an input-output voltage transfer function of a buffer satisfying the voltage thresholds given above. b) Graph an input-output voltage transfer function of an inverter satisfying the voltage thresholds given above. c) What is the highest voltage that can be output by an inverter for a logical 0 output? d) What is the lowest voltage that can be output by an inverter for a logical 1 output? e) What is the highest voltage that must be interpreted by a receiver as a logical 0? f) What is the lowest voltage that must be interpreted by a receiver as a logical 1?
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147 g) When transmitting information over a noisy wire, buffers can be used to minimize transmission errors by restoring signal values. Consider the transmission of data over a noisy wire which picks up a maximum of 80 mV symmetric peak-to-peak noise per centimeter. How many buffers are needed to transmit a signal over a distance of 2 meters in this noisy environment? h) How large are the and noise margins for a buffer in this logic family? Now consider three buffers connected in series and behaving as a single buffer. What are the noise margins for this new buffer? Solution: must produce an output less than or equal to a) Any input below input above must produce an output greater than or equal to . See Figure 5.32 for graph.
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CHAPTER 5. THE DIGITAL ABSTRACTION
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If we look at what happens with a triple-buffer at the sender side and at the receiver side, we realize that the noise margins stay the same. Basically this means we are not allowed any more noise during transmission than with a single buffer. If we look at the low noise margin, the minimum voltage the triple-buffer is guaranteed to output for a “low” is still = 0.5V (any logic gate under this static discipline) and likewise, the maximum voltage the receiving triple-buffer is guaranteed to interpret as a “low” is still = 1.6V giving us a noise margin of 1.1V s

Problem 5.14 Many manufacturing ﬂaws in digital circuits can be modeled as stuck-at faults. The output of a gate is said to suffer from a stuck-at 1 fault if the output is a 1 irrespective of its input values. Similarly, a stuck-at 0 fault at an output causes the output to produce a 0 at all times.

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b) Suppose we are given the faulty circuit in Figure 5.35a where the output of NAND gate N2 is known to have a stuck-at fault. However, we do not know whether it is a stuck-at 1 fault or a stuck-at 0 fault. Further, as illustrated in Figure 5.35b, suppose that we have access only to the inputs A, B, and C, and the output Z. In other words, we are unable to directly observe the output X of the faulty NAND gate N2. How would you go about determining whether N2 suffers from a stuck-at 1 fault or a stuck-at 0 fault.

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Solution:

150

CHAPTER 5. THE DIGITAL ABSTRACTION
a) b) c) d)

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CHAPTER 6. THE MOSFET SWITCH
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CHAPTER 6. THE MOSFET SWITCH

Exercise 6.4 Consider, again, the inverter circuit shown in Figure 6.4. The MOSFET has . Assume that and . For this exercise, a threshold voltage model the MOSFET using its switch-resistor model. Assume that the on-state resistance of the MOSFET is . a) Does the inverter satisfy the static discipline which has voltage thresholds given by and ? Explain. b) Does the inverter satisfy the static discipline for the voltage thresholds and ? Explain. c) Draw the input versus output voltage transfer curve for the inverter. d) Is there any value of Explain. e) Now assume that Solution: a) First ﬁnd the relevant threshold output and input values for the inverter: The output high voltage is 5. The output low voltage is
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CHAPTER 6. THE MOSFET SWITCH

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CHAPTER 6. THE MOSFET SWITCH
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168

CHAPTER 6. THE MOSFET SWITCH

Problem 6.7 Consider a family of logic gates which operates under the static discipline with the following voltage thresholds: , , and . Using the switch-resistor MOSFET model, design a 2-input NAND gate satisfying the static discipline for the above voltage thresholds using three n-channel MOSFETs as illustrated in Figure 6.17 (the MOSFET with its gate connected to a voltage and drain connected to the power supply serves as the pull-up). is chosen such that . The MOSFETs have and . Recall, . Assume . Further assume that the area of the NAND gate is given by the sum of . The NAND the areas of the three MOSFETs. Assume that the area of a device is gate should take as little area as possible with minimum size for or being . What is the total area of the NAND gate?

VS L1 ------W1 Z A B L2 ------W2 L3 ------W3

VA

Figure 6.17: Solution: Using the same steps as in the previous problem: The relevant issue in the design is to ensure that the output low voltage produced by the inverter is lower than or equal to .

Therefore, to ﬁnd the respective

ratios:

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Problem 6.8 Remember that a NAND gate can be implemented as a circuit with two n-channel MOSFETs and a pull-up resistor . Let us call it the NAND circuit shown in Figure 6.18. These NAND circuits are used by Penny-Wise Computer Corporation in their computer boards. In one ill-fated shipment of computer boards, the outputs of a pair shown in of NAND circuits get shorted accidentally resulting in the effective Circuit Figure 6.18.
RL

A B C D

NAND circuit NAND circuit

E

NAND circuit
Figure 6.18:

Circuit X

a) What logic function does Circuit X implement? Construct its truth table. b) If we connect identical NAND circuits together in parallel forming Circuit as shown in Figure 6.19, what is the general form of the logic function it implements? c) If for each MOSFET, , , and , how many NAND circuits can we connect in parallel and still satisfy the static discipline for the voltage thresholds given by: V and V. d) We now connect 10 identical NAND circuits together and have the resulting Circuit satisfy the static discipline for the voltage thresholds in Part c) with . Give speciﬁcations on the dimensions of the MOSFETs such that total MOSFET area is minimized. As before, assume that the area of a device is . Assume that and no resistor dimension or MOSFET gate dimension should be smaller than . For what inputs does Circuit dissipate maximum static power, and what is that power? e) Now, suppose choose a static discipline with voltage thresholds given by: V, V, V and V. As before, each MOSFET has
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170

CHAPTER 6. THE MOSFET SWITCH
I1 I2 I3 I4

NAND circuit NAND circuit Out

I2n-1 I2n

NAND circuit Circuit Y
Figure 6.19:

, , and . How many NAND circuits can we connect in parallel and still satisfy this static discipline? f) Repeat part (d) assuming the voltage thresholds given in part (e). Solution: a) Shorting the two NAND circuits is like putting two ’s in parallel above the output line and two pairs of MOSFETS in parallel where each pair is in series. Circuit X should implement the following logic function
¢

b) The logic function has the following form
©7

c) The only relevant threshold that we have to consider is NAND gate on, the following must be satisﬁed

We now have two MOSFETs in series giving us an of 1k . Our worst case with circuits would have only 1 of NAND gates on but we can’t change the fact that ¡

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0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 there are equation.

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0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

1 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0

’s in parallel giving an equivalent of

/ resulting in the following

Plugging in the values, we see this equation is satisﬁed for

11.11 so

d) Again looking at one NAND circuit, it must satisfy the following equation where =2 = 2k since there are two MOSFETs in series

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To maximize the static power, we want the equivalent possible since

and

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to be as small as

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172

CHAPTER 6. THE MOSFET SWITCH

If we turn all inputs on, the equivalent has 10 pairs of MOSFETs in parallel which gives 0.56 and the 10 resistors in parallel gives 50 .

Problem 6.9 Consider a family of logic gates which operates under the static discipline with the following voltage thresholds: V, V, V and V. a) Graph an input-output voltage transfer function of an inverter satisfying the voltage thresholds given above. b) Using the switch-resistor MOSFET model, design an inverter satisfying the static discipline for the above voltage thresholds using an n-channel MOSFET with and . Recall, . Assume and for a resistor is . Further assume that the area of the inverter is given by the sum of the areas of the MOSFET and the resistor. Assume that the area of a device is . The inverter should take as little area as possible with minimum size for or being . Graph the input-output transfer function of the inverter. What is the total area of the inverter? What is its static power dissipation? Solution: a) See Figure 6.20 b) Basically, we need to sift through the given information to see what is important. When the MOSFET is off, there is no current ﬂowing, thus the power dissipated is zero, and the output is just . When the MOSFET turns on, the output must become less than or equal to . A voltage divider relationship results in the following equations

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If we make each ratio a bit above or about 4.25 and use the minimum dimension of , we get the following values for our design

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Substituting,

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After lots of algebra,
5 VOH VOL VO

D 3 D

Figure 6.20:
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173

174

CHAPTER 6. THE MOSFET SWITCH

Chapter 7 The MOS Ampliﬁer
Exercises
Exercise 7.1 Determine the voltage shown in the circuit in Figure 7.1 when

VS

+ -

R

+ v -

i = f(v) Figure 7.1: Solution:

175

7

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¨

across the voltage-dependent current source

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CHAPTER 7. THE MOS AMPLIFIER

ANS::

Exercise 7.2 Consider the circuit containing the dependent current source shown in Figure 7.2.

vI

+ -

c) Determine d) Determine Solution:

in terms of in terms of

if

. What are the units of . What are the units of

if

is in units of

b)

has no units.

c)

has units of

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a)

or Siemens.

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b) Determine

in terms of

if

. What are the units of

s

a) Determine

in terms of

if

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iB RI + vB RL iD

+

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Figure 7.2:

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177 d)
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Exercise 7.3 The resistance in the circuit shown in Figure 7.3 depends on the voltage across resistor . Determine if

RA RB + vB -

VS

+ -

R=f(vB)

Figure 7.3: Solution:

Exercise 7.4 A MOSFET is characterized by the following equation

in its saturation region. A MOSFET operates in the saturation region for

and

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, units: none (c)

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178
¢

CHAPTER 7. THE MOS AMPLIFIER constraint in terms of and

Solution:

Exercise 7.5 The MOSFET in Figure 7.4 is characterized by the equation

in its saturation region according to the SCS model. The MOSFET operates in the saturation region for and The MOSFET operates in its triode region for

and

Suppose the MOSFET is characterized by the SR model in its triode region. In other words,

in the triode region. Assume that is a constant with respect to value is some function of . Further suppose that when

and

.

1 Ω
G D S

+ vR + vD -

+ -

5 sin (ωt )

5 V + -

Figure 7.4:

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Express the
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, but its

179 a) For , what value of makes the MOSFET versus istic continuous between its triode and saturation regions of operation.

versus for the circuit shown in Figure 7.4. This circuit is useful in b) Plot plotting the MOSFET characteristics. Assume that and . Use the value of calculated in (a). Use a volt scale for and a millivolt scale for . Solution: a) Boundary between triode and saturation regions is when
¢ @ 2
¢

b)

MOSFET is in triode region for saturation region, .
9 )

. In triode region,

vR 10mV

-5V

5V vD

-10mV

Figure 7.5: See Figure 7.5.

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180

CHAPTER 7. THE MOS AMPLIFIER

Exercise 7.6 Consider the MOSFET ampliﬁer shown in Figure 7.6. Assume that the ampliﬁer is operated under the saturation discipline. In its saturation region, the MOSFET is characterized by the equation

where is the drain-to-source current when a voltage source terminals.

VS RL D G vI + S
Figure 7.6:

vO iDS

a) Draw the equivalent circuit for the ampliﬁer based on the SCS model of the MOSFET. b) Write an expression relating c) Write an expression relating d) Write an expression relating to

. .

to to

.

e) Suppose that an input voltage results in an output voltage . By what factor must be increased (or decreased) so that the output voltage is doubled. f) Suppose, again, that an input voltage results in an output voltage . Suppose, further, that we desire an output voltage that is . Assuming that both the input voltage and the MOSFET do not change, what are all the possible ways of accomplishing the desired doubling of the output voltage. g) The power consumed by the MOSFET ampliﬁer in Figure 7.6 is given by , assuming that no current is draw out of the terminal. Which of the alternatives for doubling from parts (e) and (f) will result in the lowest power consumption.

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f)

Solution:

This can be accomplished by changing Scale by factor for

By changing

:

vI

+

-

Figure 7.7:

VS

RL

,

otherwise

iDS

vO

, or by changing both. 181

182

CHAPTER 7. THE MOS AMPLIFIER
Scale by factor

. This will only work if

By changing

:

By changing Scale

and
¡

by factor

and scale

by factor

g) The alternative from part e results in the lowest power consumption.

Exercise 7.7 Consider, again, the MOSFET ampliﬁer shown in Figure 7.6. Assume that the ampliﬁer is operated under the saturation discipline. The MOSFET in doctored so its threshold voltage is 0. In other words, the saturation region of the MOSFET is now characterized by the equation

where is the drain-to-source current when a voltage is applied across its gateto-source terminals. The following questions relate to the large-signal analysis of the ampliﬁer. a) Derive the relationship between the output voltage and the input voltage

b) Derive the range of valid input voltages. Under the saturation discipline, valid input voltages are those which result in saturation region operation of the ampliﬁer. Determine the corresponding range of output voltages ( ) and output currents ( ). c) Suppose we wish to amplify an AC input signal . Assume that has a zero can be DC offset. Draw a circuit showing how a separate DC input voltage used to bias the ampliﬁer in a region where saturation region operation is achieved for both positive and negative excursions of . Assuming the has symmetric positive and negative swings, how would you choose the input operating point for the ampliﬁer which allows a maximum peak-to-peak voltage range for . What is the corresponding output operating point ( and ).

w1

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1

7¢

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(d) (g) e

for

;

otherwise (e)

.

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(c)

for

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by factor

: where

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b)

c) See Figure 7.8.

Solution:

An operating point that is in the middle of the range of valid inputs allows a maximum peak-to-peak voltage range for .

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¢s ¤ s ¤

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183

184

CHAPTER 7. THE MOS AMPLIFIER

Exercise 7.8 The three terminal device shown in Figure 7.9a is called a bipolar junction transistor (BJT). Figure 7.9b shows a piecewise linear model for the device, in which the parameter is a constant. When and the emitter diode behaves like a short circuit, the collector diode like an open circuit, and the collector current is given by Under the above constraints, the BJT is said to operate in its active region. For the rest of this exercise, assume that .
( a § @ §

C iC B iB
+

+

vCE
-

vBE

iE E

-

(a)

Figure 7.9: (a) A bipolar junction transistor. B stands for base, E for emitter and C for collector. (b) A piecewise linear model for the BJT a) Determine the collector current using the model in Figure 7.9b.
§ 9 1

for a base current
¤

and

b) Sketch a graph of versus for . using the model in Figure 7.9b. In drawing this graph, assume that the current source turns off for
a

Solution:

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§ ' § 1

¢ £

1

§

a) Since

and

, the BJT operates in its active region.

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-

185
§

b) The graph of Then, for ANS:: (a)
1 9 §

versus

For

from 0 to 0.2V,
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greater than 0.2V,
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Exercise 7.9 Consider the bipolar junction transistor (BJT) ampliﬁer shown in Figure 7.10. Assume that the BJT is characterized by the large signal model from Exercise 7.8, and that the BJT operates in its active region. Assume further that , , , and .

VS RL iC iB vI + RI
B C E

vO

β

iE
Figure 7.10:

a) Draw the equivalent circuit for the BJT ampliﬁer based on the large signal BJT model from Exercise 7.8. b) Write an expression relating c) Write an expression relating d) Write an expression relating e) Write an expression relating to to to
§ 1

. . .

to

.
¢a £(

Solution: a)

§

1

f) What is the value of values of , and
1

for an input voltage .

V? What are the corresponding

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186 b)

CHAPTER 7. THE MOS AMPLIFIER

c)

d)

e)

Or, substituting known values

(f)

,

,

, and

Exercise 7.10 In this exercise you will perform a large signal analysis of the BJT ampliﬁer shown in Figure 7.10. Assume that the BJT is characterized by the large signal model from Exercise 7.8. Assume further that , , , and . a) Write an expression relating to .

b) What is the lowest value of the input voltage for which the BJT operates in its active region? What are the corresponding values of , , and ? c) What is the highest value of the input voltage for which the BJT operates in its active region? What are the corresponding values of , , and ? d) Sketch a graph of Solution: versus for the parameter values given above.

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187 a)

Or, substituting known values

b)
H& a

The BJT goes into cutoff if
S2

goes any lower. , , and are as follows.

The corresponding values of .

c) As increases, the BJT enters saturation when the collector diode gets forward biased. This happens when the base voltage is greater than the collector voltage by , or when falls to 0.2V. The 0.4V. In other words, when corresponding value of is obtained by solving

Solving, we get . In other words, when 0.2V, and the BJT goes into saturation. The corresponding values of , and . d) A graph of versus , , and

rises to 3V, the output falls to ,

are as follows.

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188

CHAPTER 7. THE MOS AMPLIFIER

Problems
Problem 7.1 Consider the MOSFET voltage divider circuit shown in Figure 7.11. Assume that both MOSFETs operate in the saturation region. Determine the output voltage as a function of the supply voltage , the gate voltages and , and the MOSFET geometries and . Assume that the MOSFET threshold voltage is , and remember, .

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Figure 7.11: Solution: Since the current through both MOSFETs must be the same, such that this is the case.
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Problem 7.2 An inverting MOSFET ampliﬁer is shown in Figure 7.12, together with an characteristic for the MOSFET. This characteristic is simpler than the SCS model presented in this chapter. The characteristic is simply the standard MOSFET characteristic with the triode region compressed onto the Y axis.

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189 Alternatively, this characteristic can be viewed as describing ideal switch behavior that is extended to exhibit a saturating drain-source current. In other words, for , the MOSFET behaves like an open switch with . For , the MOSFET behaves like a closed switch with provided that . However, once reaches , which is the maximum current the MOSFET can carry for a given , MOSFET operation enters a saturation region in which the MOSFET behaves as a current source of value . Saturated operation is as described by the saturation model given in Figure 7.12.

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Figure 7.12: a) Determine as a function of for

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b) What is the lowest value of

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190

CHAPTER 7. THE MOS AMPLIFIER

a) When there is current going through , the current is limited by two quantities: either or , whichever is lower. If the limit is , then the MOSFET is in the closed-switch region. If the limit is , then the MOSFET is in the saturation region. open-switch region For , the MOSFET is open, therefore

closed-switch region increases until it reaches at some gate voltage . Now drops to zeros, and both and are no longer affected by the increase in . In summary,

b) The lowest value of for which occurs when is at the transition between the saturation region and the closed-switch region. At this point, the saturation region current limit and the closed-switch region current limit are the same,

Solving for

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c) Combining the results of part (a) and (b), we obtain the following equations.

The graph is shown in the ﬁgure.

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Problem 7.3 A two-stage ampliﬁer is shown in Figure 7.13. It is constructed by cascading two one-stage ampliﬁers of the type seen in Problem 7.2. In analyzing this ampliﬁer, use the MOSFET model described in Problem 7.2 and illustrated in Figure 7.12.

vIN

+ -

a) The fact that a second ampliﬁer stage is connected to the ﬁrst ampliﬁer stage does not change the operation of the ﬁrst stage. That is, the relation between and here is the same as the relation between and in Problem 7.2. Why? What terminal characteristic of the second MOSFET must change in order for this not to be true?

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b) Derive the relation between and for

and for , and the relation between . Hint: see Problem 7.2.

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192 c) Derive the relation between and

CHAPTER 7. THE MOS AMPLIFIER for d) Determine the range of input voltages for which both MOSFETs operate under the and ? saturation discipline. What are the corresponding ranges for e) Using the numerical parameters given in Problem 7.2, graph versus for for 0 V V. Compare this graph to the input-output graph found in Problem 7.2, and explain the differences. Solution: a) The second ampliﬁer does not change the operation of the ﬁrst because its input draws no current. If the second ampliﬁer drew current from the ﬁrst, then the output of the ﬁrst ampliﬁer would be affected by the input resistance of the second ampliﬁer. b) There are three modes of operation for each ampliﬁer. The cutoff and the saturation modes will be considered, and the triode mode will be ignored for now. In saturation, the equations derived in Problem 8.2 remain valid, as does the threshold voltage. We must also ﬁgure out the threshold between the saturation and triode regimes. The MOSFET is in saturation when . This implies that , or that . This implies that
V

Let us deﬁne

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193 c) This part is trickier. First of all, if then , so the second FET will be either in saturation or triode, depending on the value of R. Let us ﬁnd the condition for saturation. a Simplifying this, one gets:

Let us assume that R is large enough that if , the second FET will be in triode. Then, while the ﬁrst FET is in saturation, we can ﬁnd the minimum value for which the second FET also enters saturation. a Substituting in for

and simplifying, we get that

Now, we can prove that the second FET entered saturation before the ﬁrst FET left it. We prove that the value just derived is less than the boundary condition for the ﬁrst FET to leave saturation. This expression:

Must be less than this expression:

This simpliﬁes to

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194

CHAPTER 7. THE MOS AMPLIFIER

This is always true for NFETs, which is what we are using, so we have proven that there will be a range for which both FETs are in saturation. Next, either the ﬁrst FET will enter triode, or the second will enter cutoff. Since we are not dealing with the triode region, it is easier to assume that the second will enter cutoff while the ﬁrst is still in saturation. Therefore, we want to have both of the following equations satisﬁed:

We ﬁnd the threshold condition for these two inequalities by setting the lower and upper bounds of the same. Simplifying, we get that a We now have two conditions on that must both be met. For now, assume that and . Therefore, we must make . We will choose and . We must now calculate the ﬁnal branch of our voltage transfer graph, which is when both inverters are in saturation. Substituting previously derived equations, we get that

In summary, if

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195

is a constant, and is an undetermined function, since both would require the use of triode equations. d) This is the third region in the previously calculated transfer function. a ¡

This holds when a e) Using the formulas derived in part (c), we ﬁnd

This is shown in Figure 7.14. Note that the transition region of this two-stage ampliﬁer is much narrower than that of the single-stage ampliﬁer earlier. This is because when the second ampliﬁer is saturated, the ﬁrst ampliﬁer is also saturated. Since is the output of the ﬁrst values. stage, its range maps into a much smaller range of ANS:: (d)

Problem 7.4 Consider again the two-stage ampliﬁer shown in Figure 7.13. Suppose that the MOSFETs are characterized by the following equation in their saturation region:

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196

CHAPTER 7. THE MOS AMPLIFIER
5 vOUT

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Figure 7.14: In other words, the threshold voltage their saturation region when

Show that there is only one input voltage for which both stages simultaneously operate under the saturation discipline. What is that input voltage? Solution:

For the saturation discipline to hold for both, the following inequalities must all be met: , , , . Substituting the equations from above,

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197 Therefore since , we ﬁnd that and , so must equal for both MOSFETs to both adhere to the saturation discipline. Solving the equation , we ﬁnd that this occurs when

ANS::

Problem 7.5 Consider the “source-follower” or “buffer” circuit shown in Figure 7.15. Use the SCS MOSFET model (with parameters and ) to perform a large-signal analysis of this circuit according to the following steps.

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D

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Figure 7.15:

a) Assuming that the MOSFET operates in its saturation region, show that related to according to a b) Determine the range of over which the assumption of saturated MOSFET oper? ation holds. What is the corresponding range for Solution: a) By Ohm’s law,

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198

CHAPTER 7. THE MOS AMPLIFIER
VS Equivalent MOSFET iD model (saturation) vIN + R + vOUT Figure 7.16: Substitute in the formula for the current source:

Substitute for

:

This can be solved using the quadratic formula to obtain: a This simpliﬁes to:

We will determine which root to use in part (b).
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199 b) Two conditions must be met for the MOSFET to remain in saturation:

Note that condition (1) also requires that

Thus we must take the negative root in the formula for

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ANS:: (b)

Problem 7.6 This problem studies the use of a mythical MOSFET-like device called a ZFET to construct an ampliﬁer as shown in Figure 7.17. The ZFET operates in its saturation region when and . In this region, the drain-source terminal relation , where is a constant having units of A/V . When , the ZFET is exhibits a short circuit between its drain and source terminals, and is said to operate outside its saturation region. Similarly, the ZFET exhibits an open circuit for as it again operates outside its saturation region. Finally, the gate terminal always exhibits an open circuit. These characteristics are summarized in the ﬁgure, beneath the symbol for the ZFET.

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200

CHAPTER 7. THE MOS AMPLIFIER

ZFET Symbol D + iDS vDS G + vGS S 3 K v GS

ZFET Ampliﬁer VS RL vOUT D

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G S

i DS =

For v GS ≥ 0

v DS > 0

Figure 7.17:

201 a) Assuming saturated operation of the ZFET, determine b) Over what range of as a function of

will the ZFET operate in its saturation region?
V

d) Given the parameters of part (c), can the ampliﬁer can be used as an inverter that provides a valid output high voltage threshold of V. Why or why not? Assume that V. e) Given the parameters of part (c), can the ampliﬁer can be used as an inverter that provides a valid output high voltage threshold of V. Why or why not? This time around, assume that V. Solution: a) Using a single KVL equation, we get that , where is the voltage drop across the resistor. This is given by the current through the ZFET (since it is the same as the current through the resistor) multiplied by the resistance. Therefore, we get that ¢
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CHAPTER 7. THE MOS AMPLIFIER

10

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203 Problem 7.7 Consider the difference ampliﬁer circuit shown in Figure 7.19. Notice that the difference ampliﬁer is powered by and power supplies. Assume that all MOSFETs operate under the saturation discipline, and, unless indicated otherwise, are characterized by the parameters and . and for the connection shown in Figure 7.19a. In this ﬁgure, the a) Determine gates of the MOSFETs are connected to ground. b) Consider the difference ampliﬁer version shown in Figure 7.19b. In this ﬁgure, a MOSFET implementation of a current source replaces the abstract current source from Figure 7.19a. Determine values for and such that the circuit in (b) is equivalent to that in (a). c) The difference ampliﬁer in Figure 7.19c is driven by two input voltages and as shown. Assume that the input voltages satisfy the following constraint at all times. Determine , , and as a function of . Solution: a) Because both FETs are identical, we know that . Solving for , and

b) The current through the new mosfet must be equal to the current of the old current source, , where . The gate to source voltage of the new MOSFET is . Substituting and letting be the value associated with the transistors of part a.,

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c) Using MOSFET characteristics and KVL, . By KVL, and using the above equations and cancelling,

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204

CHAPTER 7. THE MOS AMPLIFIER

Problem 7.8 Consider the ampliﬁer circuit shown in Figure 7.20. The ampliﬁer is powered by a and a power supply.

a) Determine and as a function of under the saturation discipline. Assume that the MOSFET parameters and are given. b) Determine the range of valid input voltages for saturation region operation. Determine the corresponding valid range for and . c) Determine the output voltage when the input is grounded. In other words, for . d) Determine the value of parameters. Solution: a) Using a single Kirchoff voltage loop, we get that can also get that a for which

in terms of

,

and the MOSFET

For the threshold between saturation and cutoff: off at this point, so and . For the threshold between saturation and triode:

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b) The two threshold conditions are

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Figure 7.20:

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205

Simplifying this, one gets that the saturation range is a For the upper bound, the current and output voltage can be found by substituting into the saturation equation. The current is: a This can be simpliﬁed to:

The voltage can be found by ﬁnding the voltage drop across the resistor and subtracting it from the supply voltage. a c) We must ﬁrst determine which region we are in. If then we are in cutoff and . This is not very likely for our purposes, since our supply voltages are at least 3 volts usually, and MOSFET threshold voltages tend to be below 2.5 volts. (For lower supply voltages, lower threshold voltages are used too.) However, if the following condition exists, then we are in triode:

Using the values V and V, we can ﬁnd a a suitable threshold for KR. Solving the quadratic equation results in the possibilities (not possible) or . Therefore, if we want to be in saturation for the chosen voltages, then we have to choose . If we are in saturation, then by substitution: a @

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206 d) For this, assume that we are in saturation.

CHAPTER 7. THE MOS AMPLIFIER

This can be solved for

, resulting in:

(d)

Problem 7.9 Consider the current mirror circuit in Figure 7.21.

VS I W1 ------L1 (a) RC

VS IL I W2 ------L2 + V - L W1 ------L1 (b)
Figure 7.21:

RC

a) Referring to Figure 7.21a, determine as a function of assuming both MOSFETs operate under the saturation discipline. Both MOSFETs have the same values for and . Does change if changes? What are the conditions under which ? b) Now consider Figure 7.21b. The current can be increased either by increasing or decreasing . Assuming that either or may be changed, and that , determine the range of values of for which both MOSFETs operate under the saturation discipline. Assume both MOSFETs have the same values for and . Solution:

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(c)

IL

RL

W2 ------L2

+ V - L

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207 a) We know that . Therefore, substituting appropriate parameters, . The equation for can not change if changes as is not present anywhere in the equation for . Logically this is so because a MOSFET’s drain to source current is only dependent on its input voltage, its threshold voltage, and its geometric parameters, of which only its input voltage can can have no effect on this MOSFETs input voltage due the conbe changed, and ﬁguration of the circuit. As the input voltages for both MOSFETs are equivalent, will equal when . . Substior for both , the second inequality always , where we know that . Finally,

¡

Problem 7.10 Consider the circuit shown in Figure 7.22. Assume that the MOSFET operates under the saturation discipline.

+

VS

-

a) Draw the SCS equivalent circuit by replacing the MOSFET by its SCS model. b) Determine . Solution: a) See Figure 7.23. and in terms of , , , and the MOSFET parameters

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b) To operate under the saturation discipline, tuting into the ﬁrst inequality from part a., MOSFETs. Given that for MOSFET 1 holds for that MOSFET. For MOSFET 2, . Substituting and solving,
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208

CHAPTER 7. THE MOS AMPLIFIER
ID vO RS
+

RD
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VS

-

Figure 7.23: b) By KVL, and . Expanding, . From here we can solve for

and substitute into the equation

.

Problem 7.11 Consider the “common-gate ampliﬁer” circuit shown in Figure 7.24. Assume that the MOSFET operates under the saturation discipline.

S vI
+

D ID G

vO RD
+ VS -

+ -

VS

Figure 7.24:

a) Draw the SCS equivalent circuit by replacing the MOSFET by its SCS model. b) Determine . and in terms of , , , and the MOSFET parameters

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209 c) Determine the range of values of for which the MOSFET operates under the saturation discipline. What is the corresponding range of ? Solution: a) See Figure 7.25.

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VS

Figure 7.25: b) There is only one relevant current, and it passes through the MOSFET, so we assume that the MOSFET is in saturation and use the relevant formula. a Then, using a Kirchoff voltage rule, we can ﬁnd that a For the boundary between saturation and cutoff: a And for the boundary between saturation and triode: a These two can be simpliﬁed to get

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210

CHAPTER 7. THE MOS AMPLIFIER

The output conditions can be found by substituting into the previously derived formula. Simplifying results in a I

Problem 7.12 Consider the MOSFET circuit shown in Figure 7.26. Determine the value of in terms of the other circuit parameters. Assume the MOSFET is in saturation and is characterized by the parameters and .

VS

R1 vA R2

RL vO

Figure 7.26: Solution: Due to the fact that the gate of a MOSFET has no input current, we can determine the Thevenin equivalent of the voltage divider produced by , , and to ﬁnd and then substitute appropriate parameters into the KVL equation .

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VS RL RF vA RG vO

Figure 7.27: Problem 7.13 Consider the MOSFET circuit shown in Figure 7.27. Determine the value of in terms of the other circuit parameters. Assume the MOSFET is in saturation and is characterized by the parameters and . Solution: Due to the fact that the gate of a MOSFET has no input current, we can determine the Thevenin equivalent of the voltage divider produced by , , and to ﬁnd . If the current through is , the current produced by the MOSFET is , and the current through is , by KCL . By KVL, , which is equal to . Solving for in terms of and substituting into our KCL equation, we can solve for .

Finally, because

, we ﬁnd that

Problem 7.14 Figure 7.28 shows a MOSFET ampliﬁer driving a load resistor . The MOSFET operates in saturation and is characterized by parameters and . Determine versus for the circuit shown. Solution:
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212

CHAPTER 7. THE MOS AMPLIFIER
VS RL vO RE

vI + -

Figure 7.28: First of all, assume that the circuit is in saturation. Call the three currents as follows: through resistor : , through the MOSFET: , and through resistor : . All three of them point from higher voltage to lower, so therefore . This is shown in Figure 7.29.

VS i1 RL vO i2 RE

vI + -

i3
Figure 7.29:

The three currents can be determined in terms of
¢

,

, and MOSFET parameters:

Substituting this into the KCL equation and solving for

, we get a ¥

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213 However, this only applies for when the MOSFET is in saturation. We must ﬁnd the range of for which this holds valid. The boundary between saturation and cutoff is merely . The boundary between saturation and triode can be found as follows. a Solving this for

, one gets the following boundary conditions for saturation: a For the cutoff region, we can ﬁnd the output voltage through a simple voltage divider relation, since no current ﬂows through the MOSFET: a The voltage transfer characteristic for triode region will not be considered for this problem.

Problem 7.15 Determine versus for the circuit shown in Figure 7.30. Assume that the MOSFET operates in saturation and is characterized by the parameters and . What is the value of when ? Solution: Start off with the following KVL equation, where across , the MOSFET, and , respectively.
@

,

, and

are the voltages

This is shown in Figure 7.31. Since the voltage across a resistor is equal to the current through it times the resistance, and there is only one relevant current in the problem, we can rewrite the equation as follows: a Now, we must ﬁnd the current. Assume that the MOSFET is in saturation - we will ﬁnd the boundaries for this assumption to be valid in a bit.

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214

CHAPTER 7. THE MOS AMPLIFIER

+ VS RD vI vO RS - VS +
Figure 7.30:

+ VS RD vI iFET vO RS - VS +
Figure 7.31:

215

We solve for to get

Now, we must ﬁnd the boundary conditions for the saturation region. For the boundary between saturation and cutoff, there is no current ﬂowing through the MOSFET, so there is no voltage drop across the resistors, so we simply have a I U@

Now, for the boundary between saturation and triode, we have this equation. a Let

, and substitute in for : a We solve this for

since that is in terms of
¡

and constants.

Now, solve for

, and ﬁnd the boundaries of the saturation region:

Now, to actually ﬁnd . Using a KVL equation, we can ﬁnd that In cutoff, since there is no current through the resistors. In saturation,

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216

CHAPTER 7. THE MOS AMPLIFIER

When there is an input voltage of zero, the system could be in cutoff, saturation, or triode. For typical values of and , the device will not be in cutoff. But if it were, the output voltage would be . For values of V, and V, we can ﬁnd a relation between that allows the device to avoid the triode region. If we substitute into the boundary condition, we get this relation: , , and

Further analysis is optional - we can assume that the device is in saturation for . If this is the case, then

Problem 7.16 Determine versus for the circuit shown in Figure 7.32. Assume that the MOSFET operates in saturation and is characterized by the parameters and . What is the value of when ? Solution: Most of the work has already been done in the previous problem. The boundaries for cutoff, saturation, and triode remain the same, as does the current. All that changes is the output voltage. Using a KVL equation, we ﬁnd that In cutoff, . In saturation, we get that
¢

. This is shown in Figure 7.33.

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217

+ VS RD vO vI

RS - VS +
Figure 7.32:

+ VS RD vO vI iFET RS - VS +
Figure 7.33:

218

CHAPTER 7. THE MOS AMPLIFIER

For an input voltage of zero, we will assume that the system is in saturation since the cutoff calculation is simply the rail voltage , and the triode calculations are unnecessarily terrible. In saturation,

Problem 7.17 Determine versus for the circuit shown in Figure 7.34. Assume that the MOSFET operates in saturation and is characterized by the parameters and .

VS RL R2 vI R1 vO

Figure 7.34: Solution: First of all, deﬁne to be the gate voltage. Also, deﬁne three currents , , and to be the currents ﬂowing through , , and the MOSFET, respectively. Deﬁne to be ﬂowing towards ground, and let . This is shown in Figure 7.35. The gate voltage can be found through a voltage divider rule since no current ﬂows from between and to the gate.

In cutoff, the output voltage and the input voltage are related by a voltage divider rule:

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219

VS i1 RL R2 vI R1 i2 vO

i3

Figure 7.35: In saturation, we have an extra current to worry about. We substitute into our original KCL equation to get

with the following subexpressions:

The boundaries for which the device is in saturation can be found by evaluating and . This evaluation is even more complicated than the previous equation, since is given in terms of , and needs to be put in terms of . In terms and , the boundary conditions are derived much more easily. of both Between saturation and cutoff:

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a

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, but it ends up being quite monstrous. Let

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220

CHAPTER 7. THE MOS AMPLIFIER

Between saturation and triode:

Problem 7.18 Consider the BJT circuit called the “common-collector ampliﬁer” shown in Figure 7.36. This BJT ampliﬁer conﬁguration is also called the source follower circuit. For this problem, use the piecewise linear BJT model from Exercise 7.8. Assume that the BJT operates in its active region.

VS iC iB RI vI + B C E

β

vO

RE

Figure 7.36:

a) Draw the active-region equivalent circuit of the BJT source follower by replacing the BJT by its piecewise linear model.
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b) Assuming active region operation, determine parameter .

in terms of

,

,

e) Determine the range of values of for which the BJT operates in its active region for the parameter values given in (d). What is the corresponding range of ? Solution:

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d) Compute the value of .
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given that

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c) What is the value of

when

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and the BJT

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At the high end, must not be too large, or else the BJT will enter saturation. The BJT enters saturation when

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Or, Therefore, we need to solve for We know In other words, when , so that the BJT is not in cutoff. 221 from

222 Thus the constraints on

CHAPTER 7. THE MOS AMPLIFIER

The corresponding constraints on

are
H& a

Problem 7.19 Consider the compound three terminal device formed by connecting two BJTs in the conﬁguration shown in Figure 7.37. The three terminals are labeled , and . The two BJTs are identical, each with . Assume that each of the BJTs operates in the active region.

C’

B’

β β

E’
Figure 7.37:

a) Draw the active-region equivalent circuit of the compound BJT by replacing each of the BJTs by the piecewise linear model shown in Exercise 7.8. Clearly label the , and terminals. b) In the conﬁguration shown, the compound device behaves like a BJT. Determine the value of the current gain for this compound BJT.

Solution: a)

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c) When the base current nals.

, determine the voltage between the

and

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for active region operation are

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223 b) The current gain of the new device is given by

c) When the base current , both transistors are in their active region. In this situation, the voltage between the and terminals is 1.2V. ANS:: (b) (c) 1.2V

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224

CHAPTER 7. THE MOS AMPLIFIER

Chapter 8 The Small Signal Model
Exercises
Exercise 8.1 Consider the ampliﬁer shown in Figure 8.1. The MOSFET operates in its saturation region and is characterized by the parameters and . The input voltage comprises the sum of a DC bias voltage and a sinusoid of the form . Assume that is very small compared to . Let the output voltage comprise a DC bias term and a small-signal response term .

VS RL vO Asin(ωt) + VI + -

Figure 8.1:

a) Determine the output operating point voltage

for the input bias of

.

b) Determine the small signal gain of the ampliﬁer. 225

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226

CHAPTER 8. THE SMALL SIGNAL MODEL

c) Draw the form of the input and output voltages as a function of time, clearly showing the DC and time-varying small-signal components. Solution: a)

c) See Figure 8.2. ANS:: (a)
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Exercise 8.2 Develop the small signal model for a two-terminal device formed by a MOSFET with its gate tied to its drain, operating under the saturation discipline, with parameters and . Solution:
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Exercise 8.3 Develop the small signal model for a two-terminal device formed between the drain and source terminals of a MOSFET with a 2 volt DC source connected between its gate and source terminals ( ). Assume the MOSFET operates under the saturation discipline. Assume further that volt for the MOSFET. Solution:

In other words, the two-terminal device formed between the drain and source terminals of the MOSFET is a current source with current . Thus, the small signal model of the two-terminal device is an open circuit.

7

ANS:: Current source

, so that the small signal model is an open circuit

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vI VS VI + A VI VI - A

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Figure 8.2:

228

CHAPTER 8. THE SMALL SIGNAL MODEL

Exercise 8.4 Consider the MOSFET ampliﬁer shown in Figure 8.3. Assume that the ampliﬁer is operated under the saturation discipline. In its saturation region, the MOSFET is characterized by the equation

where is the drain-to-source current when a voltage source terminals.

VS RL D G vI + S
Figure 8.3:

vO iDS

a) Write an expression relating to . What is its operating point output voltage , given an input operating point voltage of ? What is the corresponding operating point current ? b) Assuming an operating point input voltage of , derive the expression relating the small signal output voltage to the small signal input from the relationship between and . What is the small signal gain of the ampliﬁer at the input operating point of ? c) Draw the small signal equivalent circuit for the ampliﬁer based on the SCS model of the MOSFET assuming the operating point input voltage is . d) Derive an expression for the small signal gain of the ampliﬁer from the small signal equivalent circuit. Verify that the gain computed from the small signal equivalent circuit is identical to the gain computed in part (b). e) By what factor must change to double the small signal gain of the ampliﬁer? What is the corresponding change in the output bias voltage? f) By what factor must change to double the small signal gain of the ampliﬁer? What is the corresponding change in the output bias voltage?

¨

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7¥ ¢ is applied across its gate-to-

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Exercise 8.5 Consider again the MOSFET ampliﬁer shown in Figure 8.3. Assume as before that the MOSFET is operated under the saturation discipline, and that its parameters are and .
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c) See Figure 8.4.

f)

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To double the small signal gain, scale

The small signal gain is

+ vi -

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Figure 8.4:

must double. This will decrease

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230

CHAPTER 8. THE SMALL SIGNAL MODEL

a) What is the range of valid input voltages for the ampliﬁer? What is the corresponding range of valid output voltages? b) Assuming we desire to use voltages of the form as AC inputs to the ampliﬁer, determine the input bias point for the ampliﬁer which will allow maximum input swing under the saturation discipline. What is the corresponding output bias point voltage ? c) What is the largest value of point determined in (b)? that will allow saturation region operation for the bias

d) What is the small signal gain of the ampliﬁer for the bias point determined in (b)? e) Suppose is small compared to . Write an expression for the small signal output voltage for the bias point determined in (b). Solution:

a)

b) To maximize input swing, pick

in the center of the range of valid input voltages.

d)

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231 Exercise 8.6 Consider once more the MOSFET ampliﬁer shown in Figure 8.3. Assume as before that the ampliﬁer is operated under the saturation discipline, and that its parameters are and . a) Using the small signal circuit model of the ampliﬁer, and assuming an input bias voltage , determine the small-signal output resistance of the ampliﬁer. That is, determine the equivalent resistance of the ampliﬁer at the output port of its smallsignal model with . b) Develop a Th´ venin equivalent model for the small signal ampliﬁer as observed at e its output port. c) What is its input resistance? That is, determine the equivalent resistance of the ampliﬁer at the input port of its small-signal model. Solution:

¡

a)

+ -

b) See Figure 8.5.

Exercise 8.7 Consider the common emitter BJT ampliﬁer shown in Figure 8.6. The input voltage comprises the sum of a DC bias voltage and a sinusoid of the form , where V. For the values shown, you may assume that is very
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RL A --- ( 1 – 1 + 2K R L V S ) sin ( wt ) 2

Figure 8.5:

(c)

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232

CHAPTER 8. THE SMALL SIGNAL MODEL

small compared to . You may further assume that the BJT always operates in its active region. Figure 8.7 shows a small signal model for the BJT operating in its active region. Let the output voltage comprise a DC bias term and a small-signal response term .
15 V 50 k Ω 100 k Ω 0.001 V sin(ωt) + 0.7 V + vO β = 100

Figure 8.6:

C iC B iB
+

+

vCE
-

B ib

vBE

iE E

-

(a) BJT

Figure 8.7:

a) Determine the output operating point voltage

for the input bias of

b) Draw the small signal equivalent circuit for the ampliﬁer. c) Determine the small signal gain of the ampliﬁer. d) What is the value of , the small signal component of the output, given the small signal input shown in Figure 8.6. ¡

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(b) BJT small signal model

V.

233 e) Determine the small signal input and output resistances of the ampliﬁer. f) Determine the small signal current and power gain of the ampliﬁer, assuming that the ampliﬁer drives a load that is connected between the output node and ground. Solution: a) We determine the operating point using a large signal analysis of the BJT ampliﬁer. Since a speciﬁc large-signal model of the BJT is not suggested, we will go ahead and use the large-signal model of the BJT (in its active region) suggested in the text book. (The text book gives an example of an operating point calculation for a BJT ampliﬁer in the large-signal ampliﬁer chapter.) The relation between and
H02

(The above formula is also derived in the text book in one of the BJT examples in the large signal ampliﬁer chapter). Substituting known values b) c) Load
S)

is 50k.

d)

Or e)
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234 f) Load is now A current 2 H0t§

CHAPTER 8. THE SMALL SIGNAL MODEL in parallel with
2 H0t§

at the input results in a current

through the collector terminal. This current divides between and according to the current divider relation. The current gain is given by the ratio of and the current through . We must also add on a minus sign since the direction of is opposite to that of . Thus the current gain is given by 1

For the parameter values given

The power gain is the product of the voltage gain and the current gain. The absolute value of the voltage gain with added in parallel with will be cut in half from 50 to 25. Thus, the power gain is given by

ANS:: (a) and

(c)

(d)

(e)

and

Problems
Problem 8.1 This problem studies the small-signal analysis of the MOSFET ampliﬁer discussed in Problem 7.3 (Figure 7.13) in the previous chapter. a) First consider biasing the ampliﬁer. Determine that is biased to where of in the process. , the bias component of , so . Find , the bias component

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235 b) Next, let where is considered to be a small perturbation of around . Make the substitution for and linearize the resulting expression for . Your answer should take the form , where takes the form . Note that is the small-signal output and is the small-signal gain. Derive an expression for . c) For what value of is biased to ? For this value of , evaluate using the numerical parameters given in Problem 7.2 in the previous chapter. You should ﬁnd that this gain is the slope of the input-output graph from Problem 7.3 in the previous chapter evaluated at the bias point. Solution: a)
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From above we can solve for

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b) Let

, we ﬁrst solve for the current

going through the ﬁrst ampliﬁer,

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236

c) Recalling the equation derived in part (a), we get that

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The parameters given previously were V, these parameters, we can ﬁnd a numerical value of proximately 136.

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Now we solve for the current

is related to

by the following equations:

to

,

, which goes through the second ampliﬁer,

CHAPTER 8. THE SMALL SIGNAL MODEL

V, and . From , which turns out to be ap.

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(c)

Problem 8.2 Consider again the buffer described in Problem 7.5 (Figure 7.15) in the previous chapter. Perform a small-signal analysis of this circuit according to the following steps. Assume that the MOSFET operates in its saturation region and continue to use the and . SCS MOSFET model with parameters a) Draw the small-signal circuit model of the buffer. b) Show that the small-signal transconductance
! &

of the MOSFET is given by

where and respectively.

are the bias, or operating-point, input and output voltages,

c) Determine the small-signal gain of the buffer. That is, determine the ratio

d) Determine the small-signal output resistance of the buffer. That is, determine the equivalent resistance of the buffer at the output port of its small-signal model with . e) Assume that V, mA/V , k and V. Under this assumption, design the input bias voltage to satisfy the following two objectives. 0.25 First, MOSFET operation must remain within the saturation region for V. Second, the output resistance of the small-signal model must be minimized. f) Again assume that V, mA/V , k and V, compute the small-signal gain and output resistance.

V. For

g) Determine the small-signal input resistance of the buffer. That is, determine the equivalent resistance of the buffer at the input port of its small-signal model. Solution: a) b) Use the formula for the MOSFET large-signal current source (in saturation):

Expand this formula in a Taylor series for SIGNAL + small-signal).

(Total Signal = LARGE-

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238

CHAPTER 8. THE SMALL SIGNAL MODEL

id=gmvgs vin + R + vout vin

v + gs + -

id=gmvgs

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where the bracketed terms are evaluated at the large-signal bias point Then . Ignoring higher-order terms, where

d) Connect to ground. Apply at the output and measure . Note that and appear to be anti-associated variables, but they will be associated variables for the equivalent resistance we are measuring.

vgs + id=gmvgs vin=0V R

itest + vtest -

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(8.3)

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1

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c) Using small-signal equivalents,
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a a B¥ ¡ a

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@

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(8.1)

(8.2)

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239 e) To minimize the output resistance for a ﬁxed value of R, we need to maximize
¤ &
£ ¦

.

Substitute in the formula for

:

f) Find

using equation (3) (derived in Exercise 5-1).
¢

Plug-and-play using equations (5) and (6):

g) The input resistance is inﬁnite since the gate of a MOSFET has inﬁnite input impedance.

Problem 8.3 This problem studies the small signal analysis of the ZFET ampliﬁer from Problem 7.6 (Figure 7.17) in the previous chapter. Assume that the ampliﬁer is biased at an input voltage such that the ZFET exhibits saturated operation; the corresponding bias output voltage is . For this case, derive the small-signal voltage gain of the ampliﬁer. Solution: Referring to Problem 7.6, the large signal output is derivative of this with respect to , one gets that . Taking the

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ANS:: (c)

(d)

(e) 10.75V (f)

T (V a

¡ V V V SSB§ ¢

@ 7 §

T (V a

V

V V S9V

4 $ 1 (&

¢

Find

using equation (4).

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$1 4 &

¤

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¤ ¥§

¡ ¢

! &

¤

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x

¦ £ ¤

To maximize Choose

, maximize

.

10V + 1V - 0.25V = 10.75V

(g) inﬁnite

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240

CHAPTER 8. THE SMALL SIGNAL MODEL

This is, by deﬁnition, equal to the small-signal gain ANS::

Problem 8.4 The circuit shown in Figure 8.8 delivers a nearly constant current to its load despite the fact that the power supply is noisy. The noise is modeled by the small signal superimposed on the constant supply voltage . Thus, and are the large-signal and small-signal components of the total power supply voltage , respectively. and are the large-signal and small-signal components of the load current , respectively. The noise in the power supply voltage satisﬁes , and is responsible for the presence of in . ¡

vs Current source & load vS VS

+ -

RB

Load D G S iL = IL + il

+ -

Nonlinear resistor

i + Nonlinear resistor v -

i

1 Slope = -----RN

0
Figure 8.8:

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v

1

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241 The current source contains a MOSFET which operates in its saturation region such that . The current source also contains a nonlinear resistor whose terminal characteristics are described graphically below. Assume that . a) Assume , and

. Determine .

, the large-signal component of

, in terms of , ,

b) Following the result of Part (a), determine .

in terms of

,

,

. Draw a small-signal circuit model for the combined c) Now assume that circuit comprising the power supply, current source and load, with which can be found from . Clearly label the value of each component in the circuit model. d) Using the small-signal model from part (c), determine the ratio Solution:
¢

.

b)

c) See Figure 8.9.

vs

+ -

RB vg RN il

Figure 8.9:

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a) We know that equation,

, so . Solving,

. Substituting into the ﬁrst

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and

242 d) Using Thevenin equivalents,

CHAPTER 8. THE SMALL SIGNAL MODEL
. Given that

Problem 8.5 Figure 8.10 depicts a bipolar junction transistor (BJT). Recall that a BJT has three terminals called the base (B), the collector (C) and the emitter (E). Figure 8.10 also shows an alternative small signal model for the BJT operating in its active region. This model is slightly different from the small signal BJT model discussed in this chapter in that it includes a base resistance . In the model shown in the ﬁgure, is a constant.

B B C ib E RB

C βib

E
Figure 8.10: a) Draw the small-signal equivalent circuit for the BJT ampliﬁer shown in Figure 8.11. Use the small-signal equivalent circuit to derive the small-signal gain of the ampliﬁer. b) Draw the small-signal equivalent circuit for the BJT ampliﬁer shown in Figure 8.12. Notice that the resistor divider provides the necessary bias voltage. Use the smallsignal equivalent circuit to derive the small-signal gain of the ampliﬁer. Solution: a) See Figure 8.13.

.

§

By KVL, circuit,

. Substituting in to the KVL equation for the other side of the . Therefore the gain is

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ANS:: (a)

(b)

(d)

¡

A

, we can solve for

and then divide through by

to ﬁnd the ratio

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¢

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1

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243

VS RL vO

vI + -

Figure 8.11:

VS R1 + vI Figure 8.12:

VS

RL vO + -

vi R2

vO

vi

+ -

ib Rb βib RL

Figure 8.13:

244

CHAPTER 8. THE SMALL SIGNAL MODEL
R2 vO ib R1 Rb βib RL

vi + -

Figure 8.14: b) See Figure 8.14.

Problem 8.6 Consider the MOSFET-based ampliﬁer circuit discussed in Problem 7.8 (Figure 7.20) in the previous chapter. Assuming an input bias point voltage , draw the small signal circuit equivalent of the ampliﬁer. Determine the small signal gain of the ampliﬁer. Assume throughout that the MOSFET operates in its saturation region. Solution: The small signal model is shown in Figure 8.15.

vo vi + id = gmvi RL

Figure 8.15: Recall that the large-signal transfer characteristic for saturation derived in Problem 7.8 was: a Taking the derivative of this with respect to

, one gets a ¤

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@ T

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¦ § ¤

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@

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@

@

©

ANS:: (a)

(b)

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D

¤

D D §

©

Using KVL to ﬁnd the voltage across and combining that with that . By the same argument in part a., the gain is s §D ¥ 8@1 D

§A § ©A §

@

, we ﬁnd .

D ¢ D¥ D D §D § §

¤

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¦ £ ¤

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¤ ¥ X

¤

X

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C

§ DA

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D © D § ¥ D ¡ s F¦1
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245 This is, by deﬁnition, equal to the small-signal gain. ANS::

Problem 8.7 Consider again the ampliﬁer circuit discussed in Problem 7.8 (Figure 7.20) in the previous chapter. Suppose that the ampliﬁer is biased such that at the bias point. Draw the small signal circuit equivalent of the ampliﬁer assuming this bias point. Determine the small signal gain of the ampliﬁer at this bias point. Assume that the MOSFET operates in its saturation region. Solution: The small signal circuit is shown in Figure 8.15. Recall the formulae derived in the solutions to Problem 7.8 in the previous chapter and Problem 8.6 in this chapter. The large-signal transfer curve in saturation is equal to: a Setting

, and solving for
@

, we get that a Recalling the small-signal gain from Problem 8.6,

we substitute our freshly derived value of

, and after simplifying, get that a 8@

ANS::

Problem 8.8 Consider the common gate ampliﬁer circuit shown in Figure 7.24, and analyzed earlier in Problem 7.11 of the previous chapter. Assume that the MOSFET operates in its saturation region, and is characterized by the parameters and . a) Draw the SCS equivalent circuit by replacing the MOSFET by its SCS model.

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246

CHAPTER 8. THE SMALL SIGNAL MODEL and operating point current

b) Determine the output operating point voltage in terms of an input operating point voltage . c) Assuming an input bias point voltage pliﬁer.
¡ £

, draw the small signal model of the amof the ampliﬁer.

d) Determine the small signal gain

e) Determine the small-signal output resistance of the ampliﬁer. That is, determine the equivalent resistance of the ampliﬁer at the output port of its small-signal model with . Is the small signal output resistance greater than, less than, or equal to that of the “common source” ampliﬁer shown in Figure 8.3. f) Determine the small-signal input resistance of the ampliﬁer. That is, determine the equivalent resistance of the ampliﬁer at the input port of its small-signal model. Is the small signal input resistance greater than, less than, or equal to that of the “common source” ampliﬁer shown in Figure 8.3. Solution: a) See Figure 7.25 in the previous chapter. b) As previously determined,

c) See Figure 8.16.

id vo vi + RD

Figure 8.16: d) Taking the derivative and simplifying, we get that a ¢

a

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247 e) There is no current ﬂowing through the MOSFET since there is no signal coming into the gate and the source is grounded. Therefore, the output resistance must simply be . This is larger than the output resistance of the common-source ampliﬁer. f) Place a test voltage across the resistor, and measure the corresponding test current. a This is shown in Figure 8.17.

itest + vtest iR R

iFET

Figure 8.17: Plugging in

and simplifying, we get that a This is smaller than the input resistance of the common-source ampliﬁer.

Problem 8.9 Consider the circuit illustrated in Figure 7.30 and analyzed in Problem 7.15 in the previous chapter. Assume that the MOSFET operates in its saturation region, and is characterized by the parameters and .

¢

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s

(f)

7

D

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@

ANS:: (b) (e)

,

(d)

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248

CHAPTER 8. THE SMALL SIGNAL MODEL

a) Draw the SCS equivalent circuit by replacing the MOSFET by its SCS model. b) Determine the output operating point voltage terms of an input operating point voltage . c) Assuming an input bias point voltage d) Determine the small signal gain ¡`

and operating point current

, draw the small signal model.

.

e) Determine the small-signal output resistance. f) Determine the small-signal input resistance. Solution: a) See Figure 7.31 in the previous chapter. b) We refer to Problem 7.15 for the corresponding large-signal model, as well as several key derivations, including this one for the current through the MOSFET: a From this, we can calculate the bias voltage to be

The full calculation is done in Problem 7.15. c) See Figure 8.18.

gmvin vin RS vout RD

Figure 8.18:

a

¤

¢ C 7¤

@ ¥ ¡

The transconductance bias point.

is equal to the derivative of the -

transfer curve at the

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a

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249 d) The small-signal gain is equal to the derivative of the the operating point.
U@

e) As shown in Figure 8.19, we place a test voltage across the output, and measure the corresponding current.

iFET

itest + iRS vtest RS -

RD

Figure 8.19:

Substituting in known values, we get that a ¡ £¡ ¡

Simplifying this, one gets that a F

f) Inﬁnite. The MOSFET gate has inﬁnite input impedance, so the input resistance is therefore inﬁnite.
¢ £

(e)

(f) inﬁnite

Problem 8.10 Consider the circuit illustrated in Figure 7.32 and analyzed in Problem 7.16 in the previous chapter. Assume that the MOSFET operates in its saturation region, and is characterized by the parameters and .

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ANS:: (b)

(d)

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C D C s

a

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¤

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transfer curve at

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a I

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250

CHAPTER 8. THE SMALL SIGNAL MODEL

a) Draw the SCS equivalent circuit by replacing the MOSFET by its SCS model. b) Determine the output operating point voltage terms of an input operating point voltage . c) Assuming an input bias point voltage d) Determine the small signal gain ¡`

and operating point current

, draw the small signal model.

.

e) Determine the small-signal output resistance. f) Determine the small-signal input resistance. Solution: a) See Figure 7.33 in the previous chapter. b) From Problem 7.16, we get that the current is a From this, we can determine the voltage to be ¡ ¡

This was calculated in problem Problem 7.16. c) See Figure 8.20.

gmvin vin RS

vout

RD

Figure 8.20: The transconductance is the same as had been derived in Problem 8.9. a ¤

a

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¢ ¢

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251 d) This is equal to the slope of the
@

e) As shown in Figure 8.21, we place a test voltage across the output, and measure the corresponding current.

iFET

itest + iRD vtest RD -

RS

Figure 8.21: a Substituting in known values, we get that a ¡ £¡ ¡

Simplifying this, one gets that a f) Inﬁnite. The MOSFET gate has inﬁnite input impedance, so the input resistance is therefore inﬁnite.

ANS:: (b)

(e)

(f) inﬁnite

Problem 8.11 This problem studies the small signal analysis of the ampliﬁer analyzed in Problem 7.14 of the previous chapter (see Figure 7.28). Assume that the MOSFET operates in its saturation region, and is characterized by the parameters and .

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transfer curve at the operating point.

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252

CHAPTER 8. THE SMALL SIGNAL MODEL

a) Draw the small signal equivalent circuit of the ampliﬁer driving the load resistor , assuming an input bias voltage . b) Determine the small signal gain of the ampliﬁer when it is driving the load Solution: a) See Figure 8.22.
¢

vout
RL || RE

vin + -

id = gmvin

Figure 8.22: From Problem 7.14, we get that the current through the MOSFET is as follows: a Taking the derivative of this, we get the transconductance, a b) We note that the current has nowhere to go but through the two resistors in parallel, so we use a simple relationship to determine the output voltage. a The gain is equal to the small-signal output voltage divided by the small-signal input voltage. a This may be checked by the more traditional method of ﬁnding the output voltage as a function of the input voltage, and taking its derivative.

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253 ANS:: (b)

Problem 8.12 This problem studies the small signal analysis of the circuit analyzed in Problem 7.17 of the previous chapter (see Figure 7.34). Assume that the MOSFET operates in its saturation region, and is characterized by the parameters and . a) Draw the small signal equivalent circuit assuming an input bias voltage the value of for the MOSFET under the given biasing conditions?

b) Determine the small signal voltage gain simplify to when each of , , and Solution:

. What does the expression is much greater than 1.

a) See Problem 7.17 for key large-signal derivations. See Figure 8.23 for the smallsignal model.

vout
R2 vin + R1 id = gmvin RL

Figure 8.23:

was derived as a function of and in Problem 7.17. in terms of , but the derivation is quite messy.

can be found

b) We must use implicit differentiation to ﬁnd the small-signal gain, since we do not have in terms of , but we do have an expression that relates the two: a Differentiating this, we get a 7

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. What is

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254

CHAPTER 8. THE SMALL SIGNAL MODEL

We can substitute in

, and solve for the ratio of the differentials: a From this, when becomes very large, then the gain goes to zero. This is because resistor is the only connection from to the gate, so if it is opened up, any change in is made irrelevant. When becomes very large, the gain approaches . This makes sense because the input impedance is dependent on , and if it becomes inﬁnitely large, we are dealing with a standard MOSFET ampliﬁer. When becomes very large, the gain theoretically approaches , but this is not actually realistic since that implies cutting off the supply voltage, and thereby taking the MOSFET out of saturation. ANS:: (a) s Problem 8.13 This problem studies the small signal analysis of the source follower (or common collector) BJT circuit analyzed in Problem 7.18 of the previous chapter (see Figure 7.36). Assume that the BJT operates in its active region throughout this problem.
§

a) Determine the output operating point voltage terms of an input operating point voltage . b) Assuming an input bias point voltage follower ampliﬁer.

and operating point current

, draw the small signal model of the source

c) Determine the small signal gain

of the ampliﬁer.

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a

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255 d) Determine the small-signal output resistance of the source follower ampliﬁer. Is this resistance greater than, less than, or equal to that of the “common emitter” ampliﬁer analyzed in Exercise 8.7 and shown in Figure 8.6. e) Determine the small-signal input resistance of the ampliﬁer. Is the input resistance greater than, less than, or equal to that of the “common emitter” ampliﬁer shown in Figure 8.6. f) Determine the small signal current and power gain of the source follower ampliﬁer. Assume for this part that the ampliﬁer is driving an output load of connected between the output node and ground. Solution: a)

b) c)

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Further, when

,

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256

CHAPTER 8. THE SMALL SIGNAL MODEL

d) The small-signal output resistance is determined by applying a test voltage at the output and measuring the resulting current into the output node from the test voltage. We also set the input voltage to zero.

The factor in the denominator makes the output resistance of the BJT sourcefollower signiﬁcantly lower than that of the BJT common-emitter ampliﬁer (for comparable values of and ). at e) The small-signal input resistance is determined by applying a test voltage the input and measuring the resulting current into the input node from the test voltage.

The factor in the numerator makes the input resistance of the BJT sourcefollower signiﬁcantly higher than that of the BJT common-emitter ampliﬁer (assuming , and the same value of for both ampliﬁers).

§

@

@

¢

¥

@

§

§

When

,

§

@

¢

¥

@ 2§

1

Multiplying throughout by get

and dividing throughout by , and simplifying, we

1

§

@ 1

¢

Or, substituting for

@

1

¢`

@

@

@

@ S

§ 1

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¡@

§

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When

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@ ¤¢ ¢

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In other words

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1

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@

1

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@ ¤¢ ¢

§

@

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1 §

¥

@ 0` ¥

@ ¤¢ ¢

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@ #¡ @

¢

¢ ¢

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¢

257 f) To compute the current gain and power gain, we are given that there is a resistance connected between the output node and ground. The small-signal current gain is the ratio load resistor . , where 1 %` 1 ¡

Applying the current divider relation,

Dividing by , we get the current gain as

We know that the power gain is given by 1

Substituting for the voltage gain and the current gain

Notice that we have substituted ing the voltage gain. Simplifying, Power Gain
¢

as the effective load resistance in comput-

Problem 8.14 Consider again the compound three terminal device formed by connecting two BJTs in the conﬁguration shown in Figure 7.37 (Problem 7.19) in the previous chapter. This problem relates to the small signal analysis of this device. Assume that the two BJTs are identical, each with , and that each of the BJTs operates in the active region.

§

and ¡

(f)

and Power Gain

§

¢

¤

¡

s

¥ £

¤

¢

¢

§

()

§

¥

¢

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s

ANS:: (a)
`

and

(c)

(d)

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¨ @ ¥

§ § §D ¢ ¨D ¥ ¥ ¢ ¡ § § § ¥ § ¥ ¦ ¢ ¢ ¨§D AA § ¦¤ ¥ ¢ ¢ ¨D

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@ 7 ¥'¨ @ ¥ § 7 @

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d u

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¥ ¨

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1

¢ § ¡

Power Gain

§

@

¥ 6¥

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b

Power Gain

¨ @ ¥

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@

1

§

1

Current Gain

§

@

§

The total current into the resistance pair formed by

and

¨ @

¨ @ ¥

@

¥ ¥

1 ¥ ¥

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@

¢¡

1¥ P) ¥

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1

§ ' ¥ 1 1

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d u

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s

s

¢

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¢

¨ @
¢

1

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is the current into the output is

§

258

CHAPTER 8. THE SMALL SIGNAL MODEL

a) Draw the active-region equivalent circuit of the compound BJT by replacing each of the BJTs by the piecewise linear (large signal) model shown in Exercise 7.8. Clearly label the , and terminals. b) Develop a small signal model containing a single dependent current source for the compound device by linearizing the circuit model in (a) and simplifying suitably.

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Chapter 9 Capacitors and Inductors
Exercises
Exercise 9.1 Find the equivalent capacitance between the two terminals in each of the networks in Figure 9.1. Solution: (b) (c)

(a)

Exercise 9.2 Find the equivalent capacitance or inductance for each case in Figure 9.2. Solution: (a)

“p” = “pico” =

259

7 2a

V B§

£¤6¥ ¤£ 3

(c)

7s

g

7 a

7

7

§

(

7

7

) 3 ) 3

£¤ ¤£

(b)

£

V

§

£ ¥ ¤£ £ %3 ¤£

ANS:: (a)

(b)

(c)

£

V ` 96

£

£

` IHV

£ £ £

V ` 96

` IHV

260

CHAPTER 9. CAPACITORS AND INDUCTORS

(a) 1 µf 3 µf

(b)

1 µf

3 µf (c) 3 µf

2 µf 1 µf
Figure 9.1:

261

1 µF 2 µF (a) 1 µF 30 pF

1 µF

10 pF (b)

1 mH 10 pF (c) 2 mH (d) 1 µH 2 mH (e)
Figure 9.2:

1 µH

2 mH (f)

1 mH

262

CHAPTER 9. CAPACITORS AND INDUCTORS

ANS:: (a) 2/3

F (b) 9.9pF (c) 38.5pF (d) 3mH (e) 2mH (f) 2/3mH

Exercise 9.3 Consider a power line on a computer backplane that is 2.5 mm wide, and separated from its underlying ground plane by 25 m. Let the permittivity and permeability of the separating insulator be and , respectively. What is the capacitance and inductance of the line per 10 cm of length? If the voltage on the line is 5 V how much energy is stored in its capacitance per 10 cm of length? If the current through the line is 1 A how much energy is stored in its inductance per 10 cm of length? Solution: Exercise 9.4 A current source drives a capacitor as shown in Figure 9.3. The source current is as shown in Figure 9.4 for . If the capacitor voltage is at , what was it at ?

I(t)

C

+ v(t ) -

Figure 9.3: A current source driving a capacitor Solution: Exercise 9.5 A voltage source drives an inductor as shown in Figure 9.5. The source voltage is as shown in Figure 9.6 for . If the inductor current is at , ? what was it at Solution:

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§ £

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¥

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¥ £ §£ ¦¥¤

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(f)

) a I( eS§

§ ¡¢ ¤£ ¥ 63 ¥ ¤£6¥
) F

(e)

) 9V

§

) I

¥

(d)
) ¦

¨£ §

¨£ §

£

263

I (t ) Qo Io

0

T --2

T

t

Figure 9.4: Source current

i(t ) V(t) + L

Figure 9.5: A current source driving an inductor

V (t ) Vo

Λo

0

T --2

T

t

Figure 9.6: Source current

264

CHAPTER 9. CAPACITORS AND INDUCTORS

Exercise 9.6 Figure 9.7 shows four circuits, labeled “1” through “4”, together with the waveform for the source in each circuit. The ﬁgure also shows four branch-variable waveforms, labeled “a” through “d”, that could correspond to the branch currents or branch voltages labeled in the circuits. Match the branch variable waveforms to the appropriate circuit and source waveform.

i

i + v –

+ V

I

+ v –

V +

I

(1)
V

(2)
I V

(3)
I

(4)

t

t

t

t

t

t

(a)

(b)

(c)

Figure 9.7: Source current Solution:

1

t

t

(d)

265 Problem 9.1 A voltage source is connected in series with two capacitors as shown in Figure 9.8. The source voltage is , as shown. If the current and voltage are given by and , again as shown, what are and ?

V (t) 5V

i V (t ) + C1 + C2 t v –

i(t) 4 µC 1V

v(t)

t

t

Figure 9.8: Solution: Problem 9.2 A current source is connected in parallel with two inductors as shown in Figure 9.9. The source current is , as shown. If the current and voltage are given by and , again as shown, what are and ?

I (t) I (t) L1 A 400 --S t L2

i

+ v –

i(t) A 100 --S

v(t) 1V

t
Figure 9.9:

t

Solution: Problem 9.3 A current source drives a series-connected capacitor and inductor as shown in Figure 9.10. Let , and assume that the inductor and capacitor both . stored no energy prior to

Solution:

¡

Is there any relation between , , state the relation and determine .

and

for which

is constant for

£

¢

¥

Determine the voltage

for

. ? If so,

s

1

¡

1

¥ ¦£ ¡

C B V a

E§ ¦¤¢ ¥£¡ ¥£ ¦¤¡ C ` 0) § ¦¤¡ 1 ¥£ ¥£ C ¦¤¡ R ` ( § ¦¤¡ 1 ¥£

¥ ¦£ ¡

¨

C

¥ ¦£ ¡

C

2

§ ¥¦£¤¢ ¡ § ¦¤¡ ¥£

¥ C¥ ¡ ¢ ¦£ ¡ ¦£ ¢ Q£

¨

£ § £

¥£ ¦¤¡

¨¥

¡£

§ ¦¤¡ ¥£

§ ¥£ F¦¤¡ 1

7

s

7

¡

266

CHAPTER 9. CAPACITORS AND INDUCTORS
+ C I (t) v( t ) L –
Figure 9.10:

Problem 9.4 A voltage source drives a parallel-connected capacitor and inductor as , and assume that the inductor and shown in Figure 9.11. Let capacitor both stored no energy prior to .

i(t)

V (t) +

Figure 9.11: Solution: Problem 9.5 A constant voltage source having value drives a time-varying capacitor as shown in Figure 9.12. The time-varying capacitance is given by . Determine the capacitor current . Solution: Problem 9.6 A constant current source having value drives a time-varying inductor as shown in Figure 9.13. The time-varying inductance is given by . . Determine the inductor voltage Solution:

¥ ¡ ¢ ¦£ ¢ '£¡

¥ ¡ ¢ ¦£ ¢ '£¡

¨s

¨s

¡

¥ u

¥ u

¡

§ ¥ 9¦£ ¡

§ ¦£ ¡ ¥

¡

¡

Is there any relation between , , state the relation and determine .

and

for which is constant for

£

1

¢

¥ ¦£ ¡ 1

¥£¡ ¦¤¢

¥

Determine the current for

. ? If so,

¨£ § ¥ C¥ ¡ ¢ ¦£ ¡ ¦£ ¢ Q£¡

¨¥

§ ¦£ ¡ ¥ 1 £

1

267

i(t)

V +

C (t )

Figure 9.12:

+ I –
Figure 9.13: Problem 9.7 Consider the parallel plate capacitor shown in Figure 9.14. Assume that the dielectric is free space so that . Suppose the capacitor is charged to the voltage electric energy stored in the capacitor in this case.

vt

L (t )

The capacitor is disconnected from the charging source so that its stored charge remains constant. Following that, its plates are pulled apart so as to double the distance between them; that is, the gap separation is now . For this new conﬁguration, determine the voltage across the terminals of the capacitor and the energy stored in the capacitor. Explain how the stored energy changes. Solution: Problem 9.8 Figure 9.15 shows two capacitive two-port networks. One is a “ ” network, and one is a “T” network. For the network, ﬁnd and as functions of and . For the T network, ﬁnd and as functions of and .
¡ ¡ ¡

How must , and be related to have the same terminal relations? Solution:
¡ £
¡

,

and

for both networks to

Problem 9.9 Figure 9.16 shows two inductive two-port networks. One is a “ ” network,

¡ 7

¡ ¢s

¤¥

¤7

¡

71

¤7

¤s

¡ ¢s

¤s

1

E 9

¦¥£ § £

. Determine the charge and the

¤71

¥

¤s1

¡

7

¡

¡ ¢s

¡

268

CHAPTER 9. CAPACITORS AND INDUCTORS

Area A i
+
+ + + + E q E + + q l

v ε E E

-

Figure 9.14:

i1 p + C3 p v1 p – C1 p C2 p

i2 p + v2 p – + v 1T –

i 1T C 1T C 2T C 3T

i 2T + v 2T –

(a)

(b) two-port network

Figure 9.15: (a) a capacitive T two-port network, and (b) a capacitive

269
¡ ¡ ¢s

i1 p + L3 p v1 p – L1 p L2 p

i2 p + v2 p – +

i 1T

v 1T –

(a)

Figure 9.16: (a) an inductive T two-port network, and (b) an inductive Solution:

Problem 9.10 This problem examines in more detail why energy is lost when the switch in Figure 9.17 closes. To do so, we examine the transient that occurs during the closure be the time at which the switch ﬁrst begins of the switch. In preparation for this, let to close, and let be the time at which the circuit reaches steady state. The charges on the two capacitors prior to switch closure are given to be and .

In this way, the function is an arbitrary transient connecting the initial and ﬁnal charge during the switch closure. (a) Use the charge conservation relation s ¡

¥£ ¦¤¡ 1 §

£ ¥ ¦£ ¡

X

¡

X

s

¡

7

¡

to ﬁnd

in terms of

for

. Then, use the equation

¥7

7

¥ s ¡

¥ s

7

§ ¦¤¡ 7 ¥£

¡

s

¥ s

¡

¡

¡

¥ ¦£ ¡ s ¥

§ ¨¥ ¡

¤

£

¡

s

¡

¤ ¡

s

¡

and

is the steady state charge on the capacitor given by

s

§ ¨¥ #¡

s

¡

s

¡

Further, let

be any function deﬁned over the interval

7

¤

£

¤ ¡

s

¨£ §

¡ £

How must , and the same terminal relations?
¡

be related to

,

and

¤¥

¤ 7¡ 1 7

¤7 ¤s ¤ s ¢1¡ s

¤7

and one is a “T” network. For the For the T network, ﬁnd and

network, ﬁnd as functions of

and and

as functions of .

and

for both networks to have

L 1T

L 2T L 3T v 2T –

(b) two-port network

such that

71

1

.

¥

¤s

7

§ £

¥ ¦£ ¡

¡ ¢s

i 2T +

¥ ¡

270

CHAPTER 9. CAPACITORS AND INDUCTORS

q1

q2 C1 C2

+ v1 -

+ v2 -

Figure 9.17:

(b) During the transient, the difference between and must appear across some element or elements within the circuit. KVL requires this. For example, it could appear across the wiring resistance or the switch, or a combination of both. In any case, energy is lost as a current passes through this voltage difference. If we consider the voltage difference to be , as opposed to its opposite, then it is that passes into the positive terminal of this difference. Why? s for

(d) Integrate the power found in the previous part over the interval to ﬁnd the energy lost during the transient. Also, show that the energy lost is equal to the energy difference in

Remarkably, the energy lost is independent of the interior details of the function chosen for . Since these details are equivalent to the details of the loss mechanism, it is apparent that the amount of energy lost is independent of how it is lost. Solution: s ¡

¤

£

¤ ¥

7 7

¢

7

¡

@ s

s

¡

7

7

¡

¡

s

¥ s

¡

¡

§ ¥ ¨(

£ 4¢ ¡

¤

¡

@

£

¥ (

¤

£ 4¢ ¡

s

¡

¡

(c) The product power in terms of

is the power dissipated during the transient. Determine this .

71

7

s

to ﬁnd and , also in terms of for in terms of the arbitrary function . s s
¡ ¡

. The entire transient is now described

¥£¡ ¦¤¢

¤
£

¡

§ ¥£ ¨¦¤¡

¤ ¡

s
¡

¡

¥7

@

¥7

¡ 71

@

s

7

¤¡

s

to determine

and , again in terms of

for

¤
£

¤ ¡

71

1

. Finally, use the equation

s

Chapter 10 First-order Transients
Exercises
Exercise 10.1 Using superposition, determine the current Figure 10.1. The network is at rest for .

i1(t) 1 H vS (t)
+ -

vS(t) 1V iS(t) t
Figure 10.1:

3 kΩ

Solution: The inductor ﬁrst acts as an open circuit and eventually becomes a wire:

Assume

source points down.

271

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£

¥£ E hC 64

E Ye4 $

¥

§ ¦¤¡ 1 ¥ ¥£

1

¡ ¤ )

@ QC 6P 61 £ E 4 E 4

!

¢

¢ £¢

) V ` 99¢§

§

¥

¥

initially: ﬁnally:

(open circuit) mA

¥£ ¦¤¡ s 1

for the network shown in

§ ¦£ ¡ s 1 ¥ £ ¥ 2§ ¦£ ¡ s 1

£

@ V ` TH 96

£ 1 $ 2¥ hC 6P64 $ 1 ¡ § ¦£ ¡ s 1 ¡ ¥£ E 4 E ¥

@ 0`

£

iS(t) 1 mA t

§

§ ¥ 9¦£ ¡ s 1

¤

¡

£ ¥£ ¦¤¡ 1

272

CHAPTER 10. FIRST-ORDER TRANSIENTS

iS

vR(t) 100 Ω
-

+

Figure 10.2: Solution:

iL ( t )

0.5ms

Figure 10.3:

initially

ﬁnally
¡ ¤ )

ANS::

;

ms

@ § £

Exercise 10.3 In the circuit in Figure 10.4, A, otherwise. At time , the voltage volts. What is at time
9 2

£

Exercise 10.2 Find and sketch the zero state response for mA step at .

in Figure 10.2.

iL(t) 10 mH

t

second, zero second?

1

£

£

(

!

¥

¢

) q a

¢ £¢

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£

@ TH

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a §

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S

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2§ £

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ANS::

for

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! is a 10

) § s

¤

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@ TP¡

§ ¥£ ¨¦¤¡ s 1 § £ ¥£ ¦¤¡ 1

¥£¡ 2§ ¦¤Q 1

273
+

i(t)

10 µf
-

vC

Figure 10.4:

v C ( t ) [ volts ]
5V

slope = 10
-1s -5V 1s

t [ sec onds ]
2s

Figure 10.5: Solution:

for

a constant, otherwise, when

Therefore, second
2 S@

ANS:: -5 volts Exercise 10.4 In the circuit in Figure 10.6, the switch is closed at time second. Sketch for all times. at Solution:

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§ 1

X Y$

£ H)W!

£
§ ¥

£ and opened

X

X

3
¡

§ 1 @ § £ ¡ £ §

1
¡

§

¤ §
¥£¡ ¦¤¨9

1
¡

¤ §
§ £

274

CHAPTER 10. FIRST-ORDER TRANSIENTS

+ -

11 V

1 kΩ 10 kΩ

+

100 µf v (t) C
-

Figure 10.6:

vC ( t )
10V

10e
0

–t ---τ2

1s

time

--- τ1  10  1 – e   

–t

Figure 10.7:

275 Assume for . When the switch is closed at s ,

rises from to
¡

Volts with

second.

1kΩ
+

1 kΩ i 1µF 1kΩ 1 mH i(0) = 6 mA (b) 1 kΩ 1 kΩ

v
-

v(0) = 6 V (a)

+ 6V -

1 µF

+

v
-

1 kΩ

+ 6V -

Switch opens at t = 0 (c)
Figure 10.8: Solution: (a)

Switch opens at t = 0 (d)

(b)

Exercise 10.5 Find and sketch the zero-input response for Figure 10.8 for the given initial conditions.

i 1 mH

£

S

! ' (02 §

£

!

) 9 a

¡

3 ¡ ¢I¤¢ ¢

s

¤

E§ 7 § s

Assuming 10V with zero with

for

, when the switch is closed at , rises from 0 to ; When the switch is opened, falls exponentially back to

in each network in

1 kΩ

¡

When the switch is opened,
X Y$

falls exponentially back to zero with

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3 RH) § 7

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3 ¡ S)I§¢ ¢ § £

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9

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¢ £¢

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£9&25 § § ¤

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276

CHAPTER 10. FIRST-ORDER TRANSIENTS

v
6

2.5ms = 5 τ

t

Figure 10.9:

i
6mA

10µ s = 5 τ

t

Figure 10.10:

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,

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b &¡ £ & S§

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£

¥

ANS:: (a) (e)

(d)

(c)

,

6mA

6V

v

i

Figure 10.12:

Figure 10.11:

(b)

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5ms

t

t

(c)

277

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CHAPTER 10. FIRST-ORDER TRANSIENTS

Exercise 10.6 Find and sketch the response for in each network in Figure 10.13. Assume that the input is as shown for , and assume an initial zero state (in other words, show the zero state response).

100 Ω vA + vA = 1 V, constant (a) 1kΩ vC + vC = 10e-10 t (c)
Figure 10.13: Solution: (a)
3

i 10 mH

iB

i 1 mH

iD

i
10mA

0.5ms

Figure 10.14: i: initial value: u u ws

ﬁnal value:

£

£

v

+ -

1 µF

iB = 1 µA, constant (b)

v

+ -

.1 µF
3

10 kΩ

iD = (10-6)e-10 t (d)

t

) ¤ 9

§

¢
£

££H)§ `

uuu wws

£

¢ ¢ ¥ ¡ ¥ 1 0()@ §
¥

uuu wws
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§

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©

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u v s

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uuu ¥ d ¡1 9) § wws £ © )§ 9(()

§

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@ 19

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(1)

©

Assume

§
1

(c)

(b)

9.93mA

in the form

Now plug
© ¦ ¥ £ ¦ ¦£ ¦ ¢

into (1):

¦

©

1

i

1V

V

Figure 10.16: Figure 10.15:
1s 6.9 µ s

1V slope = -----1s

t

t

§ 1

¤

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u £ £ £ s )§ u @ s £ TH ¥ 7

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Figure 10.17:

CHAPTER 10. FIRST-ORDER TRANSIENTS

to ﬁnd :

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Figure 10.18: Exercise 10.7 For the current source shown in Figure 10.18, assume consists of a single rectangular current pulse of amplitude amps and duration seconds. a) Find the zero-state response to . u b) Sketch the zero-state response for the cases:
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initial value

(assumed zero state) ;

: Here the pulse is not long enough for to exponentially rise all the way to . only reaches 63% of its maximum before decaying.

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CHAPTER 10. FIRST-ORDER TRANSIENTS

V Io ⋅ R

to

t

Figure 10.19:

V Io ⋅ R I o ⋅ R ( 0.63 ) t t o = RC

Figure 10.20:

V

Io ⋅ R -----------10 t to Figure 10.21:

283
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Here the exponential rise is very short, since the pulse is short c) In case (iii), we see the output for a constant pulse input is triangular, or ramped; nearly the integral of the input, i.e. proportional to the area under the input curve.
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Exercise 10.8 Identify the state variable in each network in Figure 10.22. Write the corresponding state equation and ﬁnd the time constants.

R i0 R (a) 1 kΩ vC + 1 µF 1 kΩ v0 + 1 kΩ 1 mH 1 kΩ C v0 + (b) L

(c)
Figure 10.22: Solution:

(d)

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284 (a)

CHAPTER 10. FIRST-ORDER TRANSIENTS

State variable: Time constant: (b)

State variable: Time constant: (c)

State variable: Time constant: (d)

State variable: Time constant:

(d)

Solution:

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Exercise 10.9 In the circuit in Figure 10.23, mV for zero otherwise. At time seconds, A. What is at time

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, time constant 500 s

seconds, and second?

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+ v(t) Figure 10.23:

i(t) L = 1 mH

i(t ) [ A]
7

slope = 5
2 -1

1

2

3

4s

t[s]

Figure 10.24:

ANS:: 2A Exercise 10.10 Identify appropriate state variables for the network in Figure 10.25 and write the state equations.

R1 vs + -

R2 C L

Figure 10.25: Solution: State variables:

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CHAPTER 10. FIRST-ORDER TRANSIENTS

Exercise 10.11 In Figure 10.26, , , . The driving voltage for . Assume is a 3-volt step at . Make a sketch of for . Be sure to label the dimensions of the voltage and time axes and identify characteristic waveform shapes with suitable expressions.

R1  0, (t < 0) vS =  3 V, (t ≥ 0) vS + + vC -

R2 C

Figure 10.26: Solution:

vC ( t )
2V

t
5 ⋅ τ ≈ 33ms

Figure 10.27:

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Exercise 10.12 Identify state variables and write appropriate state equations for the circuit in Figure 10.28.

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ANS:: State variables:

(3)

(2)

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, for

. State equations: (1) , (3) ¢

R1

Figure 10.28:

ms

L1-M L2-M

M

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, (2)

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288

CHAPTER 10. FIRST-ORDER TRANSIENTS

Exercise 10.13 Referring to Figure 10.29, before the switch is closed, the capacitor is charged to a voltage volts. The switch is closed at . Find an expression for for . Sketch .

R + V=1V C + vC (t)

Figure 10.29: Solution:

vC
2

1

5RC

Figure 10.30:

ANS::

Exercise 10.14 Find the time constant of the circuit shown in Figure 10.31. Solution:

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1 kΩ iS(t) 1 µF

1 kΩ 1 kΩ + v (t) - S

Figure 10.31: Use the Th´ venin Equivalent taken about the capacitor terminals to ﬁnd e
¡

Time constant

ANS::

Exercise 10.15 A two-input RC circuit is shown in Figure 10.32. (Parts a, b, and c are independent questions).

1 kΩ iI(t) 0.5 µF 1 kΩ 0.5 µF 1.5 µF 1.5 µF

2 kΩ + v - O + v (t) - I

Figure 10.32: a) You should realize that the “bridge” of capacitors can be replaced by a single capacitor in this problem. What is the value of the single equivalent capacitor?

c) A different constraint is that sources and are zero for and that . Sources and undergo step transitions of +1 mA and +1 volt respectively at time . Determine for all time. Solution:

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b) Consider operation with known to be 1 volt at a time

and . Determine

for . The voltage for all .

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290

CHAPTER 10. FIRST-ORDER TRANSIENTS

b)

c)

for
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R1 v1 + -

C + R2 v2 -

Figure 10.33: Solution:

v2 ( t )
4V

t
0.045 seconds

Figure 10.34:

C

DC

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: initially

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Exercise 10.16 In the circuit in Figure 10.33, , Assume initial rest conditions (zero initial state), and assume that . Find for . Sketch and label. s , and . has a 6-volt step at

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Exercise 10.17 Consider the circuit shown in Figure 10.35. Sketch and label a step as shown in Figure 10.36. Assume for .

ib i1(t) R1 4ib C

+ vO -

Figure 10.35:

i1 I t

Figure 10.36: Solution:
I 1 ⋅ R1 -------------5

vo ( t )

R1 ⋅ C

t

Figure 10.37:

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292

CHAPTER 10. FIRST-ORDER TRANSIENTS i test Ri ib t

4i b

v test

Figure 10.38:

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Exercise 10.18 For the circuit shown in Figure 10.39, ﬁnd the characteristic equation and the zero-input response assuming that the capacitor was initially charged to 1 volt. Label your graph.

4R vI(t) + R C + vO(t) -

Figure 10.39: Solution: *Characteristic equation:

*zero input : initially ﬁnally

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vo ( t )
1V

25 ⋅ R ⋅ C

t

Figure 10.40:

Exercise 10.19 The excitation function for all four of the circuits shown in Figure 10.41 is:

For each of the circuits, select the time function on the right that corresponds in magnitude and shape to the output, . Assume that all capacitors and inductors have zero initial states, (the appropriate state variable is zero for less than zero). In no matching response exists, say so and explain brieﬂy. All responses are made up of “straight lines” and “exponentials”. You may choose a time function more than once. (Note that part (d) shows an op-amp circuit. Op-amps will be covered in later chapters). Solution: (A) (B) (C) ;
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; initially

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294

CHAPTER 10. FIRST-ORDER TRANSIENTS
(a) R vS(t) + C + vO(t) (1)
10 V t vO(t) vO(t)

Response number ______ (2) (b) R vS(t) + R 2C + vO(t) (3)

10 V t vO(t) 10 V t vO(t)

Response number ______ (4)

t -10 V

(c) vS(t) + -

L R + vO(t) (5)

vO(t) 10 V t vO(t)

Response number ______ (6) (d) R vS(t) + C - +10 V + -10 V vO(t)

5V t vO(t)

(7)

5V t vO(t)

Op-amp saturation at +10 V

Response number ______

(8) 10 V
5V t

Figure 10.41:

295 (B) 7 (C) 3 (D) 4 ; ANS:: (A) , (C)
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Exercise 10.20 An RC network is shown in Figure 10.42. The voltage and the current are constant for all time. Prior to , the circuit is in equilibrium with the switch closed. At time , the switch is opened, and it is then closed some time later. The waveform in Figure 10.43 is observed for .

2 kΩ 2 kΩ 1 kΩ 1 kΩ vC(t) + 1 µF switch i

v

+ -

Figure 10.42:

vC(t) 2V Time constant τ1 V1 (Final value) Time constant τ 2 t Switch open Switch closed
Figure 10.43: s Solution:

s

s

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What are the value of scale.

,

, and the ﬁnal value

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CHAPTER 10. FIRST-ORDER TRANSIENTS

(a)

1 µf + vOUT(t) -

vIN(t) + -

1 MΩ

(b)

500 Ω 1 mH 500 Ω

+ vOUT(t) -

vIN(t) + -

Figure 10.44:

a) The time constant of the circuit. b) an analytic expression for the signal c) A labeled sketch of the output signal the time and voltage scales. Solution: a) (i)
X Y$

as a function of time. as a function of time. Be sure to label

b) (i)

(ii)

;

c) See Figures 10.45 and 10.46.
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Recall that the notation represents an impulse at time . The notation represents the function that results from differentiating the impulse times, and the notation represents the function that results from integrating the impulse times. Thus represents the unit step at time , the the doublet at time . The unit step is also commonly represented as , and the ramp, and unit impulse as .

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Exercise 10.21 In the two following cases in Figure 10.44 the input a 10 volt step starting at time . Give for each case

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10V

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5 seconds

Figure 10.45:

v out ( t )
5V

5 µs

t

Figure 10.46:

298 u CHAPTER 10. FIRST-ORDER TRANSIENTS
(ii) ; (b) (i)

;

Exercise 10.22 In each of the following cases, ﬁnd by inspection and give i) an expression for the time constant , ii) a sketch of the signal versus time, iii) an analytic expression for the signal in terms of ters.

(a) R1 L

i R2

+ v -

Figure 10.47: b) Referring to Figure 10.48, ﬁnd given

.

b) I0 L1 R
Figure 10.48:

i1 L2

i2

c) Referring to Figure 10.49, ﬁnd to 2 at . Solution:

for

given that the switch is moved from 1

¦C D C ¢ ¤¤ D

a)

u

a) Referring to Figure 10.47, ﬁnd

for

given

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Figure 10.49:

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(b)

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CHAPTER 10. FIRST-ORDER TRANSIENTS
R vI + C vC
+

Figure 10.50:

vI

vC

t
Figure 10.51:

τ

t

Find: a) b) c)

at

Solution: a) Homogeneous solution:
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For (a), assume a trial particular solution in the form , since the input is . Note that in the homogeneous solution above is different from in the expression for .

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for

when

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when .

and

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u

when the input is the same as above but

. represents a unit step

Exercise 10.23 For the circuit in Figure 10.50, with no charge on the capacitor at given that if then . Note that represents a unit step at .

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(c)

Exercise 10.24 A digital memory element is implemented as illustrated in Figure 10.52. Sketch the waveform at the output of the memory element for the input signals shown in Figure 10.53. Assume that the switch is ideal and that the memory element has a 0 stored in it initially. Solution: See Figure 10.54

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CHAPTER 10. FIRST-ORDER TRANSIENTS

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Problems
Problem 10.1 Figure 10.55a illustrates an inverter driving another inverter . The corresponding equivalent circuit for the inverter pair is illustrated in Figure 10.55b. , , and represent logical values, and , , and represent voltage levels. The equivalent circuit model for an inverter based on the SRC model of the MOSFET is depicted in Figure 10.56.

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a) Write expressions for the rise and fall times of for the circuit conﬁguration shown in Figure 10.55. Assume that the inverters satisfy the static discipline with voltage thresholds and . Hint: The rise time of is the time requires to transition from the lowest voltage reached by (given by the voltage divider action of and ) to for a to 0V step transition at the input . Similarly, the fall time of is requires to transition from the highest voltage reached by (that is, the time ) to for a 0V to step transition at the input .
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CHAPTER 10. FIRST-ORDER TRANSIENTS

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CHAPTER 10. FIRST-ORDER TRANSIENTS

c) Write an expression for the rise time of the buffer for the circuit conﬁguration shown in Figure 10.57c. (Hint: Refer to the sketch of from part (b). The rise time of the buffer is the time requires to transition from the lowest voltage reached by to from the time the input makes a step transition from 0V to . Note that the rise time of the buffer includes the internal buffer fall delay, which is the time takes to transition from to , and the additional time takes to transition from its lowest voltage to ).

e) Referring to Figure 10.57c, assume that the input to the buffer undergoes a step transition from to 0V at time . Write an expression for for for the step transition in . (Hint: Refer to the sketch of drawn in part (d). The MOSFET in stays off for , and turns on when ). Sketch the form of for . f) Write an expression for the fall time of the buffer for the circuit conﬁguration shown in Figure 10.57c. (Hint: Refer to the sketch of from part (e). The fall time of the buffer is the time requires to transition from to from the time the input makes a step transition from to 0V. Note that the fall time of the buffer is the sum of two components: (1) the internal buffer rise delay, or the time takes to transition from its lowest voltage to and (2) the additional time takes to transition from to ).
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g) Compute the rise time and the fall time for the buffer assuming that , , , , , and

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h) What is the propagation delay of the buffer when the buffer output is connected to a single inverter using an ideal wire as shown in Figure 10.57c? i) Notice that unlike the delay calculation in Problem 10.1, we needed the value of to obtain the buffer delay. Why was it necessary in the case of the buffer?
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308

CHAPTER 10. FIRST-ORDER TRANSIENTS

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CHAPTER 10. FIRST-ORDER TRANSIENTS

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Problem 10.3 The circuit depicted in Figure 10.62 implements the logic function . Suppose the output of this circuit drives an inverter with a gate capacitance of . Assume that the MOSFETs in the circuit have on resistance , and that the high and low voltage thresholds are and respectively.

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Figure 10.62: a) What combination of logical inputs will result in the worst-case fall time for the circuit? b) Derive an expression for the worst case fall time in terms of . Not all variables need appear in your answer. c) Derive an expression for the worst case rise time. Solution: a) To make the rise time longest must be its largest possible value. To achieve this, , , , and must all be high and must be low.
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CHAPTER 10. FIRST-ORDER TRANSIENTS
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Figure 10.65: its input. Recall that by our deﬁnition is the time taken by the input to , namely , to fall from to following the 0 to 1 transition at the input of . Express your answer in terms of , , , , the wire length , and the wire model parameters. By what factor does the delay increase for a 2 increase in the wire length ? Solution:
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Problem 10.5 Figure 10.66 illustrates an inverter driving other inverters through . As in Problem 10.1, each of the inverters is constructed using a MOSFET and a resistor , and the inverters satisfy the static discipline with voltage thresholds and . Model the MOSFETs using the SRC model with MOSFET on resistance and gate capacitance as in Problem 10.1 (see Figure 10.56). a) What are the rise and fall times for ? (Hint: Sum the input capacitances of each of the inverters into a single lumped value, and use your answer from Problem 10.1 to solve this part). How does the rise time increase as the number of driven inverters increases?

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CHAPTER 10. FIRST-ORDER TRANSIENTS

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315 Problem 10.6 As can be seen from the answer to Problem 10.4, long wires have a serious negative impact on the delay. One way to alleviate the wire delay problem is to introduce buffers when driving long wires, as illustrated in Figure 10.70. Assume that the buffer is constructed as depicted in Figure 10.57c using a pair of inverters identical to the inverters in this problem. In other words, the input of a buffer has a capacitance to ground, and the output of a buffer has the same drive characteristics as an inverter output. For this problem, you will ignore the internal delay of the buffer. (See Problem 10.2c and f for a deﬁnition of the internal buffer delay). In other words, assume that a buffer driving zero output capacitance has zero delay. By introducing a buffer, the effective length of wire driven by either the inverter or the buffer is . For large , given the nonlinear relationship between wire length and delay, the sum of the delays in driving the two wire segments is smaller than driving a single wire segment of length .

INVA A B l -2 l -2

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Figure 10.70: and the input of a) Compute the propagation delay between the input of for the circuit in Figure 10.70. Assume that rising transitions are longer than falling transitions at the output of either the inverters or the buffers. to the output of is the sum of Hint: The total delay from the input of the following two quantities: (1) the propagation delay of driving the wire segment of length and a capacitance corresponding to the gate capacitance of the buffer and (2) the propagation delay of the buffer driving the second wire and a capacitance corresponding to the gate capacitance segment of length of . (Remember, the buffer has zero delay when it is driving zero output capacitance). b) Figure 10.71 shows a circuit in which buffers are introduced between and . and each of the buffers drives a segment of wire of length . Compute the propagation delay between the input of and the input of for this case. c) Determine the number of buffers for which the propagation delay for the circuit in Figure 10.71 is minimized. Solution:

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CHAPTER 10. FIRST-ORDER TRANSIENTS
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Figure 10.71: a) The delay is equivalent for each length of wire, so the total delay is twice that of a single wire of length . Using the result from Problem 4 we can easily see the following.

(c)

Problem 10.7 Figure 10.72 shows a buffer driving a large load capacitor . The buffer is built using an inverter pair as in Figure 10.57c. The width to length ratio of each NMOS transistor in the buffer is and the resistors have a value . Accordingly, the gate capacitance seen at the input of the buffer is given by . The buffer satisﬁes a static discipline with voltage thresholds given by and . The supply voltage is . Assume that the internal buffer delay (as deﬁned in Problem 10.2c) is zero. Assume that there is a 0 to 1 transition at the input at time .
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Figure 10.72: in series with driving the load for the rising transition at the input . Assuming that is much larger than the input gate capacitances of the two buffers, and that , is the delay computed in part (b) greater than or less than the delay computed in part (a)?

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Figure 10.73:

c) Consider Figure 10.74. This ﬁgure shows the use of a series of buffers in which has transistors that have a width times that of and resistors that are a factor smaller than that of . is chosen such that is times the gate capacitance of . In other words, satisﬁes the equation:

Compute the propagation delay for the sequence of buffers driving the load for the rising transition at the input . As before, assume that is larger than the input gate capacitances of each of the buffers and that .

BUF1 BUF2 BUF3 ... BUFn A
W ---- , R L L L L L ---- x W-, ---- x 2 W-, ---- x n – 1 W-, -------------- ---L x L 2 L n–1 x x R R R

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CHAPTER 10. FIRST-ORDER TRANSIENTS for which the propagation delay computed in part (b) is

Solution:

c) The result will be a sum of terms similar to those found in part (b).
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d) The limitation on x is the maximum value such that the buffer can still achieve a valid low.

Problem 10.8 In this problem, you will study the affect of parasitic inductances in VLSI packages. VLSI chips are sealed inside plastic or ceramic packages and connections to certain nodes of their internal circuitry (for example, power supply, ground, input and output nodes) need to be extended outside the package. These extensions are commonly accomplished by ﬁrst connecting the internal node to a metallic “pad” on the VLSI chip. In turn, the pad is connected to one end of a package “pin” using a wire that is bonded to the pad at one end and the pin at the other. The package pin, which extends outside the package, is commonly connected to external connections using a PC board.

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319 Together the package pin, the bond wire, and the internal chip wire are associated with a non zero parasitic inductance. In this problem, we will study the effect of the parasitic inductance associated with power supply connections. Figure 10.75 shows a model of our situation. Two inverters with load resistors and and MOSFETs with width to length ratios and respectively are connected to the same power supply node on the chip that is labeled with a voltage . Ideally this chip-level power supply node would be extended with an ideal wire outside the chip to the external power supply shown in the ﬁgure. However, notice the parasitic inductance interposed between the power supply node on the chip (marked with voltage ) and the external power supply node (marked with voltage ).

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Problem 10.10 As illustrated in Figure 10.80, a capacitor and resistor can be used to ﬁlter or smooth the waveforms we derived from a half-wave rectiﬁer, to get something closer to a DC voltage at the output, for use in a power supply for example. For simplicity, assume the voltage from source is a square wave. Assume that at , , i.e., the circuit is at rest. Now assuming that is small enough to make the circuit time constant much smaller than or , calculate the voltage waveforms for each half cycle of the input wave. Find the average value of the output voltage for

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CHAPTER 10. FIRST-ORDER TRANSIENTS
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Problem 10.11 For much larger than the value used in Problem 10.10, so that the circuit time constant is much larger than or , (so that the exponentials can be apfor the ﬁrst half cycle of , and the second proximated by straight lines) calculate half cycle. Sketch the result. Note that the solution does not return to the initial point of after one cycle, so is not in the “steady state” yet. Solution: :

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CHAPTER 10. FIRST-ORDER TRANSIENTS vO Vt 1 ------RC V ------RC Vt 1 – -------------2 ( RC )
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Problem 10.13 This problem (see Figure 10.83) involves a capacitor and two switches. The switches are periodically driven by external clock controls at frequency such that ﬁrst is closed and is open for the , and then is closed and open for time .

a) Find an effective average current by determining the average rate of charge transfer over several clock cycles. Suppose where . Sketch and on the same axes. b) Examine your results for and from part a). They should be in phase, and the amplitude of should be proportional to the amplitude of . This is a funny form
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COMMENT: Circuits of this type are now commonly used in a type of MOS integrated circuit to make elements that simulate resistors with precisely controlled values. The value of such elements is that precise control of capacitor sizes and clock frequencies is easy in MOS integrated circuits, but precise control of resistor values is hard. Solution: is closed and is open an amount of charge is dumped onto the a) When capacitor and when the switches change the charge is removed. For where above is the actual current See Figure 10.84. we can assume that the average current found .

Problem 10.14 State variables can be used to describe the behavior of a wide range of physical systems. For each of the examples below, try to determine:

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CHAPTER 10. FIRST-ORDER TRANSIENTS

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Figure 10.84: i) the number of state variables that are needed to describe the system, i.e., how many state variables. ii) Which physical variables can serve as state variables. iii) The form of the state equations, including the identiﬁcation of inputs. iv) A simple circuit that can represent the system (an electrical analog). Here are the examples: a) A hockey puck leaves a hockey player’s stick with velocity and slides along the ice until it comes to rest (assume a very large hockey rink, or a very weak shot). b) Halfway through your shower each morning, the water temperature suddenly plunges toward freezing, presumably because your roommates were up earlier and showered ﬁrst. u u

c) A simple pendulum starts from rest with an initial angular displacement rocks back and forth until it eventually comes to rest.

(COMMENT: Part (a) is easy if you concentrate only on the velocity, and is more difﬁcult in terms of the circuit analogy if you include the position as well. Parts (b) and (c) lend themselves to excellent descriptions with circuit analogs.) Solution:

, and

327 a) i) 1 ii) velocity of the puck ( )
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(no inputs, only an initial velocity)

iv) See Figure 10.85.

b)

i) 1 ii) volume of hot water left in the tank ( )

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, where Q is a constant input (with units of volume/time) draining the hot water from the tank.

iv) See Figure 10.86.

Figure 10.86: See Figure 10.86. c) i) 2 ii) angular displacement ( ) and its derivative ( )

There are no inputs, only the initial angular displacement of the pendulum. iv) See Figure 10.87.

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CHAPTER 10. FIRST-ORDER TRANSIENTS

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Load

Assume that the waveform for at as shown in Figure 10.89.

for parts a) and b) is a series of square pulses starting

Assume that the waveform for shown in Figure 10.90.

for parts c) and d) is a half-rectiﬁed sine wave as

a) Assume initial rest conditions at , and assume that both and are long compared to the time constant of the network. Determine each of the following: i) Calculate the current waveform for the ﬁrst cycle ( ), the second cycle [ ], and a typical cycle after stead-state periodic conditions have been reached. ii) How many cycles are required to go from initial rest to steady-state conditions? iii) In steady state, determine the average load current, the amplitude of the variations in load current through one cycle, the average energy stored in the inductor, and the ratio of this stored energy to the energy dissipated in the load during one complete cycle.

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330

CHAPTER 10. FIRST-ORDER TRANSIENTS and s

b) Repeat part a) for the case where both constant of the network.

c) Now assume that as a ﬁlter designer, you are faced with the problem of selecting the inductor value to produce relatively smooth, ripple-free current in a load from a voltage source with a strongly pulsating value, such as the half-wave rectiﬁed sine wave shown. What method would you use to specify the inductor value with which to achieve a speciﬁed maximum variation in load current? Why might the speciﬁcations of a huge L value, much larger than might be needed, be a poor design? d) Try your hand at a design: assume that the source waveform is half-wave rectiﬁed 60 hz 115 V AC, the load resistor is 16.2 Ohms, and it is desired to have a load current ripple of 5% of the average load current. Make reasonable approximations. Solution:

For this entire problem,

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a) Since both and are long compared to the time constant, the circuit will reach steady state during every cycle. i) :

: Every other cycle will be identical to the ﬁrst. ii) It will only take one cycle to reach steady state. It will only take one cycle to reach steady state. s The amplitude of the variations is

b) For this section we will approximate each exponential rise and decay as a straight line, with a slope equal to the initial slope of the exponential.

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CHAPTER 10. FIRST-ORDER TRANSIENTS larger than necessary, the current will take longer than necessary to reach steady state. ud d)

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Problem 10.16 Consider the circuit shown in Figure 10.91.

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336 Solution:

CHAPTER 10. FIRST-ORDER TRANSIENTS

Note that a constant of integration was added, whose value was determined using the initial condition of .

See Figure 10.96 and Figure 10.97.

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Figure 10.96:

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Problem 10.18 Referring to Figure 10.98, given an initial inductor current ﬁnd the expression for and . Plot the waveforms. Solution:

We will solve this problem using superposition, treating the initial current through the inductor to be a third independant source. For the entire problem, . Contribution from :

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§ § s is the integral of the inductor voltage in response to a step.

t

,

337

vR

t
Figure 10.97:

2R + VS IS 2R

+ vL L iL R + vR -

VS K 1t t

IS K2t t

Figure 10.98:

338

CHAPTER 10. FIRST-ORDER TRANSIENTS

Contribution from

:
@

Contribution from initial condition (

):

To ﬁnd we will ﬁrst ﬁnd the Thevenin equivalent of everything to left of the inductor and resistor of interest. The Thevenin voltage is . The Thevenin resistance is . See Figure 10.99.

+ vL -

R
VS ----- + I S R 2 + iL
Figure 10.99: From this we can see the following relation for sources and
£

L R
+ vR -

.

where is the inductor voltage due only to the is the inductor current due only to the initial conditions.

Problem 10.19 The purpose of this problem is to illustrate the important fact that although the zero-state response of a linear circuit is a linear function of its input, the complete response is not. Consider the linear circuit shown in Figure 10.102.

7

s

a) Let . Let and applied one at a time, where s be the responses resulting from voltages

and

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339

vL
K 1τ --------- + K 2 Rτ 2

t
Figure 10.100:

vR

10-3R

t
Figure 10.101:

340

CHAPTER 10. FIRST-ORDER TRANSIENTS

e1 + e2 + -

L = 1 mH

i R = 5 kΩ

Figure 10.102:

Solution:

For the entire problem

.

a) See Figure 10.103 and Figure 10.104.

It is not true that

for all

.

b) See Figure 10.105 and Figure 10.106.

It is true that

for all

.

ANS:: (a) not true (b) true Problem 10.20 In the circuit shown in Figure 10.107, the switch opens at and . and label Solution:

.
) 2 V ¤ F"a B§ ) ¤ ¦

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¤

s )I2 (S§ a @ 0` 7 0` 7 ¥ @

s

,

,

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¤

b) Consider now the zero-state responses due to Plot and as functions of . Is it true that

and

; call them for all

and

?

. Sketch

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Plot

and

as functions of . Is it true that

for all

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71

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i1

2mA

t
Figure 10.103:

i1

4mA

2mA

t
Figure 10.104:

342

CHAPTER 10. FIRST-ORDER TRANSIENTS

i1’

2mA

t
Figure 10.105:

i2’

4mA

t
Figure 10.106:

343

R1

R2

v1

+ -

L

+ -

v2

Figure 10.107:
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See Figure 10.108 and Figure 10.109.

iL

3.5mA 2.5mA

Figure 10.108:

It is not true that

for all

.

Problem 10.21 A two-input RC circuit is shown in Figure 10.110. for all .

A different constraint is that sources and are zero for and that . Sources and undergo step transitions of +1 mA and +1 volt respectively at time . Determine for all time.

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£

£

Consider operation with , to be 1 volt at time . Determine

for

. The voltage

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¡

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s

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©

t

is known

§ £

344

CHAPTER 10. FIRST-ORDER TRANSIENTS

t

-1.2V VL
Figure 10.109:

R2 = 1 kΩ 0.5µF iI(t) R1 = 1 kΩ 0.5µF 0.5µF 0.5µF

R3 = 2 kΩ + vO + - vI(t)

Figure 10.110:

345 Solution:

The four called .
¡

capacitors can be combined into one

First constraint (initial condition and no sources): Second Constraint (sources and no initial condition):

ANS:: First:

, Second:

Problem 10.22 The neon bulb in the circuit shown in Figure 10.111 has the following behavior: the bulb remains off and acts as an open circuit until the bulb voltage reaches a threshold voltage . Once reaches , a discharge occurs and the bulb acts like a simple resistor of value ; the discharge is maintained as long as the bulb current remains above the value needed to sustain the discharge (even if the voltage drops below ). As soon as drops below 10 mA, the bulb again becomes an open circuit.

R = 1 MΩ + 90 V C = 10 µF i + v Neon bulb
Figure 10.111:

a) Sketch and dimension

and

, showing the ﬁrst and second charging intervals.

b) Estimate the ﬂashing rate. Solution: a) Charging (
© ¥
¡

): a S!

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capacitor, which will be

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@ §

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1

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ms.

346

CHAPTER 10. FIRST-ORDER TRANSIENTS

See Figure 10.112.

v 90V

65V

10V t
Figure 10.112: b) Since the discharge time is so small in comparison to the charge time, we will only consider the charge time.
q©
¥

Therefore the ﬂashing rate is once every 11.63 s. ANS:: (b)

Problem 10.23 Because of the input resistance and capacitance of an oscilloscope, laboratory observations of transients, such as the step response of the circuit in Figure 10.113 may have errors in them. s ¡

@

s

@

q©

After the ﬁrst charging cycle, is the amount of time it takes for

to reach 65 V.

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The minimum when discharging is

.

. The charging time,

©

Note that when discharging approaches Also note that so the charging time is much longer than the discharging time.
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347

R1 + vA + Unit step C1 R2 C2 vB Circuit being tested Scope input impedance Displayed on scope

Figure 10.113: a) Assuming that the effect of connecting the oscilloscope to the circuit under test is to add and as shown in Figure 10.113, ﬁnd and sketch the step response that will be observed at in the above circuit. Discuss the errors introduced by the scope by comparing your result to what would be observed if the scope were ideal ( ). Assume zero initial state. b) A common method of coping with the errors of part a) is to use a compensated attenuator in series with the scope (see in Figure 10.114). For simplicity, we examine what the compensated scope displays when it is connected directly to the unit step without the circuit of part a). Assume zero initial state before the step is applied. s ¡

C3 R3 vA + Unit step Compensated attenuator R2 C2

i) What is ii) What is

immediately after the step is applied, i.e. at as
¢
g

? for all .

iii) Using your results, ﬁnd

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g

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s

7

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+ vB Displayed on scope -

Scope input impedance
Figure 10.114:

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348

iv) What conditions on and must be satisﬁed in order that there be no natural response component, i.e. no transient, in ? What is in this case?

¥

¡

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7 @

a)

s

b)

Solution:

See Figure 10.115.

R2 VA ------------------

iii)

iv) There will be no transients if

ii)

i)

R1 + R2

vB

Figure 10.115:

CHAPTER 10. FIRST-ORDER TRANSIENTS

. In this case,

DC

¢¤

¥

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¡

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ANS:: (a)

,

¡

(iii)

(b) (i)

t

(ii) (iv)

349

iL(t) vI(t) + R L

vI(t) K1t

t
Figure 10.116: Problem 10.24 The RL circuit shown in Figure 10.116 is driven with the ramp , for greater than zero, and . a) Assuming for . , sketch the current

. Also ﬁnd an analytic expression

b) In some applications, such as generating a linear sweep for a magnetically deﬂected cathode-ray tube, we want to make a linear ramp as shown in Figure 10.117.

iL(t) iL(t) = K2t

t
Figure 10.117:

Find a new input waveform values and slopes. Solution: a)
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such that

. Plot

. Label all

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350

CHAPTER 10. FIRST-ORDER TRANSIENTS

See Figure 10.118.

iL

b)

See Figure 10.119.

Problem 10.25 For the RL circuit shown in Figure 10.120, sketch and label versus . Assume , and that is ﬁve times as long as the circuit time time for constant. Solution: The until the input can be treated as a step of height . During this time simply rises exponentially to . The short pulse after will be treated as an impulse of area . Taking to be our new and no initial state we have the following. s ` ¤ s

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(b)

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351

iL

RK2

LK2

t
Figure 10.119:

vI iL Area = A Area = A 0 T1 R t vI + L

Figure 10.120:

352 Add to this the initial condion that See Figure 10.121.

CHAPTER 10. FIRST-ORDER TRANSIENTS
¤

and we have
¤

vR
A ----T1

4A – -----T1

Figure 10.121: Problem 10.26 With the capacitor initially at rest ( in Figure 10.122. switch is closed to position (1) at time

) and disconnected, the

a) Sketch the waveform for calculate the time constant.

. Label all relevant points on the ﬁgure and

b) At a time (at least ﬁve time constants later), the switch is thrown (instantaneously) to position (2). Sketch for and label all relevant points on the ﬁgure. c) With , is the time constant in part (a) greater than, less than or equal to the time constant in part (b)? Solution: s ¢ £¢

£ ¡¢ @

§ D

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¡

£

¢

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S

.

t

£

¥£ ¦¤¡ 9

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353

R1 + -

1

2 t=0 + vC(t) -

V

R2

C

R3

Figure 10.122:

See Figure 10.123.

vC V
R2 -----------------R1 + R2

See Figure 10.124. c) The time constant in part (a) is greater than the time constant in part (b). Problem 10.27 For the circuit shown in Figure 10.125, sketch and label versus time. Assume that for a long time prior to as illustrated in the ﬁgure.

D

2§ £

C

DC

s

¢¤

D

b)

¢ £¢

£

C

DC

¢¤
D C

CD

D §

a)

¥ t Figure 10.123:

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354

CHAPTER 10. FIRST-ORDER TRANSIENTS

vC V
R2 -----------------R1 + R2

t
Figure 10.124:

vI K3t K2 K1 t
Figure 10.125:

vI + -

C R

+ vR -

355 Note that this problem can be solved in a number of simple steps by breaking the problem down into parts and solving each part. There are several ways to do this breakdown, all of roughly equal ease. Solution: For , consists of a step of height plus a ramp of slope . We will use superposition to solve this problem, treating the step, the ramp, and the initial condition as three seperate inputs. Forthe entire problem, . Initial Condition: Step: Ramp:
¡

Total:

See Figure 10.126.

vR
K 3τ

K2 - K1

Figure 10.126: s ANS::

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s

D

t

356

CHAPTER 10. FIRST-ORDER TRANSIENTS

Problem 10.28 You are given the RC circuit shown in Figure 10.127.

1 MΩ + vI(t) + 1 µF vO(t) -

Figure 10.127: a) Suppose you observe that is a triangular pulse, as shown in the sketch in Figure 10.128. Find and draw the waveform which must be applied to produce this output signal. Label times and magnitudes, and signiﬁcant parameters of the function.

vO (V) 5

-10

-5 -5

Figure 10.128: b) Now the input signal is changed. You apply a ramp starting at , as the input signal . (Note that represents a unit step at Sketch and label the output signal for . c) Give an analytic expression for the output signal Solution:
©
¡

you sketched in (b).

a)

:

:

See Figure 10.129.

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t (s)

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357

vI 6V

4V

1V 5s -1V
Figure 10.129:

10s

t

vO

4V

5s
Figure 10.130:

t

358 b) See Figure 10.130.

CHAPTER 10. FIRST-ORDER TRANSIENTS

Problem 10.29 Consider the digital memory element shown in Figure 10.131. The voltage at the storage node with respect to ground is denoted . The ﬁgure also shows a parasitic resistance from the storage node to ground. This resistance will cause a leakage of the charge stored in the memory. of the memory The signal is fed to an inverter and the inverter drives the input element. All inverters shown in the ﬁgure have a load resistor and the on resistance of the pulldown MOSFETs in each of the inverters is . Assume that the on resistance of the switch driven by the Store signal is also . The supply voltage is and the threshold voltage for the MOSFETs is . In doing this problem, assume that is much larger than either or .

Store

A

dIN

vM CM RP

Figure 10.131: a) Suppose that a 0V to step is applied at the Store input of the memory element at . Sketch for , assuming that , and that is at 0V throughout. Assuming that , what is the maximum value attained by ?
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359 b) Suppose, now, that a rectangular pulse of height is applied at the Store input of the memory element, and that is at 0V throughout. The rising transition of the pulse occurs at and the falling transition at . Determine the minimum value of the pulse width so that can charge up to , where , the high voltage threshold of the static discipline. Assume the following: ; ; ; c) Let us now consider the case in which is at throughout, and . Sketch for , when a 0V to step is applied at the Store input of the memory element at . What is the minimum value attained by ? d) Suppose, now, that a rectangular pulse of height is applied at the Store input of the memory element. The rising transition of the pulse occurs at and the falling transition at . Determine the minimum value of the pulse width so that can discharge from to , where , the low voltage threshold of the static discipline. Assume as in (c) that is at throughout and that . Assume further that and that is greater than the minimum value attainable by . e) Suppose the memory element is storing a 1 (assume ) at and that Store = 0. Assuming that no further Store signals occur, determine the period of time for which the output ( ) of the memory element will be valid. (Hint: the output becomes invalid when switches from 1 to 0.) Solution: a) See Figure 10.132. Assuming
¡

is much larger than
@

.

c) See Figure 10.133.
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(e)

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(b)

(c)

(d)

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360

CHAPTER 10. FIRST-ORDER TRANSIENTS

vM(t) VS

t = CM(RL + RON)
Figure 10.132:

t

vM(t)

VS

R on VS --------------------R on + R L

t = CM(RON + RON||RL)
Figure 10.133:

t

Chapter 11 Energy and Power in Digital Circuits
Exercises
Exercise 11.1 An inverter built using a NMOS transistor and a resistor drives a capacitance . The power supply voltage is and the on resistance of the MOSFET is . The threshold voltage for the MOSFET is . Assume that logical 0’s are represented using 0V and logical 1’s using volts. a) Determine the steady-state power consumed by the inverter when a 0 is applied to its input. b) Determine the steady-state power consumed by the inverter when a 1 is applied to its input. c) Determine the static power and the dynamic power consumed by the inverter when a sequence of the form is applied to its input. Assume that signal transitions (0 to 1, or 1 to 0) happen every seconds. Assume further that is much greater than the circuit time constant. d) Assuming the input in part (c), by what factor does the dynamic power decrease if (i) is increased by a factor of 2, (ii) is decreased by a factor of 2, (iii) is decreased by a factor of 2. e) Suppose that the inverter must satisfy a static discipline with high and low voltage thresholds and respectively. You are given a MOSFET with on resistance and threshold . Assume that . Choose a value for in terms of the other circuit parameters such that the power consumed by the inverter is minimized. 361

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33 ))3 ) )

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362 Solution:

CHAPTER 11. ENERGY AND POWER IN DIGITAL CIRCUITS

a) The MOSFET is in cutoff and therefore acts as an open circuit - so in the steady state, no current ﬂows through it and therefore no power is consumed.

b) The power can be calculated using the formula , where is the supply voltage, and is the current that ﬂows from supply to ground, which in this case can be calculated using the formula . Therefore, the power is equal to , where is the total resistance.

c) The static power remains unchanged since in the steady state a capacitor acts as an open circuit, providing a fundamentally identical system as before. Therefore the static power is one-half the result derived in part B, because the circuit is only on one-half of the time. To calculate dynamic power, we use the circuit model shown in Figure 11.1.

VS RL

CL RON

Figure 11.1: Since power is equal to energy change per unit time, the best way to calculate the average total power (both static and dynamic) is to ﬁnd the total energy dissipated by each resistor per cycle, and divide by the total cycle length. Energy dissipation is the integral of instantaneous power consumption, so we get the following equation: a £ X © u @ @ ¥ £ X 7 ¦¤¨I ¢ 7 ¡ 7 ¥ ¦£ ¨I ¥£¡ ¥ ¡ @ % 0¡ ¢

The function

is shown in Figure 11.2

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363

vc(t) Vs

τ = R L R ON C L R ON V S ----------------------R ON + R L

τ = RL C L

t on T
Figure 11.2:

off

2T

It consists of two exponentials with different time-constants, as shown. The integration is an exercise in elementary calculus, and results in the following:

If we divide through by the total interval

, we get the following.

The static power is the ﬁrst term, so the second term is the dynamic power. This makes sense because if the capacitor were not there, the dynamic power consumption would disappear.
¢

e) Power actually decreases with increasing , so we can make as large as possible without violating the static discipline. However, the problem arises when we look at the dynamic behavior of the system - as is made very large, the time constant of the capacitor charging and discharging also becomes very large, making the system very slow and therefore useless.

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CHAPTER 11. ENERGY AND POWER IN DIGITAL CIRCUITS

(d) (i) halved, (ii) quartered, (iii) halved, (e) Maxiwhile looking out for dynamic constraints.

Exercise 11.2 Determine for the functions given below. Express your answer in a simpliﬁed sum of products form. (Hint: use DeMorgan’s laws).

a) b) c)

Solution:

a) b) c)

Exercise 11.3 Give a CMOS implementation (using NMOS and PMOS transistors only) of the following logic functions. In doing these exercises, is the value of the on resistance of the MOSFETs needed? Why or why not?

a) b) c)
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Solution: a) See Figure 11.3 b) See Figure 11.4

See Figure 11.5

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366

CHAPTER 11. ENERGY AND POWER IN DIGITAL CIRCUITS

The value of the resistance is not needed, because by design CMOS implementation satisﬁes the static discipline. Exercise 11.4 Write a truth table and a boolean expression that describes the operation of each of the digital circuits in Figure 11.6.

VS C A B Z A B C (a) A B C A

VS D B Z D C (b) A B D A

VS C B Z D C (c)
Figure 11.6:

VS D A C B Z A B D C (d)

Solution: a) b) c) d)
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a) See Table 11.4 b) See Table 11.1 c) See Table 11.1

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0 0 0 0 1 1 1 1

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1 0 1 0 1 0 0 0

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0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

1 1 0 1 1 1 0 1 1 1 0 1 0 0 0 0

0 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1

0 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1

Table 11.1:

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368 d) See Table 11.1

CHAPTER 11. ENERGY AND POWER IN DIGITAL CIRCUITS

Problems
Problem 11.1 This problem examines the power dissipated by a small digital logic circuit. The circuit comprises a series-connected inverter and NOR gate as shown in Figure 11.7. The circuit has two inputs, A and B, and one output, Z. The inputs are assumed as shown in the same ﬁgure. Assume that for each to be periodic with period MOSFET is zero.

VS RL A CG

VS RL Z B CL

5V A 0V t 5V B 0V T1 T2 T3 T4
Figure 11.7:

t

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369 a) Sketch and clearly label the waveform for the output Z for assume that and are both zero.

, b) Derive the time-average static power consumed by the circuit in terms of , , , and . Here, time-average power is deﬁned as the total energy dissipated by the gate during the period divided by . and are nonzero. Derive the time-average dynamic power c) Now assume that consumed by the circuit in terms of , , , , , , and . In doing so, assume that the circuit time constants are all much smaller than , , and . d) Evaluate the time-average static and dynamic powers for fF, pF, ns, ns, V, ns and k , ns.

e) What is the amount of energy consumed by the circuit in 1 minute for the parameters in part (d). f) By what percentage does the total time-average power consumption drop if the power supply voltage drops by 30%? Solution: a) The waveform for the output Z for The truth table: (see Table 11.2)

is given below in Figure 11.1.

Table 11.2: 0 0 1 1 b) Assuming , then: For 0 1 0 1

0 0 1 1 only the ﬁrst MOSFET is on, i.e.

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370

CHAPTER 11. ENERGY AND POWER IN DIGITAL CIRCUITS

V 5 A 0 5 B 0 5 Z 0
T1 T2 T3 T4

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371 For

For

only the second MOSFET is on, i.e.

Therefore, the time-average static power consumed by the circuit is given by

Thus, the time-average dynamic power consumed by the circuit is given by

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again only the ﬁrst MOSFET is on, i.e.

372

CHAPTER 11. ENERGY AND POWER IN DIGITAL CIRCUITS

f) Since the power depends linearly on , 30% drop in in the total time-average power consumption.
¢

(f)51%

Problem 11.2 Implement the logic function using NMOS transistors alone. In other words, use an NMOS transistor in place of the pull-up resistor. Your implementation must satisfy a static discipline with low and high voltage thresholds given by and , where . is the power supply voltage. As your answer, specify the values for the pullup and the pulldown transistors. For what combination of inputs does the circuit dissipate the greatest amount of static power? Determine the static power dissipation for this combination of inputs. Solution:

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Specify the

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values:

B

Figure 11.8:

VS

D C VO
373

374

CHAPTER 11. ENERGY AND POWER IN DIGITAL CIRCUITS

Problem 11.3 A circuit consists of inverters, where . Each inverter is built using a NMOS transistor and a resistor . The power supply voltage is and the on resistance of the MOSFETs is . The threshold voltage for the MOSFETs is . a) Suppose we do not know how the inverters are connected to each other or to the inputs and outputs of the circuit. How might you estimate the amount of static power that the circuit is likely to consume? b) Suppose it is known that the inverters are connected in series as one long chain. Estimate the amount of static power dissipated by the circuit. Solution: a) To estimate static power, ﬁnd all combinations of the circuit layout, and take the average of the power output of the combinations of on-off.
¢

Problem 11.4 Consider the digital memory element illustrated in Figure 11.9. Assume that the inverters are implemented using a pulldown NMOS transistor with on resistance , and a pullup resistor . The power supply voltage is . What is the instantaneous power dissipated by the memory element when it stores a logical 1? What is the instantaneous power dissipated by the memory element when it stores a logical 0?

Store dIN *
CM
Figure 11.9:

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b) On average,

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375 Solution: Instantaneous power dissipated: – for logical 1:

– for logical 0:

Problem 11.5 Give a CMOS implementation (using NMOS and PMOS transistors only) of the following logic functions.
¢ ¡

1. 2. 3. 4.
¤

Solution:
¢ ¡

1. 2. 3. 4.
¤

See Figure 11.10(a)

See Figure 11.10(b)

See Figure 11.10(c)
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Problem 11.6
¢ ¡

a) Express

in a simpliﬁed sum-of-products form given that
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b) Implement the logic function with an NMOS digital logic circuit that obeys the static discipline deﬁned by the low-level and high-level logic threshand , respectively. Assume the the supply olds voltage is , and that the on-state resistance of the NMOS transistors is . Determine the lowest value of the pull-up resistor for which the circuit will obey the static discipline in terms of , , and ; not all variables need appear in your answer.

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376

CHAPTER 11. ENERGY AND POWER IN DIGITAL CIRCUITS
(a)
VS

(b)
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A B B

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Figure 11.10:

377
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c) Implement the logic function Hint: make use of the result from Part (a).

d) Suppose that the NMOS and CMOS circuits above drive a capacitance . Assume that the on-state resistance of both the PMOS and NMOS transistors is . For both the NMOS and CMOS circuits determine the worst-case output rise time. For the purpose of this problem, assume that the worst-case output rise time is the time . Sketch the form of the output for both the the output takes to go from 0 V to NMOS and the CMOS circuit. e) Suppose that the inputs are arranged such that , and , and that a 0V-to-5V square wave signal is applied to the input . Assume the square wave cycle time is , and that is large enough so that the output comes close to its steady state value for both falling and rising transitions. Under these conditions, compute the power consumed by the CMOS and NMOS circuits when driving the capacitance load. Solution: a)
¢

b) See Figure 11.11 for logic diagram

c) See Figure 11.12 for logic diagram d) NMOS output rise time (worst-case):

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CHAPTER 11. ENERGY AND POWER IN DIGITAL CIRCUITS

VS

out A B

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Figure 11.11:

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C D out

A C

A D

B C

B D

Figure 11.12:

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NMOS

VH

0 CMOS

t

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0
Figure 11.13:

t

380

CHAPTER 11. ENERGY AND POWER IN DIGITAL CIRCUITS
CMOS output rise time (worst-case):

See Figure 11.13 for sketches e) NMOS: Power consumed: Alternates between and s ¢s s t3

VS

Ron CL Ron

Ron

Ron

Figure 11.14:

CMOS: no power dissipated
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Chapter 12 Transients in Second Order Systems
Exercises
Exercise 12.1 a) Is the zero input response of the circuit shown in Figure 12.1 underdamped, overdamped, or critically damped?

R + vC R = 15 Ω C = 0.01 µF L = 1 µH

VS

+ -

L

C

Figure 12.1: b) What is the form of the zero input response ( sketch.
S

) for the same circuit? Make a rough

c) Compare the envelope of the zero input response with the rate of delay of the zero input response of the RC circuit in Figure 12.2: How do they differ? Solution: 381

382

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

R R = 15 Ω vC C = 0.01 µF

VS

+ -

+ C

Figure 12.2:

vC e
– αt

t

“envelope”

Figure 12.3:

383 a)

UNDERDAMPED

b)
¢

(2)

above in the RLC circuit decays with “envelope” as

Therefore, the RC circuit zero-input response decays twice as fast as the RLC response; i.e. ; RLC takes twice as long to decay.

Exercise 12.2 For each of the circuits in Figure 12.4, ﬁnd and sketch the indicated zeroinput response corresponding to the indicated initial conditions. a) In Figure 12.4, ﬁnd , assuming
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b) In Figure 12.5, ﬁnd , assuming

c) Repeat (b), but with the resistor changed to Solution:
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386

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS i1 i2 + 10 V L + v1 R1 R2 i3 + v4 Figure 12.6:

i4

R2 = 1 Ω L =1H C = 0.5 F R1 = 2 Ω C

(c)

Exercise 12.3 In the circuit in Figure 12.6, a constant voltage source of 10 volts is applied at . Find all branch voltages and all branch currents at and at given amps and volts. Solution: At ,
¢

Therefore,

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Exercise 12.4 Is the zero-input response of the circuit in Figure 12.7 underdamped, overdamped, or critically damped? (Provide some kind of justiﬁcation of your answer, either a calculation or a sentence of explanation.)

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Figure 12.7: Solution: s For the zero-input case, we may treat the circuit as if

, therefore the response is underdamped.

Exercise 12.5 In the circuit in Figure 12.8, the inductor current and capacitor voltage have been constrained by some external magic to be Amps, volts. At , the external restraints are removed, and the natural response of the circuit is allowed to evolve. Find the initial slopes of the state variables. Solution:

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388

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS
R2 = 2 Ω L=3H R1=1 Ω iL C=4 F + vC -

Figure 12.8:

Amp/s

Exercise 12.6

a) Write the differential equations for the circuit in Figure 12.9 in state variable form.

vC(t)

+ -

Figure 12.9:

b) Assuming , sketch it out: just show the form.

for a very short pulse of height

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389 Solution:

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a)

b) See Figure 12.10.

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Exercise 12.7 Solve the following sets of coupled ﬁrst-order state equations for with the indicated inputs and initial values. Plot the positions of the natural frequencies in the complex plane. Sketch the state trajectories. a)

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CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

which implies

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(a)

(c)

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(b)

(d)

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, we ﬁnd 391

392

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

b)

c) s ;

d)

(ﬁrst-order circuit)

rad/sec

Problems
Problem 12.1 Electrical networks are used to model physical systems governed by linear differential equations. The most important problems which arise in such modeling concern the interplay of accuracy and simplicity. It is usually very important to know when certain effects can safely be ignored in order to simplify the model and subsequent

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393 analysis. Such knowledge can be obtained by understanding the consequences of making the simplifying assumptions. Two networks which could be used to model an acoustic system are shown in Figure 12.12. It is known that the inductance is small (speciﬁcally but it is not known whether a circuit model with no inductances will be adequate. You are to help answer this problem by determining the difference in the responses of the capacitor for the two circuits. Speciﬁcally assume: voltage

(a step of amplitude I)

Determine for for both circuits. You should identify the effects of the inductance on such characteristics of the response as the natural frequencies, approximate behavior for small , and asymptotic behavior. You can greatly simplify the form of your results by making use of some assumptions derived from Taylor’s theorem. For ,

and

+ iS R C vC iS R

L C

+ vC

Figure 12.12: Solution: A time-domain solution using differential equations is presented ﬁrst: We can write the following KCL equation: a

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(12.1)

(12.2)

394

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

We also know that: a

Substituting, we get: a I

The roots of the characteristic equation are: a

Since we know that

, we can simplify to get the following roots: a We now have the following solution to the differential equation: a 8@

By inspection, since the inductor acts as an open circuit at , we know that and , so we substitute in those values, getting the following conditions:

If we set the inductor to zero, we get the following: a £ F! ¥ £ d

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and

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1 ----Cs

Figure 12.13: An alternate, more elegant solution involves working in the frequency domain. First, draw the impedance model as shown in Figure 12.13. From here, determine the Thevenin equivalent of the left side. to

The Thevenin impedance is equal to . A voltage-divider relationship ensues:

This can be simpliﬁed to form an admittance transfer function: a We must ﬁnd the roots of the denominator: a

If we use the Taylor series approximation, we can simplify to get the following two roots: a Our new approximate admittance function is therefore: a ¡

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, while the Thevenin voltage is equal

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396

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

We substitute in that , which corresponds to transform is taken. Our output function is therefore: a This can be simpliﬁed using partial fractions to get the following:

We convert this back into a time-domain expression by taking the inverse Laplace transform: a £ ¢! ¥ £ d
¡

Substituting in that I = 1, we get the following: a £ ¢! ¥ £ d
¡

From here, we can make the following approximation if we leave out the inductor: a Not coincidentally, these are the same results that we got using differential equations in the time domain. See Figures 12.14 and 12.15 for the transfer functions. Note that without the inductor, the initial slope is nonzero, while with the inductor, the slope is zero. The natural frequencies are changed by the presence of the inductor since without the inductor there is but one natural frequency, and with the inductor there are two. For a very small inductor, the second natural frequency is very low and therefore almost negligible in comparison to the natural frequency caused by the capacitor. The asymptotic behavior is identical for both since the inductor has no long-term steady state effect. No matter the size of the inductor, the voltage across the capacitor approaches asymptotically.

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Figure 12.14:

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Figure 12.15:

+ i + v1 C1

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-

Switch closes at t = 0 + C2 v2

Figure 12.16:

398

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

Problem 12.2 Capacitor has an initial voltage . Capacitor is initially uncharged, . The voltage across element tends to zero as time tends to inﬁnity. At time , the switch is closed. See Figure 12.16. a) Compute the initial charge of the system. b) Find the voltage across both capacitors a long time after the switch has been closed. Remember that the total charge of the system must be conserved. c) Find the energy stored in the system after a long time. d) Find the ratio of ﬁnal stored energy to initial energy. Where did the rest of the energy go? e) Assume element is a resistor out the energy lost in it.

. Find its voltage or current, and from that, ﬁnd

f) Find the ratio of lost energy to initial energy. Is it what you expected? Does it depend on ? g) What would happen if an inductor was placed in series with ? Sketch the behavior of the current. (No calculations are needed.) Solution: s ¡

c) Since both capacitors have the same voltage, the energy as
¡

is

Substituting the expression we found for
¡ ¡ ¡

, we get

Charge must be conserved since there is no place for charge to go. Thus, . Substituting for , we have

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7

s

b) We are told that the voltage across tends to zero. Therefore, time. Let’s call this voltage . The ﬁnal charge of the system is

after a long

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is
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is

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f)

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400

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS
¤

Problem 12.3 Shown in Figure 12.17 is one possible circuit model for a transformer, for use where there can be a common ground between primary and secondary. Assume: , , , where , , .

R1 +

i1

i2 + v2 R2

i1 + v1 -

L1-M

L2-M + M v2 -

vS

+ -

v1 Transformer

Figure 12.17: a) Write the state equations for this network using and as state variables, and using the given circuit model to represent the transformer. b) Determine the behavior of the natural frequencies of the network as a function of the coupling constant . In particular, what are the natural frequencies in the limit of small , and in the so-called tight-coupling limit, where approaches unity? c) Assume that is a 1-volt square pulse of length 5 msec. Find for the case . Is the output a good replica of a square pulse, or are there obvious departures from the square pulse shape? Solution: a) We write the following KVL equations:

These can be simpliﬁed to get the following state equations:

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b) Since we are looking for the internal characteristics of the system, we do not need to give it a driving condition, so we set The two state equations can be simpliﬁed to give the following result:
a

From here, we can eliminate and using standard differential equation techniques and get the following equation: a This corresponds to a transfer function whose denominator is: a This can be written in terms of K: a The transfer function can also be easily found in the frequency domain, using Laplace transforms. This solution is demonstrated below. First, we must draw the impedance model for this circuit, which is shown in Figure 12.18. and are the impedances of the three inductors, and and are the currents that go through them, as shown in the diagram.

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402

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS i1 R1 + VS Z1 (L1-M)s Z3 Z2 i3 (L -M)s 2 R2 Ms V2 i2

Figure 12.18: First of all, is most easily calculated as a Thevenin equivalent voltage by a series of Norton-to-Thevenin-to-Norton simpliﬁcations, as shown in Figure 12.19. The last diagram in the ﬁgure is a voltage divider, and after simpliﬁcation, the following result ensues: a From here, it is very easy to ﬁnd , since it is the current going through resistor , so it has current . can be found by ﬁnding the voltage across , which is the sum of the voltages across and .

In order to ﬁnd the natural frequencies, we ﬁnd the roots of the denominator of the system function, which is: a This was derived in the time-domain previously. If

is close to zero, then the denominator can be factored, and the two roots are: a As gets close to 1, one of the natural frequencies increases without bound, and the other gets closer and closer to the following value: a 7 @

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Z2 R1+Z1 + Z3 VS R2

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VS ------------------R1 + Z 1

R1+Z1

Z3

R2

Z2

R1 Z 3 + Z 1 Z 3 -----------------------------R1 + Z 1 + Z 3

Z2

VS ------------------R1 + Z 1

R1 Z 3 + Z 1 Z 3 -----------------------------R1 + Z 1 + Z 3

R2

V SZ3 + -------------------------------- R1 + Z 1 + Z 3

R2

R1 Z 2 + R1 Z 3 + Z 1 Z 2 + Z 1 Z 3 + Z 2 Z 3 ---------------------------------------------------------------------------------------R1 + Z 1 + Z 3

V SZ3 -------------------------------R1 + Z 1 + Z 3

+ -

R2

V2

Figure 12.19:

404

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

c) We can ﬁnd the transfer function in the time domain by realizing that the response to a square pulse is the response to a unit step, added to a response to another step that is shifted in time. We can ﬁnd the two natural frequencies by substituting in to the characteristic equation previously derived. The two roots are and so the response to a unit step will be of the following form:

This for time , of course. The initial value is zero, since the output voltage is dependent on the current through a resistor, which is the same as the current through an inductor, and the current through an inductor cannot change instantaneously. We must ﬁnd the ﬁnal values of each of the exponentials. Since the output dies away as becomes very large, and must be equal in magnitude and opposite in sign. Therefore, we have: a ¥ wwwu uuu

The derivative of our output is:
¢ ¢

The derivative at time is equal to , and if we can ﬁnd the initial derivative another way without ﬁnding , then we can use that result to ﬁnd . That method is as follows: Very shortly after time , the inductors are so close to open circuits, that their resistance is very high, and the two ordinary resistors may be neglected. The inductors obey the rule , so the derivative of the current through any inductor may be found using simple current-divider laws. In other words, we treat the voltage-source as a voltage-source, and the inductors as resistors, and then remember that the “current” found through “resistor” is really the derivative of a current. This is an exercise in simple circuit analysis, and the easiest way to it is a TheveninNorton conversion, and then one current divider. This is shown in Figure 12.20. The result is: a

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¤

s

£ § 7 X 1

¤

§ ¦¤¡ 7 ¥£ § ¦£ ¡ 7 ¥
X
© ©

¤

§ £

F£ §

7 § ¦¤¡ ¥£

§

¤

£

£

405

L1-M M + VS L2-M

VS ---------------------L1 – M

L1-M

M

L2-M

Figure 12.20:

Substituting in the numbers, we get the following: a ¡a

The ﬁnal solution is therefore: a ¥ wwwu uuu

However, this is only the solution to the up-step. The solution to the down step must is the unit step function.) be added. ( a (H( a ¥ 2 @

This solution can be done out with less sleight-of-mind in the frequency domain. We have already found the transfer function

:

£ C¥ 2 ¤¡ 0H( a

7

£ 2 9S a

@

@ 7u 7u

C£ AA

£¡

From here, we can divide through by

and get that

2 H a

§

a

7

7 s @ 7 I @

(¢ ¡¢ a

¢¡

£ 2 ¤ 7 9H a¡

7

7 § ¥ ¨(#¡

@

7 § ¨¥ #¡

¥ C¥£ ¦£ ¡ ¦¤¡

¤

¤7

Then, we know that the resistor , so knowing , we can ﬁnd

obeys the law , which is equal to:

, so we know that

§

¤

@ §

@

¤

§ ¦£ ¡ ¥

¢¡

¢¡

7 2¨¦¥¤£¡ 7 §

7

¤

¥£ ¦¤¡

C

@

¤

406

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

The input function, can be expressed as the difference of two unit step functions, one shifted in time. We could deal directly with such a function, but it is much easier to deal with one unit step function, and, because superposition allows us to do so in a linear time-invariant system, we shift the response in time correspondingly. So we must ﬁnd the response of the system to a unit step function. This is done by multiplying the system function by the Laplace transform of the unit step: a Substituting in numbers, we get: a Finding the roots of the denominator and then doing partial fraction decomposition gives us: a 2 H a @ 2 H a

Then, an inverse Laplace transform results in: a This is the response to only half of our input. We must add an inverted and shifted unit step to this, to get our ﬁnal value: a (H( a ¥ 2 @

The graph of the output is shown in Figure 12.21. This does not resemble a square wave due to the fact that while the coupling constant is high enough to allow one natural frequency to be extremely high, the second natural frequency, which is a function of the sizes of the resistors and inductors, is too high and allows for a very quick decay. The second natural frequency must be decreased enough to allow the square wave to not dissipate quite as fast.

a

! 7 @s @ ¥ !¥

7 @s @ ¥ !¥ s ¥£ C uuu ¦¤¡ ¥ wwwu 7

£ C¥ 2 ¤¡ 0H( a

((()6¥¨!(02 ¥ 2 a 6 e

¥ (0(0 ¨!

s

7 @ ¥ 7 !7

7 @ ¥ 7 !7

£ 2 9H a

@

s

£¡

s s

@ 7u 7u

s

¢¡

@#¡ ¥ 7 ! ¥ 7 © 7 @ @#¡ ¥ 7 ! ¥ 7 © 7 @

( 0 ¥ ! a

7 (S¢ F ( a ! 2

7

£ 2 ¡ ¤ 7 9H a§

@

¥ C¥£ ¦£ ¡ ¦¤¡

s

s

§ ! ¡ 7 ¥

¡ H¥ 7
¡ H¥ 7

§ ! ¡ 7 ¥

¢¡

¥£ ¦¤¡

7 2¨¦¥¤£¡ 7 §

¥ ! %#¡

¢¡

@ TP¡ @ TP¡

7

§ 7

§ 7

407

0.05V

0

10ms 5ms

-0.05V
Figure 12.21:

(c)

Problem 12.4 Assuming , for each differential equation, ﬁnd the particular solution and the general form of the homogeneous solution. Plot the natural frequencies in the complex plane. Assume , , are constants. Do not worry about the dimensions of the right-hand side. Assume always has the appropriate dimension.

4)

Solution: The easiest way to do these would clearly be via a lookup table to get the form of the homogeneous and particular solutions, but such a “solution” is not particularly insightful.

u

©

©

©

©

6)

Assume

u

¢

u § §7

¢

¥

©

©

5)

Assume

¢

u

' t§

For 5) and 6), assume

and

¢

§ 7u

¢

' t§

¥

©

©

© u § 9¢ ¥ C C © 7

C © ¥ C © C © ¥ C ©

¢

3)

©

©

¥ ¢ §

¢

©

©

2)

§

¢

¥

©

©

1)

are both positive numbers. . .

@

¥£ ¦¤¡

7

£ 2 a 9S B@

¦

£

¤

§ ¦¤¡ ¥£

'

C § ¥ ¤ ¥ 1¥ 7 ¤ @ 7 C 7 C ¡ u @
¢
¦

D

s

ANS::
¤ ¦

(a)

§

7 ¤1

C uuu ¥ wwC wu

¤ C C

@

£ 2 a 7 u ¤ 7 ¢u §7 C 9H ¡ § C ¤ ¤ C C D¦ ¥

71

uuu a ¥(H( a @ ¤¡ C¥ § ¥ wu ¥ wwwu 7 9H a 2 £ C u £ 2 C ¦ ¤ 7 C ¤ C ¥¦£¤¡ 7 C¦ ¤ ¥C ¦ 1 ¤ ¦ ¦ ¥ C D @ s 1 s @ C §

¤1

' t§

uwu u u s s

¤

¥

£ 2 a 9H

¦

408

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

One realizes that if the driving function is of the form then the particular solution is of that form too. The homogeneous solution is determined also by inspection by substituting in and using elementary differential equation solving techniques. But again, that solution is very mechanical and probably reveals no new insight. The alternate approach involves Laplace transforms. Due to the unfortunate choice of as one of the parameter variables in this problem, we will be doing the Laplace transforms in terms of as always, but converting the form of into - note the distinction between capital and lowercase. Another convention is as follows: if is a time domain function, then is its frequency-domain equivalent. In any answer identifying the form of the homogeneous and particular solutions, and are arbitrary constants whose value are not held between problem parts. Finally, and represent initial values of a function and its derivative at zero, and are constants. 1) a £

Take the Laplace transform of this... a Simplify algebra to get:

A partial-fraction decomposition results in: a This results in a time-domain solution of: a £

¢

¢

The natural frequencies of the function are ure 12.22.

and

s G@

¡

The homogeneous solution is of the form form a £
¡

and the particular solution is of the , and are shown in Fig-

©

¡

¥ ¡ §

¡

¢

@

!

a

¢

¢

¢ s ¨! ¥ ¥ ¥ ¥ (#¡ §

¥ ¡ § ¥

¥ s¢

¥ s¢

£

¥

¥ £! £

!

s

£

¢

!

¢

¢

£

¥ !

@

£

@

¤ £ § § ¥ §

¥ ¡ § ¥

!

! #¡ ¥

£¥ ¡

§

s

¢

§ ¥

¤

'

¡

¥ !¡

X

X

¢

¥

!

¥ s¢

¢

@

¡

§

!

¥ s¢

@

¢

¡

¢

§ §

§

¡

£ ¡ ¨§

£

§

¥ ¡ §

'

¤

409

1 – -τ

s

Figure 12.22: 2) If is of the form then is of the form , and a solution can be derived from the solution to part 1 by substituting for every instance of .

The ﬁnal solutions are the same as for part 1. ¡

The homogeneous solution is of the form form a £
¡

and the particular solution is of the

1 – -τ

s

Figure 12.23: 3) This equation can be expressed as:

¢

¢

The natural frequencies of the function are ure 12.23.

and

, and are shown in Fig-

a £

£

s G@

¢

¢

¢

¥ s¢

¢

¥ £! £

£

!

£

£

¥ ¡ § ¥

¥ ¦£ ¡

¤

'

¢

¢

¥ s¢

@

¢

£

§ §

¥£ ¦¤¡

'

410

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

Figure 12.24: 4) a £

Taking the Laplace transform of this, one gets: a This can be rewritten as:

A partial-fraction decomposition results in the following:

7

a

7 ¢ ¥ 7 ! ¥ 7 ¥ ¥ #¡ § ¥ ¥ ¡ § !

¢

¢

¢

¥ 7! 7

¤

@ T!

§

¡

¥

¡

7

7

7

¢

¢

¢

!

¥ (#¡ § @ (#¡ § ! @ ¥ ¥

¥ 7

¥ 7! s

§ § 7

¢
¢ ¢

The natural frequency of the function is

as shown in Figure 12.24.

s

¡

There is no homogeneous solution, and the particular solution is of the form

a

£

a £

¥

¤ ¢

¥ ¨P¡

¤

¢

¥ 7 #¡ ¥ !

§

¡

7£ ¥ § X 7 X

u

¥

§ §
¡

¢

¢

@ T! u

@

! #¡

¡

¡

§

7! §
¡ ¡

411

This can be converted into a time-domain equation of the form:

ω0

–ω0
Figure 12.25: 5) a £

Converting this to the frequency domain, one gets: a ¢

@ T!

§ § 7

¢

¥ ¤¥ #¡ § @ ¡

§ § 7

¢

The natural frequencies of the function are ure 12.25.

and

s

¢

¡

¢

¡

¡

The homogeneous solution is of the form ular solution is of the form a and the partic-

, and are shown in Fig-

¥£ ¦P ¢ ¡ $ )! 1

£

¥ ¥ (#¡ §

¢

¤

¥£ ¦¦ ¢ ¡ $ 1 ! 7

7

s

¢

¢

¥ 7

@

¢

¥ ¦¦ ¢ IH s ¥£ ¡ !

a

¢

¥ ¥ #¡ §

7 ¥ (#¡ § ¥ ¢

¥ ¦¦ ¢ IH ¥£ ¡ !

¤

7

s

¢

¢

!

£ ¥ §X

¢

¥ 7 ¥ 7

£

@

7 ¥ ¡ § ¥

¥ ¥ #¡ §

X

¢

@

¢

7£ ¥ § 7

§ s § 7

¤

£

¡ ¡

¢
X
¡

X

@

¥ 7
¢

¥ (#¡ § !

@

¢

¥ £
@
¡

7!

7

¢

¥ 7
¢

§
¡

7

¢
¥
@ 7 ¢

¢

¥ 7
¢

§

7

¥ ¦£ 7

@ 7 ¢

¡ $ )! 1

£

¥ ¦£ 7 ¥

@ 7 ¢

¡ ! I0

£

¥ G § § £

412

From this, an inverse Laplace transform can be taken. This intermediate step will come in useful for part 6.

¢
7

¢

7

@ 7 ¢

¥

¥ 7
¢

a

£ ¤

¥ #¡ § ¥ ¥ #¡ §

¥

¢ ¢

@

@

¢
¢

§

¥

¢

7 ¥ ¡ § ¥

¥ 7
@

§

7
¢

¥ ! ¥ 7!

a

7

@ 7 ¢

a

¥ #¡ § ¥ ¥ #¡ § ¥ ¥ #¡ ¥ !

¤

¢
7
¥

7
¢

¥ ! ¥ 7! s
¡

7 ¢ ¥ ! ¥ 7 ! ¥ 7 ¥ ¥ ¡ § ¥ (#¡ § ¥ ¨! ¡ ¥ ¥
¢

¤

When this is done, the following result is gotten:

7
¢

¥

¥

¥¨! ¥ 7 ! ¥ #¡ !

In order to properly take an inverse Laplace transform, the second term must be written in the following form:

¢

¢

7

¥
@

¥ 7
¢

s
¡

¢

@ R!

@

§

¢

¥ 7
¢

§

u
¡

¢
¥

@

! u ¡

§
¡

A partial-fraction decomposition results in:

¢

¥ ! ¥ 7 #¡ ¥ !

@

! #¡ §

¡

This can be rewritten as:

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

7
¢

@

7

@

C

C © ¢
£

¥ C
¡

C ©

£

a

C

C © ¢ £ C C ©

¦

@

¥ C

C © £ C C ©

a

¥C

£

@

C

¥ ¥C

C

©
¡

C

£ © ¡
¡

£

C

7
¥

a

¥ (#¡ § ¥ ¥ #¡ §

¤

¢
¥

7 ¥ #¡ § ¥

The homogeneous solution is of the form particular solution is of the form

7

s
¡

The natural frequencies of the function are in Figure 12.26.

¢

a

£

¡

¦

£ U¥

C

©
¡

C

7

@ 7 ¢

¢ ¢ ¢

¢ ¢ ¢

¥

¢

¥ 7
¢

@

@

¥ 7
¢

@

§

This can be simpliﬁed to:

¢ ¢

§

However, since statement as:

2 –α – α – ω0

¥

£ © 3¡
¡

£

2

2 2 – α + α – ω0

,

Figure 12.26: is imaginary, so we can write the previous and

s
, and are shown and the 413

¥ G § § £

¤

¥ G § § £

¤

414

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

6) We start with this intermediate result derived in part 5:

¥ ¦£ 7 C C ¥ ¦¦ ¢ " ¥£ ¡ !

©¢

s

@ 7 ¢

¡

¡

£

¡ $ )! 1 7

¡

¥ C

£7

C ©

¡

¥ ¦£ 7 ¥

£

s

@ 7 ¢

¡

¡

¡

ANS:: (1) homogeneous: , particular: ular: (3) homogeneous: none, particular: , particular: (5) homogeneous: , (6) homogeneous: ticular: ticular:

(2) homogeneous: (4) homogeneous:

£

!

£

£ £

¢

The natural frequencies of the function are in Figure 12.27.
£

and

7

@ 7 ¢

¥ ¦£ 7

@

@ 7 ¢

¡ $1 !

¡ ! I0

£7

£s

¡

¥ ¦£ 7 ¥

The homogeneous form is of the form

solution

is of the and the particular solution , and are shown

a

¥ (#¡ § ¥ ¥ #¡ §

¤

7 ¥ #¡ § ¥

7

¢

¥

¢

¢

¥

¢

¥

¢

7

7

¥ 7

¢

¢

¢

¢

¥

¥ 7

@

¢

¢

@

¥ 7

§

We must replace all instances of

with

, which results in the following.

¥ ¦£ 7

@ 7 ¢

¡ $ )! 1 a ¥ (#¡ § ¥ ¥ #¡ §

£

¤

7 ¥ #¡ § ¥

7

7

@ 7 ¢

¢

¥

¢

¢

¥

¥

7

¥ ¦£ 7 ¥

¥ 7

¢

¢

¢

¥

@

¥ 7

¢

¢

@

@ 7 ¢

¥ 7

§

¢

¢

¢

@

§

§

¡ ! I0
!

@

¡

¢

¢

£

¡

§

§

£
£

a £ @ 7 ¢ I0 ¡ !

¡

¥ G § § £
¡

£s

a £ £ ¥ ¦£ ¢ ¡ $ 1 ! 7

¡

, partic, par, par-

£
¡ ¡

¡

¡

415

2 2 – α + α – ω0

s
2 2 –α – α – ω0

Figure 12.27:

+ CA vA iS

RA RB

+ vB CB

Figure 12.28: Problem 12.5 The circuit in in Figure 12.28 is the electrical analogue of a temperature control system. where
2 ¤ SS§ u
¡

(As a check on your state equations, the stable steady-state value of is, you should have for .)

is

b) Now assume and , where and are the steady-state values and and are small variations. Determine a small-signal linear circuit model in which and are the state variables. c) Is the zero-input response of the small-signal circuit underdamped, overdamped, or critically damped? Solution:

W

¡

a) Write dynamical equations for this network in state form. Use variables.
¢§

and

¡

¡

¥ ¢

§ £

X `

§

X ¨£ X ` ¡ X §

¥

¡

¡

¡

¥

§

¡

¥

¡

@ u

¡

Assuming
0¡

a T ¤(B§

u ¢ aSE§ ¦S` 7 @ ¤) § T

@

B§

7P¥ §

§ ¤R 1

as state . That

416

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

a) Two node equations: a See Figure 12.29 for a small-signal model.

RA + vA CA RB iS CB + vB

= -2K(Vo-VB)vB
Figure 12.29: c) First, write two new state equations using the small-signal model:
¥ y¢P' U@ u 0¡

We substitute in the numerical values given, and get the following:
2 ¢@

a

¥ '

a

a ¢

¢

¡

U@

¡

¥ '¡U@

@ ¥

@ ¥

@

u

3¡

§ ¡9 a ¥ 2

§ ¢

§

@ u 0¡

@

¢

§

@

@ ¥

¡ @ ¥

§

¥

¥

¡

@

X § ¢ 1 1 X

£ X ¡ X

@

£ X ¢ X

§ 1

¥

£

X

X

¥

¡

¥

£

X

X

¡

¡

u

b) Since

, then the following small-signal approximation is valid:

@
¡

@

¡

§

@

¥

£ X 7 ' @ u 0¡ ¥ X
¡

§

@
¡

7 ' ¥
@

@

¡

¥

¡

0¡

£

X

X
¡

¤§

¡

1

417 We can eliminate
¥

This has the following characteristic equation: a (2§

Since

, the system is overdamped. u Problem 12.6 In the circuit in Figure 12.30, the switch has been in position 1 for all . At , the switch is moved to position 2 (and remains there for ). Find and sketch and for .

10 Ω 1 + 2V Figure 12.30: Solution:

1H iL + vC .01 F

2

The natural frequency is equal to . Since the capacitor starts out charged, initially, the voltage across the capacitor is a cosine function with maximum amplitude of . The current through the inductor is the same as the current through the capacitor, and it is characterized by the capacitor I-V relation: Taking the derivative, we get a negative sinusoidal relation. ANS:: a d

See Figures 12.31 and 12.32 for the plots of these two functions. Problem 12.7 Figure 10.75 (Problem 10.8 in the chapter on ﬁrst order transients) illustrated a parasitic inductance associated with VLSI package pins. Figure 12.33 is a modiﬁcation of Figure 10.75 and shows a lumped parasitic capacitor associated with the ¡

A

©

©

a

¥ ¦£

¡

s 9

§

1

¡ $1 !

s 9

@

§ 1 ¦£ ¥

¢

s 9

¡ ! " 0 §

At time

, the circuit becomes an LC oscillator.

£

¥

©

¡

u

ANS:: (a) (c) Overdamped.
© ©

(b)

@

0¡

@

§ 1

¥ ¦

£ A D §A § £

a

§ ¥
¥ ¦

A D ¥ ¦A © ¥

¨ ¥ 7 ! & ¥ !

£ X ¢ X

¥

7 ¥ 5@

7£ X ¢ 7 X

0¡

& )

§

¥ ¡ & H¥ ) ¡

¥ ¦

£ A D §A ¥ ¤A £ £

£

, getting the following:

¥£ ¦¤¡ 1

@

¡

7
¡

¥£ ¦¤¡ 9 § 2¨£
9

£

¡

¥

S

£

418

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

VC 2V

t

0.628 s -2V

Figure 12.31:

iL 0.2A

t

0.628 s -0.2A

Figure 12.32:

419 power node within the VLSI chip. In this problem, we will study the combined effect of the parasitic inductance and capacitance . Assume that the input is 0V at all times. Assume further that the input has 0V applied to it initially. At time , a 5V step is applied at the input . Plot the form of as a function of time for the underdamped and overdamped cases, assuming that for . Clearly show the value of just prior to and just after . Assume that the on resistance of a MOSFET is given by the relation and that the MOSFET’s threshold voltage is . Also assume that . Compare this result with that for the inductor acting alone as computed in Problem 10.8 (Figure 10.75) in the chapter on ﬁrst order transients.
¤ ¤ ¡

VS

LP vP R1 A W1 ------L1 CP R2 C B=0 W2 ------L2

vA

5V 0V t0
Figure 12.33: Solution:

t

Next, the MOSFET is closed, and the voltage across the capacitor starts dropping, since the inductor current cannot build up suddenly and so the capacitor supplies the is still ﬂoating. current. Note that resistor s ¡

This occurs with a time constant of

¥ £ ¨ @ ¥

@ #¡

s

Before the switch occurs, the resistors the voltage across the capacitor for is

and .

are ﬂoating. We are also given that

. Soon the inductor current

u

£

©

u

@

£

S2

7 @

¢

@

§

¤

u

£

£ § £

7 @

¢

u

£

£

¡t§

420

CHAPTER 12. TRANSIENTS IN SECOND ORDER SYSTEMS

builds up and the voltage will rise again towards . The lower envelope of this rise will have a time constant If the system is overrdamped, then the solution is as shown in Figure 12.34 while the underdamped case is shown in Figure 12.35.

VOUT

VS

LP τ = -----RT

t0 Overdamped Case
Figure 12.34:

VOUT

VS

τ = RT C P

t0 Underdamped Case
Figure 12.35:

a

D

§

¤

τ = RT C P

t

LP τ = -----RT

t

¥ S @ 0¢ 2 & x 7 (6B§ s x u ¢ d x u 7 x a 2

¥¥
#

§ E
¤ ¤

¤ ¢ 2 V ¥ £S¢ a W § ¡

¢

x
¡

© ¤

¥ x ¡

a )E ¤ & § ¤ s £S& V a( §¨¥ a I @ V a ¡ ¥ ¡

¤ s¤ s

£ S& ()¨(¢ V a § ¥

¥
¡

¡

¡

§

¡

¡

u ¥ w s ¥ S& ¡ ¥ ¥ ¤ s ¢ ¥ s ¥ SW ¡ £ £ V ¥(" @fP¡ ` ¥ W ¦PH¥ ¢ 7 9)PH¥ w 9S#¡ V @ ¡ £ ¡ u £ 2 § £C § ¦ C 7 u u ¡ §¢ ¥ § ¡ ¥ ¥ § s ¢ s £ ¥ u d ¥ C ¡ ! u 7 ¥ ¢ ¥ ¤ ¤ ¥

¥

¥ a I

@ V (#¡ a

¥

¥
¡

£¡ u £ 2 3H¥ w 93¡
¡

¥

¥ (¢

¥ ¡

SSS: Impedance and Frequency Response

Chapter 13

Exercise 13.1 Find the magnitude and phase of each of the following expressions

Exercises

b)

¥

¡

¥

¡

d)

§

§

a)

b)

¥

§

¥

c)

a)

Solution:

421
V 9 @

¥ 0 ¥ ¥
@
¢

¥¥

¥

§

#

¢

¤

@ ¥ ! !

@

§

g

@ ¥ ! !

@

§

`

¥ ¥ 02 ¥ £ ¢ '¢ ¡

¥

¨

¥ ¥ 02 ¥ £ ¢ ¡

¥

¨ ©§¦¤ ¡ )

a

¥ ¦¥

¥ £ ¢ 4£ ¡ ¢

¨ ¨

¥ ¥

¥ ¥ 02 ¥ £ ¢ 4£ ¡ ¢

¥

¥ ¥ 02 ¥ £ ¢ ¡

g
¡

£ 9¢

u

£ V a 9S e2
¡

V S&

¥ 9 ( a ¡

¤

£ & a V & 90 (S)§

§
#

¤

¥

(6 a 2

§

¤ ¤

¤ ¢ 2 V ¥ £S¢ a W §

#

¤

#

a & ()

§

¤

x d x

x § s

¡

¡

¡

£ V S¦

¤

¡¤

£! ¡ ¤ ¡

¥

u w s ¥ 93 £ &

¥

§ ¥¤ s ¢ ¥ s ¥

VS& ¥ @ ¢ ¥ (t§ # ¢ ¤ V d 7 7 & V (W § s x s x s x ¥ 7 E u §

¤

422

c)

¥

¢

§ ¥

¥

¥

¥¥¤

d)

¦

¥

§

2¢ @ § # ¤ V (¢ tE ¤ a §

ANS:: (a) , (c)

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

,

, (b)

,

¢

2 ¢@
¢

§

#

V e¢ B§ a

¤

¥

¢

§
¢

¤

,

, (d)

,

¢

Exercise 13.3 Find the system function ﬁnd the response for

£

¢

¨ ©§¦¤

§ ¦£ ¡ 1 ¥

¥ ¡ ¦£ Q

¨

¥ ¦¥ ¥ ¦I a V
¢

¥ £ ¢ '£¡ ¥ ¥ ¥ £ ¢ ¡ ¡ ¢ V S& ¥ 9 e a

g g

¥ £

¡

£ F¢ # ¢

¥

¡ ©¦¤ ¡ ¢ # ¢ ¨ ¨¦ ©¤ ¡ )
a

§ ¢ ¥ § u ¥ ¢
¡

¥
¡ ¡

£ S

¥ ¦I a V g ¡

£ u ¢ S

u7
¡

3

¥

£ SW3

¥

¢ £
¡

£¢ #¢

§
#

¡

£ #

¥
£ 9¢ u

¡

£¡ 3H¥ u

¥
¡

£ S)
¡

¡ ¡

u

¥ u 7 3H¥ £¡
¡

¥

£ S)

¥ u7
¡

¡ H¥

¥
¡

£ Hr¡

¥ 2 (e ¥ ¡ V

Exercise 13.2 Find the real and imaginary parts of the following expressions

¢

& V (W 2§

¤

¢

b)

a)

c)

d)

d)

b)

a)

c)

Solution:

ANS:: (a)

Solution:

where

, (b)

for the network shown in Figure 13.1. Then under steady state conditions. , (c) , (d)

¨¦ ©¤ ¡ ¢

#¢

¥

¥ ©
V

¥

2 HU¥

£ 9I)P¡ 3 d

¨¦ ©¤ 7 ¥
¢

§ ¥£¡ ¨¦¤¢

¥

£
¡

©
V

¥

§ R

V

¥

V

¥ §

@ ¨! ¥ @ )!

u

§

¤

) IV

§

Exercise 13.4 Referring to Figure 13.2, given , where rad/sec, determine in the sinusoidal steady state. Assume .

T ¢

§

@

u

£

¢

¨ ©§¦¤ u
,

§ ¦£ ¡ 1 ¥

¥ ¡ ¦£ ¢ ©

D

s

¦¥£ § ¡ ¥ ¡
¢

¥ £ ¢) ¡

¨ ©§¦¤ 3
¢

D

§ ¥ ¡ ¨¦£ 4 D ¢ D §
,

7 @ ¥ 7¥
¢

¡

¥

¡

¥ £ ¢ ¡
¢

¨ ©§¦¤ 3

@

§ ¦¤¡ ¥£
¢
¡

7 @ ¥ 7¥
¢

¡ § ¢ @ ¢ s ¦¥¤§ £ -

@

§ (¢

¢

ANS::

¢

C D ¢C §

¥

Therefore,

¥

2 6

¥ £ 3 d ) ¡

¨ ©§¦¤

§ ¦£ ¡ ¥

ANS::
) q

Solution:

l

i(t)

i(t)

Figure 13.2: Figure 13.1: , angle of

R

R

L

v(t) + L + vL
423 and and

-

§ § d 9

¢

424

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

Exercise 13.5 The two-terminal linear network in Figure 13.3 is known to contain exactly two elements. The magnitude of the impedance function is as shown, (log-log coordinates).

|Z(jω)| 100 70.7 i(t) + v(t) Linear network 104 rad/sec
Figure 13.3: Draw a two-element circuit that has the impedance magnitude function indicated in the sketch. Specify the numerical value of each element. Solution:

Slope = -1

ω

+ R –
Figure 13.4: s C

Exercise 13.6 For each of the circuits shown in Figure 13.5, select the magnitude of the frequency response for the system function (i.e., impedance, admittance or transfer function) from those given. It is not necessary to relate the critical frequencies to the circuit parameters, and you may choose a magnitude response more than once.

¡

D

s

¢

D

¡

ANS::

,

,

,

¤£§

T (0) § @ (` !

4 X 9¥

)§

s

D

! (`

4 X I¥

¢

§

§ T(( S@ § D )§ s D §

D

¤£

¡

¡

425 Please note that the magnitude responses, except (7), are sketched on a log-log scale, with slopes labeled.

i1 + v1 -

(a) R C

(b) i1 R + C - v2 + v1 R C
V 2 ( jω ) H ( jω ) = ----------------V 1 ( jω )

(c) + v1 V 1 ( jω ) Z ( jω ) = ----------------I 1 ( jω )

(d) i1 R1 L C + v1 V 1 ( jω ) Z ( jω ) = ----------------I 1 ( jω )

R

L

R2

I 1 ( jω ) Y ( jω ) = ----------------V 1 ( jω )

(1) -1

(2) +1

(3) +1 -1

(4)

ω1

log ω

ω1

log ω

ω1

ω2 log ω

log ω

(5) +1

(6) -1

(7)

(8) None of the above

ω1

ω2 log ω

ω1

log ω
Figure 13.5:

ω1

ω

Solution: a 2 b 4 c 8 d 5

ANS:: (a) 2 (b) 4 (c) 8 (d) 5 Exercise 13.7 A linear network is excited with a sinusoidal voltage for all time, as shown in Figure 13.6.

¥

¡

¤¥
@

£) ¡

¨ ¤ ©§¦¡§

¥ ¡ ¦£ %

426

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE iI(t) 5π v I ( t ) = cos  t – -----  +  8 -

Z(s)

Figure 13.6: The current observed under the sinusoidal steady-state conditions is .

What is radian per second? Solution:

, the impedance of the network at an excitation frequency of one

Solution:

where s 77 @7 @ ¥ 7¥7 @ ¥ 7 @ ¢

Exercise 13.8 Find , and

in the sinusoidal steady state in Figure 13.7. Assume .

)E§

¡

¡

£ W¢

¥

¢

¡

¢

§

7 @%¤¢ ! ¥ ¢ 7 %§¢ ! @ ¢

s

@¡ 7 7

¢

s

@ § 7

§ %¢ ¥

¢

§

¡ ¢

T((2§ 7 @ & ¥£ ¦¤¡ 7

7

¢

¡

¥

ANS::

¡

§

¢ ¥

£

©

§

¡

¥

since

§
,

¥ ¡ ¦£ % 1

¢

$ V

@

£ )

©§¦¤ § ¢ ¨

§ 7¢ ¤¢ ¢ ¥ § ¤ ¢ ¡¥

$

@

£

¥

¡

¡

@

£

£

©¤ § ¢ ¨¦

©

$

§

§

$

¡

¥ ) £

¢ ¥

¨

¢

£

¥ ) s § !¡ §

¥

¤

T 00§

¥ £ '£¡ © ¡ ¢ s ¨

@

427

R1 3 V cos (4t) + L R2 + v2 -

Figure 13.7:

i(t) v(t) + Network

Figure 13.8: and

Exercise 13.9 A sinusoidal test signal is applied to a linear network that is constructed from exactly two circuit elements as shown in Figure 13.8.

¡

The magnitude portion of the Bode plot for the impedance in Figure 13.9. Draw the network and ﬁnd the element values. Solution:

§ § ¥ ¥

¡

§ ¥

¢

¡

! (`

¢

4 X 9¥ d

¥ @ §

)

b p

¥

¥

¢

¢

§

¡

¡

@

¢

7

¢

ANS::

¢ $ is shown

¥ 0 £

©§¦¤ ¨

7

¥

For

,

, and

,

¢

7 @s @ ¥ 7 @ ¥ s #¡ @

¢

¦¥£ s¢ s

©

§ %¢ ¥

¢

¢

§ ¥£ ¨¦¤¡ 7

@ (`

¡

¢

$ §

¥ 0 £

¡

¨ ©§¦¤

I`

$ 6§ s ¡

§ ¦£ ¡ 7 ¥

t§
¢

428

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

105 V ( jω ) --------------I ( jω ) 104 103 105 106 107 108 ω

Figure 13.9:

R = 1000Ω L = 0.001H

Figure 13.10:

Exercise 13.10 The circuit shown in Figure 13.11 is a highly simpliﬁed model of a power transmission system.

L1
1

v1(t)

+ -

+ vL(t) 2

Figure 13.11: and

are the voltages of two power generators:

Find the Th´ venin equivalent of this circuit at the terminals 1-2 in terms of a complex e amplitude and a complex Th´ venin impedance e .

¥

¡¥

£ ¢ ¡

¡

ANS::

,

¢

¥ @ §

§ § ¥ ¥
¡

¨ ©§¦¤

! 0`

4 ¥ d X I9)

§ 7

£

b 8

¥ ¦£ ¡ 7

¢

¨ ©§¦¤

§ D

L2 + -

v2(t)

§ s ¥ ¦£ ¡ s

7 @ ¥ 7¥

¢

¡

£
¡

¡

¢ s ©¥£ § ¡
¢
¢

¥ 7
¢ ¢

©

§ %¢ ¥

¢

¡

¢

T 2¡ § @

¤£
§

¢
¢
¡

¡

@

s ©¥¤§ ¡ £
¢

¥ 7¥
¢

@ #¡ §

¥ !
¡

¡

@ §

s

¥ @

£ ¡

¢ @ s ¦¥¤§ ¡ £
¢
¢

7 @ ¥ 7¥

¢

¡

£
¡

¡

¥
¢
¡

¡

@ ¡ @ s £ ¦¥¤§ ¡
¢
¡

¥ 7¥
£

@ ¢¡

§

¥ !

@ §

@ ¥

s

§

¡

s

Exercise 13.11 Write expressions for , its magnitude and its phase angle , as a function of in the four cases shown in Figure 13.12.

¢

¢¥

¢

¡ ¢

S `

§ ¥ C

¢

¡

¥

¢

¡

¢

W3

¡

¤ ¢ C ¡ r¤ ¢ §

C

¢¤ ¤

§ ¡¢

§ ¢¤@ ¢

F3

7

£
¡

¡

s

¥ s

¥ 7

§

!7 !

s

¥ !s

7

¥

!7

¥ ¨! s

!7

s

§

7 §

¥ s

¢¢

!7

s

§

!7 ¥ !s § ¡¢ ! 7 @ !s

§ ¢¤@ ¢
Solution:

By superposition,

ANS::

C

(a)

Solution:

(b)

¢

§

@ ¨! ¥

!

§

(c)

¢
¡

@

!

@

@

§

For

¡

(d) and

@ and §

!

¥ @

@

§

,

,

429

430

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

(a) vi = ejωt + -

R C + vo -

(b) vi =2 ejωt + -

R L + vo -

(c)

C = 1 µF = 10-6 F + vo -

vi =5 ejωt+ -

R =106 Ω

(d) vi =10 ejωt + -

L=1H + vo -

R =10 Ω

Figure 13.12:

¥0

@

g

¥ ( ¡
@ @

¥

g

¥

¢

¡

¢ ¢

¢ g ¢

¢ s

4 $ £

3 F

§ ¨¥

¢

¡

¢

¢

s

4 $ £ @

¢ @

s

4 $ £

§ ¥£ ¢P(4 $ 1

) ¢ $ £ X
¢

@ ¥ £ 4 ¥ £ ) ¤¢P(9¦1DC $

§ ¥

¢

¡

¢

¤ § 7 7

¢ ¢

¢ ¢

@ T

¥ ¨

§ ¨¥

¢

¡

¢

Exercise 13.12 Plot the log magnitude and the phase angle, both as functions of frequency (on a logarithmic scale), of the complex quantity.

£ ¡

s
¢
¡

s s

¢

£
¡ ¡

§ §

¡

£ ¡

¡

C D ¢ C§ ¥ © § C § D D ¢ C ¥ © §
¥

D

©¥£ § ¡
¢

¡

¥

@ ¡ @ ¥
£
¢

¦¥£ 2¡ §
¢

£

s

§

@ ¡ s

¦¥£ § ¡
¢

© §

¡
¡

0) ¥ 7 ) @

E§

T ( S@ §

¢
431

¢

@

s ©¥£ § ¡
¢

ANS:: (a)

For

and

Henry,

, (b)

s

¢ C§

D

§ ©

D

¥

¥

, (c)

, (d)

¥

¢

s

¢ C§

D¥ ©

*MAGNITUDE:

¥ 7 © ¥ 7 ©

§ )¢ ¥

¢

¡ ¢
Solution:

¥

Or in decibels,

¦ F0 3

X

2§%¢ ¥ ¢ ¡ ¢ § ¢ ¥ ¢ ¡ ¢

D

¢

@

s s

D

As
¢

*PHASE ANGLE:

Label all signiﬁcant asymptotes, slopes and break points.

,

©¥£ ©¥£
¢

¥

2 6

@

£ ¡ ( P

©

§ ¦¤ ¥£¡ g £

© §

¥

¨ ©§¦¤

¥
¡

( §
¢

¥
£

¡

()
¢

@ ¡ s

£ ©¥¤§ ¡
¢

C C

u u ws

¥

¢
¡

§

u

¥
¡

¥ ¦

§

!7

¤ @ ¥ C

¥ ¨

§

¤ s

¥ C@ ¥
s

s

C

§

£ ((( 4

¨¦ ©¤

¥ ( 4 £

¨¦ ©¤ s ¡

¥£¡ ¦¤) § ¦£ ¡ ¥

S` u

¥

¢

¡

£ 02§
7

¡

£
§

) A E § I¤1 ¢ES@

X

§ ¢¥

¢

¡ ¢

§ ¢¥
@

¢

¡ ¢
¢

s

§ ¥

¢

¡

¡

¢ s ¥

g

¥ #¡
@

¥

g

¥

¢

¡

¢

g ¢

432

As

,

¥ (
@

§ ¥¥

2 H¡

§ ¨¥

¡

¢

ANS:: phase angle:

Exercise 13.13 In the network shown in Figure 13.13,

¢ s

4 $ £

3

@
¡

§ ¥

¢

¡

¢

E§
¢

b) a)

b) Given voltage,

a) Determine the magnitude and phase of

As

Solution:

, the cutoff frequency,

, .

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

, magnitude:

vi(t)

+ -

Figure 13.13:

C1

, determine the sinusoidal steady state output

vo(t)

R

, the transfer function relating , or in decibels,

+ C2 -

,

.

¢

7 @s @ ¥ 7 @ ¥ s #¡ @

¢

¦¥£ s ¢

@ (`

$ §

¡ and s

@¡ 7 7
¢

s 77 @7 @ ¥ 7¥7 @ ¥ 7 @ ¢

§ %¢ ¥

¢

¡ ¢ where s

£ W¢
¡

¡

¥

¢

¡

¢
§

7 @%¤¢ ! ¥ ¢ 7 %§¢ ! @ ¢

@ § 7

T & 0(2§ 7 @ in the sinusoidal steady state for the circuit in Figure 13.14.

s

@

T( § ¥£ ¦¤¡ 7
@

u u ws

¥¥
£
¡

a

C¦¦¤ C

£ ¡ (0 ) )
¥

@

£ ¡ () )

¨ ©§¦¤ 7 s 7
¢

§ ¥£¡ R¦¤

¥

@ ¡ s

©¥£ § ¡
¢

s e

¡s ¢ s

§

¥

¥

( a

@

£ ¡ (( )P)

¨¦ ©¤

a 00

¥ ¥ 6 @ %()P¡ 2 £

¥

¨¦ ©¤
£
¡

©

§ ¦¤¡ ¥£

¥

¥

a

@

£ ¡ 0( ) )

¨ ©§¦¤

a (0

§ ¥ ¡ ¨¦£ g ¤ ¤

a (0 §
,

(( () §
¢

ANS:: (a)

¢7

Exercise 13.14 Find

¨ ©§¦¤ s u ¤ s wuu 7 ¥ ¥ ¥ 6 2

Solution:

3 cos 4t

+ -

Figure 13.14:

R1

L

R2

, (b)

+ v2 433

)

§

§ © ¢ £ © ¢ C © ¥ ¤ ¢© ¢ C © § © ¢ £ © ¥ © £©
§

§ § ¥ ¥ ¦
¥

C
©

x§ © ¢ £ © ¥ ¢ ¤ x ©C x § © ¢ £ © ¢ C © ¥ © ©

§

¥ H

¥

¥

¥ 7 ¡s

7 ¥

¥

¥

¡ §

¥

¥¥

¥! ¡ ¥ ¡ ! 0¥

7 s

C ¥ C © § ¢ £ © ¢ ¢ £ ¥© © ©C © C © § ¢ £ © ¢ © © © ¢ £ ©¥ §

¥! ¡ ¥ ¡ ! 0¥
b)

s

s

7 3 ¥

¥

¥

¡ 2¥

3 ¥

¥

¥

¥ 7 ¡

3 7

§ ¢

© ¢£ ©

C ¥ C © § ¢ £ © ¢ ¢ £ ¥ © © © © C C © § ¢ £ © ¢ ¢ £
© © © ©

¥©

§

¥ ! %#¡

S`

¥ !¡ #(¥

¥ ! %#¡

S`

¥ !¡ %#

¢

¥ 0 £

¨ ©§¦¤
7
I`

s

§ ¦£ ¡ 7 ¥
¢

¢ $

¥ 0¢ £

©§¦¤ ¨
7
s¢

©

§ %¢ ¥

¢

¡

¢

$ 6§

¡

t§
¢

434

For

,

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

, and

¥

§ ¥£ ¨¦¤¡ 7

Exercise 13.15

b) Write the transfer function

a)

a) Write the transfer function

Solution:

ANS:: (a) ANS::

¥

vI(t)

+ -

Z1

Figure 13.15:

Z2

iA(t)

, (b) . ,

for the circuit in Figure 13.15.

Z3

Z4 +

vO(t)

s

¡

¥ ¡

§
¥

¥ ! ¡ ¥ !¡ %#¥ 7

¡

¥

§ 7 3 ¥

¥

¥ ¥

¡
Solution:

¥ ! ¡ ` ! 0¥ ¥ ¡ !
¡

3

¤ ¥

D §

§ § ¥

¥ ¦

C ¢D

D

¤ ¥

D §

§ § ¥ ¥
¥

¡

¢

s s £ ¥ @ ¥ ! ¡ ! 3 § s £ ¥ ¡ ! 0¥ ! ¥ 7 @ s £ ¥ s @ ¥ ! ¡ § s 7 @ £ ¥ ! ¡ ¥ ! 7 @ ¥ 7! § s £ 7 @ ¨! ¥
¡ ¡

¥ ! ¡

S`

¥ !¡ ¥ ! %#¥ %#¡

S`

¥ !¡ #)

Exercise 13.16 Write the transfer functions ure 13.16.

ANS::

Solution:

vI(t)

+ -

,

¤ §

¢¤

Exercise 13.17 Write the transfer function

¥

¢

C

iS

R1

Y1

Figure 13.17: Figure 13.16:

iA(t)

iA
¤ ¥

Y2 C Y3 L R2

for the circuit in Figure 13.17.

Y4 + vO(t) in the circuit in Fig435

¢¤

436

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

Exercise 13.18 Find

iS(t)

Solution:

Problems
Problem 13.1 For each of the networks shown in Figure 13.19: a) Determine an expression for the indicated complex impedance or transfer function. b) Sketch the magnitude and angle of the indicated quantity as a function of frequency. You may use either linear or log-log coordinates, but it is recommended that you learn to use both kinds of axes. Solution:

s

¢

¤

ANS::

6¥ !s !s ¨! 7 @ ¥ ! 3 6¥ ¥

¡

¡

¡

¡

¡

§

!7

¥ 7!7

¤ s

¡

¡

@¡

¡

¥

¡

§

¡

§

¥

¦¥ `

¤

§

¢

©

© ¤

§

ANS::

§

§

§ § ¥ § ¥ ¦
§
§
¦

in the circuit in Figure 13.18.

R iA(t) C1 L

(let G = 1/R)

C2

Figure 13.18:

437

C2

Z

R

C

Z

R

L

Z

C1

R

Figure 13.19:
S`

b)

i) See Figure 13.20

log |Z|

1 ------RC

ii) See Figure 13.21 iii) See Figure 13.22

¡

Problem 13.2 Shown in Figure 13.23 is one possible circuit model for a transformer, for use where there can be a common ground between primary and secondary. where

7

a) Determine an expression for the sinusoidal steady-state transfer function

T ( § 7 @ ¤T ¢E§

s

@ S

7

s

©

§

2 S( a

2§ 7

Assume:
2a "e

C

C

¤

¡

¡

D

¡

¢s

ANS:: (a) (i)

(ii)

(iii)

¢ s D C C ¤ ¢

D

¡

§

D¢

¡

D §

C

¡

D

C

¤

§

¡

iii)

¢ s D C C ¤ ¢

D

¡

¡

ii)

D¢

D

¡

¢s
¡

a)

i)

D

D § §

§

∠Z

1 ------RC

ω

-45

ω

-90

Figure 13.20:

§ s . .

438

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE
∠Z
90

log |Z|

45

R -L

ω

R -L

ω

Figure 13.21:

∠Z log |Z|
90

1 -----------------C1C2R

ω 1 ---------------C1C2R ω
-90

Figure 13.22:

R1 + vS + v1 -

i1

i2 + v2 R2 + v1 -

i1

L1-M

L2-M + M v2 -

Figure 13.23:

439 b) In the tight-coupling limit, , the two natural frequencies are far apart. (See Problem 12.3 in the previous chapter.) For this speciﬁc case, sketch the magnitude and angle of the transfer function on log-log scales. Solution:
¤
¡

b) See ﬁgures on the following pages.
10
−2

10

−3

 V2/Vs 

10

−4

10

−5

10

0

10

1

¤

¡

C

¦

C ¥C ¢

ANS:: (a)

§ C ¢C ¤ ¢§C ¤ D D¥ ¦

¡

C

D ¤ D § C§

¦

C ¥C ¢

a)

§ C ¢ C ¤ ¢§ C ¤ D D¥ ¦

Figure 13.24:

g 5

¡

D ¤ D § C§

10 log(ω)

2

10

3

10

4

440

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

90

80

70

60

∠ V2/Vs

50

40

30

20

10

0 0 10

10

1

10 log(ω)

2

10

3

10

4

Figure 13.25:

441 Problem 13.3 An electrical system has the transfer function

a) Plot the magnitude of all points. b) Sketch the phase of
¢

in decibels versus the logarithm of frequency, labeling

versus the logarithm of frequency. equal ? What is the relaat these frequencies?

d) List the frequencies at which the phase of Solution: a) See Figure 13.26.

equals 45 degrees.

60

40

20

0 -1 10

100

101

102

103

104

Figure 13.26: b) See Figure 13.27.

d) 1; 10; 100; 1,000; 10,000

7

¡

§

c) The magnitude of

equals

at

. Here,

s §

§ § ¥ ¥

¡

¥

¥

¢

¡

¥

c) For what values of does the magnitude of and tionship between the magnitudes of
¢

¥ t .

¢

X

¥

¥ (0()PH¥ ¢ ¥ ( P¡ ¥ ¢ ¥ ¡ ¡ ¥ ¦(() ¡ ¥ ¢ ¦) ¡ ¥ ) ¥
¢

¥

¢

¡

¥

)E§

¡

¥

¢

¢

¡

¡

X

§ ¥ ¥

¥ ¥

¢

¢

¢

¥

¢

¡

¡

¡
¢

¡

¡

¡

§ ¥

¢

¡

(13.1)

X V

442

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

0 -20 -40 -60 -80 10-1 100 101 102 103 104

t

Figure 13.27: ANS:: (c) at (d)

R

L R1 L1 + V1 -

Vo

+ -

Figure 13.28:

d) Plot

(magnitude and phase) vs. log

for the values of

@

¢

c) Find a value of .

so that the response at high frequencies is equal to response at and found above.

¡

¢

b) Find

so that the

gain is

.

s

a) Find the transfer function

.

s

s

Problem 13.4 Refer to Figure 13.28 for this problem. Assume .

and

§

T ¢

§

(( (( S ( ) @ S`

` ) W

§ ¨¥

¥

) §
¢

¡

¢

X

§ ¨¥

¢

¥

¡

¢

¡

@

¡

¢

) 9)

443 Solution: a) b)

c)

d) See ﬁgure. ANS:: (a) (b) (c)

Problem 13.5 This problem examines the simple door-bell circuit commonly used in homes (Figure 13.29).

I1 + + V1 -

M

I2

Push-button switch + V2 Door bell +

I1

L1-M

V1 -

Power line Bell transformer 120 V AC, 60 Hz
Figure 13.29: Data for the transformer in Figure 13.29 is given below: , where

Circuit model for bell transformer

.

a) In the limit , what is the voltage with the push-button switch not pressed (open)? You should use root-mean-square amplitudes for all quantities. The voltage source is given as root-mean-square. b) The door bell operates by repetitive making and breaking of a contact and can normally be modeled as a resistance at . Determine the magnitude of the root-mean-square primary current under normal door bell operation (push button closed, door bell = ) in the limit of .

) 9(

§

¡ (&

T H § @

7

7

s

s

§ § ¢ ¤ § ¥ ¢¢ ¤ D D ¢ ¤ D ¥

©

§

T (

¡

¡

§ § ¢ ¤ § ¥ ¢¢ ¤ D D ¢ ¤ D ¥ S0

T ()

2 9 a

¡

¡

§ ¨¥

§ 7

¢

¡

T H § @
) 9(

§ ¥

2a "e

¢

¡ § §

s

L2-M

I2 +

M

V2 -

444

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

c) An important safety issue in such circuits is the prevention of ﬁre in the event that the door bell should accidently stick with its contact closed, thus becoming equal to a short circuit. This can be accomplished by adjusting the value of . Find the value of that will limit the root-mean-square primary current to for the case where the push button is pressed and the door bell acts like a short circuit. Solution: a) is approximately
2 S a ) ¤ 9(02 2 S £

b) See Figure 13.30.

I1 + -

Z1 60j(L1-M)

I2 Z3 Im 60j(L2-M) Z2 60jM 10Ω

V1

Figure 13.30: ¡0¦¥ &

©

¥ S

) ¥ 7

s

s ((& § s ¢ ¢ ¥ 7 9 (#F (((U¦() 2 a ¡ & V ¥

1 £

@

X X

s

((&

¡(&

¡ ¡(& ¥

§

¥

1 £

X X

§

¥ S
2a "e s

(V

¡((&

@

§

s

s

s s

s

¡ §

)6¥ 7 ¡(& )6¥ (& @ 7

)6¥ 7 ¡0& § ¥ 7 s (0(V @ 2 ((0V & 7 &

§

1

£

X

X

§

¦

1

£

X

X

¥

§

¦

s

¤

§ 7

s ¡((& § ¥ () ¥ 7 (&

& ¡0#¡

§ s

§

.

445

I1 + -

Z1 Im Z2

Z3

I2

V1

10Ω

Figure 13.31: c) See Figure 13.31.

ANS:: (a) 12 (b)

(c)

Problem 13.6 In the circuit in Figure 13.32, the switch has been in Position (1) for a long time. At , the switch is moved instantly to Position (2). For the particular parameter values of this circuit, the complete output waveform for all time greater than zero is

(1) + Vo (2)

C + - v(t)=V1cos (ωt )

Figure 13.32:

¡

s

a) Find

and

in terms of

and

.

¥

¥ £ ¢) ¡

¨ ©§¦¤ ¢

¥¥

8@ ¢

s

¢

§ ¦¤¡ ¥£

§

§s

C ¥

¤

¤ ud

Therefore we have

, and

. Finally,

R + Vc(t) -

¥¥

s

§

(& ¥
@

@

s

7 0¡

¡0&

@

s

7

¥

(&

§ u¥7¢s

@

¡(¦¥ &

§

s

7

(&

¡((& (& @ 7

2a

@

§

s

7 H(&

& ¡0#¡

§

u

¥7

§
¢

.

§

¢ ¢

2§ £

(13.2)

§ 9

¥
¡

@ ¢ '¢ ¡

¥ ©£ ¤ ¡¥
@

§

§ ¢

¢

§
@

¥
¡

¥ ©£ ¤ ¥

§ § ¢

¢

¥£ ¦¤¡

@

¢ "¢

¢

446

b) Find

in terms of

CHAPTER 13. SSS: IMPEDANCE AND FREQUENCY RESPONSE

and

¡

a)

@ ¢ '¢ ¡ ¡ C § D ¥ ¢ s © ¤

b)

C § D ¥ ¤

ANS:: (a)

Solution:

required to produce the

(b)

C § D ¥ ¤

¢s

C § D ¥ ¤

¢s
©

¢s

waveform.

Chapter 14 SSS: Resonance
Exercises
Exercise 14.1 a) For the circuit in Figure 14.1, assume a sinusoidal steady state at a ﬁxed frequency . Determine an equivalent circuit for the parallel combination ( ) in terms of a resistor in series with a suitable inductance .

L’ Z

Z L R

R’

Z2

Z1
Figure 14.1:

Z2

Z1

b) Determine the impedance that must be added in series with such that the total impedance is equivalent to a pure resistance at frequency . What is this value of this resistance? Solution: a) s u
¢

447

s

¤ @ ¥¤

¤

¥

@ @

§

@ ¥ ! @ )!

¥

¤

7

@

u

¢

¡

$

§ (` !

4 ¥ X I9(0(&

§

§
¢

©

7
¢

s

¢

s

¢

@

7

¢

§

¢

7

¢

s

¢

¢

£

V ` 9W§

` W§

¤T W

§ S@
¡

C§

C ¥ C ¢ DC

D §

7 ¢7 @ § 7¥ ¢¡ ¥ 7 @
¡

7 @ ¥ 7¥ @7 7
¢

7 @ ¥ 7¥ 7 @
¢

¢

448

:

7 @ ¥ 7¥ ¢ ¡ 7 @ ¥ 7 ¢ @7

Exercise 14.2 For a parallel RLC network with and . ( and

C § D ¢C C C ¥ D §

¤
@

C § D ¢ CC D

¥
§

¤

¡

¢
¡

§ §

¤
@

¤

§

¤

@ ¥

¢

¤

b) Add the capacitor in series with

§

@ ¥
¢

¢

@

ANS:: (a)

Equating real and imaginary parts above,

, (b)

CHAPTER 14. SSS: RESONANCE

, ﬁnd are the half-power frequencies.)

¡

Solution:

( H ( jω ) )

ω1 ωρ ω2

Figure 14.2:

2α ω ρ = ω 0.707 log ω u

u u ¢

¢

§
¢

! E §

7 8) ¤ a

§

¥

¢

¡

¡

Exercise 14.3 A parallel resonant RLC circuit (Figure 14.3) driven by a current source, 0.2 cos , (units of amperes) shows a maximum voltage response amplitude of at rad/sec. and at 2200 rad/sec. Find and .

H(

8@

H(

S§

©

§

¢

2 S a

§

a S e¢

§ 7

¢

a 2 H¡(§

¢

V St§ 2 SH a

§ R

7

! (`

4 ¥ X 9SI

& § ! 0`

¥ ¨

¨ 3
¢

§

¢

4 ¥ V X I9((0t§

¢

! (` ! (`

4 ¥ X 9SI 4 ¥ X IS9

& 0¢ §

¥
@

¢ ¢ @
©

§ 7
¢

&

B§

§
¢

s
¢

! (` 7

4 ¥ X 9I @
¡

(

(2
¢

§
©

7
¢

§ 7

¢

§ ! (`

@

§

¢ g § ¡

4 ¥ 2 X 9900¢§

§

@ §

¡ a

2 IH

ANS:: rad/sec

i(t)

R

Figure 14.3:

rad/sec

L

rad/sec

+

-

C v(t)

rad/sec

s

rad/sec

For this circuit,

3

¢

Solution:

£

2 (0SS§
¢

¢

a H &

449

s

@

§ !

@

Exercise 14.4 Find an expression for the value of that will balance the bridge (Figure 14.4) to make , for an input voltage cos .

£

¢

£& 0

a
¢

& §
¡

) V I¢ a 9

§

T ¤((

§ S@

A F£a IS§ ) ¢ V

¡

2 7 ¥ (0S#¡ §

§ 7
¢
¡

£& 0
@

2 ¢ 9£a

& 2§

¡

¢

¢
¡ ¡ ¡ ¡ ¡

¡

¡

¥ d b S a
¡

¡

¥ 7
¡

7

¡

s S
¡ ¡ ¡

¥

¡

¡

¡

u wu wu 7 u

7

¥ 7!
¡ ¡ ¡

u wu

77
¥

¥ ¤ ¥

§
¡ ¡ ¡

` e¡ S

` e¡ S

§

D

§ H(t§ T ((

§ S@ @ g ¢ ¥
¢

H(

§ @ 23 ¢ ¢ §
¡

450

Peak response occurs at

7¢s
CHAPTER 14. SSS: RESONANCE

¢

§ 9
¢

and at this ,

ANS::

Therefore,

We need to meet the following condition:

§ 7

@

s

Solution:

Vcos (ωt) + -

Figure 14.4:

R L v1

C R v2

¢ ¢

¢

¡

¢

451
¡

Exercise 14.5 One or two of the following statements made about the second-order RLC network in Figure 14.5 is/are inconsistent with the rest. Circle the inconsistent statement(s).

c) The admittance function

¡ ¢

)

¥ ¥7

¢

@ & ¤£)P¡ ` ¢

§ " ¨¥

¢ ¡ 9`

¥

¢

¡ ¨¥ §

¢

¡

b)

s

a) The natural frequencies (see Figure 14.6).

and

x -5

x

7!

!

¡

SE§ a

ANS::

i(t) + RLC network

vS

Figure 14.5: of this circuit are as shown in the complex plane

Figure 14.6:

3 7 @ §

7 2§ @

jω

j12

σ j12

452

CHAPTER 14. SSS: RESONANCE

d) The step response for

cos

cos
¡

Solution: (b) is inconsistent with the other statements.
V S§ a

actually.

Exercise 14.6 Consider the network shown in Figure 14.7.

iI(t) vI(t) + iC(t) 1Ω 1F iL(t)

Figure 14.7:

c) Assume that the capacitor voltage and the inductor current are both zero for Determine for when is a unit step. Solution:

£

¥£¡ ¦¤%

£

¥£ ¦¤¡ 1

b) With

as determined in part a), what is the value of

? .

a) Show that by proper choice of the value of , the impedance made independent of . What value of satisﬁes this condition?
¥

¥! #¡

§

§ § ¥ ¥

¥

ANS:: (b) is inconsistent with the other statements,

V S a

©

¢

¥

§

V SE§ a

¥ %S ¡ £ 2

@

§ 7 s !

¥(20¡ V W

e) The steady state response to

cos

¥ ¢ ¥ % ¡ £ is of the form: actually

¡ ¢

£2 S

¥

£ ¤ g

§

§ ¥£ ¨¦¤¡

§ ¦£ ¡ 1 ¥

¢

7

§ ¦¤¡ 1 ¥£
©

¢

§

¥ 7

§ 7

£ !

is of the form: (14.1)

(14.2)

¢

1Ω L

can be

453 a)

c)

Exercise 14.7 Each of the following parts makes a statement about a second-order system. Indicate whether the statement is true or false. a) The network shown in Figure 14.8 (with both natural responses of the form sin .

R1 + -

R2 +

vI(t)

C1

C2

Figure 14.8: b) The natural response of a RLC network is given by:

The

of the network is 1.2.

c) For the circuit shown in Figure 14.9, the output voltage under sinusoidal steady state conditions is zero.

¥ (¢ ` $ %)PI0 ¥ ¥ £ ¡ !

£ 2 99S§

¡

¥£¡ ¦¤¨¨

@

£

¢

£

¡

ANS:: (a)

if

, (b)

, (c)

’s and

’s positive) can exhibit

vO(t) -

D

¢ £

sD

§ ¦¤¡ 1 ¥£

@ §

§

§ S@

D

¢ £

§

sD

§ ¦¤¨01 ¥£¡

b)

¡

if

¡

Choose

to accomplish this. .

¡

We need

for

to be independent of .

!
.

¥7!

¡

3 ! ¥
¡

6¢¥ ! 0 ¥ 7 ! @ ¢ 6¥ ! ¢ D C D ¥ 7 !

¥¨ ¥ ! I! @ ¡ ¥ #H ¨! @ ¡ @¡ ¥ ¥

!

¡

¡

¡

¡

§

! ¥ %!
¡ ¡

@

¥ @ ¥ @ ¡

¥ ! ¡

§ ! ¡ ¥

¥
¥

s s

¥ @ ¥ #¡ @

@ 0 §

§ § S@ 7 @ § DC D

§

¢

@ §

E§

454

CHAPTER 14. SSS: RESONANCE
+ t I S cos  -----------  LC L R C Figure 14.9:

vO(t)

iS(t)

R

L1 C L2

Figure 14.10: d) The circuit shown in Figure 14.10 contains 3 energy storage elements and thus has 3 natural frequencies. Solution: a) False. The roots are purely real and negative from the characteristic equation. b) False. So,
V W

c) True.

.

Thus the system is second order and cannot have 3 natural frequencies.

7

7

¥ s

s

d) False. value

and

are in series, so their combination is equivalent to one inductor of

)¢ ¥ §

¡

So at

6¥ ! @ ¥ 7 ! ¥ ¥ 7 ! 5@ ¡

,

¡

¡

¡

©

¢

¡ ¢

§ !

§

§ ¥ ¨! ¡

§ 7

aS§ V S § a © ¥ 7 ¢ © §

and

2

§

E§

7

¢

§

©

¢

455

5 Slope = +1 Vo ----- ( jω ) Vi (log scale) 1
Figure 14.11: ANS:: (a) False (roots are real and negative), (b) False (Q = 1.3), (c) True (at ), (d) False. (system is second order)

1 Slope = -1 Slope = -2 ω rad/s (log scale)

10

Exercise 14.8 The voltage transfer ratio of a certain network is shown in Figure 14.11 in Bode-plot form. This transfer ratio can be expressed in the form

(14.3)

Solution: The pole at At

; it is the resonant peak frequency. is due to so that

,

7¥

is the ratio of the resonant peak to the asymptotic intersection,
¢

2 t§

¢

¤ 2¨ ¡ ¥

3 7¥

¡ ¥ 7¥7

2 a H( SE§

© §¢ ¨! ¤ ¢ ¥ ¥ )2¥ ! ¤ ¡

¢

@

7 ¢¡

u

Determine the parameters

, and .

factor in the denominator. . .

§ !

¥ ¥ ! ¤ H¥ 7 ¡

u

¢

!

¥

`

¤

u

¢ £!

¥ 7 !¡

¢

§

§ G2 ¢ G ¡ ¢ § ¥ 3

¥ ! ¡ ¥ ! ¡

E§ ¤ ) §

§ 2¢ ¥
¢

! (`

¢

4 ¥ X 9¦

` ) ¢§ )E§ ¢

¢

¡ ¢ §

¤

¢

9
¢

¡

456

CHAPTER 14. SSS: RESONANCE
, , ,

ANS::

Exercise 14.9

R + vi + C L Figure 14.12:

vo

Solution: a)

ANS:: (a)

, (b)

Exercise 14.10 The impedance of the network shown in Figure 14.13 is found to be and is purely real at all frequencies. The value of the inductor is one as shown. What are the values of and ? Solution:

In order for

to always be purely real,
¡

T S

¨! 0 ¥ 7 ! ¥ @ ¥ ! 6¥ ¦¥ @ ¥ D ¡ ¥ 7 !

)

¡

¡

§ ¦¤) ¥£¡

@ 0 §

¡

¡

¡ 5@

¢

¡

§

@ ¥

¥ %!

¥ ! ¡

! ¥ s ¥ 0 @ ¥ @ ¡ ¥ s ¥ #¡ @

C s C S ¢ s D ¢ 9 ¢

@

¡

§ ! ¡ ¥

§

@

¢

b) At

,

.

¥! #¡

F3

7!

¡

7!

¡

¥ ! @ ¨ ¥ ¥ ¨

¡

¢

§ ! ¡ ¥

u

b) Find

at the frequency

.

§

a) In the circuit in Figure 14.12, ﬁnd an expression for the complex amplitude a function of after transients have died out, assuming is a sinusoid: cos .

` ) W § as ¤

! (`
9s

4 ¥ X 9q§ ¢

§

¢

¥£ 2§ ¦¤¡

2

§

2 a H0 SE§ Ss

¥£¡ ¦¤)

£

§

¢

¢

457

+ Z(jω) C Figure 14.13:

R

R 1 mH

Then independent of .

Problems
Problem 14.1 For the series-resonant circuit in Figure 14.14, draw the impedance model, . Sketch the Bode plot of log magnitude and phase and ﬁnd the transfer function of this function versus log frequency by sketching the asymptotes, then sketching the function. This is a second-order low-pass ﬁlter. For this topology, the maximum amplitude does not occur at the resonant frequency (prove this, but don’t work out all the math). However, this is a small effect for all but very low . Find expressions for the resonant frequency (deﬁned as the frequency where the and the terms cancel in the denominator) and the . Solution: Impedance Model (Figure 14.15): Transfer Function:

Sy `

¡

ANS::

and

Farads

!

4 ¥ X IH4

§ 0(0S2@ §
¡

7 (00 § ( a

¡

u s

7 @ §

) 3

u s

2a "eS§

) 3

2a "e

¡

§

§ ((02S@

u

¢

!

7!

u

¢

458

CHAPTER 14. SSS: RESONANCE
R L + C vO(t) Figure 14.14:

vI(t)

+ -

R VI + -

Ls 1 ----Cs

+ Vo -

Figure 14.15:

Bode Plot:

See Figure 14.16 for plot.

§

¡

7¡

© ¥

@"

¡

@ I

@

§

§

¡

¡

¡

¡

¢

¨

¢

u

at

:

7¡

¡

@

¡

¢

¢

¥ ¥ ¥

¡

¡

7

@ I

¢

@

@

¡

§

u

Check if max amplitude occurs at

:

¡

Resonant Frequency:

¡

@

¢

¥ ¥

¡

7
¢

@

¡ ¥
¡

§

¡

7

¨! ¥
¢

@

¢

¡

@ T

¡

©

¡

©

s

@ ¥ 7!

©¥£
§ ¨ §
¢

u

¢

¢

@

¡

¢

¢ ¨

§

§

s
¢

¥ @ ¥ !

s

§

¨

¢

459

VO log -----VI

ω≈1

0
1 ω ≈ – -------------2 ω LC

log ( ω 0 )

log ( ω )

ϕ

0
–π ----2 –π

log ( ω 0 )
Figure 14.16:

log ( ω )

460 u CHAPTER 14. SSS: RESONANCE
¢

So,

not maximum amplitude.

Problem 14.2 Consider the circuit in Figure 14.17.

i(t)

R

L

Figure 14.17:

c) Comment on the results of part a) and part b). Solution: Find

:
¢

Bode Plot: see Figure 14.18

7

¢

¥ 7¥7

¢

¢

§

@

¡

u

¢

§ ¢ ¥ ¢ ¡ ¢

¡

a)

,

,

¥ ¥

¡

@

¢

7

¢

@ ¡ TP5@

7 7

¢

¡

¥ 7¥

§

@ ¥ !

b) Draw the Bode plot of frequency?

for

§

§

¡

¡

S

¡

@

7

¢

¢

!

§

a) Draw the Bode plot of

for

E§

§

@

¥ 7!

@

@

¡7 @

§ @

¢

¡

¢ ¥ ¡ ¢ ¡

@

¢ Fr¡ ¢ ¥ ¡

u

§ %¢ ¥ ¢ ¡ ¢

§

s

D

¥ s D ¨! ¥

¡

E§

¥
¡

§

s

§ ¨¥ ¢ ¡

¢ ¥ ¢¡ ¢

¢

§ @

ANS::

,

,

C

+ v(t) . What is the resonant frequency? . What is the resonant

¡

sD

@

§

§

Ss

@

¢

§ §

¢

¢ § s S C

§ §

461 log Z ( ω ) Z ( ω0 ) = 1

0

Z (ω) ≈ ω

1 Z ( ω ) ≈ ---ω

-1

0

log ( ω )

Figure 14.18:

log Z ( ω )

Z ( ω0 ) = 1

0

Z ( ω ) ≈ 2ω

-1

log ( ω 0 ) 0
Figure 14.19:

Bode Plot: see Figure 14.19 c) The resonant frequency drops from 1 to . As a result, the Bode plot for shifts to the left by an amount .

¢ ¥ ¢¡ ¢

7
1 Z ( ω ) ≈ -------2ω log ( ω )

¢ U¥

7¥7

¢

¢

@ TP¡

§

s

7

u

¢

7 ¥ ¢¡ ¢¤E s &

§ %¢ ¥ ¢ ¡ ¢

¡

b)

,

,

2§ just §

§ @

462

CHAPTER 14. SSS: RESONANCE

R Vin + -

sL 1 sC

+ Vo -

Figure 14.20:

a) Compute the transfer function

.

b) Set between s ©

. What is the equivalent complex impedance of the circuit evaluated and ground?

c) Parts a) and b) might lead you to believe that Th´ venin’s Theorem also applies to e and complex impedances. If this is true then we can replace the circuit between ground by a complex Th´ venin impedance ( ) and a complex open circuit voltage e ( ). Taking compute and . d) Having represented the circuit by its Th´ venin’s equivalent we wish to connect it to e another circuit having as shown in Figure 14.21.

Vo Zth + Voc 1 sC sL R Vin2 + -

Figure 14.21: 1) Are there any problems with this approach? If so state them explicitly. 2) Compute the complex

for this circuit.

s ©

Problem 14.3 The circuit shown in Figure 14.20 has an input voltage cos , and a T ¤002

§

¥£ ¦¤¡

¥ ! ¡

s © S`

¥ !¡ %#

£ ! § ¥£ %(00 () ¨¦¤¡ 7

§ 2@

§ ¥ ¨! ¡

Q

£ $ ! § ¥ Q%0(0 () 9¦£ ¡

£(

§

7
¡

©

u

) 9(2

s ©

§

§ ¥ 29¦£ ¡

u

ANS:: (a)

, (b)

s

§

¢

§

¢

£ $ Q0)

s

§
§
¡

§

¥¤ ¥¤
¢

¡

£ S& a V
¡

7 7 d¤ s ¥
¡

§

$ §
¢

@

¢

@

¡ §

§ ¥ 7 ¥ @
¢
¡

§ ws ¥ ¤ u ¢ u 7 s s ¥ § s ws u

£ V a S9 (2§

¥¤
¤ !
¡

¡

§
@ T

§ u 7 s¥ ¥
¥ 7¥

¡

£I a £ S)
¡

7

¡

7 @7 d C d F¥

¢
!

7
¢

¡

§
@

¤

§ ¥ ! ¡ §

¡

£ 9) u 7s¥
¡

¡

¢

¥ ¥

7

¢

@ T

¡ §

s © F3

§ ¡

£ u 7 s ¥ 9)
¡

¥£ $ ¦Q0 ¡ @
¢

¡

¨ ¤ ¦
§

)§ ¦¤¡ ¥£ ¡

¢

@ TP¡

¡

¡

¥ ¥ 7 ¥ @
¢

§

¥¨! @ ¥ 7 ! ! @ ¥

§

!
¡

¥ s¢ D

¡

@

¢

¥ ¥

¡

¥ ¡ ¦£ )¡

£ $ ! § ¥ Q(0 ()E9¦£ ¡ 7 © § ¦£ ¡ ¥ £ 0(H( § 7 © 2§ s © $ !

4) If

s ©

a)

7
¢

@ TP¡

§

¨! ¥
¡

@ ¥ 7!
¡

§ ¥ ¨! ¡

b) See Figure 14.22

c)

s ©

Solution:

for

3) Now let

:

sws u £ a 9 § ws s ¥ IH s ¥ £2
¡

R

Figure 14.22:

LS compute the real output voltage . Evaluate for this case. . 463

1 ----Cs

Req

464

CHAPTER 14. SSS: RESONANCE

Problem 14.4

Z1

R1

L

C

Z2

R2 L

Figure 14.23: s s

to

?

equivalent circuit for the series combination (as in c) Make a parallel Exercise 14.1) and use this equivalent circuit to calculate what the ratio of and in part b should be for in both circuits. How large is the discrepancy, if any? d) Using the values for and found in part b), make plots of and versus frequency and and versus frequency. Identify the following features of your plot:
s

i) The maximum impedance, the frequency phase angle at .

at which this occurs, and the

e) Now suppose that you have just been given a “parallel resonant” circuit , but you don’t know whether it is of the form or the form. Suggest a step-bystep experimental procedure based on measurements of and perhaps as a function of frequency to determine i) which of the two forms of parallel resonant circuit is the best model, and
¡

Solution:

ii) speciﬁc values for the three elements,

.

¥

s

¢

@

7 ¢¡

¢

`

¢

§ 7

¢ ¢

7

8@

s

7

¢

7

s

ii) The frequencies and and the phase angles at
¢

at which is smaller than the maximum, and . Calculate the quantity .

@

¢ 7 ¢

¢s ¢

7 @

© ¢ `

@

¢

¢ ¢

) §

7 @

¢

s

7 @

7

¢

s

¤@ ¤

s

¢

s

@

¡

¢

@

b) Assume What is the ratio of
@

. Find values of

and

that will yield

) §

s

7 @

@

£ )

s

§

©

s

¢

) ¦§

a) Determine

for each of the circuits in Figure 14.23 (

` 0y

¢

§

D

¡

¥ s

D

¡

¢

q ¢

§ 7 7 ¥ ¤ ¥ s d s

ANS:: (a)
¡

(b)

(c)

§ ws ¥ ¤ u ¢ u 7 s s ¥
¡

£ V a 9S e

§

¢ § 9 C ¢D
¡

§

¢ § s S C

,

£ V 9& a £t§

7 @

).

C

.

¡

© § §

u
¢

@

§ 7

¢
¡

¥ ¨! ¥ 7 !

1
¡

¤

¤¤

1

¥ 1

1 1 1

¤

@ ¥ 1

@ ¥ 1 @
@
¡

¤¤

§ §

¤

§ E

¤

1
¥

u
¢

¡

u

¢
©

s

@ 7

§
¡

¡

@

@ 2§
¡

@ § 7

¢

§ u @

§ §
¢

7 @

¡

7

u
¢

¡

© § @ 0

u
¢

§
¡

¡

§
¡

¥ !

@

¥ 7!

§ 7

¢

¥ ¨! ¥ 7 ! ¡

¡

¥

¡

¥

@ ¤ ¥ ¤¤

@ ¤ ¥ ¤ ¤ § ¦¥£ ¡ ¤ 1 ¤ ¤ @ ¥ ¤¤ § 1 ¥
¥

¡

§ ¦¤¡ 1 ¥£

¤

1
¥

@

a)

1) First circuit:

¤

¡

§ ¦¤¡ 1 ¥£

General form:

u

2) Second Circuit:

¤

§ ¥ 9¦£ ¡ 1

¤

Find

:

¤ 1

Substitute:

¤

¥ 1 ¥ 2§ ¦¤¡ 1 1 ¥£ @ @ ¥ 1 § ¦¤¡ 1 ¥£
¡

¤¤

¡

General form:

u

, so: , so:

465

¤

7 @

¤

7
¢

7 @ §

¤
7 7
¢

¤

§

@ 7 9¢
¢

¤

@

§

¢

§

¤

7 @

¤ ¤

7¤

@ ¥ 7
¢

¥

¤

7

¢

¤ @ 7¤

7
¢

¤ ¤ ¤ ¤

¤

s

¡

¥ sD

§

¤

¢

@ ¥ ¢ § § @ ¢ ¥ 7 @ §

C
¤

() § s D @ D

T (()

§

@

)
¡

§

7 @

@ § 7

u

@
¢
¡

§ u

¢
©

§
¢

s

7 @

@

§

466

b) From part (a), the values of . The ratio is then:

and

that yield

CHAPTER 14. SSS: RESONANCE

are:

s

s

c) See Figure 14.24

We want

, so:

7¤ @ ¥ 7¤ 7¤ @¤ 7¤ @ ¥ 7¤ ¤ @ 7¤ 7

§ 7 @

Substituting:

7 ¢ § 7 7 9¢ ¥ 7 @ 7 CC C C D ¥ 7 7 7 7 ¢ ¥ 77 @ § ¤ C 7 9¢ 7 @ ¥ ¤ DC ¡ 7 7 ¢

¤

¤

¤

¢

§ 7 @

L

R

Figure 14.24: .

R’

L’ and T )§ 7 @

467

Z 1(ω)

100Ω

maximum impedance

ω

1

= 9512.5

ω

2

= 10512.5

ω r = 10

4

∠Z 1 90 45 0 -45 -90

ω

1

ωr

ω

2

Figure 14.25: d) See Figure 14.25 for plots.

¤

C

D

and . The ratio is unchanged at discrepancy from part (b). s ()

§

D

7 @

u

¢

¤

¤

§

u

@

7 @

¢

7

u

§

¢

¢

s

§

s

T )

§ 7 @

s

T (()

Find new

:

7 7
, so there is no ω ω

7 @

¢

§ 7 ¥ 7 @

¤
@

§

@

C
¤

©

() §
@ s S

sD

§ § u C

s @ S

§

¢

¦

D
©

D7
§

D

§ ¥

s

§
@

¢

9s
¢

¢

sD

§

u
¢

¦

¢ ¢

u u

§
¢

¡

¢

§ (

¥ ©£

¦D

§

§ §
¢ ¢

¢ ¢

¥ !

¥ ¡4¢ § @

D u §
¢

9s 9s

¡

7

¢

¥ (

¢

§

¢

¢

¢ 7 ¤ ¥ ) @ s ¦¥£
¢
¢

@

¥
¢

¥ P¡ ©¥£ s ¢

§ 7

¢

7

u ¢ s

@ f

¡
¢ ¡ ¡

) ¥ 7 ¥ 7 ¢ ¤ ) 7 ¢ d ) ¥

§ ¢ 7 ¢

!

¤

£
¡

7
¡

77 @ 7
¢

¡

¢

@ TP¡

§ d CC ¥ ¡ § d ¥
¤ !

!

£
¡

7 7
¢

¥ 7¥ 7 7 ¥ 7 @ ¡

¥ ¥ ¤ ¡
¡

§

¡

7 @

¢

¢

@

¡ §

¢

¥

C s¢
¡

D

¢

¥ ¥ 7 ¥ 7 @

§ 7

©

¢

©

§

¢ ¢

§

s

¥7
¢

¤

)

@ f
¢ ¢

¡ ¥ ) )
@

s

£ ©¥¤§
¢

¥7 7
¢ d

¤

¥ 3 ) ¡ () ©¥£
@ f s
¢

§ )

¢

7

¥ 7¥7

) ¡

¥ 7¥7
¢

) s @ fP¡

¢

¥

¥
!

¤

§

s

§ 7 7

¢ £ a
¡

§ ¢

¢

¢

¥ 7¥ s

7
¢ ¢

@ fP¡

7 @

§
!

£
¡

§ d C ! ¤ ¢ ¤ ¥

¥¤ ¡
¡

@

s

§

¤ ¤

¢

!

7
¢

¥ 7¥

7
¢

@ TP¡

¡

7 @ §
¤ ¥ sD

¡

s

§ d C

¡

¢

¥ ¥ s 7
¢

@ TP¡

@ §

s

¥ ¥ ¤ ¡ £ C7 §

£
¡

¡

¥

s

@

¢
¡

@

¢

¢

¥ s

s

§

468

e)

See Figure 14.26 for plots.

i) Measure close to . If , then is the best model.

CHAPTER 14. SSS: RESONANCE

, then

s

ii) Measure , , : if : if :

to ﬁnd

and

S

ANS:: (a) (i)

, ,

,

, ,

, then solve the resulting system of equations for

,

,

is the best model, if

(ii)

C ()E§ ¤ D C CD D s 7D

7

s

@

¢

,

,

(b)

D

s

C

Ss
¢

§

u
¢

(c)

,

469
Z 2(ω)

100.5Ω

maximum impedance

1Ω

ω

1

= 9512.5

ω

2

= 10512.5

ω ω r = 10 4

∠Z 2 90

39 0 -5.7 -50.4 -90

ω

1

ωr

ω

ω
2

Figure 14.26:

iI(t)

R

C +

vI(t)

+ -

L -

vO(t)

Figure 14.27:

¡

¡

¡

©

7

7 @ ¥ 7¥
¡ ¡

@ TP¡

@

§

¢
¡

@ T
¤

s $ 4£
!

¥ £

¨ ©§¦¤
7
¡

§ ¦¤¡ 1 ¥£

7 @ ¥ 7¥
¡

@ TP¡

§§ §
!

£
¡

d ! d ¢¥

¥¤
£
¡

© ¥
¡

C

¢¥
£
¡

§ ¦¤¡ 1 ¥£
¡

¡

7
£
¡

7 @ ¥ 7¥

@ TP¡

d ! d ¢¥

¤ ¥¤ ¡

¡

@ ¥ ¥
£ 6
¡

@

¡ §

§

C

§

¡

¥
¡

¥

¡

¥ @
¡

§ ¦¤¡ 1 ¥£

s £
¡

¥

¥ @ §

¢

§ 6¥ !
¡

£ § t¨£ ¢
¡

¨¦ ©¤
§

@ ¥ 7!
¡ ¡

7!

§

!

¥ s @ ¥

!

§

¥ !¡ %# ¥ !¡ %#¨¨

¡

1

§ ¦¤¡ ¥£

¤

¡

1

¥ ¤1 ¥ 1 @ ¤¤ ¥ ¤ 1 @ ¥ ¤¤ 1
¡

§ ¥£ ¨¦¤¡

¤

Problem 14.5

470

d) Plot the roots of the characteristic polynomial (from part b) on the complex s-plane (Assume .)

¡

7

¡

7 @

E§
¢

£ £0 2§ ¦£ % ¢ ! ¥ ¡
.

¥ ¡ ¦£ 1

¥ ! %#¡

S`

¥ !¡ %#

b) Write the transfer function

a)

¤1

¥

¥ ¡1 @ ¨¦¤ § ¥£¡

b) Transfer function:

c) Solve for

c)

a) Write down the differential equation describing the circuit in Figure 14.27.

Solution:

assuming

, and

(let

CHAPTER 14. SSS: RESONANCE

).

471
2

1 R ------- – -------LC 4L 2

two solutions for s R – ----2L
2

1 R – ------- – -------LC 4L 2

Figure 14.28: d) See Figure 14.28

Problem 14.6 a) In the circuit in Figure 14.29, given that cos , where rad/sec. Design a lossless coupling network containing one inductor and one capacitor that will maximize the power transferred to the antenna at frequency . b) Now suppose that cos , where represents a small amount of third harmonic distortion introduced by nonlinearities somewhere in the transmitter. Since the FCC forbids the broadcast of harmonics, it is important to check that coupling networks do not inadvertently favor the coupling of harmonics to the transmitter. For your design in a), calculate how much third harmonic reaches the antenna. Solution:
¢

d S

§

¢

£

¢

£

¡

§

£

¢ WH V !

£

¥ £

C

(d)
©

§

§

©

s

¢

ANS:: (a)

(b)

(c)

¥ £

¨ ©§¦¤ C C D ¢ C 9 s ¥

7

7 @

@

¡

§ ¦¤¡ 1 ¥£

1

§

@

@

¡

C C D ¢ S 9

§
¡

¥ ¨!

@
@

¥ 7!

7 7 @ C D
¢

1

s 9

@

¥ 1 D ¥ 2¨¦£ ¡ s 1 § ¥

s 9

¤ ¤¤ §

@

1

@

D7

§ !
@

¤

¢ S D s s $ 4£

472

CHAPTER 14. SSS: RESONANCE
RS Lossless vS + coupling network Antenna
Figure 14.29:

RS = 50 Ω RL RL = 1 Ω

Transmitter

RS RS=50Ω vS + C L RL RL=1Ω

Zeq
Figure 14.30: a) , d 9
¢ D V

b)

See Figure 14.31 for equivalent circuit.

¥ 7!

7 s )

) ¥ )

!

§ 7

¡

b %

b %§

b §

§

¢

!

§

¡

¡

7

¢

¥ s

@ T

$

) ¦§

§

§

¡

§

¡

£

¨ ¤ £ ¦

¥ £

¢

¨¦ ©¤

¡

§

make

so that

, then:

!

¥ ) ¥ 7 ! ¥

!

@

¡

¡ 5@

§ !

¡

@ § ¥ s ¥ sD

§

§ 6¥ )! 7

¡

Specify ,

:

§
¢

£
¢

¨¦ ©¤

§

See Figure 14.30 for network structure.

473

RS RS=50Ω vS + Zth RL RL=1Ω

Figure 14.31:

RS L

RS L RP

Simple model of a physical inductor

More complex model

Figure 14.32:

Amount that reaches the antenna: use

:
¢

Problem 14.7 Refer to the ﬁgure in Figure 14.32 for this problem.

The

of a physical energy storage element may be deﬁned as

¥ I£ @ ¡ § ¥ ¡ )

s

d

ANS:: (b)

¡£ ¡

§¦ C

& 0 ¡@ ¥ £ ¤ § ¢ ¡@ 3

¢

¡

¥

2 ¢

¤¥£ ¢

¡

¡

¡ ¢

£

2 9¢ V

¥ §
(14.4)

¡

¢ 6 V

S¢ R@ 2 V

7 ¢
¢ ¢

@

§

¡D ¢ £ £ £ £ © ¥ @ ¡D ©

§

¡0((V

@

£

§

C

¡

¢ ¢ ¤ ¥ s

From (a),

. At

¢ e V

§ !

s

§

,

¥

474

CHAPTER 14. SSS: RESONANCE may also be deﬁned in

where is the terminal impedance of the element. The terms of energy as

Solution: s C

7

s

To compare

and

, ﬁnd the ratio

¢ 0 # § 7 0 @ § ¢ % $ © 3 ¢ £ X 7 @ § ¢ 3 ¡ © @ 7 § 0 # $ 0

.

£ X 7

©

¢

§

¡

where the Period =

:
¢

© 1 ¥ X 8%¦£ 3 ¤ £ X 7 ¢

7

s

7

¤

§

©

§

§

©

#

7

7

Find

:

@

¢

¢

¥ I£ @ ¡ § § s ¥ ¡ ) ¥ @ 2§

a) Simple Model: Find

:

u s

and ( c) Suppose two inductors with the same for the series combination in terms of .

) are connected in series. Express

s

b) For the more complex model, and assuming making reasonable approximations. s , sketch

7

s

a) For the simple inductor model, calculate and compare frequency.

@

©

u s

@

where cycle.

is the average stored energy and

¢ 0

#

¢ 0

©

$ %
#

§ 7

(14.5) is the energy dissipated per

and

as functions of as a function of

s

¢

475 b) More complex model:

See Figure 14.33
Q1

Figure 14.33: c)

Problem 14.8 Communications receivers require high-Q circuits to separate signals broadcast on adjacent channels. Due to losses, modeled by the parallel resistance , there is a limit to the that can be achieved with passive components. In the ampliﬁer circuit in Figure 14.34, a variable resistor has been added which has the effect of increasing the of the passive tuned circuit.
¡

and

variable is
¡

a) Consider ﬁrst the tuned circuit by itself, disconnected from the ampliﬁer. If chosen so that the circuit has a resonant frequency, what is its ?

¥

¤ S(§ @

C C

D ¤D £

¢ £

s

u u ws

¤ @

§

£ §

T § ¥ ¤(((0)G¤T ¢

£ §

s

ANS:: (a)

,

(b)

7 ¢7

¢

¢

¥

D

@

@ I @

s

D7 § 7

D §

assuming

:

ω

7 7

¢

¢

¥ 7 @ 7 @

7 ¢ 7 @ ¥ 7 ¢ 7 @ ¥ 7 "@ @ ¥ I£ @ ¡ § § ¢ 7 @ ¥ ¡ ) 7 ¢7 ¥ 7 @ 7 7 ¢ ¥ 7 @ ¥ @ § 7 ¢7 @ ¥ ¢ @ #¡ @ @

¥

¢

@
¥

¢

@

¥ @ §

s

D ¥ s

¡

¥ @ 2§

s

@

¢

¥ @ §

@

§ R@

476

CHAPTER 14. SSS: RESONANCE

RS vS + i

RF βi C L

+ r vO -

Source

Ampliﬁer
Figure 14.34:

Tuned circuit

b) Determine the overall transfer function

so that the overall frequency response is peaked at a c) Select values for and frequency and has a half-power band width of . (Note, the half-power bandwidth = ). What is the in this case? Solution:
¥

a)

b) See Figure 14.35 for reference. γβi ( 1 – γβ )i αβi

RS + i

RF βi C L

vS

Z
Figure 14.35:
¥ ¢

¤ @1 ¥8'

¢

Find

:

§

©

¢

§ £D

,
©

¢

¡

¥ ¥

S

¡

S t¨%#¡ ` § ¥ !

02 §

7

¢

@ fP¡ ¥

u

¢

§

§

.

¡

¡

¥

u

¢

¢

¥ s

§

¡

¤ @

¥ s

§

©

¡

§

¡

+ r vO -

¢ ¡D § § £D

§

` 7

§ ¥ ¨! ¡ 7

` s

§ ¥! ¨#¡

s

T H

¥@ ¤

¡

§

£
D

002 § § ! ¡ ¥

02

§

§
¡

¢ § D £ D ¢ § S C § ¡D §
¡ ¡ ¡

002 §

T H

¥@ ¤

T ((( b & a c( (¢
¡

(

u s

)

§

()§ ¤ @ )

b

2 ( a

$

§
¡

© § § @

u
¢

¡

¤

c)

¥ 9

@

¢

¢

@

¥ H

@

¢

¥

¤ ¥@ @ ¢ ¥ ¥
¡

7
¢

@ TP¡ ¥ ¥I ¤ @

@ §

¥ ¥@ ¤

¢

¢
¡

§ ¥! ¨#¡

¥ ¢

¥

¤ @ ¢ ¥ ¥

7
¢

@

¡ ¥ ¥@ ¤ §

¥ ¢

P¥ @

¢

@ T

¡ §

¤ ¥@

¢

@ ¦¥

¢

@ TP¡

¦¥ @ @ P¥ 1

¢ ¢

@ TP¡ @ TP¡

§ 1 §

Substitute:

¥@ ¤

¢

§

ANS:: (a)

With these values,

Find :

(b)

£

D

¥

s §

D£ D

Problem 14.9

a) Consider the two circuits in Figure 14.36.

Determine the transfer functions

,

,

and

u s

)

b & a c( (¢

(c)

1

477

478

CHAPTER 14. SSS: RESONANCE i1 i2 iS C L

iS

R

C

L

Figure 14.36: s ?

Answer:

Solution: a) First Circuit:

!

s ¥ D ¢

D

D

¢sD

§

!

¢ ¤¥ s

¥ ¥ s¢ ¤

§

s

1

1

§ ¥ ¨! ¡

s

Sketch

for

.

7 ¥ 7 ¡ £ 1 s ¥ 7¡ £1

2 0t§

¥£ ¦¤¡ s 1

For

calculate (14.6)

(2 02

¥ © ¡ £ 1 s¥

7

e2

§

§

s

£7 1

e)

reaches maxima/minima at .

For what value of

$

u

d) Write the step response

and

in terms of

¢

¥£ ¦¦

¢

¨ ©§¦¤

a a ¦( S a

¥

7 7 7 £1 ¥ ¤1 § 1

¢ ¢

§

¨

$

¡ 7¢

£ ¦

©

¢

s s s £1 ¥ ¤1 § 1

§ £

¨¦ ©¤

£

@ T

@ T

§

§

¥ ¦£ ¡ s 1

¥ ¦£ ¡ 7 1

7

Why is

not the complete steady-state response of the second circuit? and .

7

¡

F`

s

c) Calculate the “natural responses”

and

B§ £

£1

£1

@ § § ¡ E( ¨¥ #¡ 9 2¨¥ #Q 1

¥ ¦£ ¡

¤1

¤ s1

7

b) Given that and

, draw the circuits as they would appear in steady-state. (Recall represents a unit step at time ). What are the “forced responses” . Assume:

¥£ ¦¤¡

C § ¥ t¨¦£ ¡

1

C

© ¡ ¥£ ¦¤¡

s

¤1

1

does

¢
¡

u

¨ ¤ ¦
¡

£u 2§ ¤ @ § £ ¥ ¦£ u ¢

¢ ¤

¤

u

¢

¨¦ ©¤

¥ £u

¢ ¢

¨ u
¢

¡
@

§ ¥ ¦£ ¥ ¦£ u ¢

@

£ @

§ £1

s

§

§
¤

u

¢ ¤

¥

s

@ § u ¢

¡

@ ¨¥ ¡ 1 § § s £ @ ¨¥ #¡ 1 §
¢ £ ¢ ¢ ¢

¤

¨ ¡ ££
¤

§ £1 § E u ¢

s

¨©§¦¤ ¨ ©§¦¤
¡

¥ £u ¥ £u
¡

¨ ¡ £
¤

¢

¡

¥

@

¡

¥ ¦£ ¡ 7!
¡

s

C § BR

1

7!
¡

@ ¥ !

@

@ @ ¥

§ ¥ ! ¨%#¡

s

Second Circuit:

¥ ¨

§

!

s

¥ s

1 § 7 § ! ¡ 7 ¥ 1

iS

b)

See Figure 14.37 for circuit diagrams First Circuit: Second Circuit:

7 § ¤ 1 s § ¤ 1

c) First Circuit:

¤

¥

¤¤

§

¤1

Second Circuit:

¨¦ ©¤

¥ £u

7 @ § 1 £ 7 § §¨(#¡ £ 1 ¥ 7 @ §¨¥ #¡ £ 1 7 § £1
¢ £¡ ¢

¨

¤

¦ 7 §

@

Since Since

:

R

C

:

Figure 14.37:

L i1=iS

iS

C

i2=iS
479

L

d d

b 2 8S a b 2 a 8S S b

§ §

) )

£! ` )W(¢!

4 4 $ 01 X I¥ d

)

£
¢

¨¦ ©¤
§

Problem 14.10 The circuit in Figure 14.38a is to be used as a bandpass ﬁlter having the magnitude-frequency curve shown in Figure 14.38b (linear coordinates). The input voltage is

¥¦¦ ¢ £ s § £1

7 ¥ ¦ ¢ £ ¡ 7 ¢ £ ¢ s s 7 § ¤1 § ¤1

s £( @ £u C §¨¥¦£ ¡ 1 § #¡ 7 ¥! 9 ¢s s

D ¢ D £ D ¢

§ %#¡ ¥ !

£ ¦
¢

7
¤

1 ¥£ 2§ ¦¤¡ 7 1
@ T

¥£ ¦¦
¢

¨¦ ©¤

¥ P £

¢ ¢

¨©§¦¤ T§ ¤7 1 ¥ @ ¨ ¡ 7¢ £

§ £ 1 ¥ ¤ 69¦£ ¡ s 1 1 § ¥

s

s

¦ 7 §

480

d) With

e) ???

ANS:: (a)

:

,

CHAPTER 14. SSS: RESONANCE

(b)

,

(c)

¨ ¤ ¦

¨

¢

¨ ©§¦¤
C

@ S

a) Find the appropriate values of Using the values found in a):

iii) For , determine the total stored energy averaged power dissipated.

¥£ ¦¤¡ ¨ ¦¤¡ 1 ¦¤¡ 9 ¥£ ¥£

£ d ) ) E § £ 9)4 ) § d
¢

¨ ©¦¤ ¨ ¤ ¦

p& $ ¤

§

1 ¦£ ¥
,

and

and

¡

§

¢

¡ ¡ ¡

¥ ¦£ ¡

7

u

£ P

¢

D

¢

¨¦ ©¤

¥£u s ¨¦ ©¤

¢ £¡ ¢

Solution: ii) Let i) Sketch vs. . (d) . (14.7) , . Calculate . and the time-

¨

7 @T § ¥ ¨¦£ ¡ 1 7 s ¡ £ R@

481

Vo ----Vs 1 C + iS(t) + 0.707 L i R = 100 Ω + vO vS(t) = VS cos (ωt) ω (a)

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