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Lab #3 Inverter Tutorial: Layout, DRC, Extraction, LVS and Back Annotating Parastics

Yong Li
Partner: Hao Zhang
Group #2

10/10/2012
EEN532 GF

Objective
In this lab, we were asked do the layout of Inverter using the design rules for the AMI C5N (λ=0.3μ) fabrication process. Specifically, we need to do some hand-on experience on how to complete the physical design (layout), design rule check (DRC), parameter extraction, layout vs. schematic (LVS) and Back Annotating Parastics from Layout to Schematic using the Cadence tools.

Software
LSW and Virtuoso Layout Editor
We need to create a layout cellview, check it and simulate it in the software

Procedure and Data
First of all, we need to create the layout Cellview in LSW and Virtuoso Layout Editing Window. According to the instruction, we set up the display, and then we could draw everything in the layout. We also need to pay attention to the positions and the size. We drew the VDD, VGND, NMOS, PMOS, N-Well as well as all the contacts. We had to choose the correct color and the name of every component in the LSW. After that, we would connect transistors Nodes to Match schematic and Form the Inverter. And then we added the pins, which include vdd, vgnd, vin, and vout pins. The layout was like the following:

The next step was to design rule check, which to test if our layout drawing obeys the design rule. When the CIW shows “Total errors found: 0”, our design rule check is successful.

Furthermore, we were asked to do Layout Parameter Extraction because the layout we had done only contained physical data. We need to do the extraction process to get a SPICE-like netlist and other files necessary to complete the design process. Make sure of no errors by checking CIW. From the Library Manager window, we can see the extracted cellview we just created. Double click to open it.

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