Power Characteristics of Networks on Chip
Mohamed A. Abd El ghany*, Darek Korzec* and Mohammed Ismail**
Electronics Engineering Dept., German University in Cairo, Cairo, Egypt*
Electrical Engineering Dept., The Ohio State University, Columbus, USA. The RaMSiS Group, KTH, Sweden**
E-mails: mohamed.abdel-ghany@guc.edu.eg, darek.korzec@guc.edu.eg, ismail@ece.osu.edu

Abstract— Power characteristics of different Network on Chip
(NoC) topologies are developed.
Among different NoC topologies, the Butterfly Fat Tree (BFT) dissipates the minimum power. With the advance in technology, the relative power consumption of the interconnects and the associate repeaters of the BFT decreases as compared to the power consumption of the network switches. The power dissipation of interswitch links and repeaters for BFT represents only 1% of the total power dissipation of the network. In addition of providing high throughput, the BFT is a power efficient topology for NoCs.
Index Terms – NoC, Power Dissipation, BFT. CLICHÉ,
Octagon, SPIN, Interswitch Links

I.

INTRODUCTION

With the increasing number of intellectual property blocks
(IPs) in System on Chips (SoCs), billions of transistors integrated on a single chip will soon become a reality. The limitations of system scalability, bandwidth and power dissipation are becoming the major drawbacks for high performance SoCs. Recently, Network-on-Chip (NoC) architectures are emerging as the best replacement for the existing interconnection architectures [1]-[4]. NoC provide different set of constraints in the design paradigm.
Power estimation is an important aspect of NoC design.
No sufficient power analysis has been performed to characterize power dissipation of different NoC architectures.
Different researches on architectural and conceptual aspects of NoC have been published. These researches have taken a top-down approach (a high level analysis of NoC) and they didn’t touch the issues on a circuit level. Little research has been reported on power estimation of NoC design [5], [6].
They were only focusing on estimating the power dissipation of limited set of architectures. Also, the power estimation is only available late in the design cycle.
The main focus of this paper is to present power characteristics for early-stage power estimation of different
NoC architectures. Three primary parts of the communication network forming the on-chip NoC are shown in Figure 1.
Including different sources of power consumption in NoC, the total power dissipation of on chip network is analyzed.

With the advance in technology, the power dissipation which is required to implement different NoC topologies are described. To the best of our knowledge, this is the first in depth analysis, on circuit level, to estimate the power dissipation in early-stage of NoC design.

Figure 1 communication networks on chip

The paper is organized as follows: In Section II, the port architecture of NoC switch is presented. Power characteristics for different NoC architectures are provided
In Section III. In Section IV, the simulation results of the power estimation for different NoC architectures are presented. The effect of the advance in technology on the power dissipation is also analyzed. Finally, conclusions are provided in Section V.
II.

PORT ARCHITECTURE

Communication network on chip consists of three primary components; network switch, interswitch links (interconnects), and repeaters within interswitch links as shown in Figure 1. The power dissipation of the communication network is independent of the target IPs. The switch of different architectures has different number of ports. Each port of the switch includes input virtual channels, output virtual channels, header decoder, controller, input arbiter and output arbiter [4]. The input arbiter consists of a priority matrix and grant circuits [7]. The priority matrix stores the priorities of the requests. The grant circuits generate the granted signals to allow only one virtual channel to access a physical port.
The average power dissipation of NoC port is obtained by implementing the design on the transistor level using ASIC design flow. For different NoC topologies, the average power dissipation of the switch is determined according to the number of ports in the switch. The power dissipation of

the other two network components (interswitch links and repeaters) is characterized in Section III.
III.

1

POWER CHARACTERISTICS

To achieve power efficient NoC, power dissipation need to be characterized for different topologies. Including different sources of power consumption in NoC, the total power dissipation of on chip network is defined as follows:
1
2

where is the total power dissipation of the switches forming the network. is the summation of switching
(including dynamic and short circuit) power and leakage power of switches. is the total power dissipation of interswitch links. is the total power dissipation of the repeaters which are required for long interconnects. The number of repeaters depends on the length of the interswitch link. According to the topology of NoC interconnects, the interswitch wire lengths, the number of repeaters and the number of switches can be determined a priori. The power consumption of interswitch links and the power consumption of repeaters are defined by [8]

1
4

,

,

……

,

9

2

where is the optimal length of the global interconnect
[8]. Using the number of switches, the total length of interconnect and the total number of repeaters, the total power dissipation of BFT architecture (
) can be calculated using the following expression:
6
√

log
,

,

,

3
……

,

3
4
5

where is the total dynamic power dissipation of is the number of repeaters, is the optimal repeaters, repeater size, is the activity factor which is the fraction of repeaters on a chip that are switched during an average clock and is the input capacitance of a minimum size repeater. is the total short-circuit power of repeaters. is the total leakage power dissipation of repeaters. The closed form equations for the power dissipation of different NoC topologies are described in the following subsections.

1
2

,

10

Figure 2 Butterfly Fat Tree architecture

B. SPIN
An interconnect template to integrate IP blocks using
SPIN topology was proposed as shown in Figure 3. In large
SPIN, the total number of switches is 3 /4 [2]. The interswitch wire length can be determined using eq. (6). The total length of interconnect and the number of repeaters are defined by:
0.875 √
√

11

√

12

√

A. Butterfly Fat Tree
In the BFT, The number of switch levels can be expressed as
3, where N is the number of
IP blocks [4]. The total number of switches in the first level is /4. At each subsequent level, the number of required switches reduces by a factor of 2 as shown in Figure 2. The interswitch wire length and total number of switches are given by the following expression [4]:
√
2

,

1

1
4

1

2
1

7
2

where is a die size and
, is the length of the wire spanning the distance between level a and a+1 switches, where a can take integer values between 0 and (levels-1).
The total length of interconnect and the total number of repeaters can be determined from the following equations:
√
2

Figure 3 SPIN architecture

6

8

The total power dissipation of the network architecture depends on the main three parameters; the number of switches, the total length of interconnect and the number of repeaters. The total power consumption of the SPIN architecture (
) can be determined by:
8
√

√

0.875 √
√

13

C. CLICHÉ
In CLICHÉ architecture, the number of switches equals the number of IPs [1] as shown in Figure 4. The interswitch wire lengths can be determined from the following expression: √

14

√

where L is the length of four nodes; it equals to 4
.

is the summation of the global interconnect width

and space. Considering the interswitch wire lengths and the optimal length of global interconnect, the total length of interconnect and number of repeaters can be obtained by:
7
2

2

2

52

22
2

6

where is the number of basic octagon unit. The total power dissipation of the Octagon architecture can be determined by the following expression:

Figure 4 CLICHÉ architecture

The number of horizontal interswitch links between switches equals to √ √
1 , and the number of vertical
1 . interswich links between switches equals to √ √
According to the technology node, the optimal length of global interconnect can be obtained. Therefore, the total length of interconnect and the number of repeaters can be calculated by:
2√
2

1

√
√

15
√

√

1

√

23

3
14

52

2

2

2

6

24

16

Using the number of ports, number of switches, total length of interconnects and number of repeaters, the total power consumption of the CLICHÉ architecture can be determined by the following expression:
Figure 5 block diagram of basic Octagon unit

5
2

2√
√
√

1

1

√
√

√
17

D. Octagon
For Octagon architecture, a basic octagon unit consists of eight nodes and 12 bidirectional links as shown in Figure 5.
Each node is associated with a IP block and a switch.
Therefore, the number of switches equals to the number of IP blocks. For a system consisting of more than eight nodes, the octagon is extended to multidimensional space using multiple of basic octagon unit [3]. There are four types of interswitch wire length: First (connecting nodes 1-5 and 4-8), second (connecting nodes 2-6 and 3-7, third (connecting nodes 1-8 and 4-5), forth (connecting nodes 1-2, 2-3, 3-4, 56, 6-7 and 7-8). the interswitch wire lengths can be defined by: 3
4

13
13
4

18
4

19
20
21

Using the power equations presented in this section, the
Power dissipation of different high throughput (TH) architectures [9], [10] could be estimated. In these architectures, rather than using a single interconnect bus between each two switches, two buses are employed.
Therefore, the power dissipation of the interswitch links and repeaters required to implement different high throughput architectures is the double power dissipation of the interswitch links and repeaters required to implement conventional architectures. Power estimation of different architectures is presented in Section IV.
IV.

POWER COMPARISON

Using the Cadence tools, 90 nm CMOS technology, the
NoC port is implemented on the transistor level. The power dissipation of the NoC port ( is determined at 200 MHz frequency in the worst case data input patterns. According to equations (10), (13), (17) and (24), the total power dissipation of the network can be considered as a function of the number of IP blocks. Given a die size of 20mm x 20mm and supply voltage ( of 1.8 , the total power dissipation of different NoC topologies is calculated for different number of IP blocks. The change in the power consumption with the number of IP blocks for different network

Power dissipation (W)

topologies is shown in Figure 6. The power consumption for different NoC topologies increases by different rates with an increase in the number of IP blocks. The SPIN and Octagon architectures have much higher rates of power dissipation increase. Power dissipation of SPIN is increased by almost two orders of magnitude when the number of IPs increased from 16 to 1024. The BFT topology consumes the minimum power as compared to other NoC topologies, making BFT more attractive as a power-efficient NoC topology.

Table I power consumption of interswitch links and repeaters for different topologies The power consumption of interswitch links and
No.
repeaters as compared to total power of the network (%)
Technology
of node HT- HTIPs BFT CLICHÉ Octagon SPIN HT- HTBFT CLICHÉ Octagon SPIN
7.6
7.6 41.02 17.06 14.1
14.1 58.17
130 nm 361 9.32
729 4.34
4.8
4.78 33.57 8.32
9.1
9.1 50.27
90 nm
2.7
2.8 32.54 4.6
5.2
5.4
49.1
65 nm 1849 2.35
1.4
1.6 28.06 1.18
2.7
3.1 43.82
45 nm 5625 0.59

100
80

SPIN

60

Octagon

40

CLICHE

20

BFT

0
16

32

64 128 256 512 1024
Number of IP blocks

Figure 6 power dissipation of different NoC architectures.

percentage of the interconnect and repeaters Power dissipation (%)

The percentage of the power dissipation of the interswitch links and repeaters is shown in Figure 7. For the
SPIN network, the power dissipation of the interswitch links and repeaters represents 25% of the total power dissipation of the network. For the BFT, CLICHÉ and Octagon, the percentage of power dissipation of the interswitch links and repeaters decreases with increasing the number of IP blocks.
For future SoC, reducing power dissipation should be focusing on reducing the power of the switches since more power is expected to be dissipated in them.
40
30

BFT
SPIN
CLICHE
Octagon

20
10
0
16

32 64 128 256 512 1024
Number of IP blocks
Figure 7 power dissipation of interswitch links and repeaters for different
NoC architectures.

Considering a die size of 20mm x 20mm, the power consumption of interswitch links and repeaters for different architectures are shown in Table I. The power dissipation of different high throughput architectures (HT-BFT, HTCLICHÉ, HT-Octagon and HT-SPIN) is also presented in
Table I. With the advance in technology, the number of IPs increases. The number of switches is also increased. The percentage of power consumption required to implement the interswitch links and repeaters for different NoC architectures decreases as technology advances. The BFT topology consumes the minimum power dissipation to implement the interswitch links and repeaters of the network.
The power dissipation required to implement the interswitch links and repeaters for BFT is less than 1 % of the total power dissipation of the network in 45 nm technology node.
The BFT is more efficient as technology advances.

V.

CONCLUSIONS

In this paper, power characteristics for different NoC topologies are presented. Including different sources of power consumption in NoC, the total power dissipation of on chip network is analyzed. The BFT topology consumes the minimum power dissipation. The percentage of power consumption required to implement the interswitch links and repeaters for different NoC architectures decreases as technology advances. The power dissipation required to implement the interswitch links and repeaters for BFT is less than 1% of the total power dissipation of the network. In addition of providing high throughput, The BFT is a power efficient topology for NoCs. For future NoC, reducing power dissipation should be focusing on reducing the power of the switches. REFERENCES
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