...Με δεδομένo τo line size αλλάζαμε το line number και το associativity για να επιτύχουμε τη ζητούμενη ιεραρχία μνήμης: size (dc/ic) 16K 16K 32K 32K 64K associativity (dc/ic) 2 4 4 8 4 64K 8 Με τις προσομοιώσης και με τους τύπους που προαναφέρθηκαν υπολογίσαμε τα ipc για κάθε ζητούμενη ιεραρχία μνήμης και κάναμε τη γραφική(οι μετρήσεις μετά από κάθε ζητούμενο): IPC # art 1 0.045074 2 0.044773 3 0.044509 4 0.044460 gzip 0.135081 0.135202 0.135994 0.136015 mcf 0.074851 0.075072 0.075395 0.075420 equake 0.121923 0.122304 0.122627 0.122643 5 0.044464 0.137202 0.076103 0.122800 6 0.044464 0.137208 0.076056 0.122820 Για να γίνει όμως πιο κατανοητό το τι σημαίνουν αυτές οι μεταβολές παραθέτουμε τη βελτιωση % σε σχέση με την πρώτη ιεραρχία μνήμης: IPC improvement% Ακολουθεί η γραφικη για το dc_miss_rate Και οι αντίστοιχες μετρήσεις: # 1 2 3 4 5 6 art 0.250169 0.251383 0.213636 0.213695 0.212731 0.212659 gzip mcf equake 0.066665 0.186052 0.035207 0.066547 0.183907 0.032961 0.057635 0.174644 0.031160 0.057119 0.173539 0.031146 0.047042 0.158395 0.029751 0.046935 0.159030 0.029571 Στη συνέχεια η γραφική για τo ic_miss_rate Kαι οι αντίστοιχες μετρήσεις: # 1 2 3 4 5 6...
Words: 3991 - Pages: 16
...The Effect of Compiler Optimizations on Pentium 4 Power Consumption John S. Seng Dean M. Tullsen Dept. of Computer Science and Engineering University of California, San Diego La Jolla, CA 92093-0114 jseng,tullsen @cs.ucsd.edu Abstract This paper examines the effect of compiler optimizations on the energy usage and power consumption of the Intel Pentium 4 processor. We measure the effects of different levels of general optimization and specific optimization. We classify general optimizations as those compiler flags which enable a set of compiler optimizations. Specific optimizations are those which can be enabled and disabled individually. The three specific optimizations we study are loop unrolling, loop vectorization, and function inlining. The binaries used in this study are generated using the Intel C++ compiler, which allows fine-grained control over each of these specific optimizations. ¡ 1. Introduction The power consumption of general purpose microprocessors has reached a point where the problem has to be addressed at various levels of system design. Many circuit, architecture, and software algorithm techniques exist to reduce power, but one often overlooked area is the effect of the program code on power consumption. Some research has been done studying the effect of compiler optimizations on power consumption [8, 9]; this work has been generally limited to using architecture-level power models for power estimation. In this work we examine the effect of the compiler...
Words: 4099 - Pages: 17
...A Survey of Checkpointing Strategies for Shared-Memory HPC Applications Ana Gainaru,Aparna Sasidharan,Jorge Mario Cara Carmona University of Illinois, Urbana-Champaign April 25, 2012 1 Introduction Fault tolerant protocols have always been a major research topic for the HPC community. Harnessing microprocessors to solve large computational problems has required the use of many microprocessors in a single system. Whereas today the large server machines in the business sector may have as many as 32 processors, large supercomputers can have thousands or tens of thousands of processors in a single machine. While this approach has proven itself to be highly effective in expanding the limits of computational capability, it has also brought to the foreground new challenges that did not arise in smaller systems. Fault tolerance is one such critical challenge.The problem of fault tolerance in modern systems arises from two important HPC trends. First is the rising frequency of faults in systems. Second is the increasing size and running times of applications running on these systems, making them more vulnerable to these faults. HPC systems are vulnerable to faults for three major reasons. First, whereas older machines were built from custommade,high-quality components, modern systems use commodity components that were designed and built for a less reliability-aware market. Second, as modern systems are made from more and more components, the probability of one of them failing...
Words: 7288 - Pages: 30