State University of New York at Stony Brook Department of Electrical and Computer Engineering ESE218 Digital Systems Design

Lab 9. Counter design.

1. Objectives - Design of the synchronous finite state machine (FSM) with D-flip-flops and multiplexers - Verification of the circuit behavior with a CAD tool 2. Problem description Design the synchronous 4-bit counter which outputs follow the predetermined repeated sequence of states. The sequence of states represents the sequence of decimal digits of your ID number with the following exceptions: (1) digits which appear more than ones have to be deleted; (2) digit 9 has to be added at the end of the sequence if your ID has no 9. For example, for ID number 105123456 the second 1 and 5 are deleted and 9 is added at the end resulting in sequence 10523469. In the binary form the sequence is shown in Figure 1. The initial state is not critical. State 9 should be decoded to generate special signal SYNC shown in denominator in Figure 1. In the prelab: the circuit behavior has to be verified in OrCAD. The maximum clock frequency has to be calculated using timing specs of the flip-flops and multiplexers (logical gates) from datasheet. In the experiment: first, the functionality of the counter has to be tested with a pushbutton that controls the clock and a 7-segment LED display connected to the outputs. Finally, the counter sequence should be demonstrated with the logic analyzer synchronized with SYNC signal, 4inputs of the logic analyzer should be grouped into a bus. 3. Approaches Outputs of four D-flip-flops Q3Q2Q1Q0 serve as outputs of the counter. Next states Q*3Q*2Q*1Q*0 are formed from present states Q3Q2Q1Q0 with combinational excitation circuits. By design we understand determination of the minimal expressions for combinational circuits which excite flip-flop inputs D3, D2, D1, D0. Next states for unused states should be treated as don’t cares. The state table (Table 1) can be used for find implementations with MUX, K-maps for functions D3,D2,D1,D0 can also be used for circuit minimization. 0001 → 0000 → 0101 → 0010 → 0011 → 0100 → 0110 → 1001 0 0 0 0 0 0 0 1 Figure 1. An example of the state diagram (you have a different one).

Table 1. Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

D3 0 0 0 0 0 0 1 × × 0 × × × × × ×

D2 1 0 0 1 1 0 0 × × 0 × × × × × ×

D1 0 0 1 0 1 1 0 × × 0 × × × × × ×

D0 1 0 1 0 0 0 1 × × 1 × × × × × ×

SYNC 0 0 0 0 0 0 0 × × 1 × × × × × ×

The following equations for the flip-flop excitation were obtained from the state table: D3 = Q2 Q1 D2 = Q1Q0 + Q1’Q0’= (Q1⊕ Q0)’ D1 = Q2Q1’+ Q2’Q1Q0’ D0 = Q3 + Q1Q0’ + Q2’Q0’ The flip-flop excitation should be implemented with 4-to-1 and 2-to-1 MUX (see Lab 7 and Figure 2). Logical gates can be used in addition to MUX for simplification as shown for D0 in Figure 2. Since no states above 9 are used, SYNC signal for decoding state 9 can be implemented either with a 2-input NAND gate as shown in Figure 2 or with a 2-to-1 MUX and inverter. SYNC = Q3Q0 The design should be verified for presence of hang-up states: for all unused states next states have to be determined to make sure there is a path to used states. The analysis of the solution with all don’t cares is present in Table 2. Table 2 can be completed either using equations for D3,..,D0 or K-maps. A complete state diagram should be obtained (Figure 3). The state diagram shows that if the counter by any chance (for example, on powering up) enters states 8, 11, 10, 13, 15 or 14 then the counter will self-correct its behavior returning to used states through states 5, 3 and 9, respectively. However, if the counter enters unused states 7 or 12 then the return to used states does not occur.
2

1

U4A

LO

2

2 3 5 6 11 10 14 13
LO

U2 1A 1B 2A 2B 3A 3B 4A 4B 1Y 2Y 3Y 4Y 4 7 9 12 3 4 6 11 13 14 9 U1 1D 1Q 2D 2Q 3D 3Q 4D 4Q 5D 5Q 6D 6Q CLK 2 5 7 10 12 15 Q[3] Q[2] Q[1] Q[0]

7404 Q[0]

15 1

V

STROBEG SELECTAB
LO

1

Q[2]

Q[1]

14 2
LO LO HI LO LO

U3 S0 S1 EA I0A I1A ZA I2A I3A EB I0B I1B ZB I2B I3B 74153 7

CLR

74157

74174

Q[3:0]

1 6 5 4 3 15 10 11 12 13

V

V

1 2

U5A 3 7408 SY NC
V

9 1 2

U6A 3 7432

LO

Q[3]

OFFTIME = .05uS DSTM1 ONTIME = .05uS CLK DELAY = STARTVAL = 0 OPPVAL = 1

S1

DSTM2

Figure 2. Circuit diagram of the FSM implementing Table 1. Table 2. Q3 0 1 1 1 1 1 1 1 Q2 1 0 0 0 1 1 1 1 Q1 1 0 1 1 0 0 1 1 Q0 1 0 0 1 0 1 0 1 D3 1 0 0 0 0 0 1 1 D2 1 1 0 1 1 0 0 1 D1 0 0 1 0 1 1 0 0 D0 0 1 1 1 1 1 1 1 SYNC 0 0 0 1 0 1 0 1

8 10 ↓ ↓ 1→ 0 → 5→2→3→4→6→9 ↑ ↑ ↑ 11 13 ← 15 14

7→ ← 12

Figure 3. The state diagram obtained for the solution with don’t cares showing both used and unused states with decimal numbers, output SYNC is not shown for simplicity.

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Should the design with don’t cares be found to be not self-correcting (with hang-up states such as 7 and 12 in Figure 3), modification of the state diagram is necessary to make the design selfcorrecting. Redesign of the flip-flop excitation is required. In the example breaking the loop 7-12 will be sufficient to solve the problem. One can require the next state for one of the states (7 or 12) to be within the list of used states. The latter can be implemented with various approaches. One can replace certain don’t cares in solutions for present states 7 and/or 12 to make sure the next state is one of the used states. This approach would lead to more complicated circuits for flip-flop excitation. Alternatively, since 0000 state is a used state in this example, one can CLEAR the flip-flops if the counter enters state 12. Upon returning to 0000 the CLEAR signal will be removed and the counter will continue going over the normal sequence of states. Since states above 12 are unused as well, the counters can be cleared when any of the states 1100, 1101, 1110, 1111 are entered. The latter was implemented in Figure 4 with decoding only two bits Q3Q2 with NAND2 gate (a 2-to-1 MUX could be used alternatively). The circuit represents the self-correcting design.
3 4 6 11 13 14 9 U7 1D 1Q 2D 2Q 3D 3Q 4D 4Q 5D 5Q 6D 6Q CLK 2 5 7 10 12 15 Q[3] Q[2] Q[1] Q[0]

LO

CLR

1

74174

Q[3:0]

1 2

U8A 3 7408 U9A 3 7400 SY NC

1 Q[2] 2

Figure 4. The fragment of the circuit with NAND2 gate for decoding states 12, 13, 14, 15 and clearing contents of the flip-flops. The state diagram of the redesigned circuit with self-correction is shown in Figure 5.

13, 14, 15 8 10 ↓ ↓ ↓ 1→0 → 5→2→3→4→6→9 ↑ ↑ 7 → 12 11 Figure 5. The state diagram of the redesigned counter with self-correction.
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Figure 6. Timing diagram of the circuit in Figure 2. Calculation of the max clock frequency: due to propagation delays in flip-flops, excitation circuits and the requirement on the flip-flop setup time, the clock period should exceed a certain minimal value to guarantee the reliable counter operation. If the setup time is not met, the flipflop may fail to get into the desired next state. The min clock period (which is a reciprocal of max clock frequency) can be calculated as a sum of the flip-flop setup time, propagation delay from the flip-flop input D to output Q (starting at the active clock edge) and the max delay in the combinational circuits which excite the flip-flop inputs. For example, suppose the setup time is 20 ns, the flip-flop propagation time is 25 ns, the propagation delay in combination circuit is 15 ns. The total is 60 ns which is a lower limit for the clock period. The max clock frequency Fmax = 1/60 ns =(1000/60)x106 ≈ 16 MHz. 3. Preliminary Lab 1. Draw the state diagram for the sequence of states obtained from your ID number. 2. Obtain the equations for flip-flop input excitation. 3. Obtain the circuit diagram and verify the circuit behavior with timing diagram (Figure 6). 4. Sketch the layouts for the chips to be used in the experiment, show interconnects to assist in the circuit assembly and debugging interconnect errors. In is recommended to assemble the counter on the small breadboard in advance. 5. Calculate the max clock frequency using timing specification of 74LS174 and multiplexers. 4. Experiments 1. Assemble the counter (if it was not done at home) and verify the counting sequence with a pushbutton serving as a manual clock or use TTL signal generator with a period in order of 1 second. Fix erroneous interconnects (if any). 2. Obtain the counting sequence and SYNC signal on the logic analyzer with the counter outputs grouped into a bus, and SYNC signal can be used for synchronization. Show the results to a TA. 5. Report The report should contain a short description of the problem, the approaches to solution, a complete state diagram with unused states and output values for the final design, the circuit diagram, simulation of the timing diagram, explanation of the results and a brief summary. 6. TA statement of the lab completion Lab Section_____ Names________________________________________________________ ____________________________________________________________________________
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