GREEN COMPUTING
Phase-I
What is Green computing?
Green computing includes the implementation of best practices, such as energy efficiency central processing units (CPUs), peripherals and servers. In addition green technology aims to reduce resource consumption and improve the disposal of electronic waste (e-waste).

Energy star:
Energy Star (trademarked ENERGY STAR) is an international standard for energy efficient consumer products originated in the United States. It was created in 1992 by the Environmental Protection Agency and the Department of Energy. Since then, Australia, Canada, Japan, New Zealand, Taiwan and the European Union have adopted the program. Devices carrying the Energy Star service mark, such as computer products and peripherals, kitchen appliances, buildings and other products, generally use 20–30% less energy than required by federal standards. In the United States, the Energy Star label is also shown on Energy Guide appliance label of qualifying products.

Phase-II
Main Modules of Green Computing

Emerging Memory:
Emerging technologies are those technical innovations which represent progressive developments within a field for competitive advantage converging technologies represent previously distinct fields which are in some way moving towards stronger inter connections and similar goals.
Bamboo:
It is becoming increasingly popular for making casings for computers and peripherals.
Recyclable Plastics:
Computers are constructed from non-recyclable plastics i.e. recyclable polycarbonate resin.
Eco-friendly flame retardant:
There are flame retardant silicone compounds available that are flame retardant and completely non-toxic.
Inventory management:
Reducing the quality of both hazardous materials used in the process and the amount of excess raw material.
Volume reduction:
Remove hazardous portion waste from non hazardous portion. EMERGING MEMORY 1. Low-Power Electron Devices 2. Low-Power Spin Devices 3. Low-Power SRam. 4. Low-Power DRam. 5. Low-Power NV-Ram 6. One Chip Power Gating Technique. 7. Low-Power Process with NV-Ram.
Low-Power Electron Devices: Low-power electron devices are extremely important in terms of energy saving by taking advantage of the information and communication technology (ICT) as well as power reduction of electronic apparatuses themselves. Although the low-power approaches should be done in every technological aspect of the ICT technology, the low-power electron device (CMOS) technology is especially important because this technology is in a core part of many CT apparatus technology.
The issues regarding the transistor miniaturization that has enabled both reducing power and enhancing functionality of CMOS large-scale integrations (LSIs) for about 40 years, and possible solutions regarding device structure and materials are reviewed.
CMOS Miniaturization and Issues for Low Power
CMOS Miniaturization and Scaling Rule

Low-Power Spin Devices:
The spin of an electron is the elementary microscopic building block of magnets which in current microelectronic technologies are utilized for information storage and retrieval. A new area of technology has been emerging recently that makes use of the natures of electrons, spin, and the fundamental electronic charge. This emerging technology is known as spintronies.
Spintronics emerged from discoveries in the l980s concerning spin-dependent electron transport phenomena in solid-state devices. The most important finding is the independent discoveries of the giant magneto-resistance (GMR) effect by Albert Fert and Peter Grunberg in I988. It occurs in multilayer structures where a ferromagnetic thin film such as Fe and a non-magnetic thin film such as Cr are deposited alternately, and the resistance Rp is small when the magnetization directions of the ferromagnetic layers are parallel and the resistance Rap is large when the magnetization directions of the ferromagnetic layers are antiparallel. Low-Power SRam:
This research explores the challenges arising from low voltage operation of standard SRAMs and reviews numerous proposed bit—cells by various researchers in past years. Although technology scaling has enabled a dramatic increase in functionality and complexity in integrated circuit (IC) design, one major negative side effect of technology scaling is that leakage power increases significantly from one technology generation to the next and represents one of the main challenges in contemporary system-on-chip (SoC) integration ll. 3]. In addition. the demand for power sensitive designs has grown significantly, mainly due to the fast growth of battery operated portable applications. such as notebook computers, personal digital assistants (PDA). smart phones. Etc .To design integrated systems. significant attention has been given to the design of medium performance and low power circuits (tens to hundreds of MHz clock rates). Some popular methods include voltage scaling, switching activity reduction, architectural techniques, and device sizing and new device structures. Voltage scaling is one of the most effective techniques for power reduction in digital VLSI design with some limitations like, loss of static noise margins, current fluctuations due to process variations and limitations on the number of cells connected to a single bit-line. These methods are applicable in medium performance systems which are not suitable for portable battery operated gadgets. Many researchers have suggested operating a circuit in sub-threshold region to reduce power consumption in the range of micro watt. This can be achieved by fix the supply voltage close to the device‘s threshold voltage which is known as the near-threshold regime. The sub- threshold logic development elevated the need for embedded memories, primarily SRAMS. Researchers have developed several methods for reducing the standby voltage of SRAMs. so the circuit can be run at the optimum speed and then sleep after complete operation to reduce the leakage power consumption. These methods are not suitable for SRAM where data is to be stored for some specific time duration. Therefore reducing the leakage power during active region is necessary. This requirementhas led to design SRAM in sub-threshold regime.

Low-Power Dram: Dynamic random access memory (DRAM) is a volatile random access memo and the memory cell consists of a cell transistor and a capacitor. The cell transistor is used to connect a storage node (N) and a data-line (DL) by activating a word-line (WL), while the capacitor, connected between N and the plate (PL), stores information. The signal charge stored in the capacitor is reduced by the leakage currents of the memory cell and this reduction causes data loss. To avoid this a refresh operation that will be explained later is periodically required and the refresh interval is determined by storage node capacitance. The signal voltage developing on the floating DL after WL is activated is also determined by Cs. Therefore, higher capacitance (>20 fF) is crucial to achieving low standby power and stable sensing operation.
Due to the simple cell structure. a higher capacity DRAM with a smaller chip size has been developed by using an advanced technology node and reducing the size of the memory cell. To maintain Cs, high-k dielectric materials such as Ta3O5 , A1303/HfO , ZrO3/Al3O3 and SrTiO3 along with new capacitor structures have been developed. Cell transistors such as recess-channel-array transistors (RCATs) and vertical transistors have also been developed to suppress the short channel effect and to achieve low leakage current and smaller memory cells. Reducing noise is the key to achieving 6F: and 4F: cells (F: minimum feature size). `
Low-Power NV-Ram:
Memories are key devices in information communication equipment such as servers, network routers, switches, and mobile devices to improve their functions and performance. Conventional memories can be categorized into two groups. One is known as random access memory (RAM), for example. static RAM (SRAM) and dynamic RAM (DRAM). These RAMs are volatile, but they have advantageous features including infinite write cycles and fast read and write operations. Therefore, they are suitable for the main memory of electrical equipment. The other category is read-only memory (ROM). ROM is used to store data and/or source code of systems. Several kinds of memory technologies for ROM exist. The most common ROM is Flash memory. A NAND-type Flash memory is the densest kind of semiconductor memory and is now being used as the storage device in small form factor hard disk drives (HDDs).
However, some novel memory technologies that have the merits of both RAM and ROM have been proposed in recent years. Such memories are called nonvolatile RAM (NV-RAM) because they have both non-volatility and applicability for RAM operation. NV-RAM can potentially replace both ROM and RAM in information technology equipment, as shown in Fig. 6.1. The system advantages brought by introducing NV-RAM . In novel memory technologies and circuit techniques for nonvolatile RAM are described. First of all, several memory technologies that can be applied as nonvolatile RAM are compared from the viewpoint of performance. After that, spintransfer torque RAM (STT-RAM) a type of magnetic RAM (MRAM), is discussed as an example of NV-RAM. Then basic circuit techniques for STT-RAM are disclosed. In addition, some memory array circuit technologies used to achieve high-density chips are described. Finally technologies to realize memory chips using a process node of <30 nm generation are introduced as future technologies.

Low-Power Process with NV-Ram:
A simple method of keeping devices turned off is proposed in addition to low-voltage technology such as sub-l-V technology. That is we need to keep devices in a turned state as long as possible when not in use, but we need to turn them on instantly when they are required to perform optimally. We usually do this in daily situations as we are faced by increasing concerns with limited resources. But we also do it for greater efficiency. However, it is not easy to apply this concept to actual IT equipment. Although practical instant ON and OFF functions should be implemented in this approach. they require fundamental revisions to the computing architecture. This predicament also raises the need for an approach to combine power-control and computing technologies (information processing technology). To form a basic technology that will generate social innovation in our daily lives.
The key to achieving this is that any internal states of computation should be memorized at any time without consuming any power. IT equipment can only be turned on instantly and resume a state prior to interruption in this way. Thus, nonvolatile RAMs are essential components and are defined here as having an infinite number of fast write and read operations in their lifetimes with simultaneous non-volatility. Furthermore, these memories are free of soft-error due to radiation. This approach is an adaptive solution to power control in wide temporal and spatial domains. An instantaneous on/off system using nonvolatile RAMs is described in this chapter (again note that “RAMs" should have the feature of an infinite number of fast write and read operations in their lifetimes).

One Chip Power Gating Technique:
A buffer amplifier for higher driving capability with low static power is designed telescope-cascade based buffer amplifier for high resolution application in electronic display devices like TFT-LCD etc. The buffer amplifier is best suited for electronic devices for achieving the fast speed capabilities, high resolution, and low power dissipation play a significant role for essentially determine the speed, resolution, voltage swing and power consumption of the buffer amplifier circuit. A common mode rail to rail class-AB buffer amplifier use comparator circuit inside it to enhance the slewing capabilities with limited power consumption and it draw a very small quiescent current during static operation. The capacitive load at the output of the circuit is responsible for reduced distortion for swing characteristics. In electronics, a comparator is a device that compares two voltages or currents and switches its output to indicate which is larger that is commonly used in analog to digital converters (ADCs). In the buffer constraints to increase the buffer space irrotically because the buffer depth is also increases with the maximum number of allowed circulation of the data in the buffer decreases. The power gating technique is most probably used to reduce the power consumption, low leakage, high speed and higher driving capability. The power gating technique is used to apply the reduction of power by using sleep transistor. Power gating technique is a technique is used in integrated circuit design to reduce power consumption, by shutting off the flow of current to blocks of the circuit that are not currently in use. This technique is mostly used to reducing stand by or leakage power. Power gating uses low leakage PMOS transistors as header switches to shut off power supplies to parts of a design in standby or sleep mode. NMOS footer switches can also be used as sleep transistor. Inserting the sleep transistors splits the chip’s power network into a permanent power network connected to the power supply and a virtual power network that drives the cells and can be turned off. Typically high V sleep transistors are used for power gating, in a technique also known as multi threshold Cmos (MTCMOS). The sleep transistor sizing is important design parameters. Power gating has the benefit of enabling Iddq testing. In this paper, we present the benefits and costs of the power gating technique in terms of power, area, and performance. This technique is used for saving leakage leakage power by shutting off the idle blocks. In this technique negative effects of power gating may overwhelm the potential gain and may make the technique not worth the efforts. Power gating techniques is also used for data retention means of storage, access, and encryption.