CCE220-Section B: Digital Systems
Mr. Michel Owayjan (Beirut)
AMERICAN UNIVERSITY OF SCIENCE & TECHNOLOGY
FACULTY OF ENGINEERING DEPARTMENT OF COMPUTER AND COMMUNICATIONS ENGINEERING
CCE 220: Digital Systems
Spring Term 2013-2014
INSTRUCTOR CLASS HOURS Mr. Michel Owayjan MWF Room: 3:00 pm - 3:50 pm 404, Block B
OFFICE HOURS
M-W-F 2:00 pm - 3:00 pm T-TH 12:00 am - 1:00 pm Otherwise by appointment Room: 805, Block A
COURSE OBJECTIVES This is a sophomore-level course which addresses the fundamentals of digital systems needed to develop the ability of the student in understanding the concepts related to this area of engineering. The objective is to train the students on the various tools used to solve problems related to the design of digital systems. These include: i) binary number system; ii) conversion between number systems; iii) Boolean algebra; iv) logic gates; v) Karnaugh maps; vi) combinational and sequential logic; vii) SSI and MSI design; viii) flip-flops; ix) counters; x) registers; xi) memories; and, xii) state machines. The problem solving and experimental skills of the student in the above areas are enhanced by a co-requisite Laboratory Course held on a weekly basis. COURSE PREREQUISITES CSI 201: Introduction to Computing
PREREQUISITES BY TOPICS The student should have the general background in computers and algebra. COURSE CREDITS 3 Credit Hours
INSTRUCTION TECHNIQUE Lectures will be used predominantly. These will be supported by problem sets and design projects, which include virtual instrumentation projects using LabVIEWTM. REQUIRED TEXT Marcovitz A.B. Introduction to Logic Design, Third Edition. McGraw Hill, 2010. REFERENCES Marcovitz A. B. Introduction to Logic Design, 2/E. McGraw-Hill, 2005. Morris Mano. Digital Design, 3/E. Upper Saddle River, NJ, USA: Prentice Hall. Floyd. Digital Fundamentals, 7/E. Upper Saddle River, NJ, USA: Prentice Hall.
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CCE220-Section B: Digital Systems
Mr. Michel Owayjan (Beirut)
GRADE DISTRIBUTION This course involves a number of didactic activities, ranging from lectures, term papers, project assignments, and presentations to unannounced quizzes, exams, and the midterm and final exams. All of these attributes of the course are intended to help the student in developing his/her understanding of the material covered in CCE 220 and in providing the department and the course instructor with information on how the student is performing. Consequently, all of these activities are considered to be vital and will be taken into consideration while assigning grades at the end of the term. When the student is being assigned a course grade, it is imperative that this grade accurately reflects the student’s level of achievement and his/her mastery of the material covered in CCE 220. An approximate breakdown of the weighting that will be used in making this assessment is as follows: Lab Class Attendance Homework Quizzes and Class Participation Class Exams Exam 1 Exam 2 Exam 3 Exam 4 Final Exam LAB ATT HWK QZS EX1 EX2 EX3 EX4 FIN 20% 5% 5% 10% 10% 10% 10% 10% 30%
Note: Three out of the four exams will be counted towards the final course grade based on the highest grades attained. No make-up exams are allowed. Late assignments will be dealt with according to the distributed course rules and regulations, which are governed by the Department of Computer and Communications Engineering. Under severe conditions, only the Final Exam is allowed to be petitioned; however, students have to realize that in the event that a make-up Final Exam is granted, it would be unjust that the grantee becomes privileged over his/her fellow colleagues in terms of extra-time to prepare for the exam and in developing an idea about the contents of the exam. Accordingly, the make-up Final Exam will carry an increased level of difficulty of at least 20% from the regular exam. LEARNING OUTCOMES At the end of the course, the student should be able to do the following: Differentiate between digital and analog quantities and waveforms. Convert a number between base-n to base-m. Apply laws and rules of Boolean algebra to simplify Boolean expressions. Apply Karnaugh map minimization techniques to simplify Boolean functions. Derive Boolean functions and truth tables given a logic diagram. Design digital combinational circuits using SSI and MSI logic. Analyze and design sequential circuits. Discuss the operation of different types of memory devices. ATTENDANCE For legitimate reasons only, a student is allowed to absent him/herself for a maximum of 6 contact hours from the course lectures and the tutorial and laboratory sessions. However, any absence of more than one session will be counted toward the 5% evaluation of the course grade. Absences beyond the specified maximum limit will result in an automatic AW in the course and possibly other disciplinary measures. An unexcused absence from an
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CCE220-Section B: Digital Systems
Mr. Michel Owayjan (Beirut)
unannounced quiz will result in a zero on that quiz. Should the student be absent from a lecture during which a problem set or a project assignment is due, it is the duty of the student to make certain that the homework assignment is handed in on time. Failure to do so will incur a penalty on that assignment’s grade. ACADEMIC INTEGRITY The student should get familiar with the Course Rules and Regulations of the Department of Computer and Communications Engineering at AUST. These are compiled and distributed to the student at the beginning of every academic term. In particular, the student should be aware that plagiarism, abuse of laboratory facilities, and other sorts of academic dishonesty are not tolerated and can result in unsympathetic penalties. The Department of Computer and Communications Engineering (CCE) fully acknowledges the potential significance of students studying together. In this sense, the CCE Department does not have any reservation to this kind of collaboration, as long as all contestants are involved in all facets of the work, and not with each individual contributing to a fraction of the assignment. Specifically, when a student submits an assignment with his/her name on it, the CCE Department takes it for granted that the details presented in the assignment are entirely the student’s own work, and that this student has substantially participated in the creation of this work. If a portion of the work has been conceived by collaborative work, that section should be highlighted and the names of the students involved in this collaboration should be listed next to that section. Note: No snacks or beverages, including water bottles, are allowed in the classroom. PROFESSIONAL SOCIETIES Institute of Electrical and Electronics Engineering: http//www.ieee.org/index.html COURSE OUTLINE BY TOPIC The day-to-day topics to be covered in the table below may be adjusted as the subject proceeds, but all examination dates are fixed, and problem set due dates are unlikely to change.
SYLLABUS (1 Lecture) INTRODUCTION (3 Lectures)
Week No. 1 1-2
Day M
Date (MM/DD/YYYY) 02/17/2014
Review of Number Systems Review of Number Systems The Design process 2-4
W F M
02/19/2014 02/21/2014 02/24/2014
SWITCHING ALGEBRA (7 Lectures)
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Definition Basic Properties Manipulation of Algebraic Functions Implementation of Functions using AND, OR, and NOT Truth Tables to Algebraic Expressions Karnaugh Maps 4
W W F M W F M W W F
02/26/2014 02/26/2014 02/28/2014 03/03/2014 03/05/2014 03/07/2014 03/10/2014 03/12/2014 03/12/2014 03/14/2014
EXAM No. 1 (1 Lecture) Complement and product of sums NAND, NOR, XOR Simplification of Algebraic Expressions
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CCE220-Section B: Digital Systems
MORE SIMPLIFICATION TECHNIQUES (3 Lectures)
Mr. Michel Owayjan (Beirut) 5 M W F
6-7
Karnaugh Maps and Minimization Karnaugh Maps and Minimization Design Problems Solved in Class
03/17/2014 03/19/2014 03/21/2014
SOLVING LARGER PROBLEMS (6 Lectures)
-
Delay in combinatorial circuits Adders Decoders Multiplexers Gate Arrays, ROM’s, PLA’s Solving Design Problems (in Class) 7 8-11
M W F M W W F
03/24/2014 03/26/2014 03/28/2014 03/31/2014 04/02/2014 04/02/2014 04/04/2014
EXAM No. 2 (1 Lecture)
SEQUENTIAL SYSTEMS (8 Lectures)
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Latches and Flip Flops Latches and Flip Flops Design Process of Sequential Systems Analysis of Sequential Systems Flip Flop Design Techniques Design of Synchronous counters 10
M W F M W W F M W 11-12 F M W F 13
13-15 W F M
04/07/2014 04/09/2014 04/11/2014 04/14/2014 04/16/2014 04/23/2014 04/25/2014 04/28/2014 04/30/2014
EXAM No. 3 (1 Lecture)
Design of Synchronous Counters Solving Design Problems (in Class)
SOLVING LARGER SEQUENTIAL PROBLEMS (4 Lectures)
-
Counters Counters Shift Registers Shift Registers
05/02/2014 05/05/2014 05/07/2014 05/09/2014 05/12/2014
EXAM No. 4 (1 Lecture)
SPECIAL DESIGN PROBLEMS SOLVED IN CLASS (4 lectures) - Special counters - Special counters - Special counters
M
-
Sequence Detectors Introduction to Asynchronous Circuits Revision Revision Revision 15
W F M W F Sa Su M T
05/14/2014 05/16/2014 05/19/2014 05/21/2014 05/23/2014 05/26/2014 05/28/2014 05/30/2014 05/31/2014 06/01/2014 06/02/2014 06/10/2014
READING PERIOD
FINAL EXAM WEEK
16-17
DISCLAIMER: Changes may be performed to the above syllabus without any prior notification.
Copyright © 2013-2014 American University of Science & Technology – Faculty of Engineering – Department of Computer and Communications Engineering. All rights reserved.
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CCE220-Section B: Digital Systems
Mr. Michel Owayjan (Beirut)
PROBLEM SETS
All problem set assignments will be handed in class one week prior to their submission date. Concurrently, a copy of each assignment will be placed on closed reserve in the university library, Block B, 8 th Floor. Problem Set No. 1: TBA. Problem Set No. 2: TBA. Problem Set No. 3: TBA Problem Set No. 4: TBA Problem Set No. 5: TBA Problem Set No. 6: TBA Problem Set No. 7: TBA Problem Set No. 8: TBA
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