Transistors and Logic Circuits

Transistor voltage in control high allows current to flow -switch is closed (on) control low stops current flow switch is open (off)

control

voltage out

1

NOT Gate One transistor
V (high voltage) Out 0 1 In 0 1 In = high, switch is closed so current flows to ground Out is low. In = low, switch is open so current flows to Out Out is high.

NOR Gate Two transistors
V (high voltage) Out In 1 In 1 = 1, Out = 0 In 2 = 1, Out = 0 In 1 = 0 In 2 = 0, Out = 1

In 2

2

NAND Gate Two transistors
V (high voltage) Out In 1 In 1 = 1, In 2 = 1, Out = 0 In 2 In 1 = 1 In 2 = 0, Out = 1

AND Gate Three transistors
V (high voltage) V Out In 1

In 2

3

Logic Gates
In 0 1 In 0 1 In 0 1 In Out AND Gate

Out

OR Gate

Out

XOR Gate

Out

NOT Gate

Logic Circuit -- 4 input Multiplexor
0 1 Out 2 3 In

0 Control 1

1 0

4

Logic Circuit Puzzle 1
Input Binary Numbers A, B
A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7

Out

8 bit Comparator Output 1 if A = B Otherwise 0

Logic Circuit Puzzle 2
3 bit Decoder Select Output Line
In 2 In 1 In 0 D0 D1 D2 D3 D4 D5 D6 D7

5

Programmable Logic Array
• Any Logic Truth Table can be implemented • Uses block of AND gates followed by block of OR gates • Programmable
– once – many times

• Used for implementing different circuits

Truth Table to Normal Form
A 1 1 1 1 0 0 0 0 B C expression 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 and B and (A 0 A and B and C 1 A and B and ~C 1 A and ~B and C 1 0 ~A and B and C 1 0 0 0 C) or (A and B and ~C)
B and C)

or (A and ~B and C) or (~A and

6

PLA

Input

AND Gates

OR Gates

Output

PLA
In 0 In 1 In 2

What is Out 1?

Out 0

Out 1

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Normal Form to Truth Table
A 1 1 1 1 0 0 0 0 B 1 1 0 0 1 1 0 0 C 1 0 1 0 1 0 1 0 expression A and B and C 1 0 Odd Parity 0 1 A and ~B and ~C 0 ~A and B and ~C 1 ~A and ~B and C 1 0

(A and B and C) or (A and ~B and ~C) or (~A and B and ~C) or (~A and ~B and C)

PLA, Alternate Representation
AND Block uses DeMorgan Equivalence A and B = not (not A or not B)
V

OR Block uses direct or

8

PLA, Alternate Representation
A B C Outputs 0 1 2 3 Unused

Unused

PLA, Alternate Representation

Burned out to disconnect

9

PLA "Don't Cares"
A 1 1 1 1 0 0 0 0 B 1 1 0 0 1 1 0 0 C 1 0 1 0 1 0 1 0 exp 1 1 1 0 1 0 0 0 A 1 1 1 0 0 0 0 B 1 0 0 1 1 0 0 C X 1 0 1 0 1 0 exp 1 1 0 1 0 0 0

X = Don't Care

PLA "Don't Cares"
A B C A B C Reduce number of PLA lines used for expression

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