Encounter® Conformal® Equivalence Checking Reference Manual
Conformal ASIC, Conformal Ultra, and Conformal Custom Product Version 9.1 October 2009

© 1997– 2009 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, USA Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All other trademarks are the property of their respective holders. Restricted Print Permission: This publication is protected by copyright and any unauthorized use of this publication may violate copyright, trademark, and other laws. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. This statement grants you permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used solely for personal, informational, and noncommercial purposes; 2. The publication may not be modified in any way; 3. Any copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement; and 4. Cadence reserves the right to revoke this authorization at any time, and any such use shall be discontinued immediately upon written notice from Cadence. Patents: Cadence Product Encounter™ Equivalency Checker described in this document, is protected by U.S. Patent [6,842,884] Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

Encounter Conformal Equivalence Checking Reference Manual

Contents
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15

Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2 Command Reference

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18 20 22 24 27 29 31 33 35 36 38 39 41 43 45 47 49 50 52 55 57 60 62 64

Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wildcards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using UNIX Commands with Conformal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSTRACT LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD IGNORE RTLCHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD LIBRARY INSTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD MAPPING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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ADD NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ADD NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADD NOTRANSLATE LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADD NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ADD OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ADD OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADD PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ADD PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ADD PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADD PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADD PRIMARY INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ADD PRIMARY OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ADD RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ADD RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADD SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADD SEQ_CORR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ADD SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ADD TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 ANALYZE ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ANALYZE DATAPATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 ANALYZE HIER_compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 ANALYZE IMPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 ANALYZE MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 ANALYZE MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ANALYZE NETLIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 ANALYZE NONEQUIVALENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 ANALYZE POWER ASSOCIATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 ANALYZE RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 ANALYZE SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 ASSIGN PIN DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 BACKWARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 BREAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 CHANGE GATE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 CHANGE NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 CHECK LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 CHANGE NET TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

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CLOSE SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMIT CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMIT LIBRARY INSTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONFORMAL NEWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONTINUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPY MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE IGNORE RTLCHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE LIBRARY INSTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE PRIMARY INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

148 149 151 152 156 157 158 160 161 162 164 166 167 169 170 171 172 173 174 175 176 177 179 180 182 184 185 186 187 188 189 190 191 193 194 195

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Product Version 9.1

Encounter Conformal Equivalence Checking Reference Manual

DELETE PRIMARY OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE SEQ_CORR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIAGNOSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ELABORATE DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLATTEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FORWARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GENERATE ROM PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HELP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INFO SESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INVERT MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LICENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAP KEY POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOS2BUFIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOVE INSTANCE DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPEN SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRINTENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ FSM ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ LEF FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ MEMORY PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ PATTERN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ ROM PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

196 197 199 200 201 202 204 206 209 210 213 214 216 217 219 221 223 224 226 227 231 232 234 235 236 238 239 241 243 258 260 261 269 271 272 275

October 2009

6

Product Version 9.1

Encounter Conformal Equivalence Checking Reference Manual

READ RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ TESTCASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REDUCE MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REMODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REMOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT COMMAND PROFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT COMPARE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT COMPARE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT CPF LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT DATAPATH OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT DATAPATH RESOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT DESIGN DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT DESIGN SIMILARITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT FLOATING SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT KEY POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT LIBRARY DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT LOWPOWER DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

276 278 279 281 285 287 288 289 291 293 294 298 300 301 302 303 304 305 307 308 309 311 313 317 319 320 321 322 323 324 326 328 329 332 336 338

October 2009

7

Product Version 9.1

Encounter Conformal Equivalence Checking Reference Manual

REPORT MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MULTIPLIER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PARTITION RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PIN DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PRIMARY INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PRIMARY OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PULSE GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT REMOVED INSTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT SEQ_CORR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT STATISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT TESTCASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT TEST VECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT UNMAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT VERIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

339 342 344 345 347 348 349 350 351 352 353 354 355 356 358 359 361 362 363 364 365 366 367 368 370 371 373 374 375 378 380 382 385 387 388 389

October 2009

8

Product Version 9.1

Encounter Conformal Equivalence Checking Reference Manual

RESOLVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESTORE SESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RUN HIER_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RUN PARALLEL COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RUN PARTITION_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAVE DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAVE HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAVE SESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET ANALYZE OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET_ATTR INPUT_PRAGMA_KEYWORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET CASE SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET COMMAND PROFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET COMPARE EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET COMPARE OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET CPU LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET DATAPATH OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET DIRECTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET DOFILE ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET DW DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET EXIT CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET FLATTEN MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET FPGA TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET GATE REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET HDL DIAGNOSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET HDL OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET LOG FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET LOWPOWER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET MAPPING METHOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET MOS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET MULTIBIT OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET MULTIPLIER IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET MULTIPLIER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

390 392 393 397 399 400 401 402 403 404 409 411 413 414 415 416 418 420 423 426 427 429 430 436 437 439 440 441 446 450 452 456 460 461 462 465

October 2009

9

Product Version 9.1

Encounter Conformal Equivalence Checking Reference Manual

SET NAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET PARALLEL OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET PATTERN MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET RETIMING OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET ROOT MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET RULE FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET RULE HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET SCREEN DISPLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET SPICE OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET STATETABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET SYNTHESIS_OFF_COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET SYNTHESIS_ON_COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET SYSTEM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET UDP PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET UNDEFINED CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET UNDEFINED PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET UNDRIVEN SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET WIRE RESOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET X CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET XC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SETENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUBSTITUTE BLACKBOX MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUBSTITUTE BLACKBOX WRAPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCLMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIQUIFY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VALIDATE CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VALIDATE LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPXMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE BLACKBOX WRAPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE HIER_COMPARE DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

466 473 478 479 480 481 482 485 486 488 489 490 491 492 493 495 496 497 498 500 501 502 503 505 506 507 511 513 514 518 521 522 523 525 527 529

October 2009

10

Product Version 9.1

Encounter Conformal Equivalence Checking Reference Manual

WRITE LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE MEMORY PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE PARTITION DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

536 537 539 541 543

3 ECO Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADD ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD ECO LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD ECO PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD SPARE CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANALYZE ECO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLY PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE ECO PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE SPARE CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAP ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPTIMIZE PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ECO CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MISMATCH PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT SPARE CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE ECO DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

545 546 547 548 550 552 553 555 557 558 559 560 561 562 566 567 568 569 570 571

4 Modeling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F1 F2 F3 F5 F6 .................................................................. .................................................................. .................................................................. .................................................................. ..................................................................
11

573 574 575 576 577 578

October 2009

Product Version 9.1

Encounter Conformal Equivalence Checking Reference Manual

F7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F14.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F34.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F34.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F34.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614

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F51 F52 F53 F54 F55 F56 F57

................................................................. ................................................................. ................................................................. ................................................................. ................................................................. ................................................................. .................................................................

615 616 617 618 619 620 621

5 Tcl Command Entry Mode Support

. . . . . . . . . . . . . . . . . . . . . . . . . . . 623 625 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 649 650 651

find . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_compare_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_compare_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_exit_code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_current_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_fanins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_fanouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_gate_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_gate_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_gate_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_handle_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_keypoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_map_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_module_definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_parent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_primitive_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_root_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_unmap_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . set_current_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

October 2009

13

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echo_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_license_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_version_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . objtype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

652 653 654 655 656 657 659

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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About This Manual
This manual documents commands, HDL rule checking messages, and modeling messages for the following Encounter® Conformal® Equivalence Checking solutions:
■

Conformal Extended Checks Conformal Extended Checks has equivalency checking capabilities with functional checks for ASIC design flows.

■

Conformal Ultra Conformal Ultra includes Extended Checks and extends equivalency checking capabilities to datapath synthesis and layout.

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Conformal Custom Conformal Custom includes Conformal Ultra and extends equivalency checking capabilities to digital custom logic and custom memories.

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Conformal LowPower Conformal LowPower enables low power equivalence and functional checks for isolation cells, level-shifter cells, and retention-register cells.

Audience
This manual is written for experienced designers of digital integrated circuits who must be familiar with RTL, synthesis, and design verification; as well as having a solid understanding of UNIX and Tcl/Tk programming.

Related Documents
For more information about the Conformal family of products, see the following documents. You can access these and other Cadence documents with the Cadence Help online documentation system. For a complete list of documents provided with this release, see the CDSDoc library.

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Encounter Conformal Equivalence Checking User Guide Describes how to install, configure, and use Conformal to verify RTL, gate, or transistorlevel designs.

Conventions
Convention Bold Case UPPERCASE < > [ ] | \ ... * Definition Indicates the command name. Indicates the required minimum character entry. Indicates required arguments. Do not type the angle brackets. Indicates optional arguments. Do not type the square brackets. Indicates a choice among alternatives. Do not type the vertical bar. The backslash character (\) at the end of a line indicates that the command you are typing continues on the next line. Indicates multiple entries of an argument. Indicates that the entry can use the wildcard (*) to represent zero or more characters.

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2
Command Reference
This chapter describes the Encounter® Conformal® commands. The commands are presented in alphabetical order. This chapter also includes the following sections:
■ ■ ■

Command Syntax on page 18 Wildcards on page 20 Using UNIX Commands with Conformal on page 22

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Command Syntax
■ ■

Conformal commands are not case sensitive. For every Conformal ADD command, there are corresponding DELETE and REPORT commands. For example: ADD OUTPUT EQUIVALENCES DELETE OUTPUT EQUIVALENCES REPORT OUTPUT EQUIVALENCES

■

Conformal commands adhere to the “3-2-1” rule, which reduces the number of characters you must type.
❑ ❑ ❑

3: Type the leading three characters of the first term. 2: Then type the leading two characters of the second term. 1: End with the leading character of the third term.

In some cases, you must use more characters to resolve ambiguity. In this manual, the minimal sets of characters you must type are shown as uppercase letters in the syntax. When you use the 3-2-1 rule in conjunction with the syntax guide to resolve any possible ambiguity, you reduce the number of characters in a command, as the following example shows: ADD OUtput Equivalences becomes add ou e
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Reduce the number of characters you type for command options to the characters shown in uppercase in the syntax, as the following example shows: add output equivalences out10 out20 -module sub_mod1 -revised becomes add ou e out10 out20 -m sub_mod1 -r

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Searching the Help Database for Specified Strings Use the SEARCH command to search s the Help database of commands and options for matches to strings you specify. Viewing TCLmode Help Information The HELP command also displays a list of Conformal TCLmode commands. While in TCLmode, use the following syntax:
HELp

To view command usage for a specific command, use the HELP command followed by the command name.
HELp [command_name]

System prompt and command example:
TCL_SETUP> help set_current_module

Viewing Conformal UNIX-Style Man Pages Conformal includes a man directory housed in: /doc/mann/. Important Observe the following requirements for viewing UNIX-style man pages:
❑ ❑ ❑

You must type the entire command name. Do not apply the 3-2-1 rule (described below). Do replace each space in the command name with an underscore ( _ ).

1. To access this resource from your UNIX shell, add the following variable:
% setenv MANPATH “/doc:$MANPATH”

2. Type the following: man command_name

For example: man read_design man set_system_mode

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Wildcards
On an as-needed basis, Cadence adds wildcard pattern-matching support to Conformal commands. The syntax convention that alerts you to wildcard support is the asterisk (*). If you use a pattern where a filename or design object is expected, Conformal Equivalence Checker expands the pattern using the same conventions as in the UNIX shell.
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Triggering pattern matching for filenames To trigger pattern matching for filenames, a string must include at least one asterisk (*), question mark (?), or a pair of square brackets ( [ ] ).

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Triggering pattern matching for design objects To trigger pattern matching for design objects, a string must include at least one asterisk (*) or question mark (?).

In arguments that are considered patterns, the following characters have special meaning: ^, {, }, [, ], ?, *. The dash (-) also has special meaning when it falls between square brackets. Note: When you use wildcards for design objects, a wildcard can match a string that includes the hierarchical delimiter (/). For example, the pattern *[10] matches the design object a/b/c[10]. When you use wildcards for filenames, every wildcard applies to part of a single directory or filename (this convention is the normal UNIX convention). For example, the pattern *.v does not match the filename a/b/c.v.

Special Characters for Filename and Design Object Pattern-Matching Wildcard Character ? Definition Match any single character. Example a?c matches: aac, abc, a4c, a?c * Match any (possibly empty) string. a*c matches the following: ac, abc, a*c

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Special Characters for Filename and Design Object Pattern-Matching Wildcard Character [ ] Definition Match any single character listed between the square brackets: “[” and “]”. Example For filenames: a[145] matches the following: a1 a4 a5 For design objects: a*[145] matches the following:

That is, “[” followed by characters and If the first character is “^”, Conformal Equivalence Checker “]” matches any single character not listed between the brackets. If the list shown between the brackets includes x-y, Conformal Equivalence Checker matches all characters in the range x–y.

ab1 a34 To match square brackets, you must at5 include the escape character a*\[145\] matches the following: immediately preceding the square ab[145] bracket. a3[145] To be matched, the characters “-” at[145] and “]” must appear first in the list (possibly after ^). Note: For design objects, recall that a string triggers pattern matching with an asterisk or question mark. In those cases, this convention applies. ^ At the beginning of the pattern, the character “^” negates the result of the match: Matches only the character that follows the “\” character. ^a* matches any name that does not begin with a. a\[10] matches the following: a[10] But it does not match: a1 a0

\

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Special Characters for Filename and Design Object Pattern-Matching Wildcard Character {p1,p2,…} Definition Example

Matches any string matched by any design/{top,sub{5,11}}/*.v of the sub-patterns listed. matches the following: design/top/a.v design/sub5/b.v design/sub11/c.v Braces can nest. a/{d{e,f},g{h,i}}_0 matches the following: a/de_0 a/df_0 a/gh_0 a/gi_0

Using UNIX Commands with Conformal
To execute a UNIX command from within LEC or an LEC command script, start the line with an exclamation point “!” or with the SYSTEM command. When you execute commands in this way, they display to the standard output, and LEC records them in a log file, if one is active.

Using the -all Option
This option applies within the given defaults. For example, the syntax for the ADD OUTPUT EQUIVALENCES command is as follows:
ADD OUtput Equivalences [-Invert ] [-ROot | -Module | -All] [-Golden | -Revised | -Both]

In the above syntax, -golden is a default. Therefore, if you type the command with primary pin names and the -all option, but no other option, this command specifies output pin equivalences on all output boundary module pins in the Golden design.

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Using the -both Option
When you use this option in conjunction with a specific name (for example, a pin name), that name must appear in both designs. Otherwise, LEC returns an error message. For example, the syntax for the ADD PIN EQUIVALENCES command is as follows:
ADD PIn Equivalences [-Invert ] [-ROot | -Module |-All] [-User | -Hier] [-Golden | -REvised | -Both]

Notice -both in the above syntax. If you specify three primary pins (for example, a1, a2, and a) and the -both option; all three pin names must exist in both the Golden and Revised designs. If they do not, LEC returns an error message. If you specify a1, a2, a and include the -revised option; LEC applies equivalence to the pins in the Revised design only (even if these three pins also exist in the Golden design).

Saving the Command’s Output to a File
To save the command’s output to a file, Cadence recommends using the command line > operator. This works for all Conformal commands. For example, to save the default output of the REPORT GATE command to a file named gate.out, you would run the following: report gate > gate.out

You can also use the >> operator to append output text to an existing file. Note: Although some commands include a -file type option to save the command’s output to a file, Cadence recommends using the command line > operator.

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ABSTRACT LOGIC
ABSTract LOGic [-MODule ] [-All] [-PURE] [-AUTO | -NOAUTO] [-Golden | -Revised] [-ASM | -NOASM] [-TEST_VIEW] [-POWER_VIEW] (Setup Mode)

Note: This requires a Conformal GXL license. Performs functional analysis on circuit netlists, which can contain different devices, including transistors, gates, and state elements. The analysis abstracts a logically-correct gate and a state primitive model. Use the logic model and compare it to the RTL model for complete functional verification. You can also write out the logic model and use it during high-performance simulation or fault grading. Note: If neither the -all nor -module option is specified, Conformal abstracts the current root module and any modules that are instantiated under it.

Parameters
-MODule name -All -Pure -AUTO Abstracts logic information from the specified module and its hierarchy. Abstracts logic information from all cells in the database, including cells that are not used by the current root module. Performs basic gate abstraction, which is useful for debugging. Enables propagation of constants, pin constraints, non-inverted and inverted pin relationships across module boundaries. This is the default. Does not invoke hierarchical analysis. Abstracts logic from the Golden design. This is the default. Abstracts logic from the Revised design.

-NOAUTO -Golden -Revised

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-ASM

Enables the Advanced State-element Modeling (ASM) algorithm. This helps to analyze loop structure to produce better modeling of state elements, such as D-Latch, DFF, and bus-keeping I/O logic. This is the default. Disables the Advanced State-element Modeling (ASM) algorithm. Tip If there are any unexpected results, you can use this option to revert back to the functionality of the 6.2 release and earlier.

-NOASM

-TEST_VIEW

Performs structurally accurate abstraction. With this option, only limited boolean simplification is done for abstraction. As a result, the gate-level structure of the original logic is preserved as much as possible after abstraction. Runs power-aware abstraction, where the connectivity of the power and ground pins are retained. Only limited boolean simplification is run to ensure that the abstraction results are as similar as possible to the original switch-level netlist.

-POWER_VIEW

Related Commands
ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE MOS2BUFIF READ PATTERN

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT ABSTRACT MODEL REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESET ABSTRACT MODEL RESOLVE SET ABSTRACT MODEL

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ADD ALIAS
ADD ALias (Setup / LEC Mode)

Adds alias names for quick command entry. Assign an alias to long command names and arguments to minimize typing and character entry. If you add an alias with an alias name that already exists, Conformal accepts the new alias and returns a warning as shown in the following example:
//Warning: Alias ‘myread’ is already defined, will be replaced by the new definition

For the greatest benefit, create aliases at the start of a Conformal session. Also, add aliases to an initial command file: .conformal_lec. The CONFORMAL_RC Environment Variable Conformal checks for the CONFORMAL_RC environment variable. If this variable is set, Conformal uses the file this variable refers to and does not search for other files. If the CONFORMAL_RC variable is not set, Conformal continues the search as follows:
■

First, the installation directory: /share/cfm/lec/.conformal_lec

■ ■

Second, the user’s home directory: ~/.conformal_lec Third, the current working directory: ./.conformal_lec

If one or more of these initial command files exist, Conformal runs them in the order noted above. This process offers flexibility in the way you choose to use the initial command file. You can set up initial command files for any or all of the following purposes:
■ ■ ■

A global initial command file for all users A global initial command file for an individual user An initial command file for a test case

Parameters name Specifies the name of the alias.

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string

Specifies the command that the alias represents.

Related Commands
DELETE ALIAS REPORT ALIAS

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ADD BLACK BOX
ADD BLack Box [ | -All] [ | -Design | -Library]> [-Golden | -Revised | -Both] (Setup Mode)

Specifies modules or instances that will be defined as blackboxes. These newly defined blackboxes are classified in the User class of blackboxes. Blackboxes already contained in the original design are classified in the System class of blackboxes. Note: The wildcard (*) represents any zero or more characters in blackbox names.

Parameters
-Module -Instance Defines this list of module names as blackboxes. This is the default. Defines this list of instance names as blackboxes. Defines the list of names of modules or instances. Note: Wildcard names are only supported for the module names. The wildcard (*) represents any zero or more characters in the blackbox module names. -File Specifies the name of the blackbox file. This file must contain only names of modules or instances, it is not a Verilog file. The names in the file are added to the [name...] list. Blackboxes all modules except the top module. -All applies within the given defaults. (Used with the -all option only) Blackboxes all modules in the design. If you do not specify either -design or -library, blackboxing applies to both the library and the design. -Library (Used with the -all option only) Blackboxes all modules in the library. If you do not specify either -design or -library, blackboxing applies to both the library and the design.

-All -Design

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-Golden -Revised -Both

Blackboxing applies to the Golden design only. This is the default. Blackboxing applies to the Revised design only. Blackboxing applies to both the Golden and Revised designs.

Related Commands
DELETE BLACK BOX REPORT BLACK BOX

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ADD CLOCK
ADD CLock [-Module ] [-Golden | -Revised] (Setup Mode)

Defines a clock state where data can change. You can use this command to define:
■ ■

Pre-charge clock states for domino style circuits Stable nets for clock-gating modeling Caution When using the ADD CLOCK command with set flatten model -gated_clock, there is an assumption that the ENABLE signal going into the AND gate of the clock cone is stable. Use with caution.

Parameters
0 1 Specifies that the off-state of the clock pin is 0. This means that when the pin is low, pre-charge occurs. Specifies that the off-state of the clock pin is 1. Defines the listed primary input pins as clocks in pre-charged transistor-MOS.

-Module Specifies that the defined clock pin is located in this module. -Golden -Revised Specifies that the clock is in the Golden design. This is the default. Specifies that the clock is in the Revised design.

Related Commands
ABSTRACT LOGIC ADD MOS DIRECTION

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Encounter Conformal Equivalence Checking Reference Manual Command Reference ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE SET ABSTRACT MODEL

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ADD COMPARED POINTS
ADD COmpared Points (LEC Mode)

Adds mapped points to the compare list. You can add compare points for all mapped points, or for a list of the gate ID numbers, instance paths, or pin paths. If you add a compare point to the Golden design, the Conformal software also adds its mapped compare point from the Revised design. Alternately, if you add a compare point to the Revised design, the software also adds its mapped compare point in the Golden design. Wildcard: The wildcard (*) represents any zero or more characters in instance or pin paths.

Parameters
-All Adds “all” mapped points, excluding primary inputs, as compare points. -All applies within the given defaults. Adds the specified gate ID numbers as compare points. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. Adds the specified instance paths as compare points. Adds the specified pin paths as compare points. -FRONTier Adds the specified key points and its frontier to the compare list. If no key points are specified, the frontier is computed from the existing compare points, and added to the compare list. No key points are added to the compare list if the frontier contains any unmapped key points. The gate ID numbers, instance paths, or pin paths are in the Golden design. This is the default.

-Golden

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-Revised

The gate ID numbers, instance paths, or pin paths are in the Revised design.

Examples
For a set of sample commands that shows this and related commands in context, see the example for the COMPARE command.

Related Commands
DELETE COMPARED POINTS REPORT COMPARED POINTS

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ADD CUT POINT
ADD CUt Point [-Net | -Pin] [-Golden | -Revised | -Both] (Setup Mode)

Adds a cut point to the specified net or pin path. This overrides automatic feedback loop cuts, which Conformal otherwise establishes on entering the LEC mode.

Parameters pathname -Net -Pin -Golden -Revised -Both Specifies the path that is the cut point of the feedback loop. Specifies that the path is a net. This is the default. Specifies that the path is a pin. Applies the cut point to the Golden design. This is the default. Applies the cut point to the Revised design. Applies the cut point to both the Golden and Revised designs.

Related Commands
DELETE CUT POINT REPORT CUT POINT REPORT PATH

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ADD DYNAMIC CONSTRAINTS
ADD DYnamic Constraints [-INStance | -Pin | -Net | -ID] [-Golden | -Revised | -Both] (LEC Mode)

Adds dynamic constraints for use with the PROVE command. Place constraints on the following:
■ ■ ■ ■

Hierarchical instance paths Hierarchical pin paths Hierarchical net paths Gate identification numbers

These constraints are either a 0-state or 1-state. Use this command as you diagnose and debug logic cones to help prove gate equivalence.

Parameters
0 1 Constrains the identifier to a 0-state. Constrains the identifier to a 1-state. If you do not specify one of the following options, Conformal automatically determines if the identifier is a number or a path. In the case of a number, Conformal uses the -id option; otherwise, Conformal searches for the gate with the -instance, -pin, or -net option; in this respective order. Hierarchical instance path. This is the default. Pin path, which is the module instance name concatenated with the pin name. Net path, which is the instance name concatenated with the net name.

-INStance -Pin -Net

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-ID

Identification number (ID) of a gate. The identification number is an integer assigned automatically by Conformal. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

-Golden -Revised -Both

Adds the dynamic constraints to the Golden design only. This is the default. Adds the dynamic constraints to the Revised design only. Adds the dynamic constraints to both the Golden and Revised designs.

Examples
For a set of sample commands that shows this and related commands in context, see the example for the COMPARE command.

Related Commands
DELETE DYNAMIC CONSTRAINTS PROVE REPORT DYNAMIC CONSTRAINTS

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ADD IGNORE RTLCHECK
ADD IGnore Rtlcheck (Setup Mode)

Ignores RTL (HDL) rule checking for all or specified modules. Run this command before the READ LIBRARY and READ DESIGN commands. Refer to the Encounter Conformal Equivalence Checking User Guide for additional information about specific rules. Tip When using the -module option, ensure that you have entered the module name correctly. If you enter a nonexistent module name, Conformal conducts the checks and issues messages as usual. Note: If you enter multiple IGNORE RTLCHECK commands, later commands replace previous commands. In the following example, Conformal ultimately enables RTL rule checking for all modules, including module abc. add ignore rtlcheck -module abc delete ignore rtlcheck -all

Wildcard: The wildcard (*) represent any zero or more characters in module names.

Parameters
-All Ignores RTL rule checking for all modules.

-Module Ignores RTL rule checking for the specified modules.

Related Commands
DELETE IGNORE RTLCHECK REPORT RULE CHECK

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ADD IGNORED INPUTS
ADD IGnored Inputs [-ROot | -Module | -All] [-Golden | -REvised | -Both] (Setup Mode)

Specifies which input pins Conformal ignores during comparison. You can use this command when the input pins are part of a blackboxed module. Note: Specified pins must be boundary module pins. Although boundary module pins are generally not compared points, they are compared points when the corresponding module becomes a blackbox. For example, when Conformal compares two blackboxes and one of them has extra input pins, such as scan in and scan enable pins, use this command to tell Conformal to ignore these extra input pins during comparison. Wildcard: The wildcard (*) represent any zero or more characters in ignored inputs and module names.

Parameters -ROot Ignores this list of primary input pins (associated with the root module or the specified submodule). Ignores the specified input pins in the root module. This is the default.

-Module Ignores the specified input pins in this module. -All -Golden -REvised -Both Ignores the specified input pins in “all” the modules, including the root module. -All applies within the given defaults. Ignores the specified input pins in the Golden design. This is the default. Ignores the specified input pins in the Revised design. Ignores the specified input pins in both the Golden and Revised designs.

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Related Commands
DELETE IGNORED INPUTS REPORT IGNORED INPUTS

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ADD IGNORED OUTPUTS
ADD IGnored Outputs [-Module |-All] [-Golden |-REvised |-Both] [-EQuivalences] (Setup Mode)

Specifies which output pins Conformal ignores during comparison. Note: Specified pins are boundary module pins. For example, when Conformal compares two modules and one of them has extra outputs, such as scan out pins, use this command to tell Conformal to ignore these extra output pins during comparison. Wildcard: The wildcard (*) represents any zero or more characters in ignored outputs and module names.

Parameters Ignores this list of primary output pins (associated with the root module or the specified submodule).

-Module Ignores the output pins in the specified module. The default is the root module. -All -Golden -REvised -Both -EQuivalences Ignores the specified output pins in “all” the modules, including the root module. -All applies within the given defaults. Ignores the specified output pins in the Golden design. This is the default. Ignores the specified output pins in the Revised design. Ignores the specified output pins in both the Golden and Revised designs. Ignores the specified output pins and their equivalences. The equivalences of a pin must be specified by the ADD OUTPUT EQUIVALENCES command prior to using this option. Equivalences created after using this option will not be ignored.

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Related Commands
ADD OUTPUT EQUIVALENCES DELETE IGNORED OUTPUTS REPORT IGNORED OUTPUTS

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ADD INSTANCE ATTRIBUTE
ADD INstance Attribute [ | ] [-Golden | -Revised] (Setup Mode)

Specifies how to treat an attribute for a gate or transistor primitive. Attributes can either be WEAK or deleted from the database for the purposes of a complete abstraction and comparison. However, newer abstraction capabilities can make the WEAK feature unnecessary.

Parameters WEAK Applies the instance attribute to the specified module, which contains the instance. Applies the instance attribute to the specified instance. Note: This option applies to Conformal Custom. Specifies drive strength of WEAK on an attribute. In the case of multiple drivers, first the state of the node is determined by devices that are not WEAK (STRONG), then if there are none, or if all of the STRONG devices are disabled, the WEAK devices impact the net’s function. This option affects extraction behavior and loop handling. DELETE Removes the specified device from the circuit. Note: This option applies to Conformal Custom. Tip The preferred method is to use the REMOVE command. -Golden -Revised Applies the instance attribute to the Golden design. This is the default. Applies the instance attribute to the Revised design.

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Related Commands
DELETE INSTANCE ATTRIBUTE REMOVE REPORT INSTANCE ATTRIBUTE

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ADD INSTANCE CONSTRAINTS
ADD INstance Constraints [-REPlace] [-Golden | -Revised | -Both] (Setup Mode)

Places constraints on specified instance paths in either the Golden or Revised design. You can only place 0-state or 1-state constraints on the outputs of instances. You can only apply instance constraints to D flip-flops and D-latches inside the specified instance paths. Wildcard: The wildcard (*) represents any zero or more characters in instance and module names.

Parameters
0 1 Constrains the specified instance paths to a 0-state. Constrains the specified instance paths to a 1-state

Places the constraints on these instance paths. Note: The instances are either DFFs or D-latches. ... -Module * Applies the constraint to the specified module(s). -REPlace -Golden -Revised -Both Changes the previously specified instance constraint. Applies the instance constraints to the Golden design. This is the default. Applies the instance constraints to the Revised design. Applies the instance constraints to both the Golden and Revised designs.

Examples
The following two commands are equivalent: add instance constraints 0 U1/U2/out_reg -revised
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However, these will be reported differently when running the REPORT INSTANCE CONSTRAINTS command, because of the -module option.
// Command: report instance constraints Constrained instances in Golden: 0 0 /U1/U2/out_reg Module U2: Instance out_reg

Related Commands
DELETE INSTANCE CONSTRAINTS REPORT INSTANCE CONSTRAINTS

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ADD INSTANCE EQUIVALENCES
ADD INstance Equivalences [-Invert ] [-MODULE ] [-Golden | -Revised | -Both] (Setup Mode)

Defines D-latches and D flip-flops as equivalent or inverted equivalences. This command is useful in mapping and its output is verified during the comparison. Use this command when you have one state element in a design that corresponds to two or more state elements in another design. Note: Only apply instance equivalences to D flip-flops and D-latches. When used, this command includes instance equivalent results in the compare results. For example:
================================================================================ Compare results of instance/output/pin equivalences and/or sequential merge ================================================================================ Compared points DFF Total -------------------------------------------------------------------------------Equivalent 234 234 ================================================================================

Effects on Comparison This command affects comparisons when you use add compared points -all. In that situation, Conformal merges the instances specified with the ADD INSTANCE EQUIVALENCES command and then verifies them at the end of the comparison. Wildcard: The wildcard (*) represents any zero or more characters in instance names.

Parameters Defines the group of instances that are equivalent. The first instance is the representative instance. The following instances are equivalent to the representative instance. This accepts wildcards. Note: The instances are either DFFs or D-latches.

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-Invert Defines a group of instances that is an inverted equivalence of the group that is equivalent. Note: The instances are either DFFs or D-latches. -MODULE Applies the instance equivalences to the specified module.The default is the root module. -Golden -Revised -Both Applies instance equivalences to the Golden design. This is the default. Applies instance equivalences to the Revised design. Applies instance equivalences to both the Golden and Revised designs.

Related Commands
ADD COMPARED POINTS DELETE INSTANCE EQUIVALENCES REPORT INSTANCE EQUIVALENCES SET FLATTEN MODEL

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ADD LIBRARY INSTANCE
ADD LIBrary INSTance -TYPe -TARget (-CONnection { })* [-PREfix ] [-Golden | -Revised]

Adds a primitive instance to the target instance. This command requires that you specify the primitive type, the target, and the connections. The new primitive instance is inserted after the COMMIT LIBRARY INSTANCE command executes.

Parameters
-TYPe -TARget

Type of the primitive to insert. Defines where the instance is inserted. Target string should be a hierachical name of the instance pin. Defines the connections for the primitive. The first string after connection is the pin name of the primitive. The expression can be an expression of hierachical pins.

(-CONnection { })*

-PREfix

Defines the prefix name of the inserted instance. Applies to the Golden design. This is the default. Applies to the Revised design.

-Golden -Revised

Related Commands
COMMIT LIBRARY INSTANCE DELETE LIBRARY INSTANCE

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ADD LOWPOWER CELLS
ADD LOwpower Cells [-isolation | -level_shifter | [-retention -attribute ] ] [-Both | -Golden| -Revised] (Setup Mode)

Note: This is a Conformal Low Power command. Defines the low power attribute for specified modules.

Parameters -isolation Applies the low power cell attribute to the specified module(s). Wildcards are accepted. Specifies the module as isolation cell. This is equivalent to the attribute is_isolation_cell : true in the liberty library. Specifies the module as level shifter cell. This is equivalent to the attribute is_level_shifter : true in the liberty library.

-level_shifter

-retention -attribute Specifies the module as a state retention cell with its associated power gate cell attribute. This is equivalent to the attribute power_gating_cell : ATTRIBUTE in the liberty library. -Both -Golden -Revised Applies the low power cell attribute to both the Golden and Revised designs. This is the default. Applies the low power cell attribute to the Golden design. Applies the low power cell attribute to the Revised design.

Examples
■

The following command assigns cell fdf1a1 as a state retention cell with a CLK_LOW attribute: add lowpower cells fdf1a1 -retention -attribute CLK_LOW -revised

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The following command assigns cell and2b1 as an isolation cell: add lowpower cells and2b1 -iso -revised

Related Commands
CHECK LOWPOWER CELLS DELETE LOWPOWER CELLS REPORT LOWPOWER CELLS REPORT LOWPOWER DATA SET LOWPOWER OPTION

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ADD MAPPED POINTS
ADD MApped Points [-INSTance | -NET] [-OUTput_pin ] ... [-INPut_pin ] ... [-GOLden | -REVised] [-NOINVert | -INVert] (LEC Mode)

When Conformal moves from Setup to LEC system mode, it automatically maps key points and places them in the System class of mapped points. If any additional mapped points are necessary, use this command, and Conformal will place them in the User class of mapped points. Note: If you attempt to add mapped points that were already mapped, Conformal returns a warning message. In the syntax shown below, the first gate_id, instance_pathname, or pin_pathname refers to the Golden design; the second argument refers to the Revised design. The -invert option makes one mapped point inverted with respect to the other mapped point. The (-) sign represents an inverted-mapped point. The (+) sign represents a non-inverted mapped point.

Parameters Adds this gate (identified by number) as a mapped point. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. Adds this instance path as a mapped point. -NET Adds this pin path as a mapped point. Uses the specified Golden and Revised net names to map key points together.

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-RULE Uses the instance or net renaming rule with the specified original pattern and substitution pattern to map key points together. -INSTance -NET Specifies that the rule is an instance renaming rule. This is the default. Specifies that the rule is a net renaming rule.

-OUTput_pin ... Maps the specified Golden and Revised blackboxed output pins. Multiples are permitted. However, you must list Golden and Revised pins in pairs and you must precede each pair with the -output_pin option. (See the example. For each pair that is listed, the first output pin is from the Golden design and the second output pin is from the Revised design.) -INPut_pin ... Maps the specified Golden and Revised blackboxed input pins. Multiples are permitted. However, you must list Golden and Revised pins in pairs and you must precede each pair with the -input_pin option. (See the example. For each pair that is listed, the first input pin is from the Golden design and the second input pin is from the Revised design.) -GOLden -REVised -NOINVert -INVert Applies this rule pattern substitution to the Golden design. This is the default. Applies this rule pattern substitution to the Revised design. Does not invert the two mapped points with respect to one another. This is the default. Inverts the two mapped points with respect to one another.

Examples
In the following two commands, A1 is the instance path of a blackbox: add mapped points A1 A1 -input_pin in1[0] inA[0] -input_pin in1[1] inA[1] add mapped points A1 A1 -output_pin out1[0] outA[0] -output_pin out1[1] outA[1]

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Related Commands
DELETE MAPPED POINTS INVERT MAPPED POINTS MAP KEY POINTS READ MAPPED POINTS REPORT MAPPED POINTS REPORT UNMAPPED POINTS SET MAPPING METHOD SET NAMING RULE

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ADD MAPPING MODEL
ADD MApping Model ... [-Inverted] [-NONInverted] [-DESign] [-LIBrary] [-Golden | -Revised | -Both] (Setup Mode)

The ADD MAPPING MODEL command specifies the phase information for the given modules. Using this command together with SET MAPPING METHOD -PHASEMAPMODEL.

Parameters ...

Specifies the name(s) of the module(s). This accepts wildcards. Specifies inverted phase information for the given modules. This is the default. Specifies non-inverted phase information for the given modules. Specifies that the phase information applies to the modules in the design space. When -library is not specified, -design is the default. Specifies that the phase information applies to the modules in the library space. When -design is not specified, -library is the default. Specifies that the phase information applies to the modules in the Golden design. This is the default. Specifies that the phase information applies to the modules in the Revised design. Specifies that the phase information applies to the modules in both the Golden and Revised design. Displays verbose information.

-Inverted

-NONInverted -DESign

-LIBrary

-Golden

-Revised

-Both

-Verbose

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Examples
The following command specifies that module "mymod" in the library of the Golden design has an inverted phase.
MODE> add mapping model mymod -library

Related Commands
SET MAPPING METHOD

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ADD MODULE ATTRIBUTE
ADD MOdule Attribute [-Golden | -Revised | -Both] [-ECO_module] [-NOFLatten] [-HIER_Compare ] (Setup Mode)

Defines the attributes for specified modules.

Parameters -PIPELINE_Retime Applies the attribute to the specified modules. This accepts wildcards. Checks the specified modules for pipeline retiming (and remodel if pipeline retiming is detected). This option requires Conformal to check the module and remodel it if the Golden and Revised designs have pipeline-retiming. -DFF2Buffer Changes registers to buffers.This option lets you compare models with no registers to those with pipeline registers inserted.

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-COMPARE_Effort

Assigns a specified comparison effort level to the module. This option is generally applied to hierarchical comparisons where some modules need a higher compare effort than others. Low applies minimal effort to equivalency checking for the specified module. This is the default. Medium applies greater effort to equivalency checking for the specified module. High applies the maximum effort to equivalency checking for the specified module. AUto starts with low effort and automatically increases the compare effort when abort points are in the specified module. None applies no compare effort to equivalency checking for the specified module. For advanced pipeline retiming, see ANALYZE RETIMING.

-CPU_Limit #

Specifies a number of seconds for each module during hierarchical compare.This option decreases the amount of time Conformal spends comparing a particular module. Specifies that the module attribute applies to the Golden design. This is the default. Specifies that the module attribute applies to the Revised design. Specifies that the module attribute applies to both the Golden and Revised design. Ignores mismatched ports on the specified module(s) when running the WRITE HIER_COMPARE DOFILE command. Disables the specified module(s) from being flattened during the dynamic hierarchical run.

-Golden -Revised -Both -ECO_module -NOFLatten

-HIER_Compare For the specified module, replaces the default ADD COMPARED POINTS -all and COMPARE commands in the hierarchical script generated using the WRITE HIER_COMPARE DOFILE command with the specified . Note: This option is not supported if you want to perform hierarchical comparison using the RUN HIER_COMPARE command.
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Example
In the following command sequence, the hierarchical dofile script hier.do that is generated with the write hier_compare dofile command contains the commands add partition points -all, set compare effort high, add compared points -all, and compare for module modA, instead of the default add compared points -all and compare command sequence: add module attribute modA -hier_compare "add partition points -all; set compare effort high; add compared points -all; compare" write hier_compare dofile hier.do -constraints

Related Commands
ANALYZE RETIMING DELETE MODULE ATTRIBUTE REPORT MODULE ATTRIBUTE WRITE HIER_COMPARE DOFILE

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ADD MOS DIRECTION
ADD MOs Direction ... |-NOTYpe ...] |-MOdule |-PIn [-BBox ] ] [-REPlace] [-Golden | -Revised | -BOth] ] (Setup / LEC Mode)

Specifies renaming rules for key point mapping, module renaming (when reading in the library and designs for hierarchical comparisons), and pin renaming for blackboxes. Use the REPORT RENAMING RULE command to display the list of all renaming rules. Conformal applies renaming rules sequentially, in the order they were added. Key Point Mapping When you define renaming rules in the Setup system mode, they guide the automatic mapping process that occurs during the system mode switch from Setup to LEC. When you are in the LEC system mode, and find that the key point mapping is not complete, define additional renaming rules and repeat key point mapping to improve the mapping results. The automatic mapping process refers to the naming specified by the final renaming rules. Module Renaming You must use this command before the WRITE HIER_COMPARE DOFILE command. It helps map modules together for hierarchical comparisons. Pin Renaming This command applies to the specified blackbox or to all blackboxes, which is the default.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Renaming Rule Structure When defining renaming rules, the first string specifies the pattern to be matched; the second string specifies how Conformal is to rename or make substitutions. The first string can contain expressions of the following types: Matches one or more digits, [0-9]+ Matches one or more alphabetical characters, [a-zA-Z]+ Matches one or more digits or alphabetical characters, [0-9a-zA-Z]+ Matches one or more alphabetical characters or underscores, [a-zA-Z_]+ Matches one or more digits or alphabetical characters or underscores, [0-9a-zA-Z_]+ Matches character “x” Matches string “abc” Matches any single character Matches zero or more repetitions of the preceding expression Matches one or more repetitions of the preceding expression Matches “bol” only when it occurs at the beginning of a string Matches “eol” only when it occurs at the end of a string Matches “x” or “abc” Matches “o”, “z”, or “!” Matches anything that is matched by “pattern” and renders it referable (through @n) in the substitution string

%d %a %s %u %w x abc . * + ^bol eol$ x|abc [oz!] (pattern)

Any character can be preceded by the escape character “\” to cancel any special meaning it has. Use the escape character whenever any of the following special characters represents a simple character. % . * + ^ $ | ( ) [ ] \

The second string can contain expressions of the following types: Replaces string “abc” for each matched string
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@n

Replaces the string that matches the nth %d, %a, %s, or a pattern enclosed in parentheses. The n is a digit other than 0, and you can use @{nn} to refer to further matches (that is, 10…99) Where “expr” is an arbitrary expression that can only contain constant integers, @n expressions, and the operators +,-,*, / and ( )

#(expr)

The following table shows implementation examples for various pattern-matching and substitution strings. For pattern-matching strings, use parentheses to group individual patterns into a single pattern, as demonstrated in the example (ab|de)*. First String %a%d %a_%d _z_ ^abc abc$ ^abc$ ^abc$ [oz!] \%d\%s \(ab %s\.%d (x|abc) (ab|de)* %s%d %s%d reg%d\[%d\]
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Second String @1[@2] @1[@2] / XYZ XYZ XYZ XYZ $ AA ZZ @1[@2] YY YY @1[#(7-@2)] @1[#(2*@2)] reg[@2]

Source xyz123 arr_5 _z_top_z_inst abcabc abcabc abcabc abc aaoaazaa!aa %a%d%s%b (abcd xx.123 abcx abcx ababdeab abc3 abc5 reg2[5]
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Result xyz[123] arr[5] /top/inst XYZabc abcXYZ abcabc XYZ aa$aa$aa$aa %aAA%b xxZZcd xx[123] YYYY YYYY YY abc[4] abc[10] reg[5]
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Important Do not include the forward slash, “/”, at the top level for either the first or second string. For example, express /top_module/adder/reg[5] as top_module/adder/reg[5].

Parameters
-PIN_MULTIDIM_TO_1DIM Allows you to create renaming rules to map multidimensional array pins to one-dimensional array pins. -ADD -NOADD -NOASCEND -ASCEND -VERBOSE -MAp -TYpe Shows the pins found when adding the rules into the system. This is the default. Shows the pins found without adding the rules. Renames the pins in an descending order. This is the default. Renames the pins in an ascending order. Shows the renaming patterns. Specifies a rule identification name assigned to a specific renaming rule. The first string represents the pattern to be matched. The second string represents the substitution pattern. Specifies that the renaming rule applies to key point mapping. This is the default. Renames all key points with the specified type. The available types are as follows: PI E Z DFF DLAT Primary Inputs TIE-E gates TIE-Z gates D flip-flops D-latches

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CUT BBOX PO -NOTYpe

Artificial gates for breaking combinational feedback loops Blackboxes Primary Outputs

Renames all key points except the specified types. The available types are as follows: PI E Z DFF DLAT CUT BBOX PO Primary Inputs TIE-E gates TIE-Z gates D flip-flops D-latches Artificial gates for breaking combinational feedback loops Blackboxes Primary Outputs

-MOdule -PIn

Specifies that the renaming rule applies to module renaming when the library and design are read in. Specifies that the renaming rule applies to pin names of blackboxes.

-BBox Specifies that the pin renaming rules apply to the specified blackbox module. -REPlace Allows the redefinition of an existing renaming rule. Tip The difference between using add renaming rule -replace as opposed to using delete renaming rule followed by add renaming rule is that renaming rules that are redefined remain in the same position in the list of renaming rules. By deleting and adding a rule, the new definition will appear at the end of the list. In some cases, the order in which renaming rules are applied might affect the result. -Golden Specifies that the renaming rule applies to the Golden design. This is the default.
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-Revised -BOth

Specifies that the renaming rule applies to the Revised design. Specifies that the renaming rule applies to both the Golden and Revised designs.

Example
In the following command, y2[1:0][2:0] in module test2 is renamed y2[5:0]: add renaming rule -pin_multidim_to_1dim // Rule created for (test2) y2[1:0][2:0] // Rule created for (test1) y1[1:0][1:0] // Rule created for (top) y2[1:0][2:0] // Rule created for (top) y1[1:0][1:0] // Rule created for (top) ym[2:3][2:0][1:0] // 5 rules created. Rules for top module must be manually validated.

You can use the REPORT RENAMING RULE command to view the added rules.

Related Commands
CHANGE NAME DELETE RENAMING RULE MAP KEY POINTS READ DESIGN READ LIBRARY REPORT RENAMING RULE SET MAPPING METHOD SET NAMING RULE TEST RENAMING RULE

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ADD RETENTION MAPPING
ADD REtention Mapping [-TYpe ] (Setup / LEC Mode)

Note: This is a Conformal Low Power command. Adds the state retention mapping rules for validation of technology mapping of the sequential elements (DFFs or DLATs) from RTL to gate-level, gate-level to gate-level, or RTL to RTL. For a description of the default rules that are added by the system, see CHECK LOWPOWER CELLS on page 144.

Parameters -Module Specifies a rule identification name assigned to a specific retention mapping rule. Specifies the module name in the Golden design. All the DFFs or DLATs under the named module will be subjected to this rule. Specifies the instance pathname in the Golden design. Here instance pathname refers to only DFF or DLAT instances. The named DFF or DLAT instance(s) would be subjected to this rule. Wildcards (*) are supported for the instance pathname. When using a wildcard, it might point to multiple instances. -NOTag When the Golden side is an RTL design, this implies that all the DFFs or DLATs which do not have any tag-name associated with their ’process’ or ’always’ block will be subjected to this rule.

-Instance

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-Tag

Specifies the tag name in the RTL golden side. The ’tag name’ refers to the label names used with a) ’process’ blocks in the VHDL RTL and b) ’always’ blocks in the Verilog RTL. All the DFFs or DLATs under the tag-named block will be subjected to this rule. Wildcards (*) are supported.

-Attribute

Specifies the ’power gating cell attribute’ for the DFFs or DLATs in the Revised netlist. Different power gating cell attributes are defined for different sets of retention cells in the Synopsys library (liberty format). When synthesized (technology mapped), the DFFs or DLATs in the Golden design (specified using module-name, instance-name, or tag-name) should have the named attribute in Revised netlist. Specifies that, when synthesized (technology mapped), the DFFs or DLATs in the Golden design (specified using module-name, instance-name, or tag-name) should not have any attribute (power gating cell attribute) in Revised netlist. In other words, the specified DFFs or DLATs should be technology mapped as ordinary or non-retention cells.

-NOAttribute

-TYpe Indicates the sequential element type on which to apply the retention mapping rule. ALL applies the retention mapping rule to all sequential elements (both DFF and DLAT type). This is the command default when you do not specify the -TYpe option. DFF applies the retention mapping rule to DFFs only, and DLAT applies the retention mapping rule to DLATs only.

Examples
■

The following command verifies that all registers with a tag label lp_sel* are implemented with a state retention cell whose power_gating_cell attribute is LPRET_DFF1: add retention mapping R0 -tag lp_sel* -attribute LPRET_DFF1

■

The following command verifies that all registers in module blockA are implemented with a state retention cell whose power_gating_cell attribute is LPRET_DFF1: add retention mapping R1 -module dma -attribute LPRET_DFF1

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The following command verifies that all registers with instance name /U0/*/fifo_dma* are implemented with a state retention cell whose power_gating_cell attribute is LPRET_DFF2: add retention mapping R2 -instance "/U0/*/fifo_dma*" -attribute LPRET_DFF2

Related Commands
CHECK LOWPOWER CELLS DELETE RETENTION MAPPING REPORT RETENTION MAPPING

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ADD SEARCH PATH
ADD SEarch Path [ | -Design | -Library] [-Both | -Golden | -Revised] [-RECursive] (Setup Mode)

Defines additional search paths outside the current directory for filenames you use in the READ DESIGN and READ LIBRARY commands. This command is necessary because the default is to search for filenames in the current directory; but your design or library can include filenames that are housed in other directories. When you add multiple search paths to the list, Conformal does the search in the order paths were added to the list. Use the REPORT SEARCH PATH command to display all search paths. Use the tilde character (~) to shorten the specified path.

Parameters -Design Specifies the search path for filenames used in the READ DESIGN and READ LIBRARY commands. The READ DESIGN command uses the specified search path. If you do not specify -library or -design, Conformal applies this command to both the READ DESIGN and READ LIBRARY commands. -Library The READ LIBRARY command uses the specified search path. If you do not specify -library or -design, Conformal applies this command to both the READ DESIGN and READ LIBRARY commands. -Both -Golden -Revised Specifies that the search path applies to both the Golden and Revised designs. This is the default. Specifies that the search path applies to the Golden design and library. Specifies that the search path applies to the Revised design and library.

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-RECursive

Adds the subdirectories of the specified directory into the search paths.

Related Commands
DELETE SEARCH PATH READ DESIGN READ LIBRARY REPORT SEARCH PATH

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ADD SEQ_CORR
ADD SEQ_CORR (LEC Mode)

Note: This requires a Conformal XL license. Adds the Golden register and the Revised state point as the pair of sequential corresponding points. After adding the sequential corresponding pairs, use the ANALYZE RETIMING -general command to retime the Revised design to the state points according to the sequential correspondence information.

Parameters Specifies the sequential corresponding gate ID or instance pathname for the Golden register. Specifies the sequential corresponding gate ID or instance pathname for the Revised state point.

Example
The following commands add the sequential corresponding points and perform general retiming analysis: add seq_corr reg1 g1 add seq_corr reg2 g2 analyze retiming -general -verbose

Related Commands
ANALYZE RETIMING DELETE SEQ_CORR REPORT SEQ_CORR
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ADD SUPPLY
ADD SUpply [-POWER | -GROUND] [-ROOT | -Module | -ALL] [-PORT | -GLOBAL ] [-Golden| -Revised | -Both] (Setup Mode)

Note: This requires a Conformal GXL license. Defines power and ground ports of a module or the global power and ground signals for the entire design.

Parameters -POWER -GROUND -ROOT Specifies that a list of net or port names, each separated by a space, that will be specified as power or ground. Set the specified objects with power attribute. This is the default. Set the specified objects with ground attribute. Applies this supply attribute to the specified objects in the current scope and all hierarchy of this scope. This is the default. Applies the attribute setting to the specified module. This accepts wildcards. Applies the attribute setting to the objects for all module. The defined object(s) must be the port(s) at the root or the specified module level. This is the default. The defined object(s) could be the port(s) and wire(s) in the hierarchy of the root or the specified module. Specifies that the listed names are from the Golden design. This is the default. Specifies that the listed names are from the Revised design. Specifies that the listed names are from both the Golden and Revised designs.
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Related Commands
DELETE SUPPLY REPORT SUPPLY

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ADD TIED SIGNALS
ADD TIed Signals [-Net | -Pin] [-ROot | -Module | -All] [ | -Design | -Library] [-Golden | -Revised | -Both] (Setup Mode)

Assigns the specified floating nets or pins to a 0-state or a 1-state in the Golden or Revised design. These tied signals are classified in the User class of tied signals. The original tied signals of the design are classified in the System class of tied signals. Wildcard: The wildcard (*) represents any zero or more characters in net, pin, and module names.

Parameters
0 1 -Net -Pin -ROot Ties the floating nets or pins to a 0-state. Ties the floating nets or pins to a 1-state. Specifies a list of names that correspond to either floating nets or floating pins where you intend to add the tied signal. Specifies that the listed names are net names. This is the default. Specifies that the listed names are pin names. Specifies that the floating net or pin resides in the current root module. This is the default.

-Module Specifies that the floating net or pin resides in the specified module. The default is the root module. This accepts wildcards. -All -Design Applies the tied signals to “all” the modules. -All applies within the given defaults. Applies the tied signals to the design. If you do not specify -design or -library, Conformal applies tied signals to both designs and libraries.
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-Library

Applies the tied signals to the library. If you do not specify -design or -library, Conformal applies tied signals to both designs and libraries.

-Golden -Revised -Both

Adds the tied signals to the Golden design. This is the default. Adds the tied signals to the Revised design. Adds the tied signals to both the Golden and Revised designs.

Related Commands
DELETE TIED SIGNALS REPORT FLOATING SIGNALS REPORT TIED SIGNALS

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ANALYZE ABORT
ANAlyze ABort [-All | | -Number ] [-Summary | -COmpare [-THREADS ]] [-CLass ] [-Verbose] (LEC Mode)

Note: This requires a Conformal XL license. Analyzes abort points and recommends actions to help solve the abort points. This command can also provide useful information for further abort investigation.

Parameters
-ALL -Golden -Revised -Number -Summary Analyzes all abort points. This is the default. Specifies the gate ID for abort analysis. Specifies the instance pathname for abort analysis. Specifies the pin pathname for abort analysis. Specifies whether the gate ID or pathname is in the Golden design. This is the default. Specifies whether the gate ID or pathname is in the Revised design. Specifies the number of abort points to analyze. Prints out the summary count of the abort points. This is the default.

-COmpare [-THREADS ]

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Automatically compares the aborted points. Cadence recommends using this option when running the ANALYZE ABORT command. -THREADS specifies the number of threads for abort analysis. This supersedes any SET PARALLEL OPTION command’s -threads setting. Note: The -THREADS option activates the use of parallel algorithms which could help solve more abort points. -CLass Specifies the class of points to analyze. Select Abort to analyze abort points, or Notcompared to analyze not-compared points. -Verbose Prints out additional information, such as RTL statistics.

Example
The following commands run abort analysis after the initial compare: compare analyze abort -compare

Related Commands
COMPARE RUN HIER_COMPARE SET ANALYZE OPTION

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ANALYZE DATAPATH
ANAlyze DAtapath [-MODULE [-RESOURCEFILE ] [-ISOLATE_ABORT_MODULE] ] [-NOWORDLEVEL | -WORDLEVEL] [-MERGE | -NOMERGE] [-NOADDERTREE | -ADDERTREE] [-NOSHARE | -SHARE] [-SHARE_OPerator ] [-EFFort ] [-DIAGNOSIS] [-Verbose] (LEC Mode)

Note: This requires a Conformal XL license. Analyzes datapath modules. Based on the results of the analysis, Conformal can automatically resolve multipliers, operator merging, and resource sharing problems. Note: You cannot run datapath analysis without first mapping the Revised design keypoints to the Golden design keypoints.

Parameters
-MODULE Applies analysis on the datapath modules. The default is in the Revised design netlist.

-RESOURCEFILE Specifies the resource filename to analyze the datapath modules. -ISOLATE_ABORT_MODULE Isolates the module which is aborted during module-based datapath (MDP) analysis. The module’s gate-level netlist will be abstracted into RTL for comparison at the top module. -NOWORDLEVEL -WORDLEVEL Does not apply word-level datapath analysis. This is the default. Applies word-level datapath analysis. This helps analyze advanced word-level optimizations on designs with complex adder-tree clustering, product-of-sum, XOR-tree, or datapath with control logics or constants. Applies the operator merging technique. This is the default.

-MERGE

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-NOMERGE -NOADDERTREE -ADDERTREE -NOSHARE -SHARE -SHARE_OPerator

Does not apply the operator merging technique. Does not automatically add parentheses to the input operands of adder trees. This is the default. Automatically adds parentheses to the input operands of adder trees. Does not apply the resource sharing technique. This is the default. Analyzes the design for datapath resource sharing. Shares the specified operators. See the example for the recommended flow. Note: If this option is specified, only the sharing is performed, and does not run datapath analysis.

-EFFort Specifies the effort level. Choose MEDium (the default), or HIgh to help provide better analysis of some multipliers, but might increase the analysis runtime.
-DIAGNOSIS

Displays information that can help diagnose the low quality of datapath analysis. Provides additional information.

-Verbose

Examples
■

The following commands show an example of the recommended flow when using the -SHARE_OPerator option: analyze datapath -verbose -share_operator mult_30 mult_31 // Note: mult_30: shared analyze datapath -verbose -share_operator mult_32 mult_33 // Note: mult_32: shared analyze datapath -verbose // Note: add_2(clustered): quality evaluated 70% success // Note: mult_30: quality evaluated 80% success // Note: mult_32: quality evaluated 100% success

■

The following commands apply datapath module-based analysis followed by the datapath operator-level analysis: analyze datapath -verbose -module -resourcefile resourcefile.name analyze datapath -verbose

■

The following is an example of what is displayed when using the -diagnosis option:
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================================================================================ [GOLD] mult_26 (z = in1 * in2) -------------------------------------------------------------------------------Boundary Match(%) Bits(#) Const(#) Unreach(#) -------------------------------------------------------------------------------IN1 (unsigned) 100 16 0 0 IN2 (unsigned) 100 16 0 0 OUT (unsigned) 0 32 0 0 INTERNAL 8 132 15 -------------------------------------------------------------------------------Note: PPGEN boundary is not perfectly matched. -------------------------------------------------------------------------------// Note: mult_26: quality evaluated 10% success

Related Commands
ANALYZE MODULE COMPARE REPORT COMPARE DATA REPORT DATAPATH OPTION REPORT DATAPATH RESOURCE REPORT HIER_COMPARE RESULT REPORT MULTIPLIER OPTION SET DATAPATH OPTION SET MULTIPLIER IMPLEMENTATION SET MULTIPLIER OPTION WRITE HIER_COMPARE DOFILE

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ANALYZE HIER_compare
ANAlyze HIER_compare [-DOFile ] [-REPlace] [-NOCONstraints | -CONstraints ] [-KEEP_TOP_level_constraints | -NOKEEP_TOP_level_constraints] [-INPUT_OUTPUT_Pin_equivalence] [-FUNCTION_Pin_mapping] [-CONDitional] [-PREPEND_String ] [-APPEND_String ] [-COMPARE_String ] [-THReshold ] [-EXact_pin_match | -NOEXact_pin_match] [-EXACT_MODULE_match | -NOEXACT_MODULE_match] [-ECO_aware] [-ECOPIN_dofile ] [-USAge] [-VERbose] (LEC Mode)

Note: This requires a Conformal XL license. Analyzes the modules and their instantiations in LEC mode to generate the hierarchical dofile script that verifies the two hierarchical designs (starting from the lower-level modules, progressing to the top root module). To enable hierarchical dofile generation in LEC mode, you must use the following command in Setup mode.
SETUP> set flatten model -enable_analyze_hier_compare

Note: You cannot use this command when performing custom analysis of switch-level networks that were enabled through the SET XC command

Parameters
-DOFile Specifies the name of the hierarchical dofile script that verifies design hierarchy. Use the tilde character (~) to shorten the path of the file. Replaces the existing file. Does not extract or propagate the root module constraints and equivalences. This is the default.

-REPlace -NOCONstraint

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-CONstraint

Extracts and propagates the root module constraints and equivalences and adds these to the corresponding modules in the hierarchical dofile script.

-KEEP_TOP_level_constraints Automatically applies top-level pathname-based constraints to the appropriate sub-modules, during hierarchical comparison. Top-level constraints are supported for ADD PRIMARY INPUT, ADD PIN CONSTRAINTS, and ADD INSTANCE CONSTRAINTS commands. This option is the default. During hierarchical comparison, if top-level constraints take effect for the specific sub-module, they are enclosed within the following messages:
Applying top-level pathname-based constraints ... End of top-level pathname-based constraints

On the other hand, if the the pathname-based constraints do not take effect when they should have, the following warning message is generated:
// Warning: Top-level constraints might not have been fully applied

See example below. -NOKEEP_TOP_level_constraints Disables the application of top-level pathname-based constraints to the appropriate sub-modules, during hierarchical comparison. -INPUT_OUTPUT_Pin_equivalence Extracts input-output pin equivalences within a module and applies them to the hierarchical dofile script. This can be used when the design has feedthroughs or feedback buffers.

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-FUNCTION_Pin_mapping

Extracts the functional mapping for the sub-module boundary ports with correct phase. This option is useful when the netlist has gone through clock-tree-synthesis (CTS), which creates additional sub-module ports with different polarity; or, if there is an inverter push across sub-module boundaries without modifying the port names.

-CONDitional

Skips blackboxing for nonequivalent submodules during the hierarchical comparison. (The end result is that Conformal flattens these submodules.) To report the flattened modules, use the report hier_compare result -flattened command.

-PREPEND_String

Appends any string of commands to the hierarchical dofile script before key point comparison for each module. Use the semi-colon character (;) to separate commands. Use double quotes to surround each prepended command (see “Examples”). Appends any string of commands to the hierarchical dofile script after key point comparison for each module. Use the semi-colon character (;) to separate commands. Use double quotes to surround each appended command (see Examples). Replaces the default compare command with a string of compare commands in the hierarchical dofile script generation for each module. Use the semi-colon character (;) to separate commands. Use double quotes to surround each compare command (see Examples). Analyzes only modules with primitive instances greater than the threshold number. The default value of threshold is 50 primitives. Writes only those modules with matching pin names to the hierarchical dofile script. This is the default. Writes out even those modules which have mismatched pin names to the hierarchical dofile script. Writes out only the module pairs, with matching module names and instance path names, to the hierarchical dofile script. This is the default.
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-APPEND_String

-COMPARE_String

-THReshold

-EXact_pin_match -NOEXact_pin_match -EXACT_MODULE_match

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-NOEXACT_MODULE_match

Writes out module pairs, with matching instance path names (irrespective of the module name), to the hierarchical dofile script. Executes the USAGE command after each comparison and at the end of the hierarchical comparison. This option requires an ECO license. Recognizes ECO-related changes. This option recognizes ports that would otherwise be ignored for non-ECO comparisons, thus facilitating the correct comparison between the golden and revised designn.

-USAge

-ECO_aware

-ECOPIN_dofile This option requires an ECO license. Writes out a dofile for adding/deleting ECO pins to the golden design as compared to the revised design. -VERbose Provides additional information when analyzing the modules for hierarchical comparison.

Example
LEC> analyze hier_compare -dofile hier.do -replace LEC> analyze hier_compare -dofile hier.do -append_string "report compare data -class nonequivalent" -prepend_string "report unmapped points -notmapped; analyze setup" -replace

The following is a sample dofile that reads in the two hierarchical designs, writes out the hierarchical dofile script, and compares design hierarchies: set log file hier.log -replace read library golden.lib -verilog -golden read design golden.v -verilog -golden read library revised.lib -verilog -revised read design revised.v -verilog -revised set flatten model -enable_analyze_hier_compare set system mode lec analyze hier_compare -dofile hier.do -replace -constraints dofile hier.do exit -force

In the following example, top-level pathname-based constraints are applied to the appropriate sub-modules, during hierarchical comparison.

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------------------------------------------------------------------In dofile ------------------------------------------------------------------add primary input a0/b0/scan_en -net -Golden add pin constraint 0 a0/b0/scan_en -Golden analyze hier_compare -dofile hier.do -replace -constraints -keep_top_level_constraints -noexact_pin_match dofile hier.do ... ------------------------------------------------------------------During hierarchical comparison; part of logfile ------------------------------------------------------------------// Running Module modB and modB // Command: set root module modB -Golden // Command: set root module modB -Revised // Command: set module property -instance /a0/b0 -Golden // Command: set module property -instance /a0/b0 -Revised // Command: report black box -NOHidden // Command: set system mode lec Applying top-level pathname-based constraints // Command: add primary input scan_en -Golden // Command: add pin constraints 0 scan_en -Golden End of top-level pathname-based constraints // Processing Golden ... // Modeling Golden ...

Related Commands
ADD NOBLACK BOX DELETE NOBLACK BOX READ DESIGN READ LIBRARY REPORT HIER_COMPARE RESULT REPORT NOBLACK BOX RESET HIER_COMPARE RESULT RUN HIER_COMPARE SAVE HIER_COMPARE RESULT SET NAMING RULE UNIQUIFY WRITE HIER_COMPARE DOFILE
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ANALYZE IMPLICATION
ANAlyze IMplication [-ONE | -1 ] [-ZERO | -0 ] [-ADD ] [-DELete ] [-CHECK_Redundancy ] [-CHECK_Constant ] [-Block ] [-DEPTH ] [-Golden | -Revised] (LEC Mode)

Note: This requires a Conformal XL license. Analyzes implication values on the design. If you assign value(s) on certain gate(s), this command shows what the necessary values are on other gates to satisfy the assignment. It can also show if a gate has redundant fanin and if a gate is a constant gate. The results are displayed in the schematic view with the following colors:
■ ■ ■ ■

Blue: initial assignments Green: current implication values Red: gates on the conflict path Purple: location where conflict occurred

In the schematic view, you can also right click the gate and set a value. Holding the mouse pointer on a gate, an information box will show if this gate has redundant fanin and if it is a constant gate.

Parameters
-ONE | -1 -ZERO | -0 -ADD -DELete -CHECK_Redundacy
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Specifies that the following gate(s) will be assigned one. Specifies that the following gate(s) will be assigned zero. Specifies that the following assignment(s) will be added into previous assignment(s). Specifies that the following gate(s) will be removed from previous assignment(s). Checks the specified gate to see if it has redundant fanins.
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-CHECK_Constant -Block -DEPTH -Golden -Revised

Checks the specified gate to see if it is constant gate. Blocks the gate(s) so that implication will not go across it. Specifies the logic depth beyond which implication will not be performed. The default value is 10. Specifies that the gate IDs are from the Golden design. This is the default. Specifies that the gate IDs are from the Revised design.

Related Commands
READ DESIGN READ LIBRARY

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ANALYZE MODULE
ANAlyze MOdule ... [-PARTIAL_SUM_OUTPUTS] [-EFFORT ] [-MSB_TRUNCATIONS | -NOMSB_TRUNCATIONS] [-LSB_TRUNCATIONS | -NOLSB_TRUNCATIONS] [-REPLACE | -NOREPLACE] [-GOLden | -REVised] [-VERBose] (Setup Mode)

Analyzes non-exact synthesis modules in the Revised netlist and replaces the corresponding RTL models in the Golden netlist with the synthesized modules if the synthesized modules can be proven equivalent using the specified comparison mode. The method of module correspondence between the Golden and Revised netlist is identical to hierarchical comparisons. Therefore, module renaming rules and uniquification can also be applied. Caution The ANALYZE MODULE command should be used after uniquification. After running this command, all design level settings cannot be modified. These settings include, but are not limited to, pin constraints and renaming rules.

Parameters Specifies the name(s) of the module(s). This accepts wildcards. For DW02_tree modules, the module name must contain the keyword tree. For DW02_multp modules, the module name must contain the keyword multp. The tool also checks the module’s input and output interfaces to ensure they meet the specifications of DW02_tree or DW02_multp. -PARTIAL_SUM_OUTPUTS Compares the modules with their partial sums added. This is applicable only to DesignWare/ChipWare components with partial sums output.

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-EFFORT Specifies the amount of effort applied to constraint extractions. Low applies minimal effort to constraint extraction. This is the command default. Medium applies greater effort to constraint extraction. High applies the maximum effort to constraint extraction. -MSB_TRUNCATIONS Truncates the most significant bits (MSBs) of partial sum outputs when adding up for comparison. This option is helpful in proving modules equivalent when such MSBs are unreachable. This is the default. Keeps the MSBs of partial sum outputs when adding up for comparison, even if the MSBs are unreachable. Truncates the least significant bits (LSBs) of partial sum outputs when adding up for comparison. This option is helpful in proving modules equivalent when such LSBs are unreachable. This is the default. Keeps the LSBs of partial sum outputs when adding up for comparison, even if the LSBs are unreachable. Performs the replacement. This is the default. Does not perform the replacement. Replaces the module in the Golden netlist with the module from the Revised netlist if successful. This is the default. Replaces the module in the Revised netlist with the module from the Golden netlist if successful. Provides additional information for the analysis.

-NOMSB_TRUNCATIONS -LSB_TRUNCATIONS

-NOLSB_TRUNCATIONS -REPLACE -NOREPLACE -GOLden

-REVised -VERBose

Example
The following command analyzes modules DW02_multp and DW02_tree in the Revised netlist and replaces the corresponding RTL models in the Golden netlist with the synthesized modules if the synthesized modules can be proven equivalent using the partial sums outputs comparison mode:

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Related Command
WRITE HIER_COMPARE DOFILE

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ANALYZE MULTIPLIER
ANAlyze MUltiplier [-NOCDP_INFO | -CDP_INFO] (LEC Mode)

Initiates an analysis of multiplier modules. Based on the results of the analysis, Conformal can automatically resolve architecture mismatches and operand swapping problems. Additionally, use the -cdp_info option if you want Conformal to let you know when Conformal Ultra will be helpful. Use this command after switching from Setup to LEC mode: set system mode lec … analyze multiplier -cdp_info add compared points -all compare

Parameters
-NOCDP_INFO -CDP_INFO Does not display a message when Conformal Ultra can enhance multiplier analysis. This is the default. Displays a message when Conformal Ultra can enhance multiplier analysis.

Related Commands
ANALYZE DATAPATH ANALYZE MODULE REPORT DATAPATH OPTION REPORT DATAPATH RESOURCE REPORT MULTIPLIER OPTION SET DATAPATH OPTION SET MULTIPLIER OPTION

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ANALYZE NETLIST
ANALYZE NETLIST [-ABSTRACT [HFA | LIBCELL | MUXDFF] [-VERBose] [-GOLden | -REVised] (LEC Mode)

Note: This requires a Conformal XL license. Provides another view of the flattened netlist, which can help in datapath analysis, comparison, and diagnosis. This command can modify the structure of the flattened netlist. As the same Boolean function can have different representations in the netlist, this command provides a uniform structural transformation on the netlist—without changing the function for which the netlist represents. Note: You can apply this command only on the flattened netlists that do not contain datapath operators.

Parameters
-ABSTRACT HFA LIBCELL Abstracts the identified function blocks in the flattened netlist. Abstracts the half-adder or full-adder function blocks in the flattened netlist. Identifies the library cells in the flattened netlist and re-synthesizes them with a simpler circuit representation. This option is useful for netlists library cells that are not optimized.

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MUXDFF

Re-synthesizes the logic cone of the data input of a DFF, such that the logic cone is similar to the one shown in the following figure. This option is useful for retimed netlist and has been integrated in ANALYZE RETIMING command. +-----------------------------+ | +------+ +------+ | +--|D0 | | | | ----|D1 | | Q|--+ | MUX | | DFF | | O|---------|D | ----|S | | | +------+ +------+

-VERBose -GOLden -REVised

Provides additional information. Specifies the netlist to be analyzed is the golden netlist. This is the default. Specifies the netlist to be analyzed is the revised netlist.

Examples
The following command abstracts half-adder or full-adder function blocks in the revised netlist. LEC> ANALYZE NETLIST -ABSTRACT HFA -REVISED The following command identifies library cells used in the golden netlist and re-synthesizes them with a simpler circuit transformations. LEC> ANALYZE NETLIST -ABSTRACT LIBCELL -GOLDEN

Related Command
ANALYZE DATAPATH COMPARE

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ANALYZE NONEQUIVALENT
ANAlyze NOnequivalent [ | | ... [-Golden | -Revised] ] [-Type ...] [-Summary | -Verbose] (LEC Mode)

Note: This requires a Conformal XL license. Helps identify the possible causes of non-equivalent compared points.

Parameters Analyzes non-equivalent compared points for the specified gate.

... Analyzes non-equivalent compared points for the specified instance. -TYPE Analyzes non-equivalent compared points with the specified type.
■ ■ ■ ■ ■

PO: Primary output DFF: D flip-flop DLAT: D-latch BBOX: Blackbox CUT: Compared points with artifical gates to break combinational loops

-Golden -Revised

Analyzes non-equivalent compared points in the Golden design. This is the default. Analyzes non-equivalent compared points in the Revised design.

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-TYPE

Analyzes non-equivalent compared points with the specified type.
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PO—Primary output DFF—D flip-flop DLAT—D-latch BBOX—Blackbox CUT—Compared points with artifical gates to break combinational loops

-Summary -Verbose

Provides a summary of the analysis. This is the default. Provides additional information for each individual non-equivalent compared point.

Examples
The following shows an example of a report when running the ANALYZE NONEQUIVALENT command. The lines in bold indicate the cause of the problems:
LEC> analyze noneq 213 //Command analyze noneq 213 Analyzing non-equivalent compared points: (G) + 213 DFF /wbs/hvlen_reg[28] (R) + 6277 DFF /wbs/hvlen_reg[28]/U$1 The clock of DFF in Golden is not gated. The clock of DFF in Revised is gated. Analysis of non-equivalent compared points: Gated clock of of DFF or DLAT. (Occurrence: 1) Unknown reason. (Occurrence: 1) LEC> analyze noneq 170 -revised //Command analyze noneq 170 -revised Analyzing non-equivalent compared points: (G) + 167 PO /wbm_sel_o[0] (R) + 170 PO /wbm_sel_o[0] Following constraints may be necessary: Constant 1: (G) 1026 DFF /wbm/sel_o_reg[0] Analysis of non-equivalent compared points: Sequential constant. (Occurrence: 1) Unknown reason. (Occurrence: 1)

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The clock of DFF in Golden is not gated. The clock of DFF in Revised is gated.

by running the following command in Setup mode: set analyze option -auto

or the following command in LEC mode: analyze setup

Sequential Constant You can fix the second problem in the report:
Following constraints may be necessary: Constant 1: (G) 1026 DFF /wbm/sel_o_reg[0]

by running auto analysis in Setup mode with the following commands: set analyze option -auto set flatten model -seq_constant

or the following command in LEC mode: remodel -seq_constant

Related Command
ANALYZE SETUP

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ANALYZE POWER ASSOCIATION
ANAlyze POwer Association [-Golden | -Revised] [-Module ...>] [-OUT_Dofile | -OUT_CPF ] [-REPlace] (Setup / Verify Mode)

Note: This requires a Conformal GXL license. Analyzes the module’s SPICE netlist and identifies the power/ground pin for each input and output pin with which it is associated. Notes:
■ ■ ■

The power/ground pin definition can come from LEF or SPICE. Run the SET SPICE OPTION -NOBULK command before reading in the SPICE design to maintain the connectivity of power/ground ports. Each input or output pin can have only one associated power/ground pin. Multiple power/ground pin association are ignored.

Parameters
-Golden -Revised Analyze the Golden design. This is the default. Analyze the Revised design.

-Module ...> Specifies the module(s) to be analyzed. Without this option, all modules in the design are analyzed. This accepts wildcards. -OUT_Dofile Specifies the file to output the ADD POWER ASSOCIATION command. -OUT_CPF Specifies the output CPF file. -REPlace Replaces the specified -OUT_Dofile or -OUT_CPF file if it already exists.

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Related Commands
READ DESIGN -spice SET SPICE OPTION

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ANALYZE RETIMING
ANAlyze REtiming [-COMBinational_identical] [-PIPELINE [] [-BACKWARD] ] [-GENERAL [ [-BACKWARD]] ] [-MERGE | -NOMERGE] [-DIAGNOSIS [-BACKWARD] ] [-PREDICT [-BACKWARD] ] [-VERBose] [-BOth | -GOLden | -REVised] (LEC Mode)

Note: This requires a Conformal XL license. Initiates pipeline retiming, retiming for RC synthesized netlist, or retiming for designs that are combinationally equivalent. Normally, you use this command to retime a Revised design to match a referenced Golden design. If this command is successful, you can use the COMPARE command to ensure that the two designs are equivalent. If this command is unsuccessful, then the original retiming you performed is incorrect. For more guidelines and examples, see the “Advanced Capabilities” chapter in the Encounter Conformal Equivalence Checking User Guide.

Parameters
-COMBinational_identical Use this option on combinationally equivalent designs. Use option when you have retimed a design and want to confirm that it is equivalent to another design. Conformal retimes its registers to match their position in the reference design. Note: If you specify this option, it must be the first option in the command line. Tip If you can replace the DFF -> Q connections with buffers and your designs are still identical, then your Golden and Revised designs are considered combinationally equivalent.

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-PIPELINE -BACKWARD Moves all registers to the primary output side of the design as much as possible, or use the option to specify one or more registers, separated by a space. This accepts wildcards. -BACKWARD moves registers backward to the primary input side of the design as much as possible. With this option, pipeline backward retiming can be performed on either all registers or a selected set of registers. -GENERAL -BACKWARD Retimes registers in the design to state points. Use this option to specify the state points or use the added sequential corresponding points as the state points. You can specify an as the state point(s) or use the added sequential corresponding points as the state points. Use the -BACKWARD option to move registers backward to the specified state points. By default, registers are moved forward to the specified state points. -MERGE Specifies that equivalent registers are merged after registers are moved, including inverted-equivalent registers. This helps to reduce the unmapped register keypoints and the resulting false non-equivalences. This is the default. Disables the merging of equivalent registers after they are moved.

-NOMERGE

-DIAGNOSIS -BACKWARD Checks that a register can be retimed a step forward or backward. If the retime movement cannot succeed, the reason for the failure is reported. By default, this diagnoses the forward retiming step. Note: This option will not change the netlist. It only provides information about the specified retiming step. -BACKWARD specifies that the backward retiming step is diagnosed.

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-PREDICT -BACKWARD Predicts if registers can be retimed to the state point specified by . Use the -BACKWARD option to predict backward retiming. By default, this predicts forward retiming. -VERbose -BOTh -REVised -GOLden Prints additional information, including a list of current tasks and statistics. Executes this command on both the Golden and Revised designs. This is the default. Executes this command on the Revised design and uses the Golden design as the reference design. Executes this command on the Golden design and uses the Revised design as the reference design.

Examples
■

The following command initiates backward pipeline retiming for register r1 and registers whose identifiers begin with r2, such as r2a and r21, in the Revised design: analyze retiming -pipeline r1 r2* -revised -backward

■

The following command manually retimes to the specified state points: analyze retiming -general retime_state_point* -backward -verbose

The following demonstrates how to use the ANALYZE RETIMING -comb_identical command with other commands. 1. Read in your library.
SETUP> read lib -lib matrox_test1.lib // Parsing file matrox_test1.lib ... // Note: Read Liberty library successfully

2. Read in your Golden and Revised designs.
SETUP> read design -golden matrox_test1_brt.v // Parsing file matrox_test1_brt.v ... // Golden root module is set to ’hst_ssurfdes’ // Note: Read VERILOG design successfully SETUP> read design -revised matrox_test1_art.v // Parsing file matrox_test1_art.v ... // Revised root module is set to ’hst_ssurfdes’ // Note: Read VERILOG design successfully

3. Switch to LEC mode.
SETUP> set system mode LEC // Processing Golden ... // Modeling Golden ... // Processing Revised ...

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// Modeling Revised ... // Mapping key points ... . . .

4. Use the ANALYZE RETIMING -comb_identical command and attempt to retime the Revised design to match the Golden design.
LEC> analyze retiming -combinational_identical // Retimed successfully 859 registers in Revised as 141 registers // All comparison points have been deleted // All key points have been unmapped // Mapping key points ... =========================================================================== Mapped points: SYSTEM class --------------------------------------------------------------------------Mapped points PI PO DFF Total --------------------------------------------------------------------------Golden 1632 29 147 1808 --------------------------------------------------------------------------Revised 1632 29 147 1808 ===========================================================================

5. Add “all” mapped points, excluding primary inputs, as compare points.
LEC> add comp points -all // 176 compared points added to compare list

6. Use the COMPARE command to start the equivalency checking comparison.
LEC> compare =========================================================================== Compared points PO DFF Total --------------------------------------------------------------------------Equivalent 29 147 176 ===========================================================================

Related Commands
ADD SEQ_CORR ADD COMPARED POINTS ADD MODULE ATTRIBUTE COMPARE DELETE SEQ_CORR REPORT SEQ_CORR SET RETIMING OPTION

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ANALYZE SETUP
ANAlyze SEtup [-NOCUT | -CUT] [-NOLIBRARY_VERIFICATION | -LIBRARY_VERIFICATION] [-PHASE_MAPPING | -NOPHASE_MAPPING] [-SEQ_MERGE | -NOSEQ_MERGE] [-NOFORCE | -FORCE] [-EFFORT ] [-VERBose] (LEC Mode)

Note: This requires a Conformal XL license. Analyzes the netlists and sets up the flattened design for accurate comparison. This helps avoid false non-equivalences. This command can also analyze and remodel the following commonly-encountered setup issues: sequential constanting, sequential merging, loop cutting, clock gating, and phase mapping. Note: To resolve sequential constant optimization with this command, you must use the following command: set flatten model -seq_constant

Parameters
-NOCUT -CUT Does not analyze loop cutting. This is the default. Analyzes loop cutting. When creating flattened netlists, the Conformal software breaks all loops by inserting CUT gates, which could cause false non-equivalences. With this option, you can resolve these false non-equivalences.

-NOLIBRARY_VERIFICATION Does not perform setup analysis for library cell verification. This is the default. -LIBRARY_VERIFICATION Performs setup analysis for library cell verification. -PHASE_MAPPING -NOPHASE_MAPPING Enables phase adjustment for DFF/D-LATCH mapping during automatic analysis and analyze setup. This is the default. Disables phase adjustment for DFF/D-LATCH mapping during automatic analysis and analyze setup.

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-SEQ_MERGE -NOSEQ_MERGE -NOFORCE

Enables the merge of DFF/D-LATCH. This is the default. Disables the merge of DFF/D-LATCH. ANALYZE SETUP is skipped when it is called after all mapped points are added as compared points, and all compared points are either equivalent or abort. This is the default. Forces the tool to run ANALYZE SETUP, regardless of the compare status.

-FORCE

-EFFORT Specifies the effort level for automatic setup. Medium is the default. -VERBose Provides additional information.

Related Commands
ANALYZE NONEQUIVALENT SET ANALYZE OPTION

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ASSIGN PIN DIRECTION
ASSign PIn Direction [-Golden | -Revised | -Both] [-FROM_DIr ] (Setup Mode)

Defines a module pin’s direction. SPICE netlist ports do not have direction, unless you supply *.pininfo : as a CDL comment and read it in as an inout. Abstraction analyzes the circuit and assigns pin direction—when determinable. In some cases, you need to assign pin direction manually to complete abstraction. Note: You can use this command instead of the ADD MOS DIRECTION command to assist abstraction. Wildcard: The wildcard (*) represents any zero or more characters in pin names.

Parameters
IN OUT IO -Golden -Revised -Both -FROM_DIr Specifies that the assigned pin direction is input. Specifies that the assigned pin direction is output. Specifies that the assigned pin direction is I/O. Specifies that the pin resides in the specified module. Assigns a direction to the specified pin. Assigns the pin direction to the Golden design. This is the default. Assigns the pin direction to the Revised design. Assigns the pin direction to both the Golden and Revised designs. Only pins which have the direction specified by this option’s argument will be redirected.

Examples assign pin direction in mux2p sela -revised

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Encounter Conformal Equivalence Checking Reference Manual Command Reference assign pin direction out mux4p y -golden assign pin direction in mux2p sela y -both //Assigns direction to pins sela and y. assign pin direction IN mod pin_* -from_type IO //Changes all IO pins whose name matches ‘pin_*’ in //module ‘mod’ to IN pins on the golden side.

Related Commands
ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE

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BACKWARD
BACkward [] (LEC Mode)

Reports fanin gate information from the currently displayed flattened gate information. The fanin gate you choose with this command becomes the current flattened gate. Use this command to trace gates in place of repeatedly using the REPORT GATE command. Note: This command does not report gates at the design level.

Parameters Specifies which fanin gate is reported. The value 1 denotes the first fanin. The default value is 1.

Related Commands
FORWARD REPORT GATE

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BREAK
BREak (Setup / LEC Mode)

Terminates the dofile script and returns you to the system mode prompt.

Related Commands
CONTINUE DOFILE SET DOFILE ABORT

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CHANGE GATE TYPE
CHAnge GAte Type -Type [-Help] [-Golden | -Revised] (LEC Mode)

Changes the gate type of a selected object in the schematic viewer. Note: You cannot use this command on pins and nets. Note: If you invoke the Flatten Schematics window for a candidate gate (such as Corresponding Supports and Compared Points) from the Diagnosis Manager, you cannot change its gate type.

Parameters Specifies the gate ID or instance pathname. If you do not specify one of the following options, Conformal automatically determines if the identifier is a number or a path. In the case of a number, Conformal uses the -id option; otherwise, Conformal searches for the gate with the -instance, -pin, or -net option; in this respective order. -Type Changes the specified gate type, which can be AND, NAND, OR, NOR, XOR, XNOR, BUF, or INV. Note: Not all types are available for all objects -Help -Golden -Revised Returns a list of potential candidate gate types that can be applied. Specifies that the identifier is in the Golden design. This is the default. Specifies that the identifier is in the Revised design.

Related Commands
REPORT GATE

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CHANGE NAME
CHAnge NAme [-Summary | -Verbose] [-Golden | -Revised | -Both] (Setup Mode)

Converts netlist net names, port names, and cell names back to their original names. Thus, Conformal does key point mapping faster and more efficiently. The most common use of this command is to change the names in a post synthesis netlist back to their original, presynthesis forms. After Conformal reads in the file containing the original names and new names, it makes the conversion. Generally, the synthesis tool you have used generates the file describing the changes. Consult the specific vendor’s tool documentation for additional change name information. The format of the change name file is as follows:
■

The change name information is preceded by dashes. Note the dashes in the example below that separate column headers and the change name information. Conformal recognizes this file as a change name file format when it detects the dashes. The “Design” column consists of module names. For example, see mod0_module in the sample Change Name file below. The “Type” column consists of elements that belong to the specified design (that is, cell, port, and net). The “Object” is the original name. Conformal will change the name back from the “New Name” to the original name. The “New Name” is the name assigned by the synthesis tool
Design Type Object New Name ---------------------------------------------------------mod0_module port port0_input1 port0_1 mod0_module net net0_output net0_t mod1_module port port1_input1a port_1a mod1_module cell net1_subinstantiation net1_n

■ ■ ■ ■

Parameters Specifies the file that contains name changes.

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-Summary -Verbose -Golden -Revised -Both

Prints out the summary count of the number of name changes. This is the default. Prints out a message for each name change. Changes names in the Golden design. This is the default. Changes names in the Revised design. Changes names in both the Golden and Revised designs.

Related Commands
ADD RENAMING RULE DELETE RENAMING RULE REPORT RENAMING RULE

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CHECK LOWPOWER CELLS
CHEck LOwpower Cells (LEC Mode)

Note: This is a Conformal Low Power command. Performs low power checks for low power cell types that were specified with the SET LOWPOWER OPTION command. This check consists of the state retention technology mapping check, isolation and level-shifter cell check, and the power domain consistency check. These checks are described as follows: State Retention Cells For state retention cells, this command does the technology mapping check to ensure that the sequential elements (DFFs or DLATs) are technology mapped in accordance with the retention mapping rules during synthesis. These retention mapping rules include all the user rules added with the ADD RETENTION MAPPING command and the default rule added by the system. The following three default rules are added by the system: Note: For any sequential pairs, only one of the default rules take effect.
■

Default: Checks that the tag name used in the Golden design is mapped to a non-state retention cell in the Revised design. A non-state retention cell is a cell that does not have a power_gating_cell attribute. This rule is normally applied during RTL to gate-level checks. Default1: Checks that the power_gating_cell attribute in the Golden design is exactly the same as the power_gating_cell in the Revised design. This check ensures that non-state retention cells (regular DFFs or DLATs) are mapped to non-state retention cells, or state retention cells are mapped to state retention cells. This rule is normally applied during gate-level to gate-level checks. Default2: Checks that the tag name used in the Golden design is exactly the same as the tag name used in the Revised design. This rule is normally applied during RTL to RTL checks.

■

■

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Isolation Cells and Level-Shifter Cells For isolation cells and level-shifter cells, this command does the technology mapping check and equivalence check. The technology mapping check ensures that for each low power cell (isolation cell or level-shifter cell) in the Golden design, there is a corresponding low power cell in the Revised design. To establish the correspondence, the Conformal software inserts key points (cut gates) at the output of low power cells and performs name-based mapping. If it does not find mapping for a low power cut gate, it sets the status of the corresponding low power cell to FAIL; otherwise, the status is set to PASS. The equivalence check (EC) ensures that for the mapped low power cell pair, the logic feeding them is equivalent in both the Golden and Revised designs. To perform EC, the Conformal software adds the low power cut gates as compare points and these are proven equivalent or non-equivalent during compare (when running the COMPARE command). Note: The CHECK LOWPOWER CELLS command performs only the technology mapping check for isolation cells and level-shifter cells. The EC checking results are received after running the COMPARE command. After performing the low power check, a status summary is printed for all low power cells. Power Domain Consistency Check Power domain consistency checking is available in the CPF flow. This checks whether the sequential mapped pair resides in the same power domain between the Golden and Revised designs. You can perform this check after reading in the CPF files for both the Golden and Revised designs. For RTL and synthesized gate netlists, the power domain of key-points can only be obtained from the CPF specification. For the physical netlist, the power domain can be obtained either from the CPF specification or by tracing the power and ground pins. The power domain consistency check sets the status of the mapped pair to FAIL if the power domains of the Golden and Revised sequential points in the mapped pair are different. In the case of merged sequential points, if the power domains of any of the merged elements are different, the power domain consistency check will set the status of the corresponding pair to FAIL. Note: The power domain consistency check is only enabled for sequential compare points. Note: Use the SET MAPPING METHOD -unreach command to allow mapping and checking the consistency of power domains for unreachable key-points.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference If the power domain cannot be obtained for sequential element in the mapped pair, the power domain consistency check sets the mapped pair status to NOT-CHECKED. The following are the scenarios where power domains cannot be obtained for a sequential element:
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CPF is not read in. CPF specification is incomplete. For example, no default power domain is specified or CPF does not have the definition of internal power and ground nets.

■ ■

LEF file is not read in. Power and Ground pins are floating in the physical netlist.

Related Commands
ADD LOWPOWER CELLS ADD RETENTION MAPPING COMPARE REPORT LOWPOWER CELLS REPORT LOWPOWER DATA SET LOWPOWER OPTION

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CHANGE NET TYPE
CHAnge NEt Type |-Module ] [-Golden | -Revised] (Setup Mode)

Note: This requires a Conformal GXL license. Modifies the database so that it appears that the changed net types were declared in the original Verilog netlist.

Parameters
TRI TRI0 TRI1 TRIREG TRIAND TRIOR Specifies a tristate net type. This is the default. Specifies a net of type TRI0. Specifies a net of type TRI1. Specifies a net of type TRIREG. Specifies a net of type TRIAND. Specifies a net of type TRIOR.

-Module Specifies the module name of the net to be changed. By default, this command changes the net in the root module.

Related Command
ADD NET ATTRIBUTE

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CLOSE SCHEMATICS
CLOse SChematics (Setup / LEC Mode)

Closes all schematic viewer windows. Note: You cannot use this command in non-GUI mode.

Related Command
OPEN SCHEMATICS

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COMMIT CPF
COMmit CPf [-INSERT [-ISO] [-LS] [-RET] | -FUNCTIONAL INSERTION] [-GOLden | -REVised | -BOTH] [-CREATE_FUNCTIONAL_MODEL] (Setup Mode)

Note: This is a Conformal Low Power command. Applies CPF low power cell information. When performing insertion, the cell types can be isolation cells, level shifter cells, and state retention cells. These low power cells can either be defined in .lib or defined in CPF files. You can only run this command after successfully reading in the CPF files.

Parameters
-INSERT [-ISO] [-LS] [-RET] Inserts low power cells into the design. By default, this option includes isolation, level shifter, and state retention cell types. To specify any combination of these cell types, use one or more of the following -INSERT options: -ISO for isolation cell insertion. -LS for level shifter cell insertion. -RET for retention cell insertion. -FUNCTIONAL_INSERTION Inserts only isolation cells and state retention cells. In this mode, the inserted isolation cells will be close to the destination pin, thus avoiding the need for port splitting. This ignores the location specification of the rule, which is not important for checking functional behavior, such as logic equivalence.. -GOLden -REVised -BOTH Inserts low power cells in the Golden design. This is the default. Inserts low power cells in the Revised design. Inserts low power cells in both the Golden and Revised designs.

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-CREATE_FUNCTIONAL_MODEL Remodel black-boxed switch cells based on defined CPF cell declarations. The functional model ic created with power/ground port removal.

Examples
■

The following commands show an example of the CPF equivalency checking flow, which performs low power cell insertion on the Golden side, and performs equivalency checks with physical implementation in two CPF files named rtl.cpf and my_library.cpf: read lef file my_library.lef read library -liberty my_library.lib -both read design rtl.v -verilog -golden read cpf rtl.cpf my_library.cpf commit cpf -insert read design physical.v -verilog -revised set system mode lec add compare points -all compare

■

The following command inserts isolation and level shifters, but skips retention cell insertion: commit cpf -insert -iso -ls

■

The following commands insert isolation cells only in the first step, and then inserts retention cells later in the session: commit cpf -insert -ret set system mode lec add compare points -all compare set system mode setup commit cpf -insert -iso -ls set system mode lec add compare points -all compare

Related Command
READ CPF REPORT CPF LOGIC

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COMMIT LIBRARY INSTANCE
COMMIT LIBRARY INSTANCE [-Golden | -Revised]

Use this command to insert the library instance added by the ADD LIBRARY INSTANCE command.

Parameters
-Golden -Revised Applies to the Golden design. This is the default. Applies to the Revised design.

Related Commands
ADD LIBRARY INSTANCE DELETE LIBRARY INSTANCE

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COMPARE
COMpare [-NONEQ_Stop ] [-ABORT_Stop ] [-NONEQ_Print] [-ABORT_Print] [-PARALLEL ] [-GATE_TO_GATE] [-SIngle] [-NOREPORT_BBOX_INPUT | -REPORT_BBOX_INPUT] [-NOREPORT_SINGLE_LINE_SUMMARY | -REPORT_SINGLE_LINE_SUMMARY] [-THREADS [,]] [-TIMEstamp] (LEC Mode)

Starts the equivalency checking comparison between the Golden and Revised designs on the added compared points. During the comparison, the following information is displayed:
■ ■

Progress percentile number, which displays the completion rate Running count, which displays the number of key points that have been compared along with the total number of non-equivalent key points

Each compared point results in a status drawn from the following five possibilities:
■ ■ ■ ■ ■

Equivalent Inverted equivalent Nonequivalent Abort Not compared

When Conformal completes the comparison, it displays a summary table of the number of equivalent and non-equivalent compared points. Note: If you must interrupt the comparison, the Control-C keys stop the process. Note: By default, when the clock port is disabled, the data cone will not be compared. The software might perform modeling that disables the clock port, so the disabled clock might not necessarily mean the clock in original netlist is disabled.

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Parameters
-NONEQ_Stop -ABORT_Stop -NONEQ_Print -ABORT_Print Stops the comparison after finding the specified number of non-equivalent points. Stops the comparison after finding the specified number of abort points. Displays the non-equivalent points as they are found. Displays the abort points as they are found.

-PARALLEL Note: This option requires a Conformal XL license. Runs a comparison on multiple machines. Tip You can use the USAGE command to display the total CPU time used for all processes. For more information on creating a machine_file, see Multi-Threaded Processing in the Encounter Conformal Equivalence Checking User Guide. -GATE_TO_GATE -SIngle -NOREPORT_BBOX_INPUT -REPORT_BBOX_INPUT Enables an algorithm that might improve the run time of large gate-to-gate netlist comparisons. Compares each key point as a single point. By default, the COMPARE command compares by key point groups. Does not report the blackbox input pins in the compare report results. This is the default. Reports the blackbox input pins in the compare report results (Equivalent, Non-equivalent, Abort, and Not-compared).

-NOREPORT_SINGLE_LINE_SUMMARY Does not print a single line summary of the compare results. This is the default. -REPORT_SINGLE_LINE_SUMMARY Prints a single line summary of the compare results.

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-THREADS [,] Specifies the number of compare threads. This supersedes the SET PARALLEL OPTION -threads setting. -TIMEstamp Displays the system time (HH:MM format) of the last compare status update.

Examples
The following is a set of sample commands that shows this and related commands in context. The following set of commands assumes that you have read in your library, design, and have switched to the LEC mode. 1. Use the ADD COMPARED POINTS command to add mapped points to the compare list.
LEC> add compare point -all //2 compared points added to compare list

2. Use the COMPARE command to start the equivalency comparison between the Golden and Revised designs.
LEC> compare ============================================================================ Compared points PO Total ---------------------------------------------------------------------------Equivalent 1 1 ---------------------------------------------------------------------------Non-equivalent 1 1 ============================================================================

3. Use the REPORT COMPARE DATA command to report the non-equivalent points.
LEC> rep comp data -noneq Compared points are: Non-equivalent + 11 PO /x + 11 PO /x

1 compared point(s) reported ============================================================================ Compared points PO Total ---------------------------------------------------------------------------Equivalent 1 1 ---------------------------------------------------------------------------Non-equivalent 1 1 ============================================================================

4. Use the ADD DYNAMIC CONSTRAINT command to add a dynamic constraint to the design.
LEC> add dyn con 0 /c -gold LEC> add dyn con 0 /c -rev

5. Use the REPORT DYNAMIC CONSTRAINTS to report the dynamic constraints in the design.
LEC> report dynamic constraints ============================================================================ Design ID Type Value Name ----------------------------------------------------------------------------

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Golden 3 PI 0 /c Revised 3 PI 0 /c ============================================================================

6. Use the PROVE command to show whether the specified gates are equivalent or not equivalent.
LEC> prove /x /x //Compared points are: Non-equivalent //(G) + 11 PO /x //(R) + 11 PO /x

7. Use the DIAGNOSE command to diagnose the non-equivalent points.
LEC> diag /x //Diagnosis for Non-equivalent key points: //(G) + 11 PO /x //(R) + 11 PO /x The diagnosis point can be corrected by changing the following gates: ============================================================================ Correction ID (R) Type Name ---------------------------------------------------------------------------DEL_INVERTER 24 INV /gextra

8. Use the REPORT MESSAGE command to show the message related to the comparison.
LEC> report message -compare -verb // Warning: 1 DFFs/DLATs have 1 disabled clock port: skipped data cone comparison (G) + 4 (R) + 4 DLAT /z_reg - skipped data cone z_reg with corresponding clock cone z_reg DLAT /z_reg - skipped data cone z_reg with corresponding clock cone z_reg

Related Commands
ADD COMPARED POINTS DELETE COMPARED POINTS DIAGNOSE PROVE REPORT COMPARE DATA REPORT COMPARED POINTS RUN PARALLEL COMPARE SET COMPARE EFFORT USAGE

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CONFORMAL NEWS
CONFORMAL NEWS (Setup/LEC Mode)

Displays the Conformal blog in the default browser. To change the default browser for this command, use the CONFORMAL_BROWSER environment variable.

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CONTINUE
CONTinue (Setup / LEC Mode)

Used in conjunction with the BREAK command in a dofile, when a dofile executes the BREAK command, Conformal issues a warning and prompts you to use the CONTINUE command. The CONTINUE command has no effect if you type it without being prompted by Conformal. The CONTINUE command supports mixed GUI and non-GUI mode. For example, you can run a dofile in non-GUI mode, encounter a break in the dofile, issue set gui on, and run continue from the GUI. The same applies when you break in the GUI mode: switch to command mode and enter continue. Conformal also supports nested breaks inside dofiles, working in a stack fashion. For example, when you type in continue from a lower-level dofile, Conformal proceeds until it encounters the next BREAK command.

Example
//Warning: Break dofile ‘my_dofile’ at line 32. Use ‘continue’ command to continue. % continue

Related Commands
BREAK DOFILE SET DOFILE ABORT

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COPY MODULE
COPy MOdule [-LOGIC | -PINDIR] [-USE_RENAME_RULE | -NOUSE_RENAME_RULE] (Setup Mode)

Copies the logic or pin direction from a source module in one design to a target module in the other design. If you must copy both the logic and the pin direction, use two separate commands.

Parameters
-Golden -Revised -Revised -Golden -LOGIC Specifies that the source module is located in the Golden design. This is the default. Specifies that the source module is located in the Revised design. Specifies the name of the source module to be copied. Specifies that the target module is located in the Revised design. This is the default. Specifies that the target module is located in the Golden design. Specifies the name of the target module for the copy operation. Copies the logic from the source module into the target module. This is the default. If you must copy both logic and pin direction, use two separate COPY MODULE commands. -PINDIR Copies the pin direction from the source module into the target module. If you must copy both logic and pin direction, use two separate Copy Module commands. Uses renaming rules for matching pin and module names. This is the default. Does not use renaming rules for matching pin and module names.

-USE_RENAME_RULE -NOUSE_RENAME_RULE

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Related Command
ASSIGN PIN DIRECTION

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DELETE ALIAS
DELete ALias (Setup / LEC Mode)

Deletes aliases created with the ADD ALIAS command. Use the REPORT ALIAS command to display a list of all aliases. Wildcard: The wildcard (*) represents any zero or more characters in alias names.

Parameters Deletes the specified aliases.

Related Commands
ADD ALIAS REPORT ALIAS

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DELETE BLACK BOX
DELete BLack Box [-Golden | -Revised | -Both] (Setup Mode)

Deletes specified blackboxes from the design. These blackboxes were either created with the ADD BLACK BOX command or were a part of the original design. Use the REPORT BLACK BOX command to display a list of all blackboxes. Wildcard: The wildcard (*) represents any zero or more characters in module names.

Parameters ... -Module ... -Instance Specifies that the blackbox names are instance names. -All -Golden -Revised -Both Deletes “all” defined blackboxes. -All applies within the given defaults. Deletes blackboxes from the Golden design. This is the default. Deletes blackboxes from the Revised design. Deletes blackboxes from both the Golden and Revised designs. Deletes blackboxes specified by this list. -module is the default.

Related Commands
ADD BLACK BOX REPORT BLACK BOX

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DELETE CLOCK
DELete CLock [-Golden | -Revised] (Setup Mode)

Deletes clocks added with the ADD CLOCK command. Use the REPORT CLOCK command to display a list of all aliases.

Parameters
-ALL_Pin -Golden -Revised Deletes all the defined clocks within the given defaults. Deletes the primary input pins that were defined as clocks and specified in this list. Deletes the clock(s) from the Golden design. This is the default. Deletes the clock(s) from the Revised design.

Related Commands
ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION
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DELETE COMPARED POINTS
DELete COmpared Points < -All | > (LEC Mode)

Deletes compared points originally added with the ADD COMPARED POINTS command. If the compared point is deleted from the Golden design, Conformal also deletes its mapped compared point from the Revised design. Alternately, if the compared point is deleted from the Revised design, Conformal also deletes its mapped compared point from the Golden design. Use the REPORT COMPARED POINTS command to display a list of all added compared points. Wildcard: The wildcard (*) represents any zero or more characters in instance and pin paths.

Parameters
-All Deletes all compare points within the given defaults. Deletes the specified gates as compare points. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. Deletes the specified instance paths as compare points. -Golden -Revised Deletes the specified pin paths as compare points. Deletes the compare points from the Golden design. This is the default. Deletes the compare points from the Revised design.

Related Commands
ADD COMPARED POINTS COMPARE
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DELETE CUT POINT
DELete CUt Point [-Net | -Pin] [-Golden | -Revised | -Both] (Setup Mode)

Deletes cut points originally added with the ADD CUT POINT command. Use the REPORT CUT POINT command to display a list of all added cut points.

Parameters
-All -Net -Pin -Golden -Revised -Both Deletes all cut points within the given defaults. Deletes cut points from the specified paths. Specifies that the named path is a net. This is the default. Specifies that the named path is a pin. Deletes the cut points from the Golden design. This is the default. Deletes the cut points from the Revised design. Deletes the cut points from both the Golden and Revised designs.

Related Commands
ADD CUT POINT REPORT CUT POINT REPORT PATH

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DELETE DYNAMIC CONSTRAINTS
DELete DYnamic Constraints [-INStance | -Pin | -Net | -ID] [-Golden | -Revised | -Both] (LEC Mode)

Deletes dynamic constraints originally added with the ADD DYNAMIC CONSTRAINTS command. Use the REPORT DYNAMIC CONSTRAINTS command to display a list of all added dynamic constraints.

Parameters
-All Deletes all dynamic constraints within the given defaults. Deletes dynamic constraints from the specified identifier. If you do not specify one of the following options, Conformal automatically determines if the identifier is a number or a path. In the case of a number, Conformal uses the -id option; otherwise, Conformal searches for the gate with the -instance, -pin, or -net option; in this respective order. Specifies the hierarchical instance path. This is the default. Specifies the pin path, which is the module instance name concatenated with the pin name. Specifies the net path, which is the instance name concatenated with the net name. Specifies the identification number (ID) of a gate. The identification number is an integer assigned automatically by Conformal. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -Golden -Revised Deletes dynamic constraints from the Golden design. This is the default. Deletes dynamic constraints from the Revised design.

-INStance -Pin -Net -ID

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-Both

Deletes dynamic constraints from both the Golden and Revised designs.

Related Commands
ADD DYNAMIC CONSTRAINTS PROVE REPORT DYNAMIC CONSTRAINTS

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DELETE IGNORE RTLCHECK
DELete IGnore Rtlcheck (Setup Mode)

Re-enables RTL (HDL) rule checking for all or specified modules. By default, rule checking is enabled. Thus, you will only use this command to reverse the effects of the ADD IGNORE RTLCHECK command. For additional information about specific rules, see Encounter Conformal Equivalence Checking User Guide. Note: If you enter multiple IGNORE RTLCHECK commands, later commands replace previous commands. In the following example, Conformal enables RTL rule checking for all modules, including module abc. add ignore rtlcheck -module abc delete ignore rtlcheck -all

Parameters
-All Enables RTL rule checking for all modules.

-Module Enables RTL rule checking for the specified modules.

Related Commands
ADD IGNORE RTLCHECK REPORT RULE CHECK

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DELETE IGNORED INPUTS
DELete IGnored Inputs [-ROot |-Module | -ALL_Module] [-Golden | -REvised | -Both] (Setup Mode)

Deletes input pins originally added as ignored inputs in the Golden or Revised design with the ADD IGNORED INPUTS command. Use the REPORT IGNORED INPUTS command to display a list of all added ignored input pins. Wildcard: The wildcard (*) represents any zero or more characters in ignored input names.

Parameters
-ALL_Pin -ROot Deletes all previously added ignored inputs within the given defaults. Deletes the specified pins as ignored inputs. This accepts wildcards. Deletes the ignored inputs in the root module. This is the default.

-Module Deletes the ignored inputs from the specified module. -ALL_Module -Golden -REvised -Both Deletes the ignored inputs from all of the modules, including the root module. Deletes the specified ignored inputs from the Golden design. This is the default. Deletes the specified ignored inputs from the Revised design. Deletes the specified ignored inputs from both the Golden and Revised designs.

Related Commands
ADD IGNORED INPUTS REPORT IGNORED INPUTS
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DELETE IGNORED OUTPUTS
DELete IGnored Outputs [-ROot | -Module | -ALL_Module] [-Golden | -REvised | -Both] (Setup Mode)

Deletes output or I/O pins originally added as ignored outputs with the ADD IGNORED OUTPUTS command. Use the REPORT IGNORED OUTPUTS command to display a list of all added ignored output or I/O pins. Wildcard: The wildcard (*) represents any zero or more characters in ignored output names.

Parameters
-ALL_Pin -ROot Deletes all added ignored outputs within the given defaults. Deletes the specified pins as ignored outputs. This accepts wildcards. Deletes the ignored outputs in the root module. This is the default.

-Module Deletes the ignored outputs from the specified module. -ALL_Module -Golden -REvised -Both Deletes the ignored outputs from all modules, including the root module. Deletes the specified ignored outputs from the Golden design. This is the default. Deletes the specified ignored outputs from the Revised design. Deletes the specified ignored outputs from both the Golden and Revised designs.

Related Commands
ADD IGNORED OUTPUTS REPORT IGNORED OUTPUTS
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DELETE INSTANCE ATTRIBUTE
DELete INstance Attribute [-Golden | -Revised] (Setup Mode)

Deletes instance attributes originally added with the ADD INSTANCE ATTRIBUTE command. Use the REPORT INSTANCE ATTRIBUTE command to display a list of all added instance attributes.

Parameters Deletes the instance attribute from the specified module. Deletes the instance attribute from the specified instance. Specifies drive strength. Note: This option applies to Conformal Custom. -Golden -Revised Deletes the instance attribute from the Golden design. This is the default. Deletes the instance attribute from the Revised design.

Related Commands
ADD INSTANCE ATTRIBUTE REPORT INSTANCE ATTRIBUTE

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DELETE INSTANCE CONSTRAINTS
DELete INstance Constraints [-Golden | -Revised | -BOTH] (Setup Mode)

Deletes instance constraints originally added with the ADD INSTANCE CONSTRAINTS command. Use the REPORT INSTANCE CONSTRAINTS command to display a list of all added instance constraints.

Parameters Deletes constraints on the specified instance paths. Note: The names are either DFFs or D-latches. -Module Deletes the constraints from the specified module(s). This accepts wildcards. -All -Golden -Revised -BOTH Deletes all instance constraints. -All applies within the given defaults. Deletes instance constraints in the Golden design. This is the default. Deletes instance constraints in the Revised design. Deletes instance constraints in both the Golden and Revised designs.

Related Commands
ADD INSTANCE CONSTRAINTS REPORT INSTANCE CONSTRAINTS

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DELETE INSTANCE EQUIVALENCES
DELete INstance Equivalences < | -All> [-Golden | -Revised | -Both] (Setup Mode)

Deletes instance equivalences originally added with the ADD INSTANCE EQUIVALENCES command. Use the REPORT INSTANCE EQUIVALENCES command to display a list of all added instance equivalences.

Parameters Deletes equivalences on the specified instance path(s). This accepts wildcards. -All -Golden -Revised -Both Deletes all instance equivalences within the given defaults. Deletes instance equivalences in the Golden design. This is the default. Deletes instance equivalences in the Revised design. Deletes instance equivalences in both the Golden and Revised designs.

Related Commands
ADD INSTANCE EQUIVALENCES REPORT INSTANCE EQUIVALENCES

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DELETE LIBRARY INSTANCE
DELETE LIBRARY INSTANCE -TARget [-Golden | -Revised]

Deletes the primitive instance added by the ADD LIBRARY INSTANCE command. This command takes affect before the COMMIT LIBRARY INSTANCE command executes.

Parameters
-TARget

Removes the instance at the specified target. Target string should be a hierachical name of the instance pin. Applies to the Golden design. This is the default. Applies to the Revised design.

-Golden -Revised

Related Commands
ADD LIBRARY INSTANCE COMMIT LIBRARY INSTANCE

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DELETE LOWPOWER CELLS
DELete LOwpower Cells [-Both | -Golden | -Revised] (Setup Mode)

Deletes low power cells that were originally defined for modules with the ADD LOWPOWER CELLS command. Use the REPORT LOWPOWER CELLS command to display a list of the low power cells used in the design.

Parameters -ALL -Both -Golden -Revised Deletes previously added low power cells from the specified modules. This accepts wildcards. Deletes previously added low power cells from all modules. All applies within the given defaults. Deletes the low power cells in the Golden and Revised designs. This is the default. Deletes the low power cells in the Golden design. Deletes the low power cells in the Revised design.

Related Commands
ADD LOWPOWER CELLS CHECK LOWPOWER CELLS REPORT LOWPOWER CELLS REPORT LOWPOWER DATA SET LOWPOWER OPTION

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DELETE MAPPED POINTS
DELete MApped Points |[-NONEQ] |[-UNREACH] > (LEC Mode)

Deletes mapped points that were one of the following:
■ ■

Automatically identified Added with the ADD MAPPED POINTS command.

Additionally, Conformal deletes all compared points associated with the added mapped points. Use the REPORT MAPPED POINTS command to display a list of all mapped points in the User and System classes of the Golden and Revised designs. Wildcard: The wildcard (*) represents any zero or more characters in instance or pin paths of mapped points.

Parameters
-All -Class Deletes all mapped points within the given defaults. Deletes the specified class of mapped points. Full The Full class includes mapped points from both the User and System classes. This is the default. The User class includes mapped points that were previously added with the ADD MAPPED POINTS command. The System class includes mapped points that were automatically identified when Conformal exited the Setup system mode or were mapped with the MAP KEY POINTS command.

User

System

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...

Deletes mapped points with these gate ID numbers. This accepts wildcards. ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

... Deletes mapped points from the specified instance paths. This accepts wildcards. ... Deletes mapped points from the specified pin paths. -Golden -Revised -NONEQ -UNREACH Delete the mapped points from the Golden design. This is the default. Deletes the mapped points from the Revised design. Deletes all non-equivalent mapped points. Deletes all unreachable mapped points. An unreachable mapped point is one where both the Golden and Revised key points are unreachable. If the key point is the representative of the equivalence group or sequential merge group, it is considered unreachable only if all the member key points in the group are unreachable.

Related Commands
ADD MAPPED POINTS MAP KEY POINTS REPORT MAPPED POINTS REPORT UNMAPPED POINTS SET MAPPING METHOD SET NAMING RULE

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DELETE MODULE ATTRIBUTE
DELete MOdule Attribute [-Golden | -Revised] (Setup Mode)

Deletes attributes originally assigned to modules with the ADD MODULE ATTRIBUTE command. Use the REPORT MODULE ATTRIBUTE command to display a list of all added module attributes.

Parameters -ALL -PIPELINE_Retime -COMPARE_Effort -CPU_Limit -Golden -Revised Deletes previously added attributes from the specified modules. Deletes previously added attributes from all modules within the given defaults. Deletes attributes previously added for pipeline-retiming. Deletes compare effort levels previously added to modules. Deletes the CPU time limit imposed with the ADD MODULE ATTRIBUTE command. Deletes the specified module attributes in the Golden design. This is the default. Deletes the specified module attributes in the Revised design.

Related Commands
ADD MODULE ATTRIBUTE REPORT MODULE ATTRIBUTE WRITE HIER_COMPARE DOFILE

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DELETE MOS DIRECTION
DELete MOs Direction [-Golden | -Revised] (Setup Mode)

Note: This requires a Conformal GXL license. Deletes the unidirection that was placed on transistor-MOS instances with the ADD MOS DIRECTION command. Use the REPORT MOS DIRECTION command to display a list of all transistor-MOS direction instances.

Parameters -Golden -Revised Deletes MOS direction for the specified module. Deletes MOS direction for the specified instance. Deletes MOS direction from the Golden design. This is the default. Deletes MOS direction from the Revised design.

Related Commands
ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE NET ATTRIBUTE READ PATTERN

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE

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DELETE NET ATTRIBUTE
DELete NEt Attribute [-ROot | -Module | -ALL_Module] [-Golden | -Revised | -Both] (Setup Mode)

Note: This requires a Conformal GXL license. Deletes attributes that were placed on transistor-MOS nets with the ADD NET ATTRIBUTE command. Use the REPORT NET ATTRIBUTE command to display a list of all attributes placed on transistor-MOS nets.

Parameters
-ALL_Net -ROot Deletes all net attributes within the given defaults. Deletes the specified transistor-MOS net attributes. Deletes net attributes associated with the root module, which contains the transistor-MOS. This is the default.

-Module Deletes net attributes associated with the specified module, which contains the transistor-MOS. -ALL_Module Deletes a specified net attribute for all modules, or delete all net attributes for all modules. (Refer to -all_net and -net_name to understand the two choices.) Deletes net attributes from the Golden design. This is the default. Deletes net attributes from the Revised design. Deletes net attributes from both the Golden and Revised designs.

-Golden -Revised -Both

Related Commands
ABSTRACT LOGIC

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Encounter Conformal Equivalence Checking Reference Manual Command Reference ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE

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DELETE NET CONSTRAINTS
DELete NEt Constraints [-Golden | -Revised | -Both] (Setup Mode)

Deletes either the Golden or Revised design net constraints originally added with the ADD NET CONSTRAINTS command. Use the REPORT NET CONSTRAINTS command to display a list of all added net constraints.

Parameters
-Golden -Revised -Both Deletes net constraints from the Golden design. This is the default. Deletes net constraints from the Revised design. Deletes net constraints from both the Golden and Revised designs.

Related Commands
ADD NET CONSTRAINTS REPORT NET CONSTRAINTS

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DELETE NOBLACK BOX
DELete NOblack Box [-SUBmodules] [-Golden | -Revised | -Both] (Setup Mode)

Deletes the specified module names originally added with the ADD NOBLACK BOX command. Use the REPORT NOBLACK BOX command to display a list of all of the modules that will be resolved (flattened) to their parents’ modules during hierarchical dofile script generation. Wildcard: The wildcard (*) represents any zero or more characters in module names.

Parameters -All -SUBmodules Deletes the previously added noblackbox modules. Deletes all previously added noblackboxes. -All applies within the given defaults. Deletes the previously added noblackboxes on all submodules of the specified module(s) that were added using the ADD NOBLACK BOX command with the -submodules option. Deletes the specified Golden module names. This is the default. Deletes the specified Revised module names. Deletes all of the specified modules from both the Golden and Revised designs.

-Golden -Revised -Both

Related Commands
ADD NOBLACK BOX REPORT NOBLACK BOX WRITE HIER_COMPARE DOFILE

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DELETE NOTRANSLATE FILEPATHNAMES
ADD NOtranslate Filepathnames [ | -Library | -Design] [-Both | -Golden | -Revised] (Setup Mode)

Deletes the specified file pathnames originally added with the ADD NOTRANSLATE FILEPATHNAMES command. Use the REPORT NOTRANSLATE FILEPATHNAMES command to display a list of all of the library and design file pathnames. Wildcard: The wildcard (*) represents any zero or more characters in module names.

Parameters -All -Library -Design -Both -Golden -Revised Deletes the listed notranslate file pathnames. Deletes all previously added notranslate file pathnames within the given defaults. Deletes the specified library file pathnames. This is the default. Deletes the specified design file pathnames. Deletes the specified file pathnames from both the Golden and Revised designs. This is the default. Deletes the specified Golden file pathnames. Deletes the specified Revised file pathnames.

Related Commands
ADD NOTRANSLATE FILEPATHNAMES DELETE NOTRANSLATE MODULES REPORT NOTRANSLATE FILEPATHNAMES REPORT NOTRANSLATE MODULES

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DELETE NOTRANSLATE MODULES
DELete NOtranslate Modules [-Library | -Design] [-Both | -Golden | -Revised] (Setup Mode)

Deletes the specified module names originally added with the ADD NOTRANSLATE MODULES command. Use the REPORT NOTRANSLATE MODULES command to display a list of all of the library and design module names that will not be compiled. Wildcard: The wildcard (*) represents any zero or more characters in module names.

Parameters -All -Library -Design -Both -Golden -Revised Deletes the listed modules. Deletes all previously added notranslate module names within the given defaults. Deletes the specified library module names. This is the default. Deletes the specified design module names. Deletes the specified modules from both the Golden and Revised designs. This is the default. Deletes the specified Golden module names. Deletes the specified Revised module names.

Related Commands
ADD NOTRANSLATE MODULES READ DESIGN READ LIBRARY REPORT NOTRANSLATE MODULES

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DELETE OUTPUT EQUIVALENCES
DELete OUtput Equivalences [-ROot | -Module | -ALL_Module] [-Golden | -Revised | -Both] (Setup Mode)

Deletes the output pin equivalences placed on output boundary module pins with the ADD OUTPUT EQUIVALENCES command. Use the REPORT OUTPUT EQUIVALENCES command to display a list of all added output pin equivalences. Wildcard: The wildcard (*) represents any zero or more characters in output boundary module pin names.

Parameters
-ALL_Pin -ROot Deletes all output pin equivalences within the given defaults. Deletes output pin equivalences from the listed output boundary module pins. Deletes the output pin equivalences from the root module.

-Module Deletes the output pin equivalences from the specified module. -ALL_Module -Golden -Revised -Both Deletes the output pin equivalences from all modules. Deletes the specified output pin equivalences in the Golden design. This is the default. Deletes the specified output pin equivalences in the Revised design. Deletes the specified output pin equivalences in both the Golden and Revised designs.

Related Commands
ADD OUTPUT EQUIVALENCES REPORT OUTPUT EQUIVALENCES
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DELETE OUTPUT STUCK_AT
DELete OUtput Stuck_at [-ROot | -Module | -All] [-Golden | -Revised | -Both] (Setup Mode)

Deletes the output stuck_at values placed on output boundary module pins with the ADD OUTPUT STUCK_AT command. Use the REPORT OUTPUT STUCK_AT command to display a list of all added output stuck_at values and their pin names.

Parameters
-ALL_Pin -ROot Deletes all output stuck_at values within the given defaults. Deletes the output stuck_at values associated with the listed output boundary module pins. This accepts wildcards. Deletes the output stuck_at values in the root module boundary pin. This is the default.

-Module Deletes the output stuck_at values in the specified module. This accepts wildcards. -All -Golden -Revised -Both Deletes the output stuck_at values in all output boundary module pins. Deletes the output stuck_at values in the Golden design. This is the default. Deletes the output stuck_at values in the Revised design. Deletes the output stuck_at values in both the Golden and Revised designs.

Related Commands
ADD OUTPUT STUCK_AT REPORT OUTPUT STUCK_AT

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DELETE PARTITION KEY_POINT
DELete PArtition Key_point (Setup Mode)

Deletes all of the specified partition key points originally added with the ADD PARTITION KEY_POINT command. Use the REPORT PARTITION KEY_POINT command to display a list of all added partition key points.

Related Commands
ADD PARTITION KEY_POINT REPORT PARTITION KEY_POINT WRITE PARTITION DOFILE

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DELETE PARTITION POINTS
DELete PARtition Points [-NONequivalent] [-Golden | -Revised] [-NOVerbose | -Verbose] (LEC Mode)

Note: This requires a Conformal XL license. Deletes the partition points that were created with the ADD PARTITION POINTS command. Note: Partition points are always deleted in pairs. Tip You can get the pathname of the partition point with the REPORT PARTITION POINT command. Caution Deleting partition (CUT) points in LEC mode causes flattened netlists to change. As a result, all the gate-ids are subjected to change. Deleting cut points does not affect the existing compare points list; however, all the compare data is invalidated after deleting cut points.

Parameters -All -BAD_cuts Specifies the name of the path for the partition points to be deleted. Specifies that all the existing partition points will be deleted. Automatically deletes the set of partition points that cause false non-equivalence.

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-EFFORT Specifies the effort level for deleting the bad set of partition points. Increasing the effort level from Low to High will intelligently delete more partition points decreasing the probability of false non-equivalence. However, increasing the effort will result in increased time as well. The default effort level is Low. -NONequivalent -Golden -Revised -NOVerbose -Verbose Deletes partition cut points that are non-equivalent. Specifies that the partition point is in the Golden design. This is the default. Specifies that the partition point is in the revised design. Does not provide additional information. This is the default. Provides additional information.

Related Commands
ADD PARTITION POINTS REPORT PARTITION POINTS

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DELETE PIN CONSTRAINTS
DELete PIn Constraints [-Module ] [-Golden | -Revised | -Both] (Setup Mode)

Deletes constraints originally placed on named primary input pins with the ADD PIN CONSTRAINTS command. Use the REPORT PIN CONSTRAINTS command to display a list of all added pin constraints. Wildcard: The wildcard (*) represents any zero or more characters in primary input names.

Parameters
-ALL_Pin Deletes all constraints placed on primary input pins within the given defaults. Deletes constraints from the listed primary inputs.

-Module Deletes pin constraints from the specified module. -Golden -Revised -Both Deletes the specified pin constraints from the Golden design. This is the default. Deletes the specified pin constraints from the Revised design. Deletes the specified pin constraints from both the Golden and Revised designs.

Related Commands
ADD PIN CONSTRAINTS REPORT PIN CONSTRAINTS

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DELETE PIN EQUIVALENCES
DELete PIn Equivalences [-ROot | -Module | -ALL_Module] [-Golden | -REvised | -Both] (Setup Mode)

Deletes the added pin equivalences from the specified primary input pins. These equivalences were placed on primary input pins with the ADD PIN EQUIVALENCE command. Use the REPORT PIN EQUIVALENCES command to display a list of all of the added pin equivalences. Wildcard: The wildcard (*) represents any zero or more characters in primary input names.

Parameters
-ALL_Pin Deletes all added pin equivalences within the given defaults. Deletes pin equivalences from the listed primary input pins. (Pin equivalence was originally added with the ADD PIN EQUIVALENCES command.) Deletes pin equivalences from the root module.

-ROot

-Module Deletes pin equivalences from the specified module. -ALL_Module -Golden -REvised -Both Deletes pin equivalences from all modules. Deletes the specified pin equivalences from the Golden design. This is the default. Deletes the specified pin equivalences from the Revised design. Deletes the specified pin equivalences from both the Golden and Revised designs.

Related Commands
ADD PIN EQUIVALENCES REPORT PIN EQUIVALENCES
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DELETE PRIMARY INPUTS
DELete PRimary Inputs [-Golden | -Revised | -Both] (Setup Mode)

Deletes specified primary inputs that were originally added with the ADD PRIMARY INPUT command. After you delete the primary input pins from either the Golden or Revised design, the associated nets become floating nets, unless there are other net drivers. Use the REPORT PRIMARY INPUTS command to display a list of all primary inputs. Wildcard: The wildcard (*) represents any zero or more characters in paths of primary inputs.

Parameters
-All -Golden -Revised -Both Deletes all primary inputs within the given defaults. Deletes the specified primary inputs. Deletes the specified primary inputs from the Golden design. This is the default. Deletes the specified primary inputs from the Revised design. Deletes the specified primary inputs from both the Golden and Revised designs.

Related Commands
ADD PRIMARY INPUT REPORT PRIMARY INPUTS

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DELETE PRIMARY OUTPUTS
DELete PRimary Outputs > [-Golden | -Revised | -Both] (Setup Mode)

Deletes primary outputs that were originally added with the ADD PRIMARY OUTPUT command. When you delete the primary output pins from the Golden or Revised design, the nets become floating nets, unless there are other net drivers. Use the REPORT PRIMARY OUTPUTS command to display a list of all primary outputs. Wildcard: The wildcard (*) represents any zero or more characters in paths of primary outputs.

Parameters
-All -Golden -Revised -Both Deletes all primary outputs within the given defaults. Deletes the specified primary outputs. Deletes primary outputs from the Golden design. This is the default. Deletes primary outputs from the Revised design. Deletes primary outputs from both the Golden and Revised designs.

Related Commands
ADD PRIMARY OUTPUT REPORT PRIMARY OUTPUTS

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DELETE RENAMING RULE
DELete REnaming Rule [-MAp | -MOdule | -PIn] (Setup / LEC Mode)

Deletes renaming rules originally added with the ADD RENAMING RULE command. Use the REPORT RENAMING RULE command to display a list of all of the renaming rules and their rule numbers.

Parameters
-All Deletes all previously added renaming rules from the Map, Module, and Pin categories. If you do not specify a category, Conformal deletes all previously added renaming rules from the Map category. -MAp -MOdule -PIn Deletes the specified renaming rule. Deletes only map renaming rules. This is the default. Deletes only module renaming rules. Deletes only pin renaming rules.

Related Commands
ADD RENAMING RULE CHANGE NAME MAP KEY POINTS READ DESIGN READ LIBRARY REPORT RENAMING RULE SET MAPPING METHOD SET NAMING RULE
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DELETE RETENTION MAPPING
DELete REtention Mapping (Setup / LEC Mode)

Note: This is a Conformal Low Power command. Deletes the state retention mapping rules added using the ADD REtention_register Mapping command. Note: Use the REPORT RETENTION MAPPING command to display a list of all the state retention mapping rules. Note that the default rule added by the system can never be deleted. For a description of the default rules that are added by the system, see CHECK LOWPOWER CELLS on page 144.

Parameters
-All Deletes all the state retention register mapping rules added using the ADD RETENTION MAPPING Mapping command. This option does not delete the default rule added by the system. Deletes the specified state retention mapping rule. Note: The default rule added by the system cannot be deleted.

Related Commands
ADD RETENTION MAPPING REPORT RETENTION MAPPING

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DELETE SEARCH PATH
DELete SEarch Path [-Design | -Library] [-Golden | -Revised] [-RECursive] (Setup Mode)

Deletes search paths Conformal uses for the READ DESIGN and READ LIBRARY commands. Use the REPORT SEARCH PATH command to display a list of all search paths.

Parameters
-All -Design -Library -Golden -Revised -RECursive Deletes all previously added search paths within the given defaults. Deletes the specified search paths. Deletes search paths used by the READ DESIGN command. This is the default. Deletes search paths used by the READ LIBRARY command. Deletes search paths used by the Golden design or library. This is the default. Deletes search paths used by the Revised design or library. Deletes the subdirectories of the specified directory from the search paths.

Related Commands
ADD SEARCH PATH READ DESIGN READ LIBRARY REPORT SEARCH PATH

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DELETE SEQ_CORR
DELete SEQ_CORR (LEC Mode)

Note: This requires a Conformal XL license. Deletes the sequential corresponding points that were added with the ADD SEQ_CORR or ANALYZE RETIMING -general command.

Parameters
-ALL Deletes all the sequential corresponding points.

Specifies the sequential corresponding gate ID or instance pathname for the Golden register to delete. Specifies the sequential corresponding gate ID or instance pathname for the Revised state point to delete.

Example
The following command deletes all the sequential corresponding points: delete seq_corr -all

Related Commands
ANALYZE RETIMING ADD SEQ_CORR REPORT SEQ_CORR SET RETIMING OPTION

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DELETE SUPPLY
DELete SUpply [-ROOT | -Module | -ALL] [-PORT | -GLOBAL ] [-Golden| -Revised | -Both] (Setup Mode)

Note: This requires a Conformal GXL license. Deletes power and ground pins in the design that were defined with the ADD SUPPLY command.

Parameters -ROOT Specifies that the list of net or port names that will have their attribute settings deleted. Delete this supply attribute to the specified objects in the current scope and all hierarchy of this scope. This is the default. Delete the attribute setting to the specified module. This accepts wildcards. Deletes the attribute settings to the objects for all modules. The defined object(s) must be the port(s) at the root or the specified module level. This is the default. The defined object(s) could be the port(s) and wire(s) in the hierarchy of the root or the specified module. Specifies that the listed names are from the Golden design. This is the default. Specifies that the listed names are from the Revised design. Specifies that the listed names are from both the Golden and Revised designs.

-Module -ALL -PORT -GLOBAL -Golden -Revised -Both

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Related Commands
ADD SUPPLY REPORT SUPPLY

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DELETE TIED SIGNALS
DELete TIed Signals [-Net |-Pin] [-Module ] [-Class ] [-Golden |-Revised] (Setup Mode)

Deletes specified tied signals from the Golden or Revised design. Use the REPORT TIED SIGNALS command to display a list of all of the tied signals.

Parameters
-All -Net -Pin Deletes all tied signals within the given defaults. Deletes the specified tied signals. Specifies that the deleted tied signal is a net. This is the default. Specifies that the deleted tied signal is a pin.

-Module Specifies the name of the module where the floating net or pin resides. -Class Deletes tied signals of this class. Full User System -Golden -Revised Tied signals from both the User and System classes. This is the default. Tied signals the user previously added with the ADD TIED SIGNALS command. Tied signals from the original design.

Deletes tied signals from the Golden design. This is the default. Deletes tied signals from the Revised design.

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Related Commands
ADD TIED SIGNALS REPORT TIED SIGNALS

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DIAGNOSE
DIAgnose (LEC Mode)

Runs diagnosis on a specified compared point. Specify the compared point by its gate identification number, instance path, or a pin path. Use this command to determine why the software identified non-equivalence between compared points. The diagnosis displays all of the non-corresponding support key points with a list of all likely error candidates from the Revised design. The list organizes likelihood in descending order with 1.00 being the greatest possible error candidate. Use the REPORT ENVIRONMENT command to display the maximum diagnosis candidates setting. Note: The syntax above assumes you are diagnosing mapped compare points (where you only need to specify one compare point). When you are diagnosing instance/sequential merge non-equivalence, you must specify two compare points.

Parameters Diagnoses the specified gate. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. Diagnoses the specified instance path. -Golden -Revised Diagnoses the specified pin path. Diagnoses the Golden design. This is the default. Diagnoses the Revised design.

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-MERge

Diagnoses merged compare points. Note: The following options are not supported when diagnosing instance/sequential merge nonequivalence:
■ ■ ■

-SUMmary integer -SOrt -SUPport

-SUPport -NUm integer -SUMmary integer

Displays the list of corresponding and non-corresponding support points. Lists the specified number of error candidates. By default, Conformal lists all error candidates. Displays a table of the non-equivalent points with their corresponding support size, non-corresponding support size, and cone size. The integer represents the number of nonequivalent points you wish to display in the table. By default, Conformal displays all nonequivalent points.

-SOrt

Sorts the summary table results by one of the following.: SUpport SIze Sorts by corresponding support size. This is the default. Sorts by cone size

-NOneq

Diagnoses every nonequivalent point.

Examples
Note: For a set of sample commands that shows this and related commands in context, see the example for the COMPARE command.

Related Commands
PROVE REPORT COMPARE DATA REPORT ENVIRONMENT

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DOFILE
DOFile (Setup / LEC Mode)

Executes a set of commands contained in a specified file. If there is an error while the Conformal software is executing the dofile script, it terminates the dofile execution and returns to the system mode prompt. Use the SET DOFILE ABORT command to specify how you want the Conformal software to respond when an error message occurs. You can choose to terminate, continue, or exit the session. Use the BREAK command in a dofile script to terminate the dofile script and return to the system mode prompt.

Parameters -FORCE Specifies a file containing a set of commands the Conformal software executes one at a time. Allows a dofile to be executed multiple times, up to a limit of 16. Without this option, you will get an error if you attempt to run a dofile multiple times. Specifies that if the current execution is stopped because of a break in one or more dofiles, it will display the current dofile execution stack. For example:
1: 2: dofile_2 break (line:2) dofile_1 dofile dofile_2 (line:5)

-SHOW_STACK

Related Commands
BREAK CONTINUE SET DOFILE ABORT

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ELABORATE DESIGN
ELAborate DEsign [-ROot ] [-ROOTONLY] [-ROOTConfig ] [-PARAmeter [-INT | -STR | -ENUM] ] [-RAngeconstraint] [-GOlden | -REvised] (Setup Mode)

Completes the READ DESIGN command specified with the -noelaborate option. During this step, modules are synthesized and the complete design hierarchy is created. This command is typically used for mixed design flows where the Verilog modules and VHDL entity or architectures are read in separately. Then they can be elaborated using this command.

Parameters
-ROot Specifies the root module to be elaborated. If this option is not specified, the Conformal software automatically selects a root module. -ROOTONLY Elaborates the root module only and skips elaboration of the other modules that are not instantiated from the root module. Because the elaboration stage is skipped for the uninstantiated modules, this option reduces memory usage and omits the elaboration time error checking. -ROOTConfig Specifies that the design includes the specified configuration for the top-level module. Note: This option applies to only VHDL designs. Use this option when the design includes multiple configurations for the top-level module. When you use the -rootconfig option, you must also use the -root module_name option (above).

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-PARAmeter [-INT | -STR | -ENUM] Assigns design parameters or replace existing design parameters. To specify multiple parameters, use the -parameter option for each parameter you want to set. For example: read design filename -parameter parm1 value1 \ -parameter -int parm2 value2

This option applies to both Verilog and VHDL files. (Combine with -root.) When using the -parameter -int command, the will be converted to integer value, which can be a positive integer (1), negative integer (-1), an integer value recognized as a string ("1"/"-1"), or a Verilog style integer ("16’h0001"). When using a Verilog style integer, the value must be specified between double-quotes (" "). When using the -parameter -str command, the will be saved as a string. When using the -parameter -enum command, the will be converted to a VHDL enumeration literal. For example, the following command sets the parameter P4 to VHDL enumeration literal GREEN: read design -root mod1 filename \ -parameter -enum P4 GREEN

Note: Any value that is not recognized as an unsigned decimal integer value is interpreted as string value. Note: If -int or -str is not specified, then the parameter value will be interpreted as an integer if it is not between double-quotes (" "), and as a string if it is between double-quotes. Therefore, if you want to specify a Verilog format value, it must be between double-quotes and used with the -int option. -RAngeconstraint -Golden -Revised Applies range constraints during verification. If this option is not specified, all range constraints are ignored. Specifies to elaborate the Golden design. This is the default. Specifies to elaborate the Revised design.

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Related Commands
READ DESIGN READ LIBRARY

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EXIT
EXIt [-Force] (Setup / LEC Mode)

Ends the existing Conformal session and returns you to the operating system. Exit Status Codes On exiting, Conformal returns a status code. A nonzero status code means there is a potential error; that is, either no comparison was done or unmapped, abort, or nonequivalent points exist. The exit status code consists of flags that represent different conditions. Saving GUI Settings By default, Conformal does not automatically save GUI settings for future sessions. To save your preferred settings, use the GUI exit window and click the Save GUI settings check box. Refer to the Encounter Conformal Equivalence Checking User Guide for additional information about exit status codes and the procedure to save GUI settings.

Parameters
-Force Exits without confirmation.

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FLATTEN
FLAtten [-Library | -NOLibrary] [-Force | -NOForce] [-Golden | -Revised] (Setup Mode)

Note: This requires a Conformal GXL license. Tip When using this command with Conformal ECO, you should use the -nolibrary option to prevent flattening to the primitive level. Removes all hierarchy on a specified module or for all modules in the database. If you do not specify one or all modules, Conformal flattens the root module by default. Thus, this command expands all of the gate primitive or transistor primitive devices into the cell that is being flattened. The following example illustrates the effects of this command: A cell that is to be flattened contains three cells. One cell has 25 gates and the other two are the same, each with 33 gates. After flattening, the cell now contains 0 cells and 91 gates (1 * 25 + 2 * 33 = 91).

Parameters
-MODule Flattens the specified module. The default is to flatten the root module. -ALL -Library -NOLibrary Flattens all modules within the given defaults. Flattens all modules in the designs and libraries. This is the -ALL option default. Flattens all modules in the designs.

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-Force

Forces flattening of specified modules in the Golden or Revised design even if those modules have not been flattened in the complementing design. (For example, force flattening for Golden modules when the Revised have not been flattened.) This is the default. Does not force flattening when those modules have not been flattened in the complementing design. Flattens the specified module(s) from the Golden design. This is the default. Flattens the specified module(s) from the Revised design.

-NOForce -Golden -Revised

Related Command
RESOLVE

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FORWARD
FORward [] (LEC Mode)

Reports fan-out gate information from the currently displayed flatten gate information. The fan-out gate you choose with this command becomes the current flattened gate. Use this command to trace gates in place of repeatedly using the REPORT GATE command. Note: This command does not report gates at the design level.

Parameters Reports the specified fan-out gate. The value 1 denotes the first fan-out. The default is 1.

Related Commands
BACKWARD REPORT GATE

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GENERATE ROM PRIMITIVE
GENerate ROm Primitive [-MOD ] [-CODE_FILE_FORMAT [BIN | HEX]] [-NO_ACCESS_OUT_LOW | -NO_ACCESS_OUT_HIGH] (Setup Mode)

Note: This requires a Conformal GXL license. Generates a ROM primitive model that you can use to verify against a valid ROM circuit. Conformal generates a ROM primitive that has the following interface:
■ ■ ■ ■

Addr—Address bus for accessing ROM data. Dout—Output data from ROM. RE—Control clock for the output latch or flip-flop, when you set the -outstate option to dlat or dff. When RE is high, ROM data is sampled. CK—Address decode clock for ROM read operations. ROM is read when the clock is high.

This command reads in a code file that initializes the ROM. This code file should contain one number per line, in binary format. The number of entries in the code file should match the number of words in the memory. As Conformal reads the code file, it assigns each entry to a successive word element in the memory. The following illustrates sample contents for a code file called rom.code, which initializes a 4 X 4 ROM: 0000 1111 1010 0111 Note: To perform simulation, you must define the macro SIM.

Parameters
-SIM Specifies the output file for the ROM primitive.

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-CODE_FILE Specifies the code file that will initialize the ROM. This code file should contain initialization data in binary format. -MOD Specifies the module name of the ROM primitive that is created.

-CODE_FILE_FORMAT [BIN | HEX] Specifies the output file format for the ROM primitive. -NO_ACCESS_OUT_LOW -NO_ACCESS_OUT_HIGH Fills the memory address with ’0’ when it is not initialized. This is the default. Fills the memory address with ’1’ when it is not initialized.

Related Command
READ ROM PRIMITIVE

Examples
The following command generates a ROM model with a code file called rom.code. generate rom primitive -sim VROM.v -code_file rom.code -mod VROM / -code_file_format bin -no_access_out_low

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GROUP
GROUP [-net_to_pin_name] [-Golden | -Revised] (Setup Mode)

Note: This requires a Conformal GXL license. Groups defined instances together so that they become a new submodule. This command is the opposite of the RESOLVE command; it applies to submodules, latches, registers, gates, and transistors. By default, this command assigns unique and arbitrary submodule pin names. Wildcard: The wildcard (*) represents any zero or more characters in existing instance names.

Parameters
-Module Specifies a module for which to apply the grouping. -Instance Specifies the instances to group. This accepts wildcards. -NEWModule Specifies the name of the new module. -NEWInstance Specifies the instance name for the new module. -net_to_pin_name Specifies that the pin names of the new modules will be the same as the nets connected to them, and not unique and arbitrary. Applies this command to modules and instances in the Golden design. This is the default. Applies this command to modules and instances in the Revised design.
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Related Command
RESOLVE

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HELP
HELp [ | | -message] [-Verbose [-VERSION]] [-NOSHOW_ERROR_ID | -SHOW_ERROR_ID] [-NOSHOW_EXTENDED_HELP | -SHOW_EXTENDED_HELP] [-COLOR | -NOCOLOR] [-PAGE | -NOPAGE] [] (Setup / LEC Mode)

Note: Although the HELP command is still available, it is recommended that you use the MAN command. Displays the Conformal commands and their command syntax. To display a group or set of commands, use a keyword such as ADD, DELETE, REPORT, or SET. While in the Tcl mode, the HELP command displays a list of all available Conformal Tcl mode commands.

Parameters Displays the command syntax for a given command name. If you do not specify a command name, the Conformal Equivalence Checker displays all of the commands. Displays help for the corresponding rule check message. Displays all rule check messages. Expands information about the command, including descriptions of the parameters and related commands. Displays the software version at the end of the help output. This can only be used with the -Verbose option. Does not display the error ID. This is the default. Displays the error ID.

-message -Verbose -VERSION -NOSHOW_ERROR_ID -SHOW_ERROR_ID

-NOSHOW_EXTENDED_HELP Does not display the extended help. This is the default. -SHOW_EXTENDED_HELP Displays the extended help only. This does not include error IDs.
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-COLOR

Displays the help text with color highlights. This is the default. Note: This option has no effect if the terminal is not an ’xterm’, as determined by the environmental variable TERM, or when running HELP in the GUI window.

-NOCOLOR -PAGE

Disables the help text with color highlight display. Use this if the text terminal does not support color. Displays the help text one screenful at a time. This is the default. The output is paused for input after one screenful of text is displayed, where you can continue by pressing the following: space bar—displays the next page h key—displays a complete list of options q key—quits from the pager Note: Output displayed with the pager is not saved to the log file specified by SET LOG FILE command. Note: The pager is not enabled if the help text is less than a screenful, when output is redirected to a file, or when running HELP in the GUI window.

-NOPAGE

Disables the help text paging display feature. Displays the error message of the specified message ID.

Example
The following is an example of the Tcl mode system prompt and the HELP command:
TCL_SETUP> help set_current_module

Related Command
SEARCH

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INFO SESSION
INFo SEssion [-VERsion|-PLATform|-FORMAT] session_file (Setup / LEC Mode)

Displays information about a specified session file. By default (without any options specified), the tool displays the version, platform, and format for the session file. Note: Restoring a session file from a version of the tool or for a platform that is different from the one you are currently using can cause unexpected results.

Parameters
-VERsion -PLATform -FORMAT session_file Specify the LEC version where the session was created. Specify the platform where the session was created Specify in which format the session was saved Specifies the session file.

Example info session -version session_file

Related Command
SEARCH

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INVERT MAPPED POINTS
INVert MApped Points [-Golden |-Revised] (LEC Mode)

When switching the system from Setup mode to LEC mode, Conformal automatically maps key points and places them in the System class of mapped points. Use this command to invert the mapping phase for any mapped points. This command also places the points in the User class of mapped points. In the GUI Mapping Manager and in reports, a (-) sign represents an inverted-mapped point. A (+) sign represents a non-inverted mapped point.

Parameters Inverts the mapping phase for the specified gates (identified by number). Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -Golden -Revised Inverts the mapping phase for the specified instances. Inverts the mapping phase for the specified pins. Specifies that the point identifier refers to the Golden design. This is the default. Specifies that the point identifier refers to the Revised design.

Related Commands
ADD MAPPED POINTS DELETE MAPPED POINTS MAP KEY POINTS REPORT MAPPED POINTS

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LICENSE
LICense [] (Setup / LEC Mode)

Displays information about the currently installed Conformal license. By default, this command displays all available Conformal licenses.

Parameters Displays information for a specific license. You can select one of the following: conformal_explorer conformal_asic conformal_ultra conformal_custom conformal_low_power conformal_low_power_gxl conformal_eco rtl_compiler_verification

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MAN
MAN [] [-Keyword] [-Verbose] [-COLOR | -NOCOLOR] [-PAGE | -NOPAGE] (All Modes)

This displays the manual pages for a given expression. By default, the MAN command searches through command names, TCL function names, and rule or modeling message IDs for a best match. You can also use the -Keyword option to search through descriptions. If an exact match is not found, this command returns a list of all matches. Running this command without any arguments returns a list of all available pages. Note: In TCL mode, this command is VPXMODE MAN. With the man command, results are categorized according to the type of information: Category LEC-CMD CFM-RULE LEC-MODEL LEC-TCL ECO-CMD CCD-CMD CCD-LINT CCD-MODEL CCD-TCL SDC-RULE CLP-CMD CPF-RULE CLP-RULE CDC-CMD CDC-MODEL CDC-TCL Description LEC Commands HDL Rules LEC Modeling Rules LEC TCL Commands Conformal ECO Commands Conformal CD Commands Conformal CD Lint Rules Conformal CDCCD Modeling Rules Conformal CD TCL Commands SDC Rules Conformal Low Power Commands Common Power Format Rules Conformal Low Power Rules Conformal Extended Checks Commands Conformal Extended Checks Modeling Rules Conformal Extended Checks TCL Commands

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Encounter Conformal Equivalence Checking Reference Manual Command Reference For example, the following command:
LEC> man usage

has the following results:
USAGE (LEC-CMD) usage (LEC-TCL)

To obtain the man page for the usage Tcl command, use the following command:
LEC> man usage ccd-tcl

Parameters -Verbose -Keyword Specifies the search expression. By default, the MAN command display only the first section of a manual page. Use this option to display the entire manual page. Search for all commands, rules, or messages whose description contains the expression given by name. Using this option, you can also search based through specific sections. For example, the following command searches through all Example sections for the word gated_clock:
MODE> man -k example gated_clock

Keyword searching is done line by line. Therefore, the search expression cannot span over multiple lines. -COLOR Displays manual page with color highlighting. This is the default. -NOCOLOR Disables color highlighting. You can also use the c keyboard shortcut to toggle color highlighting.

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-PAGE

Displays manual pages one screen at a time. You can use the following keyboard shortcuts while in MAN:
■ ■ ■ ■ ■ ■ ■

Spacebar—Forward one screen. Return Key—Forward one line. b Key—Back one screen. d Key—Forward 1/2 screen. u Key—Back 1/2 screen. a Key—Display all the remaining text. q—Quit.

Note: The displayed output is not saved in the logfile specified by the SET LOG FILE command. The pager is not enabled if the help text is less than a screen, when output is redirected to a file, or when MAN is run in the GUI window. -NOPAGE Displays the entire man page at once.

Example
For example, the following command displays the manual page for the REPORT DESIGN DATA command:
MODE> man rep de d

For example, the following command retrieves all entries with the word datapath.
MODE> man datapath ANALYZE DATAPATH (LEC) REPORT DATAPATH OPTION (LEC)

The following lists all pages whose Syntax section contains the word thread.
MODE> man -k syntax thread

The following displays all RTL rules whose default severity is error:
MODE> man -k rule default severity error

The following lists all Ultra commands:
MODE> man -k "ultra command"

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Related Commands
HELP

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MAP KEY POINTS
MAP KEy Points (LEC Mode)

Automatically maps all key points, then displays a summary of the mapped points in the Golden and Revised designs. In addition, if there are any unmapped points, Conformal displays a summary of the unmapped points in the Golden and Revised designs. Conformal automatically executes this command the first time you exit the Setup system mode and when the flattened gate model changes.

Related Commands
ADD MAPPED POINTS ADD RENAMING RULE DELETE MAPPED POINTS DELETE RENAMING RULE REPORT MAPPED POINTS REPORT RENAMING RULE REPORT UNMAPPED POINTS SET MAPPING METHOD SET NAMING RULE TEST RENAMING RULE

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MOS2BUFIF
MOS2BUFIF [-MODule ... | -ALL] [-FORce | -DRIVENmos | -INStance ... ] [-Golden | -Revised] (Setup Mode)

Note: This requires a Conformal GXL license. After abstraction for emulation and test support, this transforms all of the unidirectional NMOS devices to BUFIF1 and unidirectional PMOS devices to BUFIF0.

Parameters
-MODule ... Transforms the specified list of modules. Note: If you do not specify modules, Conformal transforms the current root module. -ALL -FORce -DRIVENmos Transforms all modules. Converts all [r]nmos to bufif1, [r]pmos to bufif0, [r]cmos to a bufif0 – bufif1 pair. This is the default. Converts only those MOS devices that are driven by a logic gate or a primary input.

-INStance ... Transforms the specified instances. You can only use this option when you have specified a single module (see the -module definition). -Golden -Revised Applies transformation in the Golden design. This is the default. Applies transformation in the Revised design.

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Example
Sample Netlist Transformation: The following is the original netlist: nmos (out, in, ctl) ; pmos (out, in, ctl) ;

The MOS2BUFIF command transforms the netlist to the following: bufif1 (out, in, ctl) ; bufif0 (out, in, ctl) ;

Related Command
ABSTRACT LOGIC

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MOVE INSTANCE DOWN
MOVe INstance Down -MODule -From -TO [-Golden | -Revised] (Setup Mode)

Moves instances in the same parent module.

Parameters
-MODule Specifies the parent module -From Specifies the instance that is to be moved. -TO Specifies the destination instance or list of instances. -Golden -Revised Applies in the Golden design. This is the default. Applies in the Revised design.

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OPEN SCHEMATICS
OPEn SChematics [-Golden | -Revised] [] (Setup / LEC Mode)

Opens the schematic viewer and displays the root module schematics. This command cannot be used in the non-graphic mode.

Parameters
-Golden -Revised Specifies that the path is in the Golden design. Specifies that the path is in the Revised design. Opens a schematic for the specified path.

Related Commands
CLOSE SCHEMATICS DIAGNOSE REPORT GATE

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PIN GROUP
PIN GRoup [-Golden | -Revised] [-DEScend | -ASCend] [-ADDEXPression ] [-ADDList [#:#] " ..."] [-ALL | -Module " ..."] (Setup Mode)

Note: This requires a Conformal GXL license. Combines a group of single nets or pins into a bus. The Conformal software uses the following two default patterns to group pins or nets into busses:
■ ■

Name[#] Name

For example, nets blb[3] blb[4] blb[5] will be grouped into bus blb[5:3], and pins wladd wladd wladd will be grouped into bus wladd[3:1].

Parameters
-DEScend -ASCend Defines the bus in descending numerical order. This is the default. Defines the bus in ascending numerical order.

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-ADDEXPression Specifies expression(s) for rules on signals to bus. You can specify your own renaming mapping of specific names to two default patterns, so that it recognizes those names as buses also. For example:
-ADDexpression "mybus_%d_bar" "mybus_bar[@1]"

maps the following names into the first default bus name: mybus_12_bar mybus_13_bar mybus_14_bar => mybus_bar[12] mybus_bar[13] mybus_bar[14]

then the renamed names will be further grouped into bus mybus_bar[14:12] The renaming mapping syntax: mybus_%d_bar" "mybus_bar[@1]"

is defined in the ADD RENAMING RULE command. -AddList [#:#] “ ” Allows you to bus random signals. These nets can be single nets or mixed single nets and complete busses. The number of nets defined must be equal to the bus range. If a bus range more than the number of nets is defined a "-" character is used as a placeholder for that bit position. -ALL Specifies that when pins of a module are converted to a bus, all instantiations of that module need to be updated. This is the default.

-Module “ ” Specifies the module that needs to be updated pins of that module are converted to a bus.

Related Command
GROUP

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PRINTENV
PRINTENV [] (Setup / LEC Mode)

Displays environment variable values.

Parameters Prints the value of the specified variable. If you do not specify a variable, this command displays the value of every environment variable.

Related Command
SETENV

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PROVE
PROve [-Golden | -Revised] [-NOInvert | -Invert | -Both] (LEC Mode)

Starts a process that shows whether the specified gates are equivalent or nonequivalent. The proof process checks equivalency for one of the following pairs:
■ ■ ■

One gate in each of the Golden and Revised designs Two gates in the Golden design Two gates in the Revised design.

Use the ADD DYNAMIC CONSTRAINTS command to specify constraints you want to use during this proof process.

Parameters Specifies the gates from the given design as the first and second prove points. The identifier will be either a gate identification number, instance path, or pin path. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -ONe -ZEro -Golden Prove whether the gate specified by is equal to a one value. Prove whether the gate specified by is equal to a zero value. When two prove points are specified, indicates that both are from the Golden design. Note: By default (when -Golden or -Revised are not specified) the tool assumes the first prove point is from the Golden design, and the second is from the Revised design. -Revised When two prove points are specified, indicates that both are from the Revised design.

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-NOInvert -Invert -Both

Proves for equivalence. This is the default. Proves for inverted equivalence. Proves for either non inverted or inverted equivalence.

Examples
For a set of sample commands that shows this and related commands in context, see the example for the COMPARE command.

Related Commands
ADD DYNAMIC CONSTRAINTS DELETE DYNAMIC CONSTRAINTS DIAGNOSE REPORT COMPARE DATA REPORT DYNAMIC CONSTRAINTS

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READ CPF
REAd CPf [-GOLden | -REVised | -BOTH] [-VERbose] (Setup Mode)

Note: This is a Conformal Low Power command. Reads in the Common Power Format (CPF) files. Cadence recommends reading in all the CPF files at once with this command. Any subsequent runs will replace all the low power information issued by the previous READ CPF command. All READ DESIGN and READ LIBRARY commands should be run before running this command.

Parameters -GOLden -REVised -BOTH -VERBose Specifies the name of the Common Power Format file(s). Reads in the CPF files for the Golden design. This is the default. Reads in the CPF files for the Revised design. Reads in the CPF files for both the Golden and Revised designs. Displays additional messages during execution.

Example
The following command reads the lib.cpf and design.cpf files and checks that they are specified correctly: read cpf lib.cpf design.cpf

Related Commands
COMMIT CPF

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READ DESIGN
REAd DEsign [-ROot ] [-ROOTONLY] [-CONFiguration | -NOCONFiguration] [-ROOTConfig ] [-VErilog | -VERILOG2K | -SYStemverilog | -SVA | -VHdl [93 | 87] | -SPice | -Ndl | -EDIF | -LIBErty] [-NOSTRength] [-File ] [ | -REPlace | -APPend] [-Define ] [-Map ] [-MAPRecursive ] [-MAPFile ] [-LIBRary ] (this option is the same as -Map) [-STATEtable | -NOSTATEtable] [ | -BBOXUNResolve | -NOBBOXEMpty] [-BLAST_inst_port] [-RAngeconstraint | -NORAngeconstraint] [-INITial_value] [-VHDLESCaped_to_verilog] [-CONTINUOUSASSIGNment ] [-NOZPUSHing | -ZPUSHing] [-ENUMConstraint] [-VMEM_LIB] [-VMEM_ULTRA] [-SUPPLY | -NOSUPPLY] [-UNCompress ] [-UNZip ] [-PARAmeter [-INT | -STR | -ENUM] ] (combined with -ROot option) [-ARchitecture ] [-FUnctiondefault [0 | 1 | x]] [-NOKeep_unreach | -Keep_unreach] [-SEnsitive | -NOSEnsitive] [-NOELaborate] [-EXClude ] [-KEEP_ESCAPED_ID] [-VERBose] [-OPTimize | -NOOPTimize] [-KEEP_Float_instance | -REMOVE_Float_instance] [ | -LAstmod | -OVERWrite_mod] [-LOCalref] [-MErge BBox] [-Golden | -REVised] (Setup Mode)

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Use the SET NAMING RULE command first if you intend to read in an RTL design that requires specific naming conventions. Use the SET UNDEFINED CELL command before the READ DESIGN command if your design includes undefined cells that should be treated as blackboxes.

Note:
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If your design includes duplicate modules, Conformal uses the first module and ignores later ones. However, you can use the -lastmod option to specify that Conformal use the last module and ignore the earlier ones. Use the tilde character (~) to shorten the path of the file. Use the backslash character (\) at the end of a line to show that the command you are entering continues on the next line.

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Supported Options The following Verilog and VHDL considerations are offered:
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Use the -file option with a Verilog Command file list. However, only the -v, -y, +incdir, +libext, and +define options are supported. Additionally, use the -yd option to treat library modules as design modules. The VHDL option supports all VHDL constructs and all standard and IEEE packages, including synthesis packages. It has an elaboration engine and RTL logic generation that support most RTL VHDL synthesis subset constructs (see below for details). For most non-synthesizable VHDL constructs, Conformal displays warning messages.

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VHDL and Verilog 2001 Library Mapping You can specify how VHDL and Verilog 2001 libraries are mapped using the READ DESIGN command’s -map, -mapfile, or -library options. The -map and -library options work the same in that they map logical library names to physical directories. You can use multiple -map commands to map multiple physical directories to one logical library. Use the -mapfile option for more specific library mapping,

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Encounter Conformal Equivalence Checking Reference Manual Command Reference such as specifying that a list of files must be compiled into a specified library. If you read in a file without specifying its library mapping, that file is stored in a default library called work. Note: You can map a file into more than one library. In this case, the file is stored in each library for which it is mapped. See the “VHDL Support” and “Verilog Support” appendices in the Encounter Conformal Equivalence Checking User Guide for additional information, including examples on library mapping. VHDL and Verilog File Encryption Conformal tools support Verilog and VHDL files which are encrypted by the NC-Protect and Cadence encryption Cadence tools. NC-Protect is available from Cadence NC-VHDL and Verilog simulators. Cadence encryption is Cadence proprietary tool. The Cadence Verilog-XL protected files are for simulations only and are unsupported by Conformal tools. Other proprietary encryption files are unsupported by Conformal tools.

Parameters -ROot -ROOTONLY Reads in the specified file. (Required.) The specified module is the top root module. Elaborates the root module only and skips elaboration of the other modules that are not instantiated from the root module. Because the elaboration stage is skipped for the uninstantiated modules, this option reduces memory usage and omits the elaboration time error checking. -CONFiguration -NOCONFiguration Supports VHDL configuration constructs. This is the default. Does not interpret VHDL configuration.

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-ROOTConfig The design includes the specified configuration for the top-level module. Note: This option applies to only VHDL designs. Use this option when the design includes multiple configurations for the top-level module. When you use the -rootconfig option, you must also use the -root module_name option (above). -ROOTONLY Elaborates the root module only and skips elaboration of the other modules that are not instantiated from the root module. Because the elaboration stage is skipped for the uninstantiated modules, this option reduces memory usage and omits the elaboration time error checking. -VErilog Specifies that this design is a Verilog design. (Use this option for Verilog designs that comply with IEEE 1364-1995.) This is the default. Specifies that this design is a Verilog2K design (Use this option for Verilog designs that comply with IEEE 1365-2001). Specifies that this design is a SystemVerilog design. Enables SystemVerilog Assertion (SVA) support. Specifies that this design is written in VHDL with the specified standard: 93 VHDL-93 (Use this option for VHDL designs that comply with IEEE Std 1076-1993.) This is the default. VHDL-87 (Use this option for VHDL designs that comply with IEEE Std 1076-1987.)

-VERILOG2K -SYStemverilog -SVA -VHdl

87

Note: The Conformal software supports multiple uses the -vhdl 93 and -vhdl 87 options. See the example. -SPice -Ndl -EDIF -LIBErty Specifies that the design is a SPICE netlist design. Specifies that the design is an NDL design. Specifies that the design is an EDIF design. Specifies that the design has a Liberty library format type. Use this option to qualify the library as Liberty.
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-NOSTRength

Specifies that drive strengths are automatically ignored without being removed from design.

-File Reads in the specified command file as a design. Note: This option is for Verilog or VHDL command file lists. The options for are described in Table 2-1 on page 254 for Verilog and Table 2-2 on page 255 for VHDL. -REPlace -APPend Removes all designs that were previously read in, and replaces them with the specified design. Appends the design to the one that was previously read. For example, you can use this option to fix a top module and then read it in again without parsing the entire design file again: read design top.v -append -lastmod

Note: The top module cannot pass parameters to modules that are read in previously. -Define Defines `ifdef variable names in Verilog. To specify multiple definitions, use this option for each definition you want to set. For example: read design filename -define definition1=value1 \ -define definition2=value2

-Map Reads in files for the specified from . Use this option to read in all of the VHDL or Verilog files in the specified library path for the given library name. You can also map multiple directories to a single library. For example: read design -vhdl top.vhd -map mylib /design/path1 \ -map mylib /design/path2

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-MAPRecursive This option has the same function as -Map, but it searches for all VHDL or Verilog files recursively down to the subdirectories of the . -Map searches VHDL or Verilog files under the and will not search any VHDL files under the subdirectories of . -MAPFile Reads in the specified and includes them in the . Use this option to specify the files that belong to a given library. The file list terminates with the next option or the end of the READ DESIGN command. You can also use multiple -mapfile options to specify multiple files in a library. For example, the following two commands are the same: read design -vhdl top.vhd -mapfile \ mylib x1.vhd -mapfile mylib x2.vhd read design -vhdl top.vhd -mapfile mylib x1.vhd x2.vhd

-LIBRary Reads in the specified file in the given library and path for user-defined VHDL libraries. (This option is the same as -map.) -STATEtable Enables support for Synopsys Liberty state tables. This is the default. Note: This option supersedes the SET STATETABLE command. -NOSTATEtable -BBOXUNResolve Disables support for Synopsys Liberty state tables. Specifies that unresolved semantics as unsupported constructs (in VHDL) will be blackboxed instead of erroring out. Specifies that empty modules will be retained instead of being blackboxed.

-NOBBOXEMpty

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-BLAST_inst_port

Allows the cell model to have a bus pin while the instantiation is bit-blasted. By default, instantiations that contain bit-blasted connections are errored out. The Verilog standard does not allow these connections.

-RAngeconstraint

When a variable is of type integer with a value range, a value check is made against the range. If a value is out of range, it will be interpreted as don’t care. This is the default. For example: variable v : integer range 3 to 5;

With -RAngeconstraint, v will be interpreted as:
((v>=3 && v=sun && v add compared points -all // 3113 compared points added to compare list

2. Enable the report compare time feature.
LEC> report compare time -enable

3. Start your comparison.
LEC> compare =========================================================================== Compared points PO DFF DLAT BBOX Total --------------------------------------------------------------------------Equivalent 123 2983 2 5 3113 =========================================================================== // Warning: 1 DFFs/DLATs have 1 disabled clock port: skipped data cone comparison

4. Report the compare time. In this example, Conformal sorts the information based on CPU time and only reports RTL information within the cone.
LEC>report compare time -sort -rtlinfo CPU Time Used: 5.29, Result: Equivalent: (G) + 536 DFF /cpu_core/CPU/cpu_dp/alu/v_alo_1l_reg[30] (R) + 1284 DFF /cpu_core$CPU$cpu_dp$alu$v_alo_1l_reg_30_/U$1/U$1 RTL modules at Golden: RTL modules at Revised: CPU (G) (R) RTL RTL Time Used: 4.64, Result: Equivalent: + 533 DFF /cpu_core/CPU/cpu_dp/alu/o_alvo_1l_reg + 1364 DFF /cpu_core$CPU$cpu_dp$alu$o_alvo_1l_reg/U$1/U$1 modules at Golden: modules at Revised: . . .

Related Commands
ADD COMPARED POINTS COMPARE REPORT COMPARE DATA

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REPORT COMPARED POINTS
REPort COmpared Points [-SUMmary | -PO | -DFf | -DLat | -Bbox | -Cut] (LEC Mode)

Displays the compared points that were added with the ADD COMPARED POINTS command. The first row represents the Golden design; the second row represents the Revised design. It also shows a tabulated summary of the compared points for each design. This report includes the total number of compared points for primary outputs, D flip-flops, D-latches, blackboxes, and cut gates. If you do not specify any options, Conformal lists all added compared points, and a tabulated summary appears at the end of the list. However, if you use the -summary option, Conformal displays only the tabulated summary.

Parameters
-SUMmary -PO -DFf -DLat -Bbox -Cut Lists a summary table of all of the added compared points in the Golden and Revised designs. This is the default. Lists all primary output compared points. Lists all D flip-flop compared points. Lists all D-latch compared points. Lists all blackbox compared points. Lists all compared points for artificial gates that break combinational loops.

Related Commands
ADD COMPARED POINTS COMPARE DELETE COMPARED POINTS REPORT STATISTICS

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REPORT CPF LOGIC
REPort CPf Logic [-ISOlation] [-Level_shifter] [-RETention] [-Verbose] (Setup / LEC Mode)

Note: This is a Conformal Low Power command. Reports the low power cells that were inserted by the Conformal Low Power software.

Parameters
-ISOlation -Level_shifter -RETention -VERbose Reports the inserted isolation cells only . Reports the inserted level-shifter cells only . Reports the inserted state retention cells only . Reports detailed information of each defined CPF cell, including cell types and rules that triggered this cell to be inserted in the design.

Note: By default, this command reports all inserted low power cell types.

Example
The following commands read the lib.cpf and design.cpf files, performs low power cell insertion, and reports only the interted isolation and level-shifter cells: read cpf lib.cpf design.cpf commit cpf -insert report cpf logic -isolation -level_shifter

Related Commands
COMMIT CPF READ CPF

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REPORT CUT POINT
REPort CUt Point [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays all cut points from the Golden and Revised designs that were added with the ADD CUT POINT command.

Parameters
-Both -Golden -Revised Lists all cut points in both the Golden and Revised designs. This is the default. Lists all cut points in the Golden design. Lists all cut points in the Revised design.

Related Commands
ADD CUT POINT DELETE CUT POINT REPORT PATH

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REPORT DATAPATH OPTION
REPort DAtapath Option (Setup / LEC Mode)

Displays current datapath option settings.

Related Commands
ANALYZE DATAPATH ANALYZE MODULE REPORT MULTIPLIER OPTION SET DATAPATH OPTION SET MULTIPLIER OPTION SET FLATTEN MODEL

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REPORT DATAPATH RESOURCE
REPort DATapath REsource [-Verbose] [-Analyzed] [-Type ] (LEC Mode)

Displays information about datapath resources from the Golden and Revised designs.

Parameters
-Verbose -Analyzed -Type Provides additional information, such as filename and line number. Provides information only for resources analyzed by ANALYZE DATAPATH command. Provides information only for resources of the specified type. Choose one of the following: MULT — multipliers ADD — adders SUB — subtractors MERGED — merged operators

Related Commands
ANALYZE DATAPATH ANALYZE MODULE REPORT DESIGN DATA

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REPORT DESIGN DATA
REPort DEsign Data [] [-Summary | -Verbose] [-NOKey_point | -Key_point] [-Extra ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays design data on the Golden and Revised designs. It displays the number of design modules, library cells, inputs, outputs, primitives, and one-to-one mapped state points. This report includes word-level information about the design in terms of the number of arithmetic/keyword operations. This report includes datapath elements such as WMUX, WAND, WXOR and other word-level representations of Boolean logic. It displays simpler representations of datapath logic that may need to be separated out for the comparison process. Press Ctrl-C to interrupt the key point listing if you find that the report is too long.

Parameters Reports design data for the named module. By default, the Conformal software reports design data on the top root design module. Summarizes the design data for the total number of design modules, library cells, inputs, outputs, and primitives. This is the default. -Verbose Reports a detailed list of the design’s total number of design modules, inputs, outputs, each different library cell, and each different primitive. Does not report the total one-to-one mapped state points. This is the default. Reports the total one-to-one mapped state points. Note: If you use the -verbose option in conjunction with this option, Conformal reports all one-to-one mapped state points. Otherwise, Conformal reports the total in summary.

-Summary

-NOKey_point -Key_point

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-Extra

Reports the extra input, output, or I/O pins for pair-able modules between the Golden and Revised designs. INPut Output INOut Specifies input pins. Specifies output pins. Specifies inout pins.

-Both -Golden -Revised

Report design data on both the Golden and Revised designs. This is the default. Report design data on the Golden design. Report design data on the Revised design.

Related Commands
READ DESIGN READ LIBRARY REPORT DATAPATH RESOURCE

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REPORT DESIGN SIMILARITY
REPort DEsign SIMilarity [-INStance ] [-GOLDen | -REVised] (LEC Mode)

Displays the similarity degree of a design with reference to the other netlist. The similarity is measured by the number of corresponding points in the two designs. The value of similarity ranges from 0% to 100%. If the two designs are identical in structure, the similarity degree is 100%.

Parameters
-INStance Displays the similarity degree of the netlist inside the specified instance. The similarity is evaluated with reference to the other netlist. If no instance is specified, the similarity is for the entire design. -Golden Specifies that the similarity evaluation is performed on the Golden design. The Revised netlist is used for reference. This is the default. Specifies that the similarity evaluation is performed on the Revised design. The Golden netlist is used for reference.

-Revised

Examples
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The following command displays the similarity of the Golden design’s netlist. The Revised design’s netlist is used for reference. report design similarity

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The following command displays the similarities of the instances whose name begins with mult in the Golden design’s netlist: report design similarity -instance mult*

Related Topic
Reporting Design Similarities

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REPORT DYNAMIC CONSTRAINTS
REPort DYnamic Constraints [-Both | -Golden | -Revised] (LEC Mode)

Displays all of the dynamic constraints you added to the Golden and Revised designs with the ADD DYNAMIC CONSTRAINTS command.

Parameters
-Both -Golden -Revised Lists all dynamic constraints in both the Golden and Revised designs. This is the default. Lists all dynamic constraints in the Golden design. Lists all dynamic constraints in the Revised design.

Examples
For a set of sample commands that shows this and related commands in context, see the example for the COMPARE command.

Related Commands
ADD DYNAMIC CONSTRAINTS COMPARE DELETE DYNAMIC CONSTRAINTS PROVE

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REPORT ENVIRONMENT
REPort ENvironment [-Setup | -MOdeling | -MApping | -COMpare | -Diagnosis | -FUnctiondefault] (Setup / LEC Mode)

Displays global settings for the Golden and Revised designs and system settings.

Parameters
-Setup -MOdeling -MApping -COMpare -Diagnosis -FUnctiondefault Reports environment related to Setup. This is the default. Reports environment related to Modeling. Reports environment related to Mapping. Reports environment related to Compare. Reports environment related to Diagnosis. Reports environment related to the default return value.

Related Commands
SET CASE SENSITIVITY SET COMPARE EFFORT SET CPU LIMIT SET FLATTEN MODEL SET GATE REPORT SET IMPLEMENTATION SET LOG FILE SET MAPPING METHOD SET NAMING RULE SET ROOT MODULE SET SCREEN DISPLAY
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REPORT FLOATING SIGNALS
REPort FLoating Signals [-ROot | -Module | -All] [-UNDriven | -UNUsed] [ | -Net | -Pin] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays all floating signals in the Golden and Revised designs or in specified modules of a design. The reported floating signals are either nets or pins and are either undriven or unused. Use the SET UNDRIVEN SIGNAL command to specify the global behavior of the undriven floating signals in the Golden and Revised designs.

Parameters
-ROot Displays all floating signals in the root module. This is the default.

-Module Displays all floating signals in the specified module within the given defaults. -All -UNDriven -UNUsed -Net -Pin -Both -Golden -Revised Displays all floating signals in “all” design modules within the given defaults. Displays only undriven floating signals. This is the default. Displays only unused floating signals. Displays only floating nets. If you do not specify -net or -pin, Conformal displays both floating nets and floating pins. Displays only floating pins. If you do not specify -net or -pin, Conformal displays both floating nets and floating pins. Displays floating signals from both the Golden and Revised designs. This is the default. Displays floating signals from the Golden design. Displays floating signals from the Revised design.

Related Commands
ADD TIED SIGNALS
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REPORT GATE
REPort GAte [ [-INStance | -Pin | -Net | -ID] [-Golden | -Revised] [-SUPport] [-FRONTIER] [-FANIn ] [-FANOut ] [-UNReach] [-SHORT_list | -NOSHORT_list] [-SOURCE] [-Collapse] [-NODYNamic | -DYNamic] [-INDent ]] [-Type ] [-RETention] [-CORRespondence] [-SUMmary] [-CONSTRAINT] [-ASSERTION] [-ALLDNET] (Setup / LEC Mode)

Displays flattened gate information. By default, it reports the gate ID, type, name, and its fanins and fan-outs at the primitive level. After you specify options for the initial report, use the REPORT GATE command without options to generate a report on the same gates, or specify new options as needed. Important ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

Parameters If you do not specify one of the following options, Conformal automatically determines if the identifier is a number or a path. In the case of a number, Conformal uses the -id option; otherwise, Conformal searches for the gate with the -instance, -pin, or -net option; in this respective order. -INStance Instance path. This is the default.

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-Pin -Net -ID

Pin path Net path Gate identification number The identification number is an integer assigned automatically by Conformal. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

-Golden -Revised -SUPport -FRONTIER -FANIn -FANOut -UNReach -SHORT_list -NOSHORT_list -SOURCE -Collapse

The identifier is in the Golden design. This is the default. The identifier is in the Revised design. Reports the supported key points from the fanin cone. Reports the frontier key points from the fan-out cone. Reports this number of levels in the fanin cone. The default value is 0. Reports this number of levels in the fan-out cone. The default value is 0. Displays diagnosis information for unmapped points that were classified as unreachable. Lists the first and last 20 gates of a long display list. This is the default. Displays the entire display list. Reports the gate information, which includes the module name, instance name, filename, and source line. Does not report inverters and buffers in the fanin cone. The default is to report all inverters and buffers in the fanin/fan-out cone. Use this option in conjunction with the -fanin option. The fanin cone does not stop at a gate with dynamic constraints. This is the default.

-NODYNamic

-DYNamic

Use this option in conjunction with the -fanin option. The fanin cone stops at the gate with dynamic constraints.

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-INDent -Type

Displays this amount of whitespace when reporting the fanin and fan-out cones. The default value is 2. Reports all gates with the specified gate type. The available gate types are as follows: PI: Primary inputs 0: TIE-0 gates 1: TIE-1 gates E: TIE-E gates Z: TIE-Z gates BBOX: Blackboxes DFF: D flip-flops DLAT: D-latches CUT: Artificial gates for breaking combinational feedback loops OUT: Artificial gates for the multiple outputs of blackboxes COMB: Combinational gates PO: Primary Outputs

-RETention

Note: This is a Conformal Low Power option. If the gate is a sequential element (DFF or DLAT) and belongs to the Golden Design, this option reports the tag-name (if any) associated with the DFF or DLAT. If the gate is a sequential element (DFF or DLAT) and belongs to the Revised Design, this option reports the power gating cell attribute (if any) associated with the DFF or DLAT. For non-sequential elements, nothing is reported.

-CORRespondence

Reports the correspondence gates in the other (Golden or Revised design) netlist. The correspondence gate is potentially equivalent with the gate specified in this command. Use the PROVE command to formally prove the equivalence. Reports gate type statistics. The default is not to report the statistics. Displays the gates in the netlist that represent constraint functions.

-SUMmary -CONSTRAINT

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-ASSERTION -ALLDNET

Displays the gates in the netlist that represent assertion functions. Displays all the design-level nets.

Related Commands
BACKWARD CHANGE GATE TYPE FORWARD REPORT PATH SET GATE REPORT

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REPORT HIER_COMPARE RESULT
REPort HIer_compare Result [-Summary | -Equivalent | -NONEQuivalent | -Abort | -UNcompared | -FLattened | -DYNamicflattened | -EXTRA_po | -ALL] [-USage] (Setup / LEC Mode)

Displays the results of the hierarchical comparison. If the WRITE HIER_COMPARE DOFILE command is used, this command is automatically placed at the end of the hierarchical dofile script. It lists the summary results and any modules that are nonequivalent, aborted, or uncompared.

Parameters
-Summary -Equivalent -NONEQuivalent -Abort -UNcompared -FLattened Displays a summary table of the hierarchical comparison results. This is the default. Displays only the hierarchical modules that are equivalent. Displays only the hierarchical modules that are nonequivalent. Displays only the hierarchical modules that had abort key points. Displays only the hierarchical modules that are not compared. Displays only the hierarchical modules that were found to be nonequivalent and, as a result, were flattened. Use this option when you have used write hier_compare dofile -conditional -DYNamicflattened Displays only the hierarchical modules that were either found to be non-equivalent, or were equivalent but caused non-equivalence at the parent level, and were automatically flattened. Use this option when performing hierarchical comparison with the RUN HIER_COMPARE command. -EXTRA_po -ALL Displays only the hierarchical modules that have extra (not-mapped) primary outputs. Displays the results of all of the modules.

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-USage

Displays the CPU use time for each module comparison.

Related Commands
RESET HIER_COMPARE RESULT RUN HIER_COMPARE SAVE HIER_COMPARE RESULT WRITE HIER_COMPARE DOFILE

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REPORT IGNORED INPUTS
REPort IGnored Inputs [-ROot | -Module | -All] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays the input pins, which were added as ignored inputs, in the Golden and Revised designs. These pins were originally specified with the ADD IGNORED INPUTS command.

Parameters
-ROot Displays only the input pins in the root module. This is the default.

-Module Displays only the ignored input pins in the named module. -All -Both -Golden -REvised Displays all ignored input pins in all modules within the given defaults. Displays both the Golden and Revised added ignored inputs. This is the default. Displays the added ignored inputs from the Golden design. Displays the Revised ignored inputs.

Related Commands
ADD IGNORED INPUTS DELETE IGNORED INPUTS

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REPORT IGNORED OUTPUTS
REPort IGnored Outputs [-ROot | -Module | -All] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays the output or I/O pins, which were added as ignored outputs, in the Golden and Revised designs. These outputs were originally specified with the ADD IGNORED OUTPUTS command.

Parameters
-ROot Displays only the input pins in the root module. This is the default.

-Module Displays only the ignored output or I/O pins in the specified module. -All -Both -Golden -REvised Displays all ignored input pins in all modules within the given defaults. Displays both the Golden and Revised added ignored outputs. This is the default. Displays only the Golden added ignored outputs. Displays only the Revised ignored outputs.

Related Commands
ADD IGNORED OUTPUTS DELETE IGNORED OUTPUTS

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REPORT INSTANCE ATTRIBUTE
REPort INstance Attribute [-ROot | -Module | -All] [-Summary | -Verbose] [-Both | -Golden | -REvised] (Setup Mode)

Displays the attributes placed on instances in the Golden and Revised designs. These attributes were originally specified with the ADD INSTANCE ATTRIBUTE command.

Parameters
-ROot Displays only the added instance attributes in the root module. This is the default.

-Module Displays only the added instance attributes in the specified module. -All -Summary -Verbose -Both -Golden -REvised Displays all added instance attributes within the given defaults. Displays a summary message of the total number of added instance attributes. This is the default. Displays all added instance attributes. Displays the added instance attributes in both the Golden and Revised designs. This is the default. Displays the added instance attributes in the Golden design. Displays the added instance attributes in the Revised design.

Related Commands
ADD INSTANCE ATTRIBUTE DELETE INSTANCE ATTRIBUTE

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REPORT INSTANCE CONSTRAINTS
REPort INstance Constraints [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the constraints placed on instances in the Golden and Revised designs. These constraints were originally specified with the ADD INSTANCE CONSTRAINTS command.

Parameters
-Both -Golden -Revised Displays the instance constraints in both the Golden and Revised designs. This is the default. Displays the instance constraints in the Golden design. Displays the instance constraints in the Revised design.

Related Commands
ADD INSTANCE CONSTRAINTS DELETE INSTANCE CONSTRAINTS

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REPORT INSTANCE EQUIVALENCES
REPort INstance Equivalences [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the equivalences placed on instances in the Golden and Revised designs. These equivalences were originally specified with the ADD INSTANCE EQUIVALENCES command.

Parameters
-Both -Golden -Revised Displays the instance equivalences in both the Golden and Revised designs. This is the default. Displays the instance equivalences in the Golden design. Displays the instance equivalences in the Revised design.

Related Commands
ADD INSTANCE EQUIVALENCES DELETE INSTANCE EQUIVALENCES

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REPORT KEY POINT
REPort KEy Point [[-TYpe ... | -NOTYpe ...] | -Mapped | -UNMapped | -UNReached] [-PROPerty] [-DC] [-Golden | -REVised] (Setup / LEC Mode)

Report key points in the design.

Parameters
-TYpe -NOTYpe Displays all key points with the specified type. Displays all key points except the specified type. The available types for -Type and -NOType are as follows: PI: Primary inputs E: TIE-E gates Z: TIE-Z gates DFf: D flip-flops DLat: D-latches CUt: Artificial gates for breaking combinational feedback loops BBox: Blackboxes PO: Primary Outputs -Mapped -UNMapped -UNReached -PROPerty -DC -Golden Displays all mapped key points in the design. Displays all unmapped key points in the design. Displays diagnosis information for unmapped key points that were classified as unreachable. Displays support and fan-out key points for each key point Displays the number of DC gates in the compare cone Specifies that the report applies only to the Golden design. This is the default.
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-Revised

Specifies that the report applies only to the Revised design.

Related Commands
MAP KEY POINTS

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REPORT LIBRARY DATA
REPort LIbrary Data [-Source] [-SORT ] [-SKIP_Unref] [-Golden | -Revised] (Setup / LEC Mode)

Displays the following columns:
■ ■ ■

ID—Specifies the cell ID. Name—Specifies the cell name. Cost—Specifies the cost of each library cell, which is the product of the number of instances of primitive gates within each library cell (Ins) and the number of times the library cell is instantiated (Ref). Ins—Displays the number of instances of primitive gates within each library cell. Ref—Displays the number of times the library cell is referenced in the design. TOT—Displays the total number of gates per library cell. This total is calculated by Ins times Ref. If Ins is 3 and Ref is 3, the total is 9. If Ins is 3 and Ref is 0, the total is 0.

■ ■ ■

■ ■ ■ ■ ■ ■

DFF—Specifies whether the cell contains a D flip-flop. DLAT—Specifies whether the cell contains a D-latch. BUF—Specifies whether the cell contains a buffer. NOT—Specifies whether the cell contains an inverter gate. BBOX—Specifies whether the cell contains a blackbox. UDP—Specifies whether the cell is a UDP.

By default, Conformal reports on the library for the Golden design if you do not specify options. Note: When you read in a library, you can specify whether it is for the Golden or Revised design.

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Parameters
-SOURCE -SORT Displays the source filename and line number for each cell. Sorts report data as specified: NAME REFerence INStance -SKIP_Unref -Golden -Revised Sorts report data alphabetically by library cell name. Sorts report data according to the Reference column, in descending order. Sorts report data according to the Instance column in descending order.

Does not display unreferenced library modules. Displays the library data for the Golden design. This is the default. Displays the library data for the Revised design.

Related Commands
READ LIBRARY READ DESIGN REPORT DESIGN DATA

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REPORT LOWPOWER CELLS
REPort LOwpower Cells [-Module | -Instance] [-Summary] (Setup / LEC Mode)

Note: This is a Conformal Low Power command. Reports the low power cells used in the design.

Parameters
-Module -Instance -Summary Reports only the modules with low power cells. This is the default. Reports only the instances with low power cells. Displays a summary of low power cells.

Related Commands
ADD LOWPOWER CELLS CHECK LOWPOWER CELLS DELETE LOWPOWER CELLS REPORT LOWPOWER DATA SET LOWPOWER OPTION

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REPORT LOWPOWER DATA
REPort LOwpower Data [-STatus ] [-TYpe [All | Retention_cell_check [ -Rule ] | Isolation_cell_check | Level_shifter_cell_check | POWER_domain_check] ] [-SUMmary | -Verbose] (LEC Mode)

Note: This is a Conformal Low Power command. Reports the low power data. These are the results of the low power check performed on low power cells using the CHECK LOWPOWER CELLS command. For a description of the default rules that are added by the system, see CHECK LOWPOWER CELLS on page 144.

Parameters
-STatus Specifies the status reporting. For retention-register cell types, the -STatus arguments are described as follows: All: Reports all the sequential pairs (LEC mapped points) that passed or failed the default rule or user rule. This is the default. Pass: Reports all the sequential pairs that passed the default rule or user rule Fail: Reports all the sequential pairs that failed the default rule or user rule Notcheck: Reports the sequential pairs that were not checked for retention-register consistency

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For isolation and level-shifter cell types, the -STatus arguments are described as follows: All: Reports all the low power cut gates that passed or failed the technology mapping check. This is the default. Pass: Reports all the low power cut gates that passed the technology mapping check Fail: Reports all the low power cut gates that failed the technology mapping check Notcheck: Reports the low power cut gates that were not checked for isolation and level-shifter consistency For the power domain consistency check, the -STatus arguments are described as follows: All: Reports all the mapped sequential points that passed and failed the power domain consistency check. This is the default. Pass: Reports the mapped sequential points that passed the power domain consistency check Fail: Reports the mapped sequential points that failed the power domain consistency check Notcheck: Reports the mapped sequential points that were not checked for power domain consistency -TYpe Specifies the module type reporting. All Reports on all low power cells. This is the default.

Retention [-Rule ] Reports on only the low power state retention cells. -Rule reports all the sequential pairs that passed or failed the specified rulename. -Isolation_cells Reports on only the low power isolation cells. -Level_shifter_cells Reports on only the low power level-shifter cells.

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-POWER_domain_check Reports the results of power domain consistency check for the mapped sequential points. -SUMmary -Verbose Displays the status summary of the check performed on low power cells. This is the default. For state retention cells, this reports the sequential pairs (LEC mapped points) that passed or failed the default rule or user rule. For each passed or failed sequential pair, the corresponding rule it passed or failed on is also reported. In addition, this reports any tag-name for the sequential element in the Golden Design, and any power gating cell attribute for the sequential element in the Revised Design. For isolation cells and level-shifter cells, this reports the PASS or FAIL status of low power cut gates that correspond to the isolation cells and level-shifter cells.

Related Commands
ADD LOWPOWER CELLS CHECK LOWPOWER CELLS DELETE LOWPOWER CELLS REPORT LOWPOWER CELLS SET LOWPOWER OPTION

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REPORT MAPPED POINTS
REPort MApped Points [< | | ... | [-TYpe < PI | E | Z | DFf | DLat | CUt| BBox | PO> ... | [-NOTYpe < PI | E | Z | DFf | DLat | CUt| BBox | PO> ... > [-INVert_mapped] | -SUMmary] [-LOng] [-CLass ] [-INput] [-OUTput] [-GRoup] [-REName] [-Golden | -REVised] [-RETention] [-METHOD] [-UNReachable] [-FUNCTIONAL_mapped | -NAME_mapped] (LEC Mode)

Displays the mapped points that were automatically identified or added with the ADD MAPPED POINTS command. Each mapped point from the Golden and Revised design is displayed along with a summary of all Golden and Revised mapped points. The summary includes the total number of primary inputs, primary outputs, D flip-flops, D-latches, TIE-Es, TIE-Zs, blackboxes, and cut gates. If no options are entered, the command default is to display both the User and System classes of mapped points. Wildcard: The wildcard (*) represents any zero or more characters in instance or pin paths of mapped points.

Parameters Reports the mapped points for the identified gate. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. Reports the mapped points for the named instance path(s). This accepts wildcards.

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-Type -NOType

Reports the mapped points for the named pin path(s). This accepts wildcards. Displays all mapped points with the specified type. Does not display mapped points with the specified type. The available types for -Type and -NOType are as follows: PI: Primary inputs E: TIE-E gates Z: TIE-Z gates DFf: D flip-flops DLat: D-latches CUt: Artificial gates for breaking combinational feedback loops BBox: Blackboxes PO: Primary Outputs

-INVert_mapped -SUMmary -LOng -INput -Class

Displays all mapped points with inverted mapping. Displays a table summary of the mapped points in the Golden and Revised designs. Displays pairs of mapped points on separate lines. Displays the input port mapping pairs of the specified DFF, DLAT, or blackbox gate. Displays the following class of mapped points. Full System User Mapped points from both the User and System classes. This is the default. Mapped points from the original design. Mapped points added with the ADD MAPPED POINTS command

-OUTput

Displays the output port mapping pairs of the specified blackbox gate.

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-GRoup

Displays the mapping pairs in which either the Golden or Revised key point is a group of equivalent gates rather than a single gate. The group can be defined with the ADD INSTANCE EQUIVALENCE command or the -seq_merge option of the SET FLATTEN MODEL command. A key point group is counted as one key point.

-REName -Golden -REVised -RETention

Lists the keypoint with renaming rules applied to the names. The mapped points are from the Golden design. This is the default. The mapped points are from the Revised design. Note: This is a Conformal Low Power option. If the mapped point is a sequential pair (DFF or DLAT pair), this option reports the status of the mapped point (Pass, Fail, or Unknown) in accordance with the state retention mapping rules. This also reports the tag-name (if any) associated with the Golden DFF or DLAT and the power gating cell attribute (if any) associated with the Revised DFF or DLAT. For non-sequential elements, nothing is reported.

-METHOD -UNReachable

Shows the method used in mapping the keypoints. Lists unreachable keypoints. Unreachable key points are those that do not eventually affect the primary output of the design. Displays all functional mapped points. Displays all name mapped points.

-FUNCTIONAL_mapped -NAME_mapped

Related Commands
ADD MAPPED POINTS DELETE MAPPED POINTS MAP KEY POINTS REPORT STATISTICS REPORT UNMAPPED POINTS
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REPORT MESSAGES
REPort MEssages [-MOdeling | -MAPping | -Compare] [-RUle ] [-Summary | -Verbose] [-NOSORT | -SORT] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays either a summary or complete list of the warning messages that come from the modeling, mapping, or comparison process. (The modeling process occurs when Conformal exits the Setup mode.) A summary of the warning messages is always displayed when the modeling, mapping, or comparison process is in progress; however, this command displays each individual warning message for the Golden and Revised designs, according to your specifications. See “Modeling Messages” in the Encounter Conformal Equivalence Checking User Guide for information on the Modeling Messages and the commands/options that trigger them.

Parameters
-MOdeling Displays only warning messages from the processing and modeling of the Golden and Revised designs. This is the default. Displays warning messages only from the automatic key point mapping process. Displays warning messages only from the comparison process. Displays only the named rule. Displays only a summary message for common warning messages. This is the default. Displays all warning messages. Does not sort messages. This is the default. Sorts messages alpha-numerically. (Use this option with the -verbose option.)

-MAPping -Compare -RUle -Summary -Verbose -NOSORT -SORT

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-Both -Golden -REvised

Displays warning messages that come from both the Golden and Revised designs and libraries. This is the default. Displays warning messages that come from the Golden design and library. Displays warning messages that come from the Revised design and library.

Related Commands
READ DESIGN READ LIBRARY SET FLATTEN MODEL

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REPORT MODULE ATTRIBUTE
REPort MOdule Attribute [-ALL | -PIPELINE_Retime | -COMPARE_Effort | -CPU_Limit] [-Both | -Golden | -Revised] (Setup Mode)

Displays the module attributes in the Golden and Revised designs. These attributes were originally added with the ADD MODULE ATTRIBUTE command.

Parameters
-ALL -PIPELINE_Retime -COMPARE_Effort -CPU_Limit -Both -Golden -Revised Displays “all” added module attributes within the given defaults. Displays only the modules added for pipeline-retiming. Displays only the modules that have specified compare effort levels. Displays the modules with a specified CPU time limit. Displays the module attributes for both the Golden and Revised designs. This is the default. Displays the module attributes for the Golden design. Displays the module attributes for the Revised design.

Related Commands
ADD MODULE ATTRIBUTE DELETE MODULE ATTRIBUTE READ DESIGN READ LIBRARY WRITE HIER_COMPARE DOFILE

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REPORT MODULES
REPort MOdules [-ROot | [-Up | -Down] | -All | -Top] [-Source] [-INSTantiation] [-USer] [-VHDLname] [-LEVEL ] [-Library] [-NOINTERLeave |-INTERLeave] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays module information for the Golden and Revised designs. If you specify a module, Conformal displays additional information on modules and library cells up or down the hierarchy of the given module name.

Parameters
-ROot Displays the name of the root module. Reports module information on the specified module. An additional option lets you report on modules and library cells either up or down the hierarchy of the specified module name. The default is to report modules and library cells up the hierarchy of the specified module name. -Up Reports on modules and library cells up the hierarchy of the specified module name. This is the default. Reports on modules and library cells down the hierarchy of the specified module name.

-Down -All -Top -Source -Instantiation

Displays all the modules within the given defaults. The top root module is denoted by (T). Displays the top modules. Displays the source-code information identifying where the module is located. Displays instances and modules.

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-USer

Reports only the modules defined in the design files, and skips the internal modules which are not defined in the design files. Note: Some internal modules can be created by the Conformal tools after reading the design files. These internal modules are not defined in the design files.

-VHDLname

Displays the full name, rather than just the entity name. For example: libname.entityname(architecturename).

-LEVEL -Library -NOINTERLeave

Shows modules in a hierarchical order up to the specified level. Displays all of the library cells that are in the module hierarchy. Reports the Golden and Revised module hierarchies separately, first list Golden modules, and then list Revised modules. This is the default. Reports the Golden and Revised module hierarchies together. Displays information for both the Golden and Revised designs. This is the default. Displays module information for the Golden design. Displays module information for the Revised design.

-INTERLeave -Both -Golden -Revised

Examples
This example shows the difference between running the REPORT MODULES command without any options versus running the command with the -USer option. The following design file contains only one module named test. Module VDW_mult_nbw_u8_u8_16 is internal module which is not defined in this file: module test(aa, bb, oo); input [7:0] aa, bb; output oo; assign oo = aa * bb; endmodule

Running the following command: report modules

the Conformal software reports the test and VDW_mult_nbw_u8_u8_16 modules. However, when running the following command: report modules -user
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Related Commands
REPORT MODULE ATTRIBUTE REPORT PATH

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REPORT MOS DIRECTION
REPort MOs Direction [module_name] [-Summary | -Verbose] [-BIdirection | -UNidirection ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Note: This requires a Conformal GXL license. Displays the unidirectional and bidirectional transistor-MOS instances with their source and drain ports.

Parameters module_name -Summary Reports on the named module. Displays a summary message of the total number of unidirectional and bidirectional transistor-MOS. This is the default. Displays all of the unidirectional and bidirectional transistor-MOS. Displays only the bidirectional transistor-MOS instances. This is the default. Displays only the unidirectional transistor-MOS instances. Displays MOS direction from both the Golden and Revised designs. This is the default. Displays MOS direction from the Golden design. Displays MOS direction from the Revised design.

-Verbose -BIdirection -UNidirection -Both -Golden -Revised

Related Commands
ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE
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REPORT MULTIPLIER OPTION
REPort MUltiplier Option (Setup / LEC Mode)

Displays current multiplier option settings.

Related Commands
ANALYZE DATAPATH ANALYZE MODULE REPORT DATAPATH OPTION SET DATAPATH OPTION SET MULTIPLIER OPTION SET FLATTEN MODEL

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REPORT NET ATTRIBUTE
REPort NEt Attribute [-ALL | -VDD | -GND | -CLOCK0 | -CLOCK1 | -DYNSTate] [-Module ] [-Both | -Golden | -Revised]

Note: This requires a Conformal GXL license. Displays attributes on transistor-MOS nets. The attributes were originally added with the ADD NET ATTRIBUTE command.

Parameters
-ALL -VDD -GND -CLOCK0 -CLOCK1 -DYNSTate Displays “all” added net attributes within the given defaults. Displays only the added VDD net attributes. Displays only the added GND net attributes. Displays only the added Clock-0 net attributes. Displays only the added Clock-1 net attributes. Displays only the added dynamic state net attributes.

-Module Reports net attributes from the named module. -Both -Golden -Revised Displays net attributes from both the Golden and Revised designs. This is the default. Displays net attributes from the Golden design. Displays net attributes from the Revised design.

Related Commands
ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE

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REPORT NET CONSTRAINTS
REPort NEt Constraints [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays all net constraints in the Golden and Revised designs that were added with the ADD NET CONSTRAINTS command.

Parameters
-Both -Golden -Revised Displays added net constraints in both the Golden and Revised designs. This is the default. Displays the added net constraints in the Golden design. Displays the added net constraints in the Revised design.

Related Commands
ADD NET CONSTRAINTS DELETE NET CONSTRAINTS

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REPORT NOBLACK BOX
REPort NOblack Box [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays all of the modules in the Golden and Revised designs that will not be included in the hierarchical dofile script generation. These modules were originally specified with the ADD NOBLACK BOX command.

Parameters
-Both -Golden -Revised Displays added noblackboxes in both the Golden and Revised designs. This is the default. Displays the added noblackboxes in the Golden design. Displays the added noblackboxes in the Revised design.

Related Commands
ADD NOBLACK BOX DELETE NOBLACK BOX WRITE HIER_COMPARE DOFILE

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REPORT NOTRANSLATE FILEPATHNAMES
REPort NOtranslate Filepathnames [ | -Library | -Design] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays all of the library and design file pathnames originally added with the ADD NOTRANSLATE FILEPATHNAMES command. The Conformal software will not compile these modules defined in libraries and design files.

Parameters
-Library -Design -Both -Golden -Revised Displays only the added library file pathnames. Displays only the added design file pathnames. Displays added file pathnames in both the Golden and Revised designs. This is the default. Displays the added file pathnames in the Golden design. Displays the added file pathnames in the Revised design.

Related Commands
ADD NOTRANSLATE FILEPATHNAMES ADD NOTRANSLATE MODULES DELETE NOTRANSLATE FILEPATHNAMES DELETE NOTRANSLATE MODULES REPORT NOTRANSLATE MODULES

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REPORT NOTRANSLATE MODULES
REPort NOtranslate Modules (Setup / LEC Mode)

Displays all of the library and design modules originally added with the ADD NOTRANSLATE MODULES command. Conformal will not compile these modules when reading in libraries and designs.

Related Commands
ADD NOTRANSLATE MODULES DELETE NOTRANSLATE MODULES READ DESIGN READ LIBRARY

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REPORT OUTPUT EQUIVALENCES
REPort OUtput Equivalences [-ROot | -Module | -All ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the output pin equivalences in the Golden and Revised designs. These output pin equivalences were originally added with the ADD OUTPUT EQUIVALENCES command.

Parameters
-ROot Displays all output pin equivalences from the root module. This is the default.

-Module Displays the output pin equivalences in the specified module. -All -Both -Golden -Revised Displays “all” output pin equivalences in all modules within the given defaults. Displays the output pin equivalences in both the Golden and Revised designs. This is the default. Displays the output pin equivalences in the Revised design. Displays the output pin equivalences in the Golden design.

Related Commands
ADD OUTPUT EQUIVALENCES DELETE OUTPUT EQUIVALENCES

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REPORT OUTPUT STUCK_AT
REPort OUtput Stuck_at [-ROot | -Module | -All ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the output stuck_at values and pin names in the Golden and Revised designs. These output stuck_at values were originally added to pins with the ADD OUTPUT STUCK_AT command.

Parameters
-ROot Displays the output stuck_at values and pin names from the root module. This is the default.

-Module Displays the output stuck_at values and pin names from the specified module. -All -Both -Golden -Revised Displays all output stuck_at values and pin names in all modules within the given defaults. Displays the output stuck_at values and pin names in both the Golden and Revised designs. This is the default. Displays the output stuck_at values and pin names in the Revised design. Displays the output stuck_at values and pin names in the Golden design.

Related Commands
ADD OUTPUT STUCK_AT DELETE OUTPUT STUCK_AT

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REPORT PARTITION KEY_POINT
REPort PArtition Key_point (Setup / LEC Mode)

Displays the partition key points originally added with the ADD PARTITION KEY_POINT command.

Related Commands
ADD PARTITION KEY_POINT DELETE PARTITION KEY_POINT WRITE PARTITION DOFILE

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REPORT PARTITION POINTS
REPort Partition Points [-Both | -Golden | -Revised] [-Verbose | -Summary] (LEC Mode)

Note: This requires a Conformal XL license. Displays the partition points that were created with the ADD PARTITION POINTS command.

Parameters
-Both -Golden -Revised -Verbose -Summary Lists the partition points in both the Golden and Revised designs. This is the default. Lists the partition points in the Golden design. Lists the partition points in the Revised design. Displays all added partition points. This is the default. Displays a summary message of the total number of added partition points.

Related Commands
ADD PARTITION POINTS DELETE PARTITION POINTS

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REPORT PARTITION RESULT
REPort PArtition Result (Setup Mode)

Displays the results after running partition dofile.

Related Commands
ADD PARTITION KEY_POINT DELETE PARTITION KEY_POINT WRITE PARTITION DOFILE

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REPORT PATH
REPort PAth [-Source] [-NET] [-SEQ_ASYNC] [-Golden | -Revised] (Setup / LEC Mode)

Displays the paths between a source gate and a destination gate. The -feedback option displays all feedback paths for all CUT gates. The source and destination gates can begate ID numbers, instance paths, or pin paths. To report the feedback path on one CUT gate, use the same CUT gate ID, instance path, or pin path for both the source and the destination.

Parameters Specifies the gate ID number, instance path, or pin path of the source gate. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. Specifies the gate ID number, instance path, or pin path of the destination gate. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -Feedback -SELF -Source -NET -SEQ_ASYNC Reports the feedback path of all CUT gates, within the given defaults. Reports all loops to DFF and DLATs. If you specify a gate, it reports only loops to that gate. Displays the file and line number location of the gate in the path. Displays the corresponding net of the gate in the path. Reports DFF/DLAT to DFF/DLAT paths passing through the asynchronous set or reset of a sequential element.

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-Golden -Revised

Reports the specified path in the Golden design. This is the default. Reports the specified path in the Revised design.

Related Commands
ADD CUT POINT DELETE CUT POINT REPORT CUT POINT REPORT GATE

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REPORT PIN CONSTRAINTS
REPort PIn Constraints [-ROot | -Module | -All] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the constraints placed on primary input pins in the Golden and Revised designs. These constraints were originally specified with the ADD PIN CONSTRAINTS command.

Parameters
-ROot Displays the pin constraints from the root module. This is the default.

-Module Displays the pin constraints from the specified module. -All -Both -Golden -Revised Displays pin constraints in all modules within the given defaults. Displays the constrained primary input pins from both the Golden and Revised designs. This is the default. Displays the constrained primary input pins from the Golden design. Displays the constrained primary input pins from the Revised design.

Related Commands
ADD PIN CONSTRAINTS DELETE PIN CONSTRAINTS

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REPORT PIN DIRECTION
REPort PIn Direction [-IO | -IN | -OUT] [] [-Summary | -Verbose] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the assigned pin directions for each module. The default is to display only a summary message. Note: Use the ASSIGN PIN DIRECTION command to assign pin direction to module I/O pins.

Parameters
-IO -IN -OUT -Summary -Verbose -Both -Golden -Revised Reports assigned module I/O pins. This is the default. Reports assigned module input pins. Reports assigned module output pins. Reports pin direction for the specified module. The default is to report pin direction for all modules. Displays only a summary message of assigned pin directions. This is the default. Displays all assigned pin directions. Reports the assigned pin directions in both the Golden and Revised designs. This is the default. Reports the assigned pin directions in the Golden design. Reports the assigned pin directions in the Revised design.

Related Commands
ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION

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REPORT PIN EQUIVALENCES
REPort PIn Equivalences [-ROot | -Module | -All] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays a list of added pin equivalences and inverted pin equivalences. These pin equivalences were originally added with the ADD PIN EQUIVALENCE command. Inverted pin equivalences are distinguished by a “-” next to the primary input pin name.

Parameters
-ROot Displays pin equivalences from the root module. This is the default.

-Module Displays pin equivalences from the specified module. -All -Both -Golden -REvised Displays pin equivalences in all modules within the given defaults. Displays pin equivalences from both the Golden and Revised designs. This is the default. Displays pin equivalences from the Golden design. Displays pin equivalences from the Revised design.

Related Commands
ADD PIN EQUIVALENCES DELETE PIN EQUIVALENCES

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REPORT PRIMARY INPUTS
REPort PRimary Inputs [-Class ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays primary input pins from the Golden and Revised designs.

Parameters
-Class Displays the following class of primary inputs. Full System User -Both -Golden -Revised Primary inputs from both the User and System classes. This is the default. Primary inputs from the original design Primary inputs added with the ADD PRIMARY INPUT command

Displays both the Golden and Revised primary inputs. This is the default. Displays the Golden design primary inputs. Displays the Revised design primary inputs.

Related Commands
ADD PRIMARY INPUT DELETE PRIMARY INPUTS

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REPORT PRIMARY OUTPUTS
REPort PRimary Outputs [-Class ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays primary output pins from the Golden and Revised designs.

Parameters
-Class Displays the following class of primary outputs. Full System User -Both -Golden -Revised Primary outputs from both the User and System classes. This is the default. Primary outputs from the original design Primary outputs added with the ADD PRIMARY OUTPUT command

Displays both the Golden and Revised primary outputs. This is the default. Displays Golden design primary outputs. Displays Revised design primary outputs.

Related Commands
ADD PRIMARY OUTPUT DELETE PRIMARY OUTPUTS

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REPORT PULSE GENERATOR
REPort PUlse Generator [-ALL | MODule ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Note: This requires a Conformal GXL license. Reports the instances that were transformed with the SET ABSTRACT MODEL -transform_pulse_generator_on command.

Parameters
-ALL Displays all instances. This is the default.

-MODule Displays a specified module that was transformed. -Both -Golden -Revised Applies to both the Golden and Revised designs. This is the default. Applies to the Golden design. Applies to the Revised design.

Related Commands
SET ABSTRACT MODEL

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REPORT REMOVED INSTANCE
REPort REMoved Instance [-Golden | -Revised] (Setup / LEC Mode)

Report instances removed with the REMOVE command.

Parameters
-Golden -Revised Reports instances removed from the Golden design. This is the default. Reports instances removed from the Revised design.

Related Command
REMOVE

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REPORT RENAMING RULE
REPort REnaming Rule [ |-MAp | -MOdule | -PIn] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the list of renaming rules for mapping, module, and pin renaming. These rules were originally added with the ADD RENAMING RULE command. The list displays a rule number along with a renaming rule. If you do not enter options, Conformal displays all renaming rules.

Parameters
-MAp -MOdule -PIn -Both -Golden -Revised Displays only mapping renaming rules. If you do not specify -map, -module, or -pin, Conformal reports all renaming rules. Displays only module renaming rules. Displays only pin renaming rules. Displays the renaming rules applied to both the Golden and Revised designs. This is the default. Displays the Golden design renaming rules. Displays the Revised design renaming rules.

Related Commands
ADD RENAMING RULE DELETE RENAMING RULE READ DESIGN READ LIBRARY SET MAPPING METHOD SET NAMING RULE TEST RENAMING RULE

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REPORT RETENTION MAPPING
REPort REtention Mapping (Setup / LEC Mode)

Note: This is a Conformal Low Power command. Reports the retention mapping rules. The set of rules reported include the user rules added using the ADD RETENTION MAPPING command and the default rule added by the system. For a description of the default rules that are added by the system, see CHECK LOWPOWER CELLS on page 144. Note: The default rule is always reported even if no user rule is added using the ADD RETENTION MAPPING command.

Related Commands
ADD RETENTION MAPPING DELETE RETENTION MAPPING

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REPORT RULE CHECK
REPort RUle Check [-All | -MODIfied | [-SETTING] ] [-File []] [-MODUle ] [-Summary | -Verbose] [-HELP] [ | -Design | -Library] [-Ignore] [-Note] [-Warning] [-Error] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays the list of rule violations after the designs and libraries have been read in. Use the -summary option to display all of the violated rules. Use the SET RULE HANDLING command to change the handling of any of these reported rule violations. See the Encounter Conformal Equivalence Checking User Guide for rule definitions and sample cases. Rules with a severity of “Ignore” are not reported except with the rule_name or -ignore options.

Parameters
-All -MODIfied -SETTING Reports all rule violations encountered in the designs and libraries within the given defaults. This is the default. Reports all the rule check violations that have a different severity level than the original default. Reports specified rule violations. Wildcards are supported. Displays the current severity level for the rule.

-File [] Reports all rule check messages in a file. With the option, you can report all rule check messages for a specific line number. -Module
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Reports the rule checks that are specific to the specified module. -Summary -Verbose -HELP -Design Display a summary of the rule violations. This is the default. Displays each instance of the rule violation. Lists the names and numbers of all HDL rules. Reports the design rule violations. If you do not specify -design or -library, the Conformal software reports rule violations from both designs and libraries. -Library Reports the library rule violations. If you do not specify -design or -library, the Conformal software reports rule violations from both designs and libraries. -Ignore -Note -Warning -Error Reports violations that have a severity level of Ignore. Reports violations that have a severity level of Note. Reports violations that have a severity level of Warning. Reports violations that have a severity level of Error.

Note: By default, rules with severity levels other than Ignore will be reported -Both -Golden -Revised Reports the rule violations from Golden and Revised designs and libraries. This is the default. Reports the Golden design and library rule violations. Reports the Revised design and library rules violations.

Related Commands
READ DESIGN READ LIBRARY SET RULE HANDLING

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REPORT SEARCH PATH
REPort SEarch Path [ | -Design | -Library] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the paths Conformal searches to locate filenames included in the READ DESIGN and READ LIBRARY commands.

Parameters
-Design Reports the search path used by the READ DESIGN command. If you do not specify -design or -library, Conformal reports the search path used by both the READ DESIGN command and the READ LIBRARY command. -Library Reports the search path used by the READ LIBRARY command. If you do not specify -design or -library, Conformal reports the search path used by both the READ DESIGN command and the READ LIBRARY command. -Both -Golden -Revised Reports the search path used by both the Golden and Revised designs. This is the default. Reports the search path used by the Golden design and library. Reports the search path used by the Revised design and library.

Related Commands
ADD SEARCH PATH DELETE SEARCH PATH READ DESIGN READ LIBRARY

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REPORT SEQ_CORR
REPort SEQ_CORR [-ALL [-GOLden | -REVised]] [-GATe [-GOLden | -REVised]] [-UNAccounted] [-RETime < ALL | SUCCESS | FAIL>] (LEC Mode)

Note: This requires a Conformal XL license. Displays the sequential corresponding points that were automatically identified or added with the ADD SEQ_CORR command. Use this command to help debug general retiming by displaying the sequential correspondence and retiming results.

Parameters
-ALL [-GOLden | -REVised] Displays all pairs of the sequential corresponding points. -GOLden displays pairs of the sequential corresponding points where the first elements of the pairs are from the Golden design. This is the option default. -REVised displays pairs of the sequential corresponding points where the first elements of the pairs are form the Revised design -GATe [ -GOLden | -REVised ] Displays the gates in the other design that sequentially correspond to the specified gate. -GOLden indicates that the gate specified by is from the Golden design. This is the option default. -REVised indicates that the gate specified by is from the Revised design. -UNAccounted Displays the registers in the Golden design that neither can be mapped by name to any register in the Revised design, nor have any sequential corresponding point in the Revised design.

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-RETime < ALL | SUCCESS | FAIL> Displays the general retiming results of the sequential corresponding points in the Revised design. ALL displays all the Revised state points’ retiming results. SUCCESS displays only the state points where retiming is successful. FAIL displays only the state points where retiming failed.

Examples
■

The following command reports a list of Golden registers that are neither mapped by name nor have sequential correspondence: report seq_corr -unaccounted

■

The following command reports a list of failed general retiming: report seq_corr -retime fail

Related Commands
ANALYZE RETIMING ADD SEQ_CORR DELETE SEQ_CORR SET RETIMING OPTION

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REPORT STATISTICS
REPort STatistics (LEC Mode)

Summarizes the mapping and comparison statistics for the Golden and Revised designs in a table.

Related Commands
REPORT COMPARE DATA REPORT COMPARED POINTS REPORT MAPPED POINTS REPORT UNMAPPED POINTS

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REPORT SUPPLY
REPort SUpply [-ROOT| -Module | -ALL] [-PORT | -GLOBAL] [-Golden | -Revised | -Both] (Setup Mode)

Note: This requires a Conformal GXL license. Reports the power and ground pins in the design that were defined with the ADD SUPPLY command.

Parameters
-ROOT Reports the supply attribute to the specified objects in the current scope and all hierarchy of this scope. This is the default. Reports the attribute setting to the specified module. This accepts wildcards. Reports the attribute settings to the objects for all modules. The reported object(s) must be the port(s) at the root or the specified module level. This is the default. The reported object(s) could be the port(s) and wire(s) in the hierarchy of the root or the specified module. Specifies that the listed names are from the Golden design. This is the default. Specifies that the listed names are from the Revised design. Specifies that the listed names are from both the Golden and Revised designs.

-Module -ALL -PORT -GLOBAL -Golden -Revised -Both

Related Commands
ADD SUPPLY DELETE SUPPLY
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REPORT TESTCASE
REPort TEstcase < [-NONEQ] [-ABORT] [-Golden ] [-Revised ] [-DATAPATH_module | ] > [-FIle ] [-DIR_name ] [-NAME | -NONAME] [-KEYPOINT_DEPTH ] [-REPlace | -APPend] (LEC Mode)

Automatically extracts testcases for selected key points and generates a dofile and a file containing mapping information. Running the generated dofile can reproduce the problem in original design, such as non-equivalences and aborts. The -datapath_module option applies the testcase extraction to datapath modules in the resource file. This option is used after datapath module-based analysis. The extracted testcase is encapsulated in the XML file.

Parameters
-NONEQ -ABORT -GOlden -Revised -DATAPATH_module Specifies that all non-equivalent points will be selected for the generated testcase. Specifies that all abort points will be selected for the generated testcase. Applies the testcase extraction to the Golden design. Applies the testcase extraction to the Revised design. Specifies the gate ID of the testcase. You can specify multiple gate IDs. Specifies the instance pathname of the testcase. You can specify multiple instance pathnames. Applies report testcase on datapath modules. The default is in the Revised design netlist. If only this option specified, datapath modules in the resource file will be listed.

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-INST_name ... Specifies the instance name to report testcase on datapath modules. You can specify multiple instance names. This accepts wildcards. -QUAlity Specifies a number to report testcase on datapath modules. The testcases whose evaluated quality less than or equal to the specified number will be reported. Specifies the filename where the datapath modules will be written to. If not specified, the name of the file will be datapath_module.xml.

-FIle

-DIR_name Specifies the name of the testcase directory. If not specified, the name of the directory will be LEC_testcase. -NAME -NONAME Includes the names of design objects (nets, instances, ports) in the generated testcase. This is the default. Does not includes the names of design objects (nets, instances, ports) in the generated testcase.

-KEYPOINT_DEPTH Specifies the depth of the key points to report. Starting from the selected key point, the closest key point in its fanin or fan-out cone is a depth of 1. The default is 3. -REPlace -APPend Overwrites the existing testcase directory. This is the default. Prepends the root module name to the specified filename to avoid overwriting the same file, especially used in hierarchical compare flow.

Examples
■

The following command selects all non-equivalent points, all abort points, and key points with gate id 10, with instance dlat in the Golden design netlist and the key point with instance dff in the Revised design netlist, allowing the names of design objects to be included in the generated testcase: report testcase -noneq -abort -golden 10 dlat -revised dff

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■

The following command will select key point with gate id 10 in Revised design netlist for testcase extraction. The names of design objects will use generic names (gate type and a serial number) report testcase -revised 10 -noname

■

The following command will select all non-equivalent points for testcase extraction, using keypoint depth: report testcase -noneq -keypoint_depth 1

■

The following command will report testcases on the datapath module whose instance name starts with add into the file add.xml under the directory LEC_testcase: report testcase -datapath_module -inst_name add* -file \ add.xml -dir_name LEC_testcase -replace

■

The following command will report testcase on the datapath modules whose evaluated quality are less than or equal to 30% into the file low_quality.xml under the directory LEC_testcase: report testcase -datapath_module -quality 30 -file low_quality.xml \ -dir_name LEC_testcase -replace

Related Command
READ TESTCASE

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REPORT TEST VECTOR
REPort TEst Vector [ [-Index ]] [-Golden | -Revised] | [-NONEQ] (LEC Mode)

Displays error patterns for a specific nonequivalent compared point.
■ ■

The first argument is the nonequivalent compared point. This point can be identified with a gate identification number, instance path, or a pin path. The second argument, which is optional, is the diagnosis input point. These points are gates that connect directly to the input ports of the nonequivalent compared point where the logic cones are different. The display shows the diagnosis input point to the nonequivalent compared point; corresponding and non corresponding support key points with their simulation values; and final simulation result of the diagnosis input point The Index option is used to specify which error pattern is displayed after you use the command. If you do not specify an index number, Conformal displays the first error pattern.

■

You can also use this command with the -noneq option to report error patterns for every nonequivalent compared key point.

Parameters | | Specifies the gate identification number, instance path, or pin path of the nonequivalent compared point. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

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| | Specifies the gate identification number, instance path, or pin path of the diagnosis input point to the nonequivalent compared point. Note: These options apply only to diagnosis points for DFF, DLAT, and BBOX. If you enter a point that is not a diagnosis point, Conformal will error out. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -Index -Golden -Revised -NONEQ Displays the specified error pattern. The default is to display the first error pattern. Specifies that the nonequivalent compared point is from the Golden design. This is the default. Specifies that the nonequivalent compared point is from the Revised design. Displays the error pattern for every nonequivalent point.

Related Command
DIAGNOSE

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REPORT TIED SIGNALS
REPort TIed Signals [-ROot | -Module ] [ | -TIE0 | -TIE1 | -TIEZ | -TIEX] [ | -Net | -Pin] [-Class ] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays tied signals from the Golden and Revised designs.

Parameters
-ROot Displays tied signals in the root module. This is the default.

-Module Displays tied signals in the specified module. -TIE0 -TIE1 -TIEZ -TIEX -All -Net -Pin -Class Displays signals tied to logic 0. If you do not specify the logic, Conformal displays signals tied to logic 0, 1, Z, and X. Displays signals tied to logic 1. If you do not specify the logic, Conformal displays signals tied to logic 0, 1, Z, and X. Displays signals tied to logic Z. If you do not specify the logic, Conformal displays signals tied to logic 0, 1, Z, and X. Displays signals tied to logic X. If you do not specify the logic, Conformal displays signals tied to logic 0, 1, Z, and X. Displays all net and instance names, within the given defaults, that have tied signals assigned to them. This is the default. Displays net names that have tied signals assigned to them. Displays pin names that have tied signals assigned to them. Displays this class of tied signals: Full System User Tied signals from both the User and System classes. This is the default. Tied signals from the original design. Tied signals added with the ADD TIED SIGNALS command.

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-Both -Golden -REvised

Displays tied signals from both the Golden and Revised designs. This is the default. Displays tied signals from the Golden design. Displays tied signals from the Revised design.

Related Commands
ADD TIED SIGNALS DELETE TIED SIGNALS

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REPORT UNMAPPED POINTS
REPort UNmapped Points [-SUMmary| -Extra | -UNReachable | -NOTmapped | [ -TYpe ... |-NOTYpe ...] ] [-GRoup] [-LIBName | -NOLIBName] [-RETention] [-NODLAT_GATED_CLOCK] [-GOlden | -Revised] (LEC Mode)

This report lists unmapped points, along with a summary of all of the unmapped points in the Golden and Revised designs. Note: If you do not specify options, Conformal identifies all unmapped points and displays a summary. Furthermore, if you do not specify either Golden or Revised, Conformal reports unmapped points for both designs.

Parameters
-SUMmary -Extra Lists a summary report of all of the unmapped points in the Golden and Revised designs. This is the default. Lists extra points. These points are unmapped because they do not map with a counterpart in the comparison design. Extra points do not affect the circuit. Lists unreachable unmapped points. Unreachable key points are those that do not eventually affect the primary output of the design. Lists “Not-mapped” unmapped key points. Not-mapped key points are those that failed to be mapped.

-UNReachable

-NOTmapped

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-Type

Lists unmapped points of the specified type. Available types are as follows: PI: Primary input E: TIE-E Z: TIE-Z DFf: D flip-flop DLat: D-latch CUt: All unmapped points for artificial gates that break combinational loops BBox: Blackbox PO: Primary output

-NOType -GRoup

Does not list unmapped points of the specified type. Displays the unmapped groups in which either the Golden or Revised key point is a group of equivalent gates rather than a single gate. The group can be defined with the ADD INSTANCE EQUIVALENCE command or the -seq_merge option of the SET FLATTEN MODEL command. A key point group is counted as one key point.

-LIBName -NOLIBName -RETention

When displaying unmapped points, includes suffixes. This is the default. When displaying unmapped points, does not include suffixes. Note: This is a Conformal Low Power option. If the unmapped point is a sequential element (DFF or DLAT) and belongs to the Golden Design, this option reports the tag-name (if any) associated with the DFF or DLAT. If the unmapped point is a sequential element (DFF or DLAT) and belongs to the Revised Design, this option reports the power gating cell attribute (if any) associated with the DFF or DLAT. For non-sequential elements, nothing is reported. The sequential unmapped points are not written out during the CHECK RETENTION MAPPING command, but if present, they are reported as ’Not-Checked’ in the summary section.

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-NODLAT_GATED_CLOCK Does not report deglitching clock-gating DLATs under the Unreachable category. -GOlden -Revised Lists only the Golden unmapped points. This is the default. Lists only the Revised unmapped points.

Related Commands
ADD MAPPED POINTS DELETE MAPPED POINTS MAP KEY POINTS REPORT MAPPED POINTS REPORT STATISTICS SET MAPPING METHOD SET NAMING RULE

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REPORT VERIFICATION
REPort VErification [-Verbose] [-Summary] (LEC Mode)

Reports a table of all violated checklist items for the following categories:
■

Non-standard modeling options used:
❑ ❑ ❑ ❑

Tristated output: checked | not checked Revised X signals set to E: yes | no Floating signals tied to Z: yes | no Command add clock for clock-gating used: yes | no

■

Incomplete verification:
❑ ❑ ❑ ❑ ❑ ❑

All primary outputs are mapped: yes | no All mapped points added as compare points: yes | no All compare points compared: yes | no User added black box: yes | no Black box mapped with different module name: yes | no Command add ignore outputs used: yes | no

■

Modification to design:
❑ ❑ ❑

Change gate type: yes | no Change wire: yes | no Primary inputs added: yes | no

■

Conformal extended checks recommended:
❑ ❑ ❑ ❑

FSM encoding: used | not used RTL5.1 Overlapped case items in parallel case statement: used | not used RTL5.4 Partial case items in full case statement: used | not used Multiple clocks in the design: yes | no

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■

Design ambiguity:
❑ ❑

Duplicate module definition: yes | no Black box due to undefined cells: yes | no

■

Compare results: FAIL | ABORT | INCOMPLETE | EQ | NOT_COMPARED
❑ ❑ ❑ ❑

Number of EQ compare points: Number of NON-EQ compare points: Number of Aborted compare points: Number of Uncompared compare points:

Parameters
-Verbose -Summary Prints out each category and the count of violations. Prints all items for each category and the violated items are marked with an asterisk (*).

Related Command
COMPARE

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RESET
RESET (Setup / LEC Mode)

Resets the system to the initial state. All existing designs and libraries are deleted, and all previously issued commands are cancelled.

Related Commands
RESET HIER_COMPARE RESULT EXIT

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RESET ABSTRACT MODEL
REset ABSTract Model [-ALL | -MODule ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Note: This requires a Conformal GXL license. Resets the abstraction conditions that you set using the SET ABSTRACT MODEL command.

Parameters
-All Resets abstraction conditions for all modules.

-MODule Resets abstraction conditions for the specified modules. -Both -Golden -Revised Resets abstraction conditions for both the Golden and Revised designs. This is the default. Resets abstraction conditions for the Golden design. Resets abstraction conditions for the Revised design.

Related Commands
ABSTRACT LOGIC REPORT ABSTRACT MODEL SET ABSTRACT MODEL

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RESET HIER_COMPARE RESULT
RESet HIer_compare Result (Setup / LEC Mode)

Resets the results of the hierarchical comparison. It is useful when you do multiple hierarchical compare runs and you wish to display the results of each hierarchical compare separately.

Related Commands
RUN HIER_COMPARE REPORT HIER_COMPARE RESULT RESET SAVE HIER_COMPARE RESULT WRITE HIER_COMPARE DOFILE

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RESOLVE
RESolve [-All] [-Golden | -Revised] (Setup Mode)

Note: This requires a Conformal GXL license. Ungroups a module in the Golden or Revised design hierarchy. Resolving or ungrouping is the process of eliminating a module and promoting its content up one level of the hierarchy.

Parameters -All -Golden -Revised Resolves hierarchy for the specified module. Resolves the specified module within all hierarchies of the specified design. Resolves hierarchy in the Golden design. This is the default. Resolves hierarchy in the Revised design.

Related Commands
ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN

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RESTORE SESSION
REStore SEssion (Setup / LEC Mode)

Restores a session you previously initiated and saved using the SAVE SESSION command. Before entering this command, Conformal must be in its initial state. Therefore, you must either use the RESET command, or exit Conformal and restart it. Important You must run this restarted session on the same platform and same Conformal version.

Parameters Restores the specified session.

Related Commands

INFO SESSION RESET SAVE SESSION

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RUN HIER_COMPARE
RUN HIer_compare [-ROOT_module ] [-DYNamic_hierarchy | -NODYNamic_hierarchy] [-NOREStart | -REStart] [-ANALYZE_abort] [-RETIMED_modules [-TOP | -NOTOP]] [-BREAK_NONEQ] [-BREAK_ABORT] [-ANALYZE_BOUNDARY_conditions | -NOANALYZE_BOUNDARY_conditions] [-VERBOSE] [-REStart] (Setup Mode)

Note: This requires a Conformal XL license. Runs dynamic hierarchical comparison. This command on completion produces one of the following three statuses:
■ ■ ■

Equivalent—all the compared modules are equivalent. Non-Equivalent—at least one of the compared module is non-equivalent. Inconclusive—indicates one of the following conditions:
❑ ❑ ❑

at least one of the compared module has abort points at least one module is not-compared (for example, due to running the add module attribute -compare_effort none command) at least one module has incomplete compare result (for example, due to extra primary outputs)

Note: When the status is Inconclusive the number of abort modules, not-compared modules, or modules that have incomplete compare result are reported.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference For more information, see Dynamic Hierarchical Comparison in the Encounter Conformal Equivalence Checking User Guide. Specifies the name of the hierarchical dofile that was generated with the WRITE HIER_COMPARE DOFILE command. Note: Cadence does not recommend manually editing or modifying this hierarchical dofile prior to running the RUN HIER_COMPARE command. This might lead to unexpected results. If you want to edit or modify the hierarchical dofile, use the static hierarchical comparison (dofile hier.do). -ROOT_module Uses the specified modules as the root modules. This is similar to the -Module option with the WRITE HIER_COMPARE DOFILE command without having to the regenerate the dofile. -DYNamic_hierarchy Auto-flattens the submodules to propagate any design errors to the top level. The flattened modules are merged to the next level in the hierarchy and compared at that level. This is the default. -NODYNamic_hierarchy Runs static hierarchical comparison without auto-flattening the submodules. Note: Do not use this option if the hierarchical dofile is generated using the WRITE HIER_COMPARE DOFILE -run_hier_compare command. -NOREStart Continues an interrupted session, preserving the previous compare results. This is the default. You can interrupt dynamic hierarchical comparison by pressing Ctrl-c. -REStart -ANALYZE_abort Deletes the previous comparison results. Inserts the ANALYZE ABORT -compare command into each uncompared and aborted module’s compare script.

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-RETIMED_modules [-TOP | -NOTOP] Compares and blackboxes the submodules with the PIPELINE_Retime attribute. The PIPELINE_Retime attribute can be attached to a module using the ADD MODULE ATTRIBUTE command. For this option to work correctly, modules with PIPELINE_Retime attribute should exist in the hierarchical dofile script. -TOP runs the comparison of the top module such that submodules without the PIPELINE_Retime attribute are fully flattened. This is the default for -RETIMED_module. -NOTOP specifies that comparison stops after the modules with the PIPELINE_Retime attribute have been compared and blackboxed. The hierarchical result is reported as ‘Inconclusive’ because the entire design is not compared. -BREAK_NONEQ The comparison stops when it encounters a non-equivalent module. To continue comparing from the next module in the hierarchy, use the RUN HIER_COMPARE command. The comparison stops when it encounters an abort module. To continue comparing from the next module in the hierarchy, run the RUN HIER_COMPARE command.

-BREAK_ABORT

-ANALYZE_BOUNDARY_conditions Reduces the number of flattened modules by resolving boundary constraints. This is the default. -NOANALYZE_BOUNDARY_conditions Does not perform resolution on boundary constraints. Note: Do not use this option if the hierarchical dofile is generated using the WRITE HIER_COMPARE DOFILE -run_hier_compare command. -VERBOSE -REStart Lists all the hierarchical constraints and additional information. Deletes the previous comparison results. Note: This option deletes all existing pin-based renaming. To add any pin-based renaming rule, insert them into the specific modules.

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Examples
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The following command uses the hier.do dofile for hierarchical comparison: run hier_compare hier.do

If the previous comparison run of the hier.do dofile resulted in three aborted modules, you can run a second comparison using the following command: run hier_compare hier.do -analyze_abort

This command only operates on aborted modules from the previous run, and automatically runs the ANALYZE ABORT -compare command after the default COMPARE command.
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The following command uses m4 as the root module for both the Golden and Revised designs, deleting the previous comparison results: run hier_compare hrcmod.do -root_module m4 m4 -restart

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The following command runs hierarchical comparison on modules with the PIPELINE_Retime attribute attached: run hier_compare hier.do -retimed_modules

Related Commands
ANALYZE ABORT COMPARE REPORT HIER_COMPARE RESULT RESET HIER_COMPARE RESULT SAVE HIER_COMPARE RESULT WRITE HIER_COMPARE DOFILE

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RUN PARALLEL COMPARE
RUN PArallel Compare [-NONEQ_Stop ] [-ABORT_Stop ] [-NONEQ_Print] [-ABORT_Print] [-GATE_TO_GATE] [-TEST] [-SUBMIT_OPTIONs ] (LEC Mode)

Note: This requires a Conformal XL license. Runs equivalency checking comparison between the Golden and Revised designs on the added compared points using parallel processing. During the comparison, the Conformal software displays following information:
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A progress percentile number that shows the completion rate A running count that shows the number of key points that have been compared along with the total number of non-equivalent key points

Parameters
-NONEQ_Stop Stops the comparison after finding the specified number of non-equivalent points. -ABORT_Stop Stops the comparison after finding the specified number of abort points. -NONEQ_Print -ABORT_Print -GATE_TO_GATE -TEST -SUBMIT_OPTIONs Displays the non-equivalent points as they are found. Displays the abort points as they are found. Enables an algorithm that might improve the run time of large gate-to-gate netlist comparisons. Launches qualification run to test if the environment is suitable for parallel processing. Specifies the options which will replace the keyword in the submit command line (see the SET PARALLEL OPTION -SUBMIT_COMMAND_LINE command).
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Examples
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The following command tests if the environment is suitable for parallel processing: run parallel compare -test

The following command will start the equivalency comparison using parallel processing with the parameters specified by the previously run SET PARALLEL OPTION command.: run parallel compare

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The following commands run the first parallel job in queue q1, and the second parallel run in queue q2. run parallel compare -submit_options "-q q1" run parallel compare -submit_options "-q q2"

Related Commands
COMPARE SET PARALLEL OPTION

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RUN PARTITION_COMPARE
RUN PArtition_compare [-Keypoint ] [-Number ] [-VERBOSE] [-THREADS [, ]] (LEC Mode)

Note: This requires a Conformal XL license. Runs comparisons with functional partitioning. You can specify partitioned key points in the Golden design and the number of key points for a partition. If no key points are specified, this command will automatically choose appropriate key points for the partition. Note: You do not need to switch to Setup mode to flatten the netlist in each partition iteration. With the constants assigned on the selected key points, comparison can become easier in each partition iteration. For example, when abort points are encountered in comparison, you can run this command to do functional partitioning for the abort points.

-Keypoint Specifies the partition key point in the Golden design. The key point can be specified by gate instance pathname or gate ID. If no key points are specified, this command will automatically choose appropriate key points for the partition. -Number Specifies the number of key points for a partition. The maximum number of compare iterations is the base-2 exponent of the partitioned key point number. The default partitioned key point number is 8. Provides additional information in the functional partition.

-VERBOSE

-THREADS [, ] Specifies the number of threads that can be executed at the same time.

Related Commands
COMPARE

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SAVE DOFILE
SAVe DOfile [-Replace] (Setup / LEC Mode)

Saves the commands entered during the current session to a file. Use the saved dofile later as a batch file to repeat the Conformal session. When running a Conformal session from a dofile, this command does not save individual commands included in a separate dofile (that is, Conformal saves the manually entered commands, which can include a dofile command). Note: If the filename you specify already exists, you must use either the -replace or -append option. Writes the dofile to the specified file. Replaces the contents of the specified preexisting file.

-Replace

Related Commands
DOFILE SET COMMAND PROFILE SET LOG FILE

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SAVE HIER_COMPARE RESULT
SAVe HIer_compare Result (LEC Mode)

Saves the hierarchical comparison results of the module comparison. If the WRITE HIER_COMPARE DOFILE command is used, this command is placed after every module compared. After the hierarchical comparison of all modules is complete, use the REPORT HIER_COMPARE RESULT command to display the results of the hierarchical comparison.

Related Commands
REPORT HIER_COMPARE RESULT RESET HIER_COMPARE RESULT RUN HIER_COMPARE WRITE HIER_COMPARE DOFILE

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SAVE SESSION
SAVe SEssion [-REPlace] (Setup / LEC Mode)

Saves your session up to a current point and outputs the session file in gzip format. You can then restore the session later using the RESTORE SESSION command. You can use this command if priorities demand that another session preempt your session. Important When you use the RESTORE SESSION command, you must run the restarted session on the same platform and same Conformal version.

Parameters
-REPlace Replaces the existing session. If the session already exists, it will be overwritten and no backup copy will be created. By default, backup copies are created automatically. This option is useful if you want to save disk space and only need to save your session occasionally. Attaches this session name to the saved session.

Related Command

INFO SESSION RESTORE SESSION

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SEARCH
SEArch [-USage] [] ... (Setup / LEC Mode)

Searches the database of commands and parameters, and displays those commands that match all of the specified strings. Strings can be specified in any order; however, every specified string must match.

Parameters
-USage Displays the commands that have parameters that match the search string. This outputs the entire command syntax for each command. Displays commands that match the specified string. Displays commands that match additional specified strings.

...

Related Command
HELP

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SET ABSTRACT MODEL
SET ABSTract Model [-ALL |-MODule ] [-NOKEEPER2PUllup | -KEEPER2PUllup ] [-NOWEAKPULLUP | -WEAKPULLUP ] [-NOWEAKPULLDOWN | -WEAKPULLDOWN ] [-NOKEEPERSTate | -KEEPERSTate ] [-NODYNSTate | -DYNSTate ] [-NOPRE_CHARGE_KEEP_Clock | -PRE_CHARGE_KEEP_Clock ] [-NODOMINOLATch | -DOMINOLATch ] [-NOMEM_BL_EQualizer | -MEM_BL_EQualizer] [-NOBUF_AMP | -BUF_AMP] [-NOMULTICLOCKPRECHARGE | -MULTICLOCKPRECHARGE] [-REPHASE_BY_NAME_POSitive ] [-REPHASE_BY_NAME_NEGative ] [-TRANSFORM_PULSE_GENERATOR_ON] [-NOIGNORE_DLAT_CONTENTION | -IGNORE_DLAT_CONTENTION] [ | -RESTRICT_Patterns | -RESTRICT_Modules] [-Both | -Golden | -Revised ] (Setup Mode)

Note: This requires a Conformal GXL license. Specify certain conditions for abstracting transistor logic. Refer to the Encounter Conformal Equivalence Checking User Guide for additional information about using this command in the Conformal Custom flow.

Parameters
-ALL Abstracts transistor logic from all modules within the given defaults. This option is the default.

-MODule Abstracts transistor logic from the specified modules. -NOKEEPER2PUllup -KEEPER2PUllup -NOWEAKPULLUP -WEAKPULLUP Does not regard charge keepers as weak pull-up devices. This is the default. Regards charge keepers as weak pull-up devices. Does not regard devices that are tied to PMOS as weak devices. This is the default. Regards devices that are tied to PMOS as weak devices.

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-NOWEAKPULLDOWN -WEAKPULLDOWN -NOKEEPERSTate -KEEPERSTate -NODYNSTate -DYNSTate

Does not regard devices that are tied to NMOS as weak devices. This is the default. Regards devices that are tied to NMOS as weak devices. Does not regard charge keepers as latches. This is the default. Regards charge keepers as latches. Does not regard tristate table nets as latches. This is the default. Regards tristatetable nets as latches.

-NOPRE_CHARGE_KEEP_Clock In domino logic, does not regard pre-charge clocks as part of the logic function. This is the default. -PRE_CHARGE_KEEP_Clock For domino logic, regards pre-charge clocks as part of the logic function. This option includes the defined pre-charge clock in the abstracted logic function (the default behavior removes the defined pre-charge clock from the abstracted logic). This is indicated when you define a precharge clock with one of the following commands: add net attribute CLOCK0 | CLOCK1 add clock 0 | 1

When you use -pre_charge_keep_clock, the resulting logic is equivalent to RTL that explicitly models the pre-charge condition, rather than RTL that models only the evaluate function. In the latter, the output function is not defined during pre-charging. -NODOMINOLATch -DOMINOLATch -NOMEM_BL_EQualizer Does not handle bit-line pre-charge, and equalization. This is the default. Does not abstract pre-charge logic functions as a latch. This is the default. Abstracts pre-charge logic functions as a latch. This assumes that data input is stable in active clocks.

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-MEM_BL_EQualizer -NOBUF_AMP -BUF_AMP

Handles circuits that include bit-line pre-charge, and equalization. Does not handle buffered-type sense amplifiers, level shifters, pre-charge, and equalization. This is the default. Handles the following portions of a circuit: buffered-type sense amplifiers, level shifters, pre-charge, and equalization.

-NOMULTICLOCKPRECHARGE Does not propagate clocks through logic gates which have more than one clock input. This is the default. -MULTICLOCKPRECHARGE Propagates clocks through logic gates which have more than one clock input. -REPHASE_BY_NAME_POSitive Gives abstract logic a hint about the desired phase of state elements, such as D-latches and DFFs. When abstracting state elements, abstract logic will choose a phase for each state element, where specifies the net which will be driven by the ’Q’ pin, if possible. If this is not possible, then abstraction will try to choose a net for the ’Qn’ pin which has a name specified by the -REPHASE_BY_NAME_NEGative option. Note: The SET MAPPING METHOD command’s -phase option will allow mapping and comparison of state elements with different phases in the Golden and Revised designs. Consider running SET MAPPING METHOD -phase before using this option, as it requires less effort. -REPHASE_BY_NAME_NEGative Specifies the net which will be driven by the ’Qn’ pin, if possible. -TRANSFORM_PULSE_GENERATOR_ON Enables pulse transformation. -NOIGNORE_DLAT_CONTENTION Stops forming the D-Latch when contention on a net is detected. This is the default.

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-IGNORE_DLAT_CONTENTION Continues to form the D-Latch, even if contention on a net is detected. By default, the SET ABSTRACT MODEL command stops the execution of abstraction of latches and flip-flips (state elements) when a power to ground through a stack of active ON transistors is possible. Use this option to report the short and continue to abstract the state element. -RESTRICT_Patterns Restricts the pattern to the specified modules specified and restricts the specified modules to use only those patterns. Other unspecified modules can be abstracted using other patterns not associated with that or any other module. By default, the pattern and module linkage and abstraction uses only patterns for that module, but still can use that pattern and any pattern for modules that are not defined -RESTRICT_Modules -Both -Golden -Revised Restricts the pattern matching to the specified modules. Specifies abstraction conditions for both the Golden and Revised designs. This is the default. Specifies abstraction conditions for the Golden design. Specifies abstraction conditions for the Revised design.

Examples
Sample Dofile: read design test.v -golden set abstract model -keeper2pullup -weakpullup -golden report abstract model -golden abstract logic

Related Commands
ABSTRACT LOGIC ADD CLOCK ADD NET ATTRIBUTE

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT ABSTRACT MODEL REPORT PULSE GENERATOR RESET ABSTRACT MODEL SET PATTERN MATCH

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SET ANALYZE OPTION
SET ANalyze Option [-NOAUTO | -AUTO [-ANALYZE_SETUP | -NOANALYZE_SETUP] [-ANALYZE_ABORT | -NOANALYZE_ABORT] [-NOREPORT_MAP | -REPORT_MAP] [-PHASE_MAPPING | -NOPHASE_MAPPING] [-SEQ_MERGE | -NOSEQ_MERGE] [-EFFORT ] ] (Setup Mode)

Note: This requires a Conformal XL license. Automatically determines the best place to run the ANALYZE SETUP command. In addition, the Conformal software automatically runs the ANALYZE ABORT command whenever the comparison returns abort points but no non-equivalent points.

Parameters
-NOAUTO -AUTO -ANALYZE_SETUP -NOANALYZE_SETUP -ANALYZE_ABORT -NOANALYZE_ABORT -NOREPORT_MAP -REPORT_MAP -PHASE_MAPPING -NOPHASE_MAPPING -SEQ_MERGE Disables automatic analysis. This is the default. Enables automatic analysis. Enables automatic setup analysis. This is the default when running this command with the -AUTO option. Disables automatic setup analysis. Enables automatic abort point analysis. This is the default. Disables automatic abort point analysis. Does not report the mapping results after completing automatic analysis. This is the default. Reports the mapping results after completing automatic analysis. Enables phase adjustment for DFF/D-LATCH mapping during automatic analysis. This is the default. Disables phase adjustment for DFF/D-LATCH mapping during automatic analysis. Enables the sequential merge modeling of DFF/D-LATCH during automatic analysis. This is the default.

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-NOSEQ_MERGE

Disables the sequential merge modeling of DFF/D-LATCH during automatic analysis.

-EFFORT Specifies the effort level for automatic setup. Medium is the default.

Related Command
ANALYZE ABORT ANALYZE SETUP

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SET_ATTR INPUT_PRAGMA_KEYWORD
SET_ATtr INPUT_PRAGMA_Keyword (Setup Mode)

Specifies a keyword that the Conformal software must consider as an input pragma when it encounters it as the first word in a Verilog or VHDL source comment. A pragma is a comment in the Verilog or VHDL source and is set off from ordinary comments by the pragma keyword. The pragma keyword is the first word listed in a pragma, and it notifies the Conformal software that the remainder of the comment is a command and not a comment. Changing this keyword allows you to set up compatibility with other tools.

Parameters string Specifies the name of the keyword for a tool vendor. Default: pragma, synthesis, synopsys, cadence, ambit, conformal

Examples
Sample Dofile: set_attr input_pragma_keyword rtl set synthesis_off_command turn_off set synthesis_on_command turn_on

After running these three commands, the Conformal and VHDL parsers will recognize the pragmas in the VHDL and Verilog Source files. In a VHDL file, the code between -- rtl turn_off and -- rtl turn_on will not be translated. In a Verilog file, the code between // rtl turn_off and // rtl turn_on will not be translated.

Related Commands
SET SYNTHESIS_OFF_COMMAND

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SET CASE SENSITIVITY
SET CAse Sensitivity (Setup Mode)

Specifies whether names you enter are case sensitive. The system default is no case sensitivity for both the Golden and Revised designs. Execute this command before READ LIBRARY and READ DESIGN. Use the REPORT ENVIRONMENT command to display the case sensitivity setting.

Parameters
ON OFf Names that are entered are case sensitive. Names that are entered are not case sensitive. This is the system default.

Related Command
REPORT ENVIRONMENT

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SET COMMAND PROFILE
SET COmmand PRofile [OFF | ON] (Setup / LEC Mode)

Starts or stops recording a profile of commands executed in Conformal. This command records the order of command execution and the memory use. The profile includes commands used in the GUI mode. Use the REPORT COMMAND PROFILE command to view the profile.

Parameters
OFF ON Stops tracking executed commands. This is the default. Starts tracking executed commands.

Related Commands
REPORT COMMAND PROFILE SET LOG FILE

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SET COMPARE EFFORT
SET COmpare Effort (Setup / LEC Mode)

Specifies the amount of effort equivalency checking applies to the key points comparison. If you know your designs have many complex key points, increase the effort level. However, when you raise the effort level, you also increase the amount of time involved in checking. Hence, you increase the total CPU time. Use the REPORT ENVIRONMENT command to display the compare effort setting. The system default is set to low compare effort.

Parameters
Low Medium High Auto COMPlete Applies minimal effort to equivalency checking for each gate. This is the default. Applies greater effort to equivalency checking for each gate. Applies the maximum effort to equivalency checking for each gate. Starts with low effort and automatically increases the compare effort when abort points are present in the design. Performs equivalency checking for each gate until the comparison results in an EQ or Non-EQ result. With this option, the tool never returns an abort (in other words, if EQ or Non-EQ is not returned, the compare will go on indefinitely).

Related Commands
COMPARE REPORT ENVIRONMENT

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SET COMPARE OPTIONS
SET COmpare Options [-GENLATCH | -NOGENLATCH] [-NOALLGENLATCH | -ALLGENLATCH] [-VERIFY_Disabled_ports] [-THREADS [,] (Setup / LEC Mode)

Turns on options to the comparison process.

Parameters
-GENLATCH Compares latches as generic latches by analyzing all logic cones simultaneously. The software automatically determines which latches are to be compared as generic latch, and the rest are compared by individual logic cones. This is the default. With this option, you can compare latches that are truly functionally equivalent, even though the logic cones of the separate input pins are not. -NOGENLATCH -NOALLGENLATCH Specifies that no latch is compared as a generic latch. All latches are compared by individual logic cones. Does not compare all latches as generic latches. This is the default. This option has no effect when using -NOGENLATCH. Note: The input cones compared are set cones, reset cones, clock cones, and data cones. -ALLGENLATCH Compares all latches as generic latches. This option has no effect when using -NOGENLATCH. -VERIFY_Disabled_ports Compares data cones even if their clocks are disabled. By default, a data cone will not be compared if its corresponding clock port is tied to a constant (for DFFs) or to zero (for latches). Note: You should use this command option before running the first COMPARE command. If you use this after running COMPARE, this option has no effect.

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-THREADS [,] Specifies the number of compare threads for the COMPARE command. This supersedes the SET PARALLEL OPTION -threads setting.

Related Command
COMPARE SET PARALLEL OPTION

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SET CPU LIMIT
SET CPu Limit [-NOKill] [-WALLTIME] [-COMMAND ] (Setup / LEC Mode)

Specifies the time limit for the compare effort. The system default is 525,600 minutes. Set the time limit for minutes, hours, or days. Use the REPORT ENVIRONMENT command to display the setting for the CPU time limit. Note: When the Conformal software reaches the specified CPU limit, it stops all processing and exits.

Parameters -Days -Hours -Minutes -NOKill -WALLTIME Specifies a positive integer for the CPU time limit. Specifies that the CPU time limit refers to days. Specifies that the CPU time limit refers to hours. Specifies that the CPU time limit refers to minutes. Prevents the software from exiting. This returns the command prompt. Specifies that the time limit is in real clock time.

-COMMAND Specifies a Conformal command to run before exiting the software.

Examples
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The following commands show an example of using the SET CPU LIMIT command with and without the -WALLTIME option. The time is 11:00 am and you start two Conformal sessions on the same machine, executing the same dofile, that will run more than 20 minutes. You set the time limit for session 1 in real clock time with the following command: set cpu limit 10 -minutes -walltime

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Encounter Conformal Equivalence Checking Reference Manual Command Reference You set the time for session 2 at the same limit but without using the real clock time with the following command: set cpu limit 10 -minutes.

At 11:10, session 1 will terminate because the real clock time has elapsed 10 minutes. However, session 2 might not terminate because the real time it consumed during this 10 minutes is less than 10 minutes if some of the time is consumed by other processes running on the machine.
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The following command specifies that before the software exits after reaching 1 minute CPU time limit, it will run the USAGE command. set cpu limit 1 -minute -command usage

Related Command
REPORT ENVIRONMENT

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SET DATAPATH OPTION
SET DAtapath Option [-NOAUTO | -AUTO [-MODULE [-RESOURCEFILE ] [-ISOLATE_ABORT_MODULE] ] ] [-NOWORDLEVEL | -WORDLEVEL] [-MERGE | -NOMERGE] [-NOADDERTREE | -ADDERTREE] [-NOSHARE | -SHARE] [-EFFort ] [-Verbose] (Setup / LEC Mode)

Specifies whether Conformal automatically analyzes datapaths on switching from Setup to LEC mode and whether to apply operator merging. The results of the analysis enable Conformal Ultra to automatically resolve multipliers, operator merging, and resource sharing problems. Note: You cannot run datapath analysis without first mapping the Revised design keypoints to the Golden design keypoints.

Parameters
-NOAUTO -AUTO Does not automatically analyze datapaths when switching from Setup to LEC mode. This is the default. Automatically analyzes datapaths when switching from Setup to LEC mode. This also performs additional carry-save adder (CSA) analysis. Automatically applies analysis on the datapath modules in the Revised design netlist. This option must be used with -AUTO.

-MODULE

-RESOURCEFILE Specifies the resource filename to analyze the datapath modules. -ISOLATE_ABORT_MODULE Isolates the module that is aborted during module-based datapath (MDP) analysis. The module’s gate-level netlist will be abstracted into RTL for comparison at the top module. -NOWORDLEVEL Does not apply word-level datapath analysis. This is the default.
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-WORDLEVEL

Applies word-level datapath analysis. This helps analyze advanced word-level optimizations on designs with complex adder-tree clustering, product-of-sum, XOR-tree, or datapath with control logics or constants. You can use this option only if you use the -auto option. Automatically applies the operator merging technique when switching from Setup to LEC mode. This is the default. Does not automatically apply the operator merging technique when switching from Setup to LEC mode. Does not automatically add parentheses to the input operands of adder trees when switching from Setup to LEC mode. This is the default. Automatically adds parentheses to the input operands of adder trees when switching from Setup to LEC mode. Does not apply the resource sharing technique. This is the default. Analyzes the design for datapath resource sharing.

-MERGE -NOMERGE -NOADDERTREE

-ADDERTREE -NOSHARE -SHARE

-EFFort Specifies the effort level. Choose MEDium (the default), or HIgh to help provide better analysis of some multipliers, but can increase the analysis runtime. -Verbose Provides additional information.

Examples
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The following command applies module-based datapath analysis followed by the operator-level datapath analysis when switching from Setup to LEC mode: set datapath option -auto -module -verbose set system mode lec

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The following command applies operator-level datapath analysis when switching from Setup to LEC mode: set datapath option -auto set system mode lec

Related Commands
ANALYZE DATAPATH
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SET DIRECTIVE
SET DIrective [ [synthesis | ] ] [-file ] (Setup Mode)

Specifies whether to enable or disable the effects of the specified synthesis directives when reading in a Verilog or VHDL file. If you enter this command and do not specify any directives, this command enables or disables all of the directive effects. The system default enables all directives. Thus, if you want Conformal to enable all directives, no action is necessary. Execute this command before READ LIBRARY and READ DESIGN. For each disabled directive used in the HDL source code, Conformal responds as follows:
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If the directive is supported but disabled, Conformal returns a message stating the directive is disabled. If the directive is unsupported and disabled, Conformal returns a message stating that the directive is unsupported.

See Conformal Directive Examples in the Encounter Conformal Equivalence Checking User Guide for short descriptions and examples of supported Conformal directives.

Parameters
ON OFf synthesis Enables the specified directives. (The initial system default enables all directives.) Disables the specified directives. If you do not specify directives, all directives are disabled. Enables (or disable) the specified Synplicity synthesis directives. Enables or disable the specified synthesis directives when they are used with the specified prefix. Supported vendors are ambit, cadence, conformal, pragma, quickturn, synopsys, and synthesis.

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Enables or disables the specified synthesis directives. If you do not specify any directives, all directives are enabled or disabled, accordingly. See Supported Directives in the Encounter Conformal Equivalence Checking User Guide for the list of synthesis directives.

-File

Enables (or disables) a list of directives that are specified in a RTL file. This accepts wildcards. for the list of supported directives.

Examples
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The Conformal, Synopsys, and Ambit directives are enabled by default. The Quickturn directives are disabled by default. To recognize the Quickturn directives, you must first turn on all of the directives for Quickturn using the following command: set directive on quickturn

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When you employ the SET DIRECTIVE command and you do not specify a directive, the command applies to all directives. In the following example, the objective is to enable only the parallel_case directive. To do so, first disable all directives, then enable the specified directive (parallel_case).
//disable all directives set directive off //enable parallel_case set directive on parallel_case

■

In the following example, the objective is to disable all Synopsys directives (synopsys translate_off, synopsys translate_on, synopsys full_case ...).
//disable all synopsys directives set directive off synopsys

■

In the following example, the objective is to disable synopsys translate_off and synopsys translate_on. This command has no effect on conformal translate_off and conformal translate_on.
//disable synopsys translate_off and synopsys translate_on set directive off synopsys translate_off translate_on

■

In the following examples, we have 2 RTL files: test.v and test1.v.
❑

In the following command, the synthesis directive parallel_case is on (enabled) in file test.v: set directive on parallel_case -file test.v

❑

In the following command, the synthesis directive parallel_case is on (enabled) in file test.v and test1.v: set directive on parallel_case -file *.v

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Related Commands
READ DESIGN READ LIBRARY

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SET DOFILE ABORT
SET DOfile Abort (Setup / LEC Mode)

Specifies how Conformal handles the dofile when an error message occurs.
■ ■ ■

If the dofile abort handling is set to On, the dofile terminates when an error message occurs. This is the default. If the dofile abort handling is set to Off, the dofile continues even if an error message occurs. If the dofile abort handling is set to Exit, the session exits when an error message occurs.

Parameters
ON OFf Exit Terminates the dofile if an error message occurs. This is the default. Continues the dofile even if an error message occurs. Exits the session if an error message occurs.

Related Commands
BREAK CONTINUE DOFILE

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SET DW DEFINITION
SET DW Definition (Setup Mode)

Specifies the DesignWare (DW*) modules’ definition that the Conformal software will use. By default, the software specifies using the user-defined DW* modules first. If you are using the built-in directory (where the DW* files are located), you can set the path with the following command: setenv DW_DEFINE

By default, the Conformal software uses the following path:
/share/cfm/lec/library/verilog/dw

Parameters
-USER_FIRST [-BBOX] Specifies using the user-defined DW* modules first. Resolved referenced but undefined DW* modules use built-in modules. This is the software default. Use the -BBOX option to specify that when attempting to resolve blackboxed DW* modules, it will use built-in modules. -USER_ONLY -BUILTIN_only -DW_MULt_div Specifies using user-defined DW* modules only. Specifies using built-in DW* modules only and skips user-defined DW* modules. Specifies using user-defined DW* modules only except DW_MULT* and DW_DIV* modules.

Example
The following shows an example of the RTL code in a file absval.v. module sample( A, ABSVAL ); input [7 : 0] A; output [7 : 0] ABSVAL; DW01_absval #(width) U1 ( .A(A), .ABSVAL(ABSVAL) ); endmodule

The command to read in the design is:

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Encounter Conformal Equivalence Checking Reference Manual Command Reference read design absval.v

The DW01_absval.v file is automatically read in from the built-in directory because there is no definition provided.

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SET EXIT CODE
SET EXit Code [-CLEAR] [-VERBOSE] [ | -INTERNAL_ERROR | -NOINTERNAL_ERROR] [ | -COMMAND_ERROR | -NOCOMMAND_ERROR] (Setup / LEC Mode)

Controls and displays the exit code for the Conformal session. This command is useful when running a complex flow, such as hierarchical comparison and iterative comparison.

Parameters
-CLEAR -VERBOSE -INTERNAL_ERROR -NOINTERNAL_ERROR -COMMAND_ERROR -NOCOMMAND_ERROR Clears the exit code to only reflect most current running status. Displays a table listing the status codes. Sets the internal error bit. Clears the internal error bit. Sets the command error bit. Clears the command error bit.

Examples
■ ■

The following command displays current exit code: set exit code

If a failing comparison was followed by a passing comparison (after fixing some constraints), bit 4 in the exit code is still non-zero. However, the following command clears the exit code and displays a table listing the status codes and decimal exit code: set exit code -clear -verbose

■

The following command set command error bit to 1: set exit code -command_error

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SET FLATTEN MODEL
SET FLatten Model [-Map | -NOMap] [-NOPin_keep | -PIN_keep] [-NOLATCH_Fold | -LATCH_Fold] [-NOLATCH_Transparent | -LATCH_Transparent] [-NOLATCH_FOLD_Master | -LATCH_FOLD_Master] [-NOLATCH_MERGE_PORT | -LATCH_MERGE_PORT] [-NOALL_SEQ_Merge | -ALL_SEQ_Merge] [-NOSEQ_Merge | -SEQ_Merge] [-NOALL_INV_SEQ_Merge | -ALL_INV_SEQ_Merge] [-NOSEQ_Redundant | -SEQ_Redundant] [-NOLIB_SEQ_Redundant | -LIB_SEQ_Redundant] [-NOSEQ_SIMPLIFY_Clock | -SEQ_SIMPLIFY_Clock] [-NOSEQ_Constant | -SEQ_Constant] [-NOGATED_Clock | -GATED_Clock] [-DFF_TO_DLAT_ZERO | -NODFF_TO_DLAT_ZERO] [-NODFF_TO_DLAT_ONE_CLOCK | -DFF_TO_DLAT_ONE_CLOCK] [-DFF_TO_DLAT_FEEDBACK | -NODFF_TO_DLAT_FEEDBACK] [-NOLOOP_AS_DLAT | -LOOP_AS_DLAT] [-SEQ_CONSTANT_FEEDBACK | -NOSEQ_CONSTANT_FEEDBACK] [-SEQ_CONSTANT_X_TO < 0 | 1 >] [-AUTO_MODELING | -NOAUTO_MODELING] [-OUTPUT_Z | -NOOUTPUT_Z] [-NOBBOX_MERGE | -BBOX_MERGE] [-SHOW_MESSAGE_NAME] [-NOKEEP_IGnored_PO | -KEEP_IGnored_PO] [-CUT_REMOVE_REDUNDANT] [-NOECO | -ECO] [-NOBREAK_IOPAD_PATH | -BREAK_IOPAD_PATH] [-IN_TO_INOUT | -NOIN_TO_INOUT] [-OUT_TO_INOUT | -NOOUT_TO_INOUT] (Setup Mode)

Specifies certain conditions for the flattened model. Refer to the arguments table for a complete list of options and their effects. Use the REPORT ENVIRONMENT command to display the settings for the flattened model, or you can run this command without any options (in either Setup or LEC mode) to report a complete list of flattened modeling options.

Parameters
-Map Does automatic key point mapping. This is the default.
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-NOMap -NOPin_keep -PIN_keep

Skips the automatic key point mapping when the system mode is changed from Setup to LEC. In an effort to reduce memory use, Conformal does not keep certain gate pins. This is the default. Keeps all gate pin information for gate reporting. Use this option when reporting gate information at the design level. It will increase memory use. Does not fold a master-slave latch into a D flip-flop. This is the default. Folds a master-slave latch into a D flip-flop. Does not treat latches that are always enabled as transparent. This is the default. Converts D-Latches into buffers if the clock ports of the D-latches are always enabled. Does not convert two latches in an LSSD format into a DFF gate when the reset signal is connected only to the master. Converts two latches in an LSSD format into a DFF gate when the reset signal is connected only to the master. Does not collapse multi-port latches into a single-port latch. This is the default. Collapses multi-port latches into a single-port latch. Does not merge state elements that are functionally equivalent. This is the default. Merges state elements that are functionally equivalent. Does not merge sequential elements in the clock cone of a DFF or D-latch. This is the default. Merges common groups of sequential elements into one sequential element in the clock cone of a DFF or D-latch. Does not merge state elements that are functionally inverted. This is the default. Merges state elements that are functionally inverted.

-NOLatch_fold -Latch_fold -NOLATCH_Transparent -LATCH_Transparent -NOLATCH_FOLD_Master

-LATCH_FOLD_Master

-NOLATCH_Merge_port -LATCH_Merge_port -NOALL_SEQ_Merge -ALL_SEQ_Merge -NOSEQ_Merge -SEQ_Merge

-NOALL_INV_SEQ_Merge -ALL_INV_SEQ_Merge

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-NOSEQ_Redundant -SEQ_Redundant -NOLIB_SEQ_Redundant -LIB_SEQ_Redundant -NOSEQ_SIMPLIFY_Clock

Does not remove redundant fan-out gates from DFFs and DLATs. This is the default. Removes redundant fan-out gates from DFFs and D-Latches. Retains redundant fan-out gates from DFFs and DLATs in the Library. This is the default. Removes redundant fan-out gates from DFFs and DLATs in the Library. Does not fold master and slave latches when there is a redundant interaction between the clock and reset signals. This is the default. Folds master and slave latches when there is a redundant interaction between the clock and reset signals. Does not propagate constant data through latches and registers. This is the default. Propagates constant data through latches and registers. Does not remodel gated-clock sequential instances. This is the default. Remodels the gated-clock logic of the clock port of a DFF. If the clock pin cannot be automatically determined, use the ADD CLOCK command to define the clock pin. Converts a DFF to a DLAT if the clock port is zero. This is the default. Does not convert a DFF to a DLAT if the clock port is zero. Does not convert a DFF to a DLAT if the clock port value is 1. This is the default. Converts a DFF to a DLAT if the clock port value is 1. Note: The clock to DLAT is tied to 0.

-SEQ_SIMPLIFY_Clock

-NOSEQ_Constant -SEQ_Constant -NOGATED_Clock -GATED_Clock

-DFF_TO_DLAT_ZERO -NODFF_TO_DLAT_ZERO -NODFF_TO_DLAT_ONE_CLOCK -DFF_TO_DLAT_ONE_CLOCK

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-DFF_TO_DLAT_FEEDBACK -NODFF_TO_DLAT_FEEDBACK -NOLOOP_AS_DLAT -LOOP_AS_DLAT -SEQ_CONSTANT_FEEDBACK

Converts a DFF to a DLAT if the Q output feeds back to the D input. This is the default. Does not convert a DFF to a DLAT if the Q output has feedbacks to the D input. Does not use a DLAT to model a combinational loop. This is the default. Uses a DLAT to model a combinational loop. Remodels registers that also have feedback to constants. Use this option with -seq_constant. This is the default. Does not remodel registers that also have feedback to constants. Use this option with -seq_constant. Optimizes a flop to a constant value (either zero or one) when the flop is always in a don’t care (X) state. Use this with the -seq_constant switch. 0: Optimizes a flop to a constant zero. 1: Optimizes a flop to a constant one.

-NOSEQ_CONSTANT_FEEDBACK -SEQ_CONSTANT_X_TO

-AUTO_MODELING

Enables selective modeling for designs that can be mapped mostly by name. This option applies only to sequential constants. This is the default. Disables the auto modeling feature. Checks for floating conditions at top-level output ports and inputs to blackboxes. This is the default. Does not check for floating conditions at top-level output ports and inputs to blackboxes. Does not perform automatic blackbox merging. This is the default. Performs automatic blackbox merging. Prints message names to the log as they occur. Does not retain the ignored primary outputs (added with the ADD IGNORED OUTPUTS command) in the flattened netlist. This is the default.

-NOAUTO_MODELING -OUTPUT_Z -NOOUTPUT_Z -NOBBOX_MERGE -BBOX_MERGE -SHOW_MESSAGE_NAME -NOKEEP_IGnored_PO

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-KEEP_IGnored_PO

Retains the ignored primary outputs (added with the ADD IGNORED OUTPUTS command) in the flattened netlist. These ignored primary outputs appear as unreachable unmapped points in the design. Removes as many redundant cuts as possible. Use this option if you suspect that the software inserted more cuts than necessary. Does not preserve extra circuit information for model flattening. This is the default. Preserves extra circuit information during model flattening for subsequent ANALYZE ECO command runs. Does not partition the I/O pad path. This is the default. Partitions the I/O pad path (the input side of the logic block and the output side of the logic block). By default, I/O pads combine the input side of the logic block to the output side of the logic block. Using this option, the input side of the logic block and the output side of the logic block are handled separately. This could be helpful for abort resolution.

-CUT_REMOVE_REDUNDANT

-NOECO -ECO

-NOBREAK_IOPAD_PATH -BREAK_IOPAD_PATH

-IN_TO_INOUT

Models sub-module input ports as inout ports. In other words, all sub-module input ports are treated as bi-directional. This is the default. Does not model sub-module input ports as inout ports. Models sub-module output ports as inout ports. In other words, all sub-module output ports are treated as bi-directional. This is the default. Does not model submodule ouput ports as inout ports.

-NOIN_TO_INOUT -OUT_TO_INOUT

-NOOUT_TO_INOUT

Examples set flatten model -latch_fold set flatten model -pin set flatten model -latch_transparent set flatten model -nomap set flatten model -seq_merge

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Encounter Conformal Equivalence Checking Reference Manual Command Reference set flatten model -nodff_to_dlat_zero set flatten model -seq_constant -noseq_constant_feedback set flatten model -gated_clock set flatten model -seq_redundant set flatten model -all_seq_merge set flatten model -nodff_to_dlat_feedback

Related Commands
READ MAPPED POINTS REMODEL REPORT ENVIRONMENT REPORT MESSAGES SET GATE REPORT

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SET FPGA TECHNOLOGY
SET FPga Technology [NONE | VIRTEX | VIRTEX2] (Setup Mode)

Note: This command is an FPGA command. Turns on FPGA-specific processing. It is included in the fpgaR2G.do dofile.

Parameters
NONE VIRTEX VIRTEX2 Does not turn on any FPGA-specific processing. This is the default. Turns on the Xilinx Virtex processing. Turns on Virtex2 processing.

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SET GATE REPORT
SET GAte Report [-PRImitive | -DESign] [-DYNamic | -NODYNamic] [-FUNction | -STRucture] (Setup / LEC Mode)

Specifies the detail level of gate reports in the Conformal gate information display. Gate report features include the following:
■ ■ ■

Returns information at the design or primitive level Displays the dynamic constraints Displays the fanin cone of the zero/one gates

By default, this command reports gate information at the primitive level, displays the dynamic constraints, and does not display the fanin cone of the zero or one gates. Use the REPORT ENVIRONMENT command to display the gate report level settings. Note: If the gate report is set to Design, you must use the SET FLATTEN MODEL command with the -pin_keep option in the Setup system mode. The gate information is reported in the LEC system mode.

Parameters
-PRImitive -DESign -DYNamic -NODYNamic -FUNction -STRucture Displays the gate report information at the primitive level. This is the default. Displays the gate report information at the design level. Displays the dynamic constraints in the gate report information. This is the default. Does not display the dynamic constraints in the gate report information. Does not display the fanin cone of the zero/one gates in the gate report information. This is the default. Displays the fanin cone of the zero/one gates in the gate report information.

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Related Commands
REPORT ENVIRONMENT REPORT GATE SET FLATTEN MODEL

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SET GUI
SET GUi [ON | OFf] (Setup / LEC Mode)

Switches Conformal to the GUI mode from the non-GUI mode or to the non-GUI mode from the GUI mode.

Parameters
ON OFf Switches to the GUI mode. This option is the initial system default. Switches to the non-GUI mode.

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SET HDL DIAGNOSIS
SET HDl Diagnosis (Setup Mode)

Enables the debugging features before reading design and libraries. By default, the source code debugging features (such as tracing drivers and loads) are off. Execute this command before READ LIBRARY and READ DESIGN.

Parameters
OFf ON Disables the Source Code Manager’s debugging features. This option is the initial system default. Enables the Source Code Manager’s debugging features.

Related Commands
DIAGNOSE REPORT TEST VECTOR

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SET HDL OPTIONS
SET HDl Options [-VERILOG_OUTOFBOUNDWrite ] [-VHDL_OUTOFBOUNDWrite ] [-VERILOG_OUTOFBOUNDRead ] [-VHDL_OUTOFBOUNDRead ] [-VERILOG_TRIMINDex ] [-VHDL_TRIMINDex ] [-READ_TRANSLATE_MSFF ] [-PRIMITIVE_INPUT_Conversion ] [-ZERO_REPLICATE_AS_ZERO ] (Setup Mode)

Controls the interpretation of some RTL semantics.

Parameters
-VERILOG_OUTOFBOUNDWrite Controls the interpretation of Verilog bit (or part)-select of vector typed variable/signal when index is out of the defined index range. Noeffect specifies that out-of-bound writing will have no effect. This is the default. X specifies that when there is out-of-bound writing, the related part of the variable/signal is assigned value ’x’. -VHDL_OUTOFBOUNDWrite Controls the interpretation of VHDL bit (or part)-select of vector typed variable/signal when index is out of the defined index range. X specifies that when there is out-of-bound writing, the related part of the variable/signal is assigned value ’x’. This is the default. Noeffect specifies that out-of-bound writing will have no effect.

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-VERILOG_OUTOFBOUNDRead Controls the interpretation of Verilog bit (or part)-select of vector typed variable/signal when index is out of the defined index range. PARTIAL_X specifies that out-of-bound reading will have values from the valid index locations of the vector, and will have ’x’ value from the invalid (i.e. out of bound) locations of the vector. This is the default. ALL_X specifies that when there is out-of-bound reading, the selected portion of the vector will be treated as all ’x’ values. -VHDL_OUTOFBOUNDRead Controls the interpretation of VHDL bit (or part)-select of vector typed variable/signal when index is out of the defined index range. ALL_X specifies that when there is out-of-bound reading, the selected portion of the vector will be treated as all ’x’ values. This is the default. PARTIAL_X specifies that out-of-bound reading will have values from the valid index locations of the vector, and will have ’x’ value from the invalid (i.e. out of bound) locations of the vector. -VERILOG_TRIMINDex ON controls to trim the index to necessary bits for the Verilog files. OFF is the command default. Note: This option might be used to verify implementations in which indexes are intentionally trimmed. -VHDL_TRIMINDex ON controls to trim the index to necessary bits for the VHDL files. OFF is the command default. Note: This option might be used to verify implementations in which indexes are intentionally trimmed.

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-READ_TRANSLATE_MSFF Models master-slave DFF of Liberty flip-flop cells that have clock_on and clock_on_also attributes. ON translates master-slave flip-flops (MSFF) to master slave latches. With this option, two D latches are used to model the master-slave DFF. This is the command default. OFF keeps the master slave flip-flops. With this option, two flip-flops are used to model the master-slave DFF. -PRIMITIVE_INPUT_Conversion Specifies how the software’s Verilog parser handles multiple-bit expressions. LSB takes the least significant bit from the multiple-bit vector expression. This is the default for the Verilog parser. LOGIC treats the entire multiple-bit expression as a logic true/false value. For example, for wire [0:5] net0; or I00 (out, net0[0:5]);

net0[0:5] used in I00 is treated as net0[5] by default, and it is treated as a logic true/false value when using the LOGIC option. -ZERO_REPLICATE_AS_ZERO When set to ON, treats zero replication as 'b0 for Verilog designs. OFF is the default.

Examples
The following examples use the Verilog language to show how to control index out of bound handling. You can use similar VHDL command options to control the interpretations for the VHDL language designs. In the following RTL-1 example, the index range of variable mem is 0 to 2. RTL-1 wire a; reg [2:0] index; reg [2:0] mem; always @(*) mem[index] = a;
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Encounter Conformal Equivalence Checking Reference Manual Command Reference If index is greater than 2, it is out of the index range. Some synthesis tools might intentionally interpret the RTL the same as with the following RTL-2 example: RTL-2 wire a; reg[2:0] index; reg[2:0] mem; always @(*) mem[index[1:0]] = a;

But with simulation, RTL-1 and RTL-2 behave differently. With the Conformal software, when running the command: set hdl options -verilog_outofboundwrite x

then
■ ■ ■ ■

index=0 : mem[0] is assigned to the value of a index=1 : mem[1] is assigned to the value of a index=2 : mem[2] is assigned to the value of a index=3,4,5,6,7 : mem[0], mem[1], and mem[2]are assigned to the value of 1’bx.

This interpretation assumes that out-of-bound writing will not happen, and consequently ignores the behavior difference when index is greater than 2. When running the command: set hdl options -verilog_outofboundwrite noeffect

then
■ ■ ■ ■

index=0 : mem[0] is assigned to the value of a index=1 : mem[1] is assigned to the value of a index=2 : mem[2] is assigned to the value of a index=3,4,5,6,7 : mem[0], mem[1], and mem[2]will not be affected with their current value.

Based on this interpretation, RTL-1 and RTL-2 are considered functional non-equivalent, and consequently the implementation from RTL-2 will be non-equivalent to RTL-1. Using the same RTL-1 and RTL-2 examples, when running the command: set hdl options -verilog_trimindex on

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Encounter Conformal Equivalence Checking Reference Manual Command Reference The Conformal software will interpret RTL-1 as RTL-2 by ignoring index[2] in the expression mem[index] (RTL-1). With the -verilog_trimindex on option, RTL-1 and RTL-2 are considered equivalent.

Related Command
ELABORATE DESIGN READ DESIGN

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SET IMPLEMENTATION
SET IMPlementation [-Both | -Golden | -Revised] (Setup Mode)

Specifies the multiplier and divider implementations in the Golden and Revised designs. Execute this command before READ LIBRARY and READ DESIGN. The types of multipliers supported are:
■ ■ ■ ■ ■

Carry Save Adder (CSA) Ripple Carry Adder (RCA) Booth Encoded-Wallace tree (WALL) Non-Booth Encoded-Wallace tree (NBW) Brent-Kung Adder (BKA)

Default Multiplier Implementation Is Automatically Determined By default, Conformal automatically determines the multiplier implementation as follows: If a_width + b_width =42, Conformal chooses WALL. The -auto default setting is best suited when you are using Synopsys Design Compiler with DesignWare Foundation. If you are not using DesignWare Foundation, it is probably best to specify -csa. The types of dividers supported are:
■ ■ ■ ■

Ripple Borrow (RPL) Borrow Look-Ahead Carry Look-Ahead Carry Look-Ahead, 2-Way

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Required Options With this command, you must include either the multiplier or divider option; however, Conformal permits both options, as shown below: set implementation multiplier -csa divider -bla

Specifying Multiplier Implementations with Directives Specify the multiplier implementation with a Synopsys or Conformal directive in the design. (See the Set Implementation examples below and in the Examples section of this command.)
■

Synopsys Directive:
// synopsys dc_script_begin // set_implementation [instance_name] // synopsys dc_script_end

■

Conformal Directive:
// conformal multiplier

Note: Use either directive for multipliers specified with operational assignments. For DesignWare instances, use only the Synopsys directive along with the instance name.

Parameters
MULtiplier By default, Conformal automatically determines the multiplier implementation as follows: If a_width + b_width < = 52, Conformal chooses NBW. If a_width + b_width > 52, Conformal chooses WALL. The multiplier type is one of the following: -AUTO The -auto default setting is best suited when you are using Synopsys Design Compiler with DesignWare Foundation. If you are not using DesignWare Foundation, it is probably best to specify -csa. This is the default. Carry Save Adder Booth Encoded, Wallace tree Ripple Carry Adder Non-Booth Encoded, Wallace tree
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-BKA DIVider

Brent-Kung Adder

The divider type is one of the following: -RPL -BLA -CLA -CLA2 Ripple Borrow, which is the initial default Borrow Look-Ahead Carry Look-Ahead Carry Look-Ahead, 2-Way

The following options specify how to treat over signed division overflow, which is when a minimum negative value is divided by -1. -OVERFLOW_TRUNCATE Truncates results as defined by twos-complement arithmetic. This is the default. -OVERFLOW_SATURATE Saturates results to the largest positive value. -OVERFLOW_DONTCARE Treats overflow results as don’t cares. DIVider can be inferred from either DW_div instantation or RTL arithmetic operation (for example, ‘/’ in Verilog). The following options specify the divider class for the preceeding settings. -ALL_div -RTL_div -DW_div -Both -Golden -Revised Specifies that dividers are inferred from both RTL and DW. This is the default. Specifies that dividers are only inferred from RTL operation. Specifies that dividers are only inferred from DW_div instantiation.

Specifies the implementation type for both the Golden and Revised designs. This is the default. Specifies the implementation type for the Golden design. Specifies the implementation type for the Revised design.

Examples
Synopsys Directive The following examples illustrate Conformal-supported use of the Synopsys directive:
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// synopsys dc_script_begin // set_implementation wall // synopsys dc_script_end assign out = in1 * in2; // synopsys dc_script_begin // set_implementation wall U1 // synopsys dc_script_end DW02_mult #(10,10) U1 (.A (in1), .B (in2), .TC (1’b0), .PRODUCT (out)); // synopsys dc_script_begin // set_implementation wall cla2 U1 // synopsys dc_script_end DW_div #(A_width, B_width, TC_mode, REM_mode) U1 (...);

Conformal Directive The following example illustrates the Conformal directive. Note: The directive applies to only the statement on the following line. In this example, it does not apply to assign out2…:
// conformal multiplier wall assign out1 = in1 * in2; assign out2 = in3 * in4;

Related Command
READ DESIGN

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SET LOG FILE
SET LOg File [ [-Replace | -Append] [-PROGRESS | -NOPROGRESS] [-NOBACkup]] (Setup / LEC Mode)

Writes the transcript to a specified file. The commands and any output information write to this file. As you review the file, identify commands by the keyword:
//Command:

When you want the Conformal software to stop writing to the log file, enter the command without any options. Note: If the filename you specify already exists, you must use either the -replace or -append option. If you do not include an option, the Conformal software generates an error message that the file exists. If you receive this message, reenter the command with either a new filename or the appropriate option. If the filename is not writable, the software writes it to the /tmp directory. If you are writing the transcript to a file, you might want to turn off the screen transcript display with the SET SCREEN DISPLAY command. (If you do not specify otherwise, the transcript prints to the screen.) To store log files based on the software version, use the LEC_VERSION environment variable. For example: set log file lec.$LEC_VERSION.log -replace

To verify the current log file setting, use the REPORT ENVIRONMENT command.

Parameters -Replace -Append -PROGRESS Writes the transcript run to this file. If the specified filename already exists, overwrites the contents of that file. Appends the transcript run to the end of the specified filename. Writes the percentage completion progress to the log file. This is the default.

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-NOPROGRESS -NOBACkup

Does not write the percentage completion progress to the log file. Does not create a backup file. Note: If you do not specify this option, it will create a backup file when you replace or append a file.

Related Commands
REPORT ENVIRONMENT REPORT COMMAND PROFILE SET COMMAND PROFILE SET SCREEN DISPLAY

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SET LOWPOWER OPTION
SET LOwpower Option [-NOauto | -Auto ] [-NORetention_cells_check | -Retention_cells_check] [-NOIsolation_cells_check | -Isolation_cells_check] [-NOLevel_shifter_cells_check | -Level_shifter_cells_check] [-NOPOWER_domain_check | -POWER_domain_check [-GOLDen_power_domain [CPF | PHYsical | HYbrid]] [-REVised_power_domain [PHYsical | CPF | HYbrid]] ] [-NOMerge | -MERge] (Setup Mode)

Note: This is a Conformal Low Power command. Enables the low power check for low power cell types. Low power checking includes technology mapping checks for state retention cells, technology mapping checks and equivalence checks for isolation and level-shifter cells, and power domain consistency checks for the sequential elements. For more information on these low power checks and cell types, see CHECK LOWPOWER CELLS.

Parameters
-NOauto Does not automatically enable the low power checks. This is the default; however, in the CPF low power cell insertion flow, the technology mapping check for state retention cells is enabled by default. Enables the low power checks. However, in the CPF low power cell insertion flow, the technology mapping check and equivalence check for isolation cells and level-shifter cells is disabled by default.

-Auto

-NORetention_cells_check Disables the technology mapping check for state retention cells only. This is the default.

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-Retention_cells_check Enables the technology mapping check for state retention cells only. In the CPF low power cell insertion flow, the Default1 rule check is enabled by default. For a description of the default rules that are added by the system, see Default Rules in the Encounter Conformal Low Power User Guide. -NOIsolation_cells_check Disables the technology mapping check and equivalence check for isolation cells only. This is the default. -Isolation_cells_check Enables the technology mapping check and equivalence check for isolation cells only. This option is only valid in the non-CPF flow, or the CPF flow without low power cell insertion. -NOLevel_shifter_cells_check Disables the technology mapping check and equivalence check for level-shifter cells only. This is the default. -Level_shifter_cells_check Enables the technology mapping check and equivalence check for level-shifter cells only. This option is only valid in the non-CPF flow, or the CPF flow without low power cell insertion. -NOPOWER_domain_check Disables the power domain consistency check for the sequential compare points. This is the default. -POWER_domain_check Enables the power domain consistency check for the sequential compare points in CPF low power cell insertion flow. This option is only valid in the non-CPF flow, where this option is the default, or the CPF flow without low power cell insertion.

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-GOLDen_power_domain [CPF | PHYsical | HYbrid] Specifies the mechanism for obtaining the power domains in the Golden design to perform power domain consistency checking. CPF obtains the power domain from the CPF specification. This is default for the Golden design. PHYsical extracts the power domains by tracing the power and the ground pins. HYbrid extracts the power domains by tracing the power and the ground pins. If the power domain cannot be obtained by tracing the power and ground pins, the software obtains the power domain from the CPF specification. -REVised_power_domain [PHYsical | CPF | HYbrid] Specifies the mechanism for obtaining the power domains in the Revised design to perform the power domain consistency checking. PHYsical extracts the power domains by tracing the power and the ground pins. This is default for the Revised design. CPF obtains the power domain from the CPF specification. HYbrid extracts the power domains by tracing the power and the ground pins. If the power domain cannot be obtained by tracing the power and ground pins, the software obtains the power domain from the CPF specification. -NOMerge -MERge Does not merge the equivalent outputs of the isolation and level-shifter cells. This is the default. Merges the equivalent outputs of the isolation and level-shifter cells. This is enabled only in the non-CPF flow, or the CPF flow without low power cell insertion when -level_shifter_cells_check, -isolation_cells_check, or -auto is specified.

Examples
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The following commands perform low power checking that includes both the technology mapping check and the equivalence check in the non-CPF flow, or the CPF flow without low power cell insertion:

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Encounter Conformal Equivalence Checking Reference Manual Command Reference set lowpower option -auto set lowpower option -retention -level_shifter

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The following command performs power domain consistency checking on sequential cells in CPF low power cell insertion flow: set lowpower option -power_domain_check -golden CPF -revised CPF

Related Commands
ADD LOWPOWER CELLS CHECK LOWPOWER CELLS DELETE LOWPOWER CELLS REPORT LOWPOWER DATA

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SET MAPPING METHOD
SET MApping Method < [-NAme |-NOName] [-NOPhase | -Phase] [-NOSensitive | -Sensitive]> [-NOUNREACH | -UNREACH] [-REPORT_UNREACH | -NOREPORT_UNREACH] [-NAME_EFFORT ] [-NONETS | -NETS] [-BBOX_NAme_match | -NOBBOX_NAme_match] [-REPORT_SUMMARY_SHOW_ZERO_COUNT] [-TIMEOUT_minutes ] [-PHASEMAPMODEL] [-MEM] (Setup / LEC Mode)

Specifies the mapping method, phase, case sensitivity, and handling for unreachable points and blackboxes when Conformal maps the key points. With the -name option, paths of the gates indicate some type of starting point to map key points. The system default is name first. This default lets Conformal first map key points with the same paths, then map the remaining unresolved key points with a mapping algorithm. All remaining unresolved key points become unmapped points. Use the REPORT ENVIRONMENT command to display the setting of the mapping method and phase.

Parameters
-NAme The mapping method operates under the modes described as follows: First Conformal maps the key points with the paths of the gates first. Then, Conformal uses the mapping algorithm to map the rest of the key points. This option is the system default. Conformal maps key points with a mapping algorithm first. Conformal only maps the key points based on the paths of the gates

Guide Only

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-NOName

Does not map key points based on the paths of the gates. If the mapping algorithm cannot map a key point, it remains unmapped. Does not map key points with an inverted phase. This is the default. These key points are represented with the symbol “+”. Comparison results are either equivalent or nonequivalent.

-NOPhase

-Phase

Maps key points with an inverted phase. These key points are represented with the symbol “-”. Comparison results are either inverted-equivalent or nonequivalent.

-NOSensitive -Sensitive -NOUNREACH

Specifies that key point names are not case sensitive. This is the default. Specifies that key point names are case sensitive. Does not map unreachable key points. Unreachable key points are those that don’t eventually affect the PO of the design. This is the default. Maps unreachable key points. Unreachable key points are those that don’t eventually affect the PO of the design. Reports unreachable key points. This is the default. Does not report unreachable key points. Uses the specified amount of effort for key point mapping. This option eliminates the need for simple renaming rules such as: add renaming rule R1 “reg\[%d\]” “reg(@1)” -golden, which maps the following Golden and Revised design DFFs: Golden: DFF A/B/C_reg[5] Revised: DFF A/B/C_reg(5) This option applies to only DFFs and DLATs. HI MEDIUM Specifies a high effort for key point mapping. This option is the system default. Specifies a medium effort for key point mapping.
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-UNREACH -REPORT_UNREACH -NOREPORT_UNREACH -NAME_EFFORT

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LOW -NONETS -NETS -BBOX_NAme_match -NOBBOX_NAme_match

Specifies a low effort for key point mapping.

Does not map according to net names. This is the default. Maps key points according to net names. Maps blackboxes only if both the module names and instance names match. This is the default. Maps blackboxes if instance names match.

-REPORT_SUMMARY_SHOW_ZERO_COUNT Specifies that the summary will be reported with ZERO count if there is an unmapped point of the same type either in Golden or Revised design. -TIMEOUT_minutes Specifies the number of minutes for the mapping process to continue before it is interrupted. The default value is zero (0), which disables this check. -PHASEMAPMODEL Uses the phase information provided by the ADD MAPPING MODEL command to determine the mapping phase. Use this option when there is a phase mismatched between the simulation model and the synthesis model. Uses a mapping method that is compatible with memory array structures and results in faster and more accurate memory array element mapping and consequently more accurate comparison, reducing the number of false errors due to incomplete or incorrect mapping and reducing the need for renaming rules. This option should be set when the design to be verified is a memory circuit.

-MEM

Related Commands
ADD MAPPED POINTS ADD RENAMING RULE DELETE MAPPED POINTS DELETE RENAMING RULE

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SET MOS MODEL
SET MOs Model [] (Setup Mode)

Note: This requires a Conformal GXL license. Specifies the MOS model names used in SPICE. You can then re-read the SPICE netlist. When reading in SPICE netlists, the parser automatically identifies transistor model names as PMOS and NMOS types. However, if you have models that were not defined using .MODEL statements, the parser identifies them as ERROR. Instead of altering your SPICE file, you can use this command. Note: You must run this command before reading in the SPICE netlist.

Parameters
NMOS PMOS Defines the model name as an N-Channel device. Defines the model name as a P-Channel device. Specifies a single or list of names for which to define models.

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SET MULTIBIT OPTION
SET MULTIBIT Option [-Delimiter ] [-GROUP ] (All Modes)

Splits an instance name into a multibit library cell, using a name delimiter and group pattern. This can facilitate the successful mapping of the individual bits for the multibit cell.

Parameters
-Delimiter

Specifies the name delimiter as a Perl regular expression. The default value is "_MB_". Specifies the name group as a Perl regular expression. It must be in the format of "()". The default value is "(.*?)".

-GROUP

Example
The following command splits instance name "a_reg[0][1]_a_reg[0][2]_a_reg[0][3]_a_reg[0][4]" into "a_reg[0][1]", "a_reg[0][2]", "a_reg[0][3]" and "a_reg[0][4]".
MODE> set multibit option -group "(.*?(_reg)+(\[\d+\])+)" -delimiter "_"

Related Commands
SET MAPPING METHOD

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SET MULTIPLIER IMPLEMENTATION
SET MUltiplier Implementation [-Both | -Golden | -Revised] [-Verbose] (Setup Mode)

Specifies the multiplier implementation in the Golden and Revised designs. Execute this command before READ LIBRARY and READ DESIGN. The types of multipliers you can specify are:
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Carry Save Adder (CSA) Ripple Carry Adder (RCA) Booth Encoded-Wallace tree (WALL) Non-Booth Encoded-Wallace tree (NBW) multipliers Brent-Kung Adder (BKA)

The CSA multiplier implementation is the default. An alternate method for specifying the multiplier implementation is to use a Synopsys or Conformal directive in the design. See the following set multiplier implementation examples for using these directives and those shown in the “Examples” section below. Synopsys Directive:
// synopsys dc_script_begin // set_implementation [instance_name] // synopsys dc_script_end

Conformal Directive:
// conformal multiplier

Note: Use either directive for multipliers specified with operational assignments. However, for DesignWare instances, use only the Synopsys directive along with the instance name.

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Parameters
AUTO The system default for Conformal is that it automatically determines the multiplier implementation as follows: If a_width + b_width < = 52, Conformal chooses NBW. If a_width + b_width > 52, Conformal chooses WALL.

The auto default setting is best suited when you are using Synopsys Design Compiler with DesignWare Foundation. If you are not using DesignWare Foundation, it is probably best to specify csa. CSA RCA WALL NBW BKA -Both -Golden -Revised -Verbose Specifies that the multiplier type is a Carry Save Adder (CSA) multiplier. Specifies that the multiplier type is a Ripple Carry Adder (RCA) multiplier. Specifies that the multiplier type is a Booth Encoded, Wallace tree multiplier. Specifies that the multiplier type is a non-Booth Encoded, Wallace tree multiplier. Specifies that the multiplier type is a Brent-Kung Adder (BKA). Specifies the multiplier implementation type for both the Golden and Revised designs. This is the default. Specifies the multiplier implementation type for the Golden design. Specifies the multiplier implementation type for the Revised design. Provides additional information.

Examples
Synopsys Directive The following two examples illustrate Conformal-supported use of the Synopsys directive:
// synopsys dc_script_begin // set_implementation wall
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// synopsys dc_script_end assign out = in1 * in2; // synopsys dc_script_begin // set_implementation wall U1 // synopsys dc_script_end DW02_mult #(10,10) U1 (.A (in1), .B (in2), .TC (1’b0), .PRODUCT (out));

Conformal Directive The following example illustrates the Conformal directive. Note: The directive applies to only the statement on the following line. In this example, it does not apply to assign out2…:
// conformal multiplier wall assign out1 = in1 * in2; assign out2 = in3 * in4;

Related Command
READ DESIGN

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SET MULTIPLIER OPTION
SET MUltiplier Option [-NOAUTO | -AUTO] [-NOCDP_INFO | -CDP_INFO] [-Verbose] (Setup Mode)

Specifies whether Conformal will automatically analyze multipliers when switching from Setup to LEC mode. Additionally, use the -cdp_info option if you want Conformal to let you know when Conformal Ultra will be helpful.

Parameters
-NOAUTO -AUTO -NOCDP_INFO -CDP_INFO -Verbose Does not automatically analyze multipliers when switching from Setup to LEC mode. This is the default. Automatically analyzes multipliers when switching from Setup to LEC mode. Does not display a message when Conformal Ultra can enhance multiplier analysis. This is the default. Displays a message when Conformal Ultra can enhance multiplier analysis. Provides additional information.

Related Commands
ANALYZE DATAPATH ANALYZE MODULE REPORT DATAPATH OPTION REPORT MULTIPLIER OPTION SET DATAPATH OPTION SET FLATTEN MODEL

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SET NAMING RULE
SET NAming Rule [-Both | -Golden | -REvised] (Setup Mode)

Specifies the naming rules for an RTL or hierarchical design. Execute this command before READ LIBRARY and READ DESIGN. Naming rules for RTL designs specify the following:
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Hierarchical separator Tristate and register names Array delimiter

Naming rules for hierarchical designs specify the hierarchical separator.
■

Use the hierarchical separator string when matching key points between the Golden and Revised designs. The hierarchical separator setting has no effect on the way key points are reported (for example, when you use the REPORT GATE command). Use the register, tristate, and array delimiter strings to instruct the Verilog RTL compiler how key point names (inferred flip-flop/latch instance names) are constructed. Use the following example to understand the correct use of the inverted pin extension string. Golden design: pin a Revised design: inverted pin a_BAR Type the following command: set naming rule _BAR -inverted_pin_extension -golden

■ ■

■

The parameter string defines the name of the new parameterized module name when new parameters are passed. When an existing module has defined parameters and it is being instantiated with new parameters, a duplicate module is created with the specified parameter string.

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The instance strings define the way instance names are generated. Different synthesis tools use different schemes to generate instance names. To facilitate the compare process, you can use this command to instruct Conformal to generate instance names in the same way as the synthesis tool. The variable strings define the way variable names are generated.

■

Each string for all of the settings must be enclosed in double quotes (“ ”). These double quotes can be empty. Use the REPORT ENVIRONMENT command to display the settings for the naming rules for the Golden and Revised designs.

Parameters -Hierarchical_separator A character or string that specifies the hierarchical separator. The default is “/”. -Tristate -REGister A string that specifies the tristate naming. The default is “%s_tri”. The string must contain exactly one “%s”. A string that specifies the register naming. The default is “%s_reg”. The string must contain exactly one “%s”.

-Inverted_pin_extension A string that specifies the inverted pin extension. This option appends the string to the Golden or Revised pin name. Refer to the example shown in “Definition”. -Parameter A string that specifies parameter naming. The default is “_%s”. -Array_delimiter Two strings that specify the left and right array delimiter. The default is “[” and “]” for the left and right string. -Field_delimiter Two strings that specify the left and right record field delimiter for VHDL designs. The default is “[” and “]” for the left and right string.

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label_string forgen_string instance_string -instance [-ALL | -VLG | -VHDL] forgen_string applies to “for generate” blocks that have a name and index, label_string applies to all of the other blocks. label_string specifies how to include the block name in the instance name, where: %L specifies the block name. %s specifies the current instance name. The default setting for label_string is:
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%L.%s for Verilog, Verilog2k, and SystemVerilog designs %s for VHDL designs

For example, instance ins1 is inside block b1, and b2 is inside b1. If you specify a label_string of %L_%s, this command generates the instance name b1_b2_ins1.

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forgen_string specifies how to use the generated block name and loop index to form an instance name, where: %L specifies the block name. %s specifies the current instance name. %d specifies the block index. The default setting for forgen_string is:
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%L[%d].%s for Verilog, Verilog2k, and SystemVerilog designs $s_%d for VHDL designs

For example, instance ins1 is inside block b2 with a forloop index of 3, and b2 is inside block b1 with a forloop index of 0. If you specify a forgen_string of %L[%d].%s, this command generates the instance name b1[0].b2[3].ins1. instance_string denotes how to specify the instance name, where %s specifies the current instance name. For example, your current instance name is ins1. If you specify an instance_string of %s_INS, this command replaces the instance name with ins1_INS. Note: The result of this option replaces the %s in label_string and forgen_string. The default setting for instance_string is %s. -ALL Specifies that this user-defined naming rule applies to Verilog/Verilog2k/SystemVerilog and VHDL designs. This is the default. -VLG Specifies that this user-defined naming rule applies to only Verilog/Verilog2k/SystemVerilog designs. -VHDL Specifies that this user-defined naming rule applies to only VHDL designs. Note: The -ALL, -VLG, and -VHDL options must be used immediately after the -instance option.

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label_string forgen_string variable_string -variable [-ALL | -VLG | -VHDL] The variable naming scheme is similar to the instance naming scheme. forgen_string applies to generated blocks that have a name and index, label_string applies to all of the other blocks. label_string specifies how to include the block name in the variable name (applies to all variables inside the “for generate” block), where: %L specifies the generated block name. %s specifies the current variable name. The default setting for label_string is:
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%L.%s for Verilog, Verilog2k, and SystemVerilog designs %s for VHDL designs

forgen_string specifies how to use the generated block name and loop index to form a variable name, where: %L specifies the generated block name. %s specifies the current variable name. %d specifies the generated block index. The default setting for forgen_string is:
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%L[%d].%s for Verilog, Verilog2k, and SystemVerilog designs $s for VHDL designs

variable_string denotes how to specify the variable name, where %s specifies the current variable name. The default setting for variable_string is %s. -ALL Specifies that this user-defined naming rule applies to Verilog/Verilog2k/SystemVerilog and VHDL designs. This is the default. -VLG Specifies that this user-defined naming rule applies to only Verilog/Verilog2k/SystemVerilog designs.

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-VHDL Specifies that this user-defined naming rule applies to only VHDL designs. Note: The -ALL, -VLG, and -VHDL options must be used immediately after the -variable option. -Both -Golden -REvised The naming rule applies to both the Golden and Revised designs. This is the default. The naming rule applies to the Golden design alone. The naming rule applies to the Revised design alone.

Examples set naming rule “:” -hierarchical_separator -golden set naming rule “register_%s” -register -revised set naming rule “tristate_%s” -tristate set naming rule “” -array -golden

For instance name generation, consider the following sample Verilog code: generate begin: blkA for (i=0;i module design(clk, rst, cs, wr, rd_addr, wr_addr, din, dout); input clk, rst, cs, wr; input [2:0] rd_addr, wr_addr; input [4:0] din; output[4:0] dout; DW_ram_r_w_s_dff #(5, 8, 0) ram (.clk(clk), .rst_n(rst), .cs_n(cs), .wr_n(wr), .rd_addr(rd_addr), .wr_addr(wr_addr), .data_out(dout), .data_in(din) );

1. Specify that Conformal treat undefined cells as blackboxes.
> set undefined cell black_box

2. Read in the Golden design, which contains our sample module.
> read design gol.v

3. Write a wrapper file dir/_DW_ram_r_w_s_dff_5_8_0.v for blackbox module DW_ram_r_w_s_dff_5_8_0. write blackbox wrapper DW* -directory dir break

Note: This command also generates synthesis script template files dir/dc.tcl and dir/rc.tcl. 4. Use the dir/dc.tcl script with your own synthesis tool to generate dir/_DW_ram_r_w_s_dff_5_8_0.g.v.
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> read design -append dir/*.g.v

6. Substitute the old module of blackbox instance ram with the new module _DW_ram_r_w_s_dff_5_8_0_DW_ram_r_w_s_dff_5_8_0_0(dir/_DW_ram_r_w _s_dff_5_8_0.g.v:229).
> substitute blackbox wrapper DW*

Related Command
WRITE BLACKBOX WRAPPER

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SYSTEM
SYSTEM (Setup / LEC Mode)

Enables any command your UNIX operating system recognizes. Note: In GUI mode, the Conformal software prints the return in the transcript window. You can substitute the exclamation mark (!) for the word “System”, as shown in the “Example” section, below.

Parameters Any valid UNIX command.

Example system ls system pwd !pwd

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TCLMODE
TCLMODE (Setup / LEC Mode)

Switches from native Conformal command entry mode (VPX mode) to Tcl command entry mode. VPX mode is the default command mode. There are two types of Tcl mode commands:
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Native Tcl commands Conformal Tcl commands

Note: When issuing commands in Tcl mode, you must type them in lowercase. In Tcl mode, you must use a backslash to specify the following special characters: { } $ [ ] ". TCL For more information about native Tcl commands, refer to the public Tcl manual, which is widely available online. Conformal Tcl commands are discussed in detail in the Encounter Conformal Equivalence Checking User Guide. Tip To start the Conformal software in Tcl mode without executing any initialization script, run the following command at a UNIX system prompt:
UNIX% lec -tclmode

Tip In the Tcl command entry mode, you can save report data to a file using the redirection command. For example, the following command saves the gate report data to a file named gate.out:
TCL_SETUP> report_gate -type dff > gate.out

Related Command
VPXMODE

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TEST RENAMING RULE
TESt REnaming Rule [-All | -NEw_rule ] [-MAp [-TYpe … |-NOTYpe < PI | E | Z | DFf | DLat | CUt | BBox | PO>…] |-MOdule |-PIn [-BBox ]] [-RULE_USAGE | -NORULE_USAGE] [-Both | -Golden | -Revised] [-SORTNAme] [-File [-REPlace]] [-VErbose] (LEC Mode)

Displays the results of the key point matching based on the user-specified renaming rules. Use this command to obtain a quick summary of how well the key points will be mapped based on the specified renaming rules. Test new and existing rules.

Parameters
-Design Tests the renaming rules on the entire design. This argument instructs Conformal to display a summary of the Golden and Revised pairs and groups and Golden and Revised single un-grouped key points for the entire design. Does not display the key point pairs, un-grouped single key points, or grouped key points. This is the default. Displays key points as follows: Single Pair Group string -GATE_id -All Un-grouped single key points Key point pairs Grouped key points

-NOprint -Print

A string that the renaming rule uses as an example. Tests renaming rules on the specified gate. Tests all renaming rules within the given defaults. This is the default.

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-NEw_rule A new renaming rule. The first string is the pattern to be matched; the second string is the substitution pattern. -MAp -TYpe -NOTYpe Tests the renaming rules on key points that will be mapped. This is the default. Tests renaming rules for all key points of the specified type. This is the default. Tests renaming rules for all key points except the specified types. The available types are as follows: PI E Z DFF DLAT CUT BBOX PO -MOdule -PIn -RULE_USAGE -NORULE_USAGE Primary Inputs TIE-E gates TIE-Z gates D flip-flops D-latches Artificial gates for breaking combinational feedback loops Blackboxes Primary Outputs

Tests the renaming rules on the modules in the design. Tests the renaming rules on pin names of blackboxes. Displays the number of matches for the specified string. This option is turned on by default. Does not display the number of matches for the specified renaming rule.

-BBox Tests the pin renaming rule on the specified blackbox module. The default is to test all blackboxes. -Both -Golden -Revised Tests the renaming rules on both the Golden and Revised designs. This is the default. Tests the renaming rules on the Golden design. Tests the renaming rules on the Revised design.

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-SORTNAme -File -REPlace -VErbose

When this option is used with the -print option, the results appear in alphabetical order by name. Writes the results to the specified file. Replaces the above file, if it exists. Displays both the original key point name and the renamed key point.

Examples
■

The following command displays the summary results of the renaming rules on the designs: test renaming rule -design -all

■

The following command displays a list of all Golden/Revised un-grouped single key points: test renaming rule -design -print single

■ ■ ■ ■

The following command displays a list of all Golden/Revised grouped key points: test renaming rule -design -print group

The following command displays a list of all Golden/Revised pair key points: test renaming rule -design -print pair

The following command writes a list of all Golden/Revised grouped key points to a file: test renaming rule -design -print group -file group_list

The following command displays the summary results of the renaming rule on the designs with a new rule: test renaming rule -design -new_rule

■

The following command displays the summary results of the renaming rules applied to a sample string: test renaming rule -all

■

The following command displays the summary results of the new renaming rule applied to a sample string: test renaming rule -new_rule

Related Commands
ADD RENAMING RULE DELETE RENAMING RULE

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UNIQUIFY
UNIQuify | -ALL [-Library | -NOLibrary]> [-Force] [-USE_RENaming_rules] [-Summary | -Verbose] [-Golden | -Revised] (Setup Mode)

Makes the specified module, which has multiple instances, unique. This command lets you remedy the “incompatible” instantiations warnings during hierarchical script generation. If Conformal does not make the modules unique, they are not included in the hierarchical dofile. Use this command before any commands with pathname-based specifications so that the effect can be propagated during hierarchical constraint extraction. For example, the following command sequence:
SETUP> add primary input usub_0/net -golden SETUP> add pin constraint 0 usub_0/net -golden SETUP> uniquify -all -nolib Uniquified 1 instance(s) referring to module 'sub_0' in Golden // Warning: Added primary input(s) are deleted

should be:
SETUP> uniquify -all -nolib Uniquified 1 instance(s) referring to module 'sub_0' in Golden SETUP> add primary input usub_0/net -golden SETUP> add pin constraint 0 usub_0/net -golden

When using hierarchical compare for abort resolution, this command allows you to include more modules in the hierarchical dofile, therefore reducing the compare complexity of helping resolve aborts. For more information, see Hierarchical Comparison for Abort Resolution in the Encounter Conformal Equivalence Checking User Guide.

Parameters -ALL -Library Makes the specified module(s) unique. Makes all modules, within the given defaults, in the specified design unique. Makes all modules in designs and libraries unique. This is the default.
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-NOLibrary -Force

Makes all modules in designs unique. Forcibly makes specified modules in the Golden or Revised design unique, even if those modules have not been made unique in the complementing design. (For example, forcibly make Golden modules unique when the Revised modules have not been made unique.)

-USE_RENaming_rules Considers renaming rules for instances. When adding renaming rules, the software renames the Golden design instances to be same as in the Revised design, so running a subsequent UNIQUIFY command with this option will make the Golden modules that have matching instance names in the Revised design unique. -Summary -Verbose -Golden -Revised Summarizes the outcome of making modules unique. This is the default. Provides expanded information about the modules that were made unique. The specified modules are in the Golden design. This is the default. The specified modules are in the Revised design.

Example
The following command example creates a hierarchical dofile script named hier.do containing the compare script for the sub-modules and the root module, then runs hierarchical compare. This is can help in resolving aborts.
... uniquify -all write hier_compare dofile hier.do run hier_compare hier do

Related Commands
RESOLVE RUN HIER_COMPARE WRITE HIER_COMPARE DOFILE

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USAGE
USAge [ | -Elapse | -Delta] [-MIN_COMMAND_SECONDS ] [-NOAuto | -Auto] (Setup / LEC Mode)

Displays the total CPU run time and peak memory use since you started Conformal.

Parameters
-Elapse -Delta Displays the elapsed time of a process. Displays the difference, in seconds, between the current CPU run time and CPU run time when you last issued the usage command.

-MIN_COMMAND_SECONDS For a single command, sets the minimum CPU run time (in seconds) required to trigger the automatic print out of usage. You must set the -auto option to use this option. Default value is 0.1 seconds. -NOAuto -Auto Does not automatically run this command after running other commands. This is the default. Automatically displays usage at the end of every command.

Related Command
COMPARE

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VALIDATE CIRCUIT
VALidate CIrcuit [-Revised | -Golden] [-BBOXSCRipt ] [-MODule ] [-DOfile ...] [-POWERPINs ... ] [-PRESERVE_MODEL_OPTIONs | -NO_PRESERVE_MODEL_OPTIONs] [-POWERPIN_TO_INput | -NO_POWERPIN_TO_INput] [-ASM | -NOASM] (Setup Mode)

Note: This requires a Conformal XL license. Checks circuit libraries and custom blocks (when applicable), and enables equivalence checking on the full integrated circuit design. Use this command at the integrated-circuit level for RTL or Gate to final circuit. This application is for checking the consistency of pre-defined libraries during design verification. Important Do not use this command for validating the library itself. To validate library itself, use the VALIDATE LIBRARY command instead. For both the Golden and Revised designs, refer to the same library so that any inconsistencies at the library cell level will not affect the equivalence checking on design level. After which, all the library cells under this checking will be replaced by their counterpart reference cells. Note: You can use this to check a verified circuit. However, you need a Conformal XL license to diagnose logic abstraction and errors that relate to library comparisons.

Parameters
-Revised -Golden Validates the Revised database. This is the default. Validates the Golden database.

-BBOXSCRipt Creates a dofile with the specified name that blackboxes all validated cells for structural verification, which is more accurate than logical verification. -MODule
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Validates the specified module. By default, the software validates the root module. Use this option to validate a module other than the root module. Note: The software validates only the topmost library and custom cells (that exist in the reference side) that are used by the specified module. -DOfile ... Specifies the name of the dofile that was used to verify all custom blocks so that they can be re-checked. If a custom module has not been verified yet, blackbox it before running the VALIDATE CIRCUIT command. VALIDATE CIRCUIT can check for consistency in custom blocks, but it cannot verify custom blocks. Use Conformal Custom to verify custom blocks. -POWERPINs ... Defines names for the pin(s) that are used as extraneous power pins, which are ignored during cell verification. For multiple power pins, each pin name must be separated by a space. Cadence recommends that you use the ADD PIN CONSTRAINTS command to tie power pins to 1 and ground pins to 0.

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-PRESERVE_MODEL_OPTIONs Preserves any user-defined settings made prior to this command. This is the default. This option disables any flattening options that VALIDATE CIRCUIT sets by default. By default, the following flatten model options are set when VALIDATE CIRCUIT compares two modules: -seq_redundant -latch_fold -all_inv_seq_merge -all_seq_merge -seq_const See the SET FLATTEN MODEL command for an explanation of these options. With -PRESERVE_MODEL_OPTIONs, the comparison is done without changing any flatten model options. Any options that were set prior to running validate circuit are used instead. -NO_PRESERVE_MODEL_OPTIONs Does not disable any flattening options that VALIDATE CIRCUIT sets by default. -POWERPIN_TO_INput Specifies that if there are power pins that are input/output pins, they will be changed to input pins before validation. This is the default. -NO_POWERPIN_TO_INput Specifies that power pins that are input/output pins will NOT be changed to input pins before validation. -ASM Enables the Advanced State-element Modeling (ASM) algorithm. This helps to analyze loop structure to produce better modeling of state elements, such as D-Latch, DFF, and bus-keeping I/O logic. This is the default.

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-NOASM

Disables the Advanced State-element Modeling (ASM) algorithm. Tip If there are any unexpected results, you can use this option to revert back to the functionality of the 6.2 release and earlier.

Related Commands
READ DESIGN READ LIBRARY SET FLATTEN MODEL

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VALIDATE LIBRARY
VALidate LIbrary [-Revised | -Golden] [-NOSPIce | -SPIce] [-NOGOLPINDir | -GOLPINDir] [-PRESERVE_MODEL_OPTIONs | -NO_PRESERVE_MODEL_OPTIONs] [-POWERPINs ... ] [-POWERPIN_TO_INput | -NO_POWERPIN_TO_INput] [-ASM | -NOASM] [-SKIP_EXTRA_CELL] (Setup Mode)

Note: This requires a Conformal XL and Conformal GXL license, where noted. Compares all top-level cells with matching names. Conformal abstracts the modules on the SPICE side before comparison. This application is for library verification during library design. Important To abstract SPICE modules, you must have a Conformal GXL license.

Parameters
-Revised -Golden -NOSPIce Validates the Revised database. This is the default. Validates the Golden database. Abstracts and validates the modules that are not SPICE. This is the default. Note: This option requires a Conformal GXL license. -SPIce Abstracts and validates the SPICE modules. Note: This option requires a Conformal GXL license. -NOGOLPINDir -GOLPINDir Does not copy the pin directions from the Golden design to the Revised design. This is the default. Copies the pin directions from the Golden design to the Revised design. This is for all pins within the library cells being validated.

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-PRESERVE_MODEL_OPTIONs Preserves any user-defined settings made prior to this command. This is the default. This option disables any flattening options that VALIDATE LIBRARY sets by default. -NO_PRESERVE_MODEL_OPTIONs Does not disable any flattening options that VALIDATE LIBRARY sets by default. -POWERPINs ... Defines names for the pin(s) that are used as extraneous power pins, which are ignored during cell verification. For multiple power pins, each pin name must be separated by a space. Cadence recommends that you use the ADD PIN CONSTRAINTS command to tie power pins to 1 and ground pins to 0. -POWERPIN_TO_INput Specifies that if there are power pins that are input/output pins, they will be changed to input pins before validation. This is the default.

-NO_POWERPIN_TO_INput Specifies that power pins that are input/output pins will NOT be changed to input pins before validation. -ASM Enables the Advanced State-element Modeling (ASM) algorithm. This helps to analyze loop structure to produce better modeling of state elements, such as D-Latch, DFF, and bus-keeping I/O logic. This is the default. Disables the Advanced State-element Modeling (ASM) algorithm. Tip If there are any unexpected results, you can use this option to revert back to the functionality of the 6.2 release and earlier. -SKIP_EXTRA_CELL Skips reporting the cells that only exist in the Golden or Revised design.

-NOASM

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Related Command
VALIDATE CIRCUIT

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VERSION
VERsion (Setup / LEC Mode)

Displays the current version release number of Conformal. You can use this command after the SET LOG FILE command so the version becomes a part of the transcript log. In this way, you record the Conformal version that created your results. This command is also helpful when you use the SAVE SESSION and RESTORE SESSION commands, because you must use the same Conformal version when you restore a session.

Related Commands
RESTORE SESSION SAVE SESSION SET LOG FILE

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VPXMODE
VPXMODE (Setup / LEC Mode)

Switches from Tcl mode to native Conformal command entry mode (VPX mode). VPX is the default command mode. Important When issuing this command in the Tcl command interpreter, you must type this in lowercase. For example:
TCL_LEC> vpxmode

Tip In VPX mode, you can save report data to a file using the redirection command. For example, the following command saves the gate report data to a file named gate.out:
SETUP> report gate -type dff > gate.out

Related Command
TCLMODE

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WRITE BLACKBOX WRAPPER
WRIte BLackbox Wrapper -DIRectory (Setup Mode)

Creates a wrapper for each blackbox instance in your design whose module name matches those in a specified pattern list. Use this command to help complete equivalency checking for designs that contain DesignWare or ChipWare blackboxed modules. This command produces a module instantiation wrapper file for each blackboxed module wrapper, and synthesis script templates that you can use with your own synthesis tool to synthesize the modules that Conformal blackboxed. Synthesize the wrapper modules using the outputted scripts. Then, read in the newly-synthesized files using the READ DESIGN -append command. Finally, use the SUBSTITUTE BLACKBOX WRAPPER command to substitute the old blackboxed modules with the newly synthesized modules. Note: When specifying the cells that Conformal will treat as blackboxes, use the set undefined cell black_box command instead of the add notranslate modules command.

Parameters
-DIRectory Writes out the module instantiation wrapper file and the scripts to this directory. Writes out module wrappers for blackbox instances whose module name matches the specified pattern(s). This option accepts the “*” wildcard.

Examples
The following is a set of sample commands that show this and related commands in context. Sample module:
> module design(clk, rst, cs, wr, rd_addr, wr_addr, din, dout); input clk, rst, cs, wr; input [2:0] rd_addr, wr_addr; input [4:0] din; output[4:0] dout; DW_ram_r_w_s_dff #(5, 8, 0) ram (.clk(clk), .rst_n(rst), .cs_n(cs), .wr_n(wr), .rd_addr(rd_addr), .wr_addr(wr_addr), .data_out(dout), .data_in(din) );
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> set undefined cell black_box

2. Read in the Golden design, which contains our sample module.
> read design gol.v

3. Write a wrapper file dir/_DW_ram_r_w_s_dff_5_8_0.v for blackbox module DW_ram_r_w_s_dff_5_8_0. write blackbox wrapper DW* -directory dir break

Note: This command also generates synthesis script template files dir/dc.tcl and dir/rc.tcl. 4. Use the dir/dc.tcl script with your own synthesis tool to generate dir/_DW_ram_r_w_s_dff_5_8_0.g.v. 5. Read the newly created dir/_DW_ram_r_w_s_dff_5_8_0.g.v file into the design.
> read design -append dir/*.g.v

6. Substitute the old module of blackbox instance ram with the new module _DW_ram_r_w_s_dff_5_8_0_DW_ram_r_w_s_dff_5_8_0_0(dir/_DW_ram_r_w _s_dff_5_8_0.g.v:229).
> substitute blackbox wrapper DW*

Related Command
SUBSTITUTE BLACKBOX WRAPPER

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WRITE COMPARED POINTS
WRIte COmpared Points [-CLass ] [-TYpe ] [-File ] [-Replace] (LEC Mode)

Writes compared points information to a file. You can use this file to add a specific class and type of compared points to a compare list.

Parameters
-CLass Writes out the class of compared points. By default, the command writes out all classes. All Writes all compared point classes. This is the default if you do not specify the -CLass option. Writes compared points that are equivalent.

Eq INVequivalent

Writes the compared points that are inverted equivalent. NONeq ABort NOTcompared -TYpe Writes the compared points that are non-equivalent. Writes the aborted compared points. Writes the compared points that are not compared.

Writes out the type of compared points. By default, the command writes out all types. All Writes all compared point types. This is the default if you do not specify the -TYpe option. Writes the compared points of the primary outputs. Writes the compared points of the D flip-flops.
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DLat Bbox Cut -File -Replace

Writes the compared points of the D-latches. Writes the compared points of the blackboxes. Writes the compared points for artificial gates that break combinational loops.

Specifies the filename. Replaces the existing file.

Related Commands
ADD COMPARED POINTS

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WRITE DESIGN
WRIte DEsign [ | -ALL | -Module | -BBOX] [-Used] [-SKIP_Undefined] [-Library] [-REPlace] [-RTL] [-TEST_VIEW] [-Golden | -REVised] (Setup / LEC Mode)

Writes out the Golden or Revised design in Verilog format to examine how Conformal abstracts RTL descriptions into gate-level descriptions. Use the tilde character (~) to shorten the path of the file.

Parameters -ALL Writes the design to this file. Writes out all modules that are stored in the design space.

-Module Writes out the specified module that is stored in the design space. -BBOX Writes out all of the empty module descriptions of blackboxes in the design. By default, the command writes out the design tree of the root module, excluding modules in the library space. -Used -SKIP_Undefined -Library -REPlace Writes out the specified modules and all the referenced modules, including modules in the design space. Does not write undefined modules to the output. Writes out the library information. Replaces the existing file.

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-RTL

Outputs word-level operator expressions such as *, +, and -. By default, the command writes out the design without using the word-level operators. Without this option, the command writes out the design in Verilog primitive gates. Writes out the abstraction result of ABSTRACT LOGIC -test_view. The result might include Encounter Test primitives. To read the netlist back, use the READ DESIGN command’s -define option for ET_EC_MODEL. For example: read design -define ET_EC_MODEL

-TEST_VIEW

-Golden -REVised

Writes out the Golden design only. This is the default. Writes out the Revised design only.

Related Command
READ DESIGN

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WRITE HIER_COMPARE DOFILE
WRIte HIer_compare Dofile [-MODULE [-HIERarchical | -FLATten]] [-Black_box | -NOBlack_box] [-CONDitional] [-Exact_pin_match | -NOExact_pin_match] [-NOConstraint | -Constraint [-EXTRACT_Clock] [-INPUT_OUTPUT_Pin_equivalence [-RUN_HIER_compare] ] [-KEEP_TOP_level_constraints | -NOKEEP_TOP_level_constraints] [-PREPEND_String ] [-APPEND_String ] [-COMPARE_String ] [-Threshold ] [-LEVEL ] [-All] [-Usage] [-Replace] [-RETIMED_modules] [-IGNORE_MISMATCH_ports] [-ECO_aware] [-ECOPIN_dofile ] [-VERBOSE] (Setup Mode)

Writes out a hierarchical dofile script that verifies the two hierarchical designs starting from the lower-level modules and progressing to the top root module. Use options to specify one of the following actions:
■ ■ ■ ■

Blackbox modules after comparison Write modules with different numbers of pins to the dofile script Propagate the constraints to lower-level modules and apply them to the dofile script Change the minimum number of module primitives considered for hierarchical comparison

Use the tilde character (~) to shorten the path of the file. This command also generates a dofile script to compare two libraries, such as a Liberty and Verilog library. Use the -all option to write all library models to the dofile script for comparison.

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Parameters Specifies the name of the dofile script that verifies design hierarchy.

-MODULE Writes the specified Golden module and Revised module to the hierarchical dofile script. Note: Renaming rules must still be applied if the module names are different. -HIERarchical -FLATten -Black_box -NOBlack_box -CONDitional Includes all of the submodules of the specified module in the hierarchical dofile script. This is the default. Flattens all of the submodules of the specified module. Blackboxes each module after comparison. This is the default. Does not blackbox each module after comparison. Skips blackboxing for nonequivalent submodules during the hierarchical comparison. (The end result is that Conformal flattens these submodules.) To report the flattened modules, use the report hier_compare result -flattened command. -Exact_pin_match -NOExact_pin_match -NOConstraint Writes only those modules with matching pin names to the hierarchical dofile script. This is the default. Writes all modules to the hierarchical dofile script. Does not apply the root module constraints and equivalences to the hierarchical dofile script. This is the default. Propagates root module constraints and equivalences and applies them to the hierarchical dofile script.

-Constraint

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-EXTRACT_Clock

Extracts the clock pins in the Golden and Revised designs, and automatically adds the renaming rules to hierarchical dofile script to map the clock ports in the two designs. This can be used when the design has undergone Clock-Tree-Synthesis (CTS).

-INPUT_OUTPUT_Pin_equivalence Extracts input-output pin equivalences within a module and applies them to hierarchical dofile script. This can be used when the design has feedthroughs or feedback buffers. -RUN_HIER_compare Writes out more modules in the hierarchical dofile script by performing less stringent constraint checking. The resulting dofile must only be processed by the RUN HIER_COMPARE command and its default options. -KEEP_TOP_level_constraints Allows application of top-level pathname-based constraints to the appropriate sub-modules, during hierarchical comparison. The top-level constraints are supported for the ADD PRIMARY INPUT, ADD PIN CONSTRAINTS, and ADD INSTANCE CONSTRAINTS commands. This is the default. During hierarchical comparison, if top-level constraints take effect for the specific sub-module, they are enclosed within the following messages:
Applying top-level pathname-based constraints End of top-level pathname-based constraints ...

If the top-level constraints do not take effect when they should have, the following warning message is generated:
// Warning: Top-level constraints might not have been fully applied

Example provided in the Examples section. -NOKEEP_TOP_level_constraints Disables the application of top-level pathname-based constraints to the appropriate sub-modules, during hierarchical comparison.

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-PREPEND_String Appends any string of commands to the hierarchical dofile script before key point comparison for each module. Use “;” to separate commands. Use double quotes to surround each prepended command (see “Examples”). -APPEND_String Appends any string of commands to the hierarchical dofile script after key point comparison for each module. Use the semi-colon character (;) to separate commands. Use double quotes to surround each appended command (see Examples). -COMPARE_String Replaces the default compare command with a string of compare commands in the hierarchical dofile script generation for each module. Use the semi-colon character (;) to separate commands. Use double quotes to surround each compare command (see Examples). -Threshold This threshold is the minimum number of primitives within a module that will be written to the hierarchical dofile script. The minimum default number is 50 primitives. -LEVEL -All Writes all modules to the hierarchical dofile script up to the specified hierarchical level. Writes all library modules, within the given defaults, to the hierarchical dofile script. Use this option for library verification. Executes the USAGE command after each comparison and at the end of the hierarchical comparison. Replaces the existing file.

-Usage -Replace

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-RETIMED_modules

Writes out only those modules which have the PIPELINE_RETIME attribute attached to them. Use the ADD MODULE ATTRIBUTE command to attach the PIPELINE_RETIME attribute to a module.

-IGNORE_MISMATCH_ports Forces all modules with mismatched ports to be written out in a hierarchical dofile. -ECO_aware This option requires an ECO license. Recognizes ECO-related changes. This option recognizes ports that would otherwise be ignored for non-ECO comparisons, thus facilitating the correct comparison between the golden and revised designn. -ECOPIN_dofile This option requires an ECO license. Writes out a dofile for adding/deleting ECO pins to the golden design as compared to the revised design. -VERBOSE Provides additional information when writing out the hierarchical dofile script.

Examples write hier_compare dofile hier.do -replace write hier_compare dofile lec.do -replace write hier_compare dofile hier.do -append_string “usage” -prepend_string “report unmapped points -notmapped” -replace ■

The following is a sample dofile that reads in the two hierarchical designs, writes out the hierarchical dofile script, and compares design hierarchies: read library golden.lib -verilog -golden read design golden.v -verilog -golden read library revised.lib -verilog -revised read design revised.v -verilog -revised write hier_compare dofile hier.do -replace set log file hier.log -replace dofile hier.do exit -force

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■

The following is a sample dofile that reads in a synthesis library and simulation library, writes out all of the library models, and compares library hierarchies: read design syn.lib -liberty -golden read design simulation.v -verilog -revised write hier_compare dofile lib_ver.do -replace -all set log file lib_ver.log -replace dofile lib_ver.do exit -force

■

In the following command, the default compare command is replaced with two commands during each module comparison, set compare effort low and compare -abort_stop 1 -noneq_stop 1: write hier_compare dofile -compare_string \ “set compare effort low; compare -abort_stop 1 -noneq_stop 1”

■

The following command example creates a hierarchical dofile script named hier.do containing the compare script for the sub-modules and the root module, then runs hierarchical compare. This is can help in resolving aborts.
... uniquify -all write hier_compare dofile hier.do run hier_compare hier do

The following example illustrates the -KEEP_TOP_level_constraints option. For example, your dofile contains: add primary input a0/b0/scan_en -net -Golden add pin constraint 0 a0/b0/scan_en -Golden write hier_compare dofile hier.do -replace -constraints -keep_top_level_constraints -noexact_pin_match dofile hier.do ...

During hierarchical comparison, the logfile will contain the following messages:
// Running Module modB and modB // Command: set root module modB -Golden // Command: set root module modB -Revised // Command: set module property -instance /a0/b0 -Golden // Command: set module property -instance /a0/b0 -Revised // Command: report black box -NOHidden // Command: set system mode lec Applying top-level pathname-based constraints // Command: add primary input scan_en -Golden // Command: add pin constraints 0 scan_en -Golden End of top-level pathname-based constraints // Processing Golden ... // Modeling Golden ... ...

Related Commands
ADD NOBLACK BOX ANALYZE HIER_compare DELETE NOBLACK BOX READ DESIGN
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WRITE LIBRARY
WRIte LIbrary [-Verilog] [-REPlace] [-Golden | -REVised] (Setup / LEC Mode)

Writes out the Golden or Revised library to a Verilog file. The default is to write out the library as functional Verilog model descriptions. Use this command to examine how Conformal abstracts complex UDP library models. Use the tilde character (~) to shorten the path of the file.

Parameters -Verilog -REPlace -Golden -REVised Specifies the library filename. Writes out the library in Verilog format. This is the default. Replaces the existing file. Writes out only the Golden library. This is the default. Writes out only the Revised library.

Related Command
READ LIBRARY

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WRITE MAPPED POINTS
WRIte MApped Points [-CLass < Full | System | User> [-TYpe …] [-NOTYpe …] [-REPlace] (LEC Mode)

Writes the mapped point information to a file. If the comparison needs to be done at a later time, you can use this command to accelerate the mapping process. Use the READ MAPPED POINTS command to read the file. Use the tilde character (~) to shorten the file’s path.

Parameters -CLass Specifies the filename. Writes out the System, User, or Full classes of mapped points. Full System User Both the User and System class. This is the default. Key points that are mapped automatically. User class: key points that are manually mapped with the ADD MAPPED POINTS command.

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-TYpe -NOTYpe

Writes only the mapped key points of the specified type. Does not write the mapped key points of the specified type. Available types are as follows: PI: Primary input E: TIE-E Z: TIE-Z DFf: D flip-flop DLat: D-latch CUt: All unmapped points for artificial gates that break combinational loops BBox: Blackbox PO: Primary output

-REPlace

Replaces the existing file.

Related Commands
READ MAPPED POINTS WRITE PARTITION DOFILE

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WRITE MEMORY PRIMITIVE
WRIte MEmory Primitive [-Module | -All] [-REPlace] [-OPTionsdef ] [-COMmondef ] (LEC Mode)

Note: This requires a Conformal GXL license. Writes memory primitives to a file. Use this command to retrieve information for simulation. For additional information about memory primitives, refer to the “Memory Primitive Data Sheet” located at /doc/MEM_datasheet.pdf. Use the tilde character (~) to shorten the path of the file. Note: The wildcard (*) represents any zero or more characters in module names.

Parameters Specifies the filename.

-Module Writes only the memory primitives for the specified module. This accepts wildcards. -All -REPlace Writes out memory primitives for all modules. Replaces the existing file.

-OPTionsdef Writes parameter option definitions to a separate file. This will write the ‘define statements, which are options to available parameters, from the memory primitives to a separate file.

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-COMmondef Writes the common module called Vpx_wireOrlatOrff_data to a separate file. This module is common to all memory primitives. You can write common memory primitive definitions to a separate file during each call to WRITE MEMORY PRIMITIVE, or you can use an existing file using the -rep option.

Related Command
READ DESIGN

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WRITE PARTITION DOFILE
WRIte PArtition Dofile [-Map ] [-Usage] [-Replace] [-PREPEND_String ] [-APPEND_String ] [-COMPARE_String ] (Setup / LEC Mode)

Writes out a partition dofile script based on the key point names specified with the ADD PARTITION KEY_POINT command. The number of compare iterations is based on whether the key point names have all-pattern, one-hot, or one-cold constraints. Use the tilde character (~) to shorten the path of the file.

Parameters -Map -Usage -Replace The partition dofile is written to this file. Uses the specified file for key point mapping. (You must use the WRITE MAPPED POINTS command before using this option.) Executes the USAGE command after each comparison and at the end of the partition dofile. Replaces the existing file.

-PREPEND_String Appends any string of commands to the partition dofile script before key point comparison for each module. Use “;” to separate commands. Use double quotes to surround each prepended command (see “Examples” below).

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-APPEND_String Appends any string of commands to the partition dofile script after key point comparison for each module. Use “;” to separate commands. Use double quotes to surround each appended command (see “Examples” below). -COMPARE_String Replaces the default compare command with a string of compare commands in the partition dofile script generation for each module. Use “;” to separate commands. Use double quotes to surround each compare command (see “Examples”).

Example write partition dofile partition.do -replace write partition dofile ptn.do -append_string “usage” -prepend_string “report unmapped points -notmapped” -replace

In the following command, the default compare command is replaced with two commands during each module comparison, set compare effort low and compare -abort_stop 1 -noneq_stop 1: write partition dofile -compare_string “set compare effort low; compare -abort_stop 1 -noneq_stop 1”

Related Commands
ADD PARTITION KEY_POINT DELETE PARTITION KEY_POINT REPORT PARTITION KEY_POINT WRITE MAPPED POINTS

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WRITE RULE CHECK
WRIte RUle Check [-DEsign | -LIbrary] [-Golden | -REVIsed] [-Replace] (Setup Mode)

Writes the rule violations into a rule file. Use this command the first time you run a session. For later runs, exclude the violations already flagged with the read rule check -exclude command. Use the tilde character (~) to shorten the path of the file.

Parameters -DEsign Writes rule check violations to the specified file. Writes only design rule check violations. If you do not specify -design or -library, Conformal writes rule check violations from both designs and libraries. Writes only library rule check violations. If you do not specify -design or -library, Conformal writes rule check violations from both designs and libraries. Writes rule check violations from the Golden design. This is the default. Writes rule check violations from the Revised design. Replaces the previously saved file.

-LIbrary

-Golden -Revised -REPlace

Examples
In the following example, the second report rule check will not report any rules. read design g.v -golden read design r.v -revised write rule check rule.g -golden -replace write rule check rule.r -revised -replace read design g.v -golden -replace read design r.v -revised -replace report rule check -verbose -both

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Related Command
READ RULE CHECK

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Encounter Conformal Equivalence Checking Reference Manual ECO Command Reference

3
ECO Command Reference
This chapter describes the Encounter® Conformal® ECO commands. The commands are presented in alphabetical order.
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■

ADD ECO CELL on page 546 ADD ECO LIBRARY on page 547 ADD ECO PATCH on page 548 ADD ECO PIN on page 550 ADD SPARE CELL on page 552 ANALYZE ECO on page 553 APPLY PATCH on page 555 DELETE ECO CELL on page 557 DELETE ECO PATCH on page 558 DELETE ECO PIN on page 559 DELETE SPARE CELL on page 560 MAP ECO PATCH on page 561 OPTIMIZE PATCH on page 562 REPORT ECO CELL on page 566 REPORT ECO CHANGES on page 567 REPORT ECO PATCH on page 568 REPORT MISMATCH PIN on page 569 REPORT SPARE CELL on page 570 WRITE ECO DESIGN on page 571

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ADD ECO CELL
ADD ECo Cell [-DEFfile ] [-FReedcell] [-SParecell ... ] (Setup Mode)

Adds the spare cells or freed cells as the available cells for the MAP ECO PATCH command.

Parameters
-DEFfile Specifies the DEF filename. This searches for the spare cell in the DEF file. By default, the spare cell is searched for in current hierarchy. -FReedcell Specifies that freed cells will be used for mapping.

-SParecell ... Specifies the spare cells to be added. This accepts wildcards.

Related Commands
ADD SPARE CELL DELETE ECO CELL MAP ECO PATCH REPORT ECO CELL

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ADD ECO LIBRARY
ADD ECo Library [ | -ALL] [-Golden | -Revised] (Setup Mode)

Adds the library to the library list used by the by the MAP ECO PATCH command.

Parameters -ALL -Golden -Revised Specifies the name of the library. Adds all the libraries in Golden or Revised. Specifies that the library is in the Golden library. This is the default. Specifies that the library is in the Revised library.

Related Commands
MAP ECO PATCH

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ADD ECO PATCH
ADD ECo PAtch [-PATH ] (Setup Mode)

Specifies the ECO patch and adds the patch module to be mapped by the MAP ECO PATCH command.

Parameters Specifies the name of the module being changed for ECO. Specifies the name of the patch module that contains the ECO changes. [-PATH ] Specifies the hierarchy path to the module under ECO. This is for the ADD ECO CELL command to locate the freed cell locations in DEF file.

Examples
In the following command sequence, the ECOs defined in the G1_eco and G2_eco patch modules will be applied to the design and mapped to the spare cells and freed cells, and will write out the new mapped patch modules to the map.v file. add eco patch G1 G1_eco -path /U1/U1 add eco patch G2 G2_eco -path /U1/U2 add eco library typical add eco cell -def layout.def -freed -spare *spare* map eco patch map.v -replace

Related Commands
ADD ECO CELL ADD ECO LIBRARY
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ADD ECO PIN
ADD ECo PIn | ... [-INput | -OUTput | -IO] [-FORce] [-Golden | -Revised] (Setup Mode)

Adds a pin to a module. If the Revised module has extra ports, you can use this command to add new pins to the Golden module. Cadence recommends that you add the extra pins before running the WRITE HIER_COMPARE DOFILE command.

Parameters Specifies the name of the module. Specifies the name of the pin(s). Specifies the name of the bus(es), where is [msb:lsb], for example, [16:0]. You must include the braces in the command. See the Examples section. -INput -OUTput -IO -FORce -Golden -Revised Specifies that the pin is an input pin. This is the default. Specifies that the pin is a output pin. Specifies that the pin is an input/output pin. Renames the signal if it conflicts with the port name. See the Examples section. Applies to the Golden design. This is the default. Applies to the Revised design.

Examples
■

The following command adds wr_req input port and data[15:0] input bus to module mod_A add eco pin mod_A wr_req data[15:0] -input -golden

■

This example shows how the command’s -force option affects the following design: module top(x,y);

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Encounter Conformal Equivalence Checking Reference Manual ECO Command Reference wire z; endmodule

❑

The following command will error out because there is a conflict between the net z and the new port z: add eco pin -output top z

❑

The following command will not error out and net z will be renamed z_1: add eco pin -output top z -FORce

Related Commands
ANALYZE ECO DELETE ECO PIN WRITE HIER_COMPARE DOFILE

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ADD SPARE CELL
ADD SPare Cell [-DEFfile ] [-FReedcell] [-SParecell ... ] [-GAFiller ... ] (Setup Mode)

Adds the spare cells or freed cells as the available cells for the OPTIMIZE PATCH command. When using OPTIMIZE PATCH with the -usespare option, the spare cell count for each cell type is considered. When using OPTIMIZE PATCH with the -def option, the spare cell instances are considered for location-aware optimization.

Parameters
-DEFfile Specifies the DEF filename. This searches for the spare cell in the DEF file. By default, the spare cell is searched for in current hierarchy. -FReedcell Specifies that freed cells will be used for mapping.

-SParecell ... Specifies the spare cells to be added. This accepts wildcards. -GAFiller ... Specifies the gate array filler to be added. This accepts wildcards.

Related Commands
ADD ECO CELL DELETE SPARE CELL OPTIMIZE PATCH REPORT SPARE CELL

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ANALYZE ECO
ANAlyze ECo [-REPlace] [-EFFort ] [-PRESERVE_clock] (LEC Mode)

Analyzes the ECO change in the Revised root module comparing to the Golden root module. The logic change is written to the specified patch file, which contains the Verilog module with the port names corresponding to the nets in the Golden design. Note: Only the logic cone under Non-EQ points are analyzed by the command.

Parameters -REPlace Specifies the name of the patch file. Replaces the existing file.

[-EFFort ] Specifies the analysis effort level. The command default is HIGH. -PRESERVE_clock Attempts to minimize the changes to the clock network.

Examples
In the following commands, module G1 contains the placed and routed netlist, and module G2 contains the synthesized netlist from modified RTL. The two netlist will be compared first, then the ANALYZE ECO command will analyze the change implemented by G2 and generates a patch file, which contains a single Verilog module G1_eco. The patch can then can be read back and applied to G1 with the APPLY PATCH command, such that the G1 will be equivalent to G2, meaning that G1 implements the ECO change in G2. Note: The patch can be remapped or optimized by other tools before it is read back.
SETUP> set root module G1 -golden SETUP> set root module G2 -revised SETUP> set system mode lec LEC> add compare point -all LEC> compare

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LEC> analyze eco patch.v -replace SETUP> set system mode setup SETUP> read design patch.v -append SETUP> apply patch G1 G1_eco

Related Commands
ADD ECO PATCH APPLY PATCH COMPARE WRITE HIER_COMPARE DOFILE

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APPLY PATCH
APPly PAtch [ | -AUTO] [-KEEPHierarchy | -NOKEEPHierarchy] [-NETnaming ] [-INStancenaming ] [-SEQuentialnaming ] [ | -KEEPFREED | -TIEFREED0 | -TIEFREED1] [-AUTO] [-Golden | -Revised] (Setup Mode)

Applies the ECO change specified in the patch module, generated by the ANALYZE ECO command, to the module under ECO. The patched module can be written out with the WRITE DESIGN command. Note: The patch generated by the ANALYZE ECO command can contain unmapped primitives. You can use the synthesis tool or the MAP ECO PATCH command to map the patch.

Parameters Specifies the name of the module being changed for ECO. Specifies the name of the patch module containing the ECO changes. -AUTO -KEEPHierarchy -NOKEEPHierarchy Does not put ECO changes in a submodule. -NETnaming Specifies the net naming format of the ECO nets. For example, for eco_net_%d, the %d will be an integer that makes the net name unique. Automatically reads in and applies all patches that were created with the ANALYZE ECO command in the current session. Specifies that the ECO changes will be put in a submodule. This is the default.

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-INStancenaming Specifies the instance naming format of the ECO combinational cells. For example, for eco_instance_%d, the %d will be an integer that makes the instance name unique. -SEQuentialnaming Specifies the instance naming format of the ECO registers and latches. For example, eco_%s, where %s is the original register name. -KEEPFREED -TIEFREED0 -TIEFREED1 -Golden -Revised Retains all freed instances and leaves input pins connected. Retains all freed instances and applies a value of ’0’ (tie low) to the input pins of any freed instance. Retains all freed instances and applies a value of ’1’ (tie high) to the input pins of any freed instance. Applies to the Golden design. This is the default. Applies to the Revised design.

Related Commands
MAP ECO PATCH OPTIMIZE PATCH

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DELETE ECO CELL
DELete ECo Cell [-FReedcell ] [-SParecell ] [-ALL] (Setup Mode)

Deletes the spare cells or freed cells from the available cells for the MAP ECO PATCH command.

Parameters
-FReedcell -SParecell -ALL Specifies the name(s) of the freed cell(s) to be deleted. This accepts wildcards. Specifies the name(s) of the spare cell(s) to be deleted. This accepts wildcards. Deletes all the cells.

Related Commands
ADD ECO CELL DELETE SPARE CELL MAP ECO PATCH REPORT ECO CELL

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DELETE ECO PATCH
DELete ECo PAtch [-ALL| [] ] (Setup Mode)

Deletes the ECO patch from the module list to be mapped by the MAP ECO PATCH command.

Parameters
-ALL Deletes all the added ECO patches.

Specifies the name of the module to delete Specifies the name of the patch module that contains the ECO changes.

Related Commands
ADD ECO PATCH MAP ECO PATCH REPORT ECO PATCH

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DELETE ECO PIN
DELete ECo PIn | ... [-KEEPFreed] [-Golden | -Revised] [-REPort ] (Setup Mode)

Deletes the pins from the module.

Parameters Specifies the name of the module. Specifies the name of the pin(s). Specifies the name of the bus(es). Note: You cannot delete only partial bits. For example, if there is a bus port OUT[1:0], the command should be: delete eco pin top OUT

not delete eco pin top OUT[1:0]

-KEEPFreed -Golden -Revised -REPort

Deletes only the pin, but does not free up the unreachable instances and nets. Applies to the Golden design. This is the default. Applies to the Revised design. Specifies the name of the report.

Related Commands
ADD ECO PIN MAP ECO PATCH REPORT MISMATCH PIN

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DELETE SPARE CELL
DELete SPare Cell [-FReedcell ... ] [-SParecell ... ] [-ALL] (Setup Mode)

Deletes the spare cells or freed cells that were added with the ADD SPARE CELL command.

Parameters
-FReedcell -SParecell -ALL Specifies the name(s) of the freed cell(s) to be deleted. This accepts wildcards. Specifies the name(s) of the spare cell(s) to be deleted. This accepts wildcards. Deletes all the cells.

Related Commands
ADD SPARE CELL OPTIMIZE PATCH

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MAP ECO PATCH
MAP ECo Patch [-NOConstraint] [-REPlace] (Setup Mode)

Maps the ECO patch(es), specified by the ADD ECO PATCH command, to the available ECO cells. The available ECO cells are specified by the ADD ECO CELL command. The target technology libraries are specified by the ADD ECO LIBRARY command.

Parameters -NOConstraint Specifies the file name for the mapped netlist. Specifies that the mapping process will use the cells in the ECO library to implement the patch. Use this option for a pre-mask ECO. Replaces the existing file.

-REPlace

Related Commands
ADD ECO CELL ADD ECO LIBRARY ADD ECO PATCH OPTIMIZE PATCH

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OPTIMIZE PATCH
OPTimize PAtch -WORKdir -LIBrary [-RCExec ] [-SDC ] [-VERbose] [-KEEPHierarchy | -NOKEEPHierarchy] [-CLEANUP] [-AVOID *] [-USE *] [-POSTLIBscript ] [-POSTSYNscript ] [-PRESYNscript