Gate Effect on Nanowire Tunneling Field Effect Transistor (FET)
Bai Ke, Department of Electrical & Computer Engineering, National University of Singapore
Abstract—The simulation study on Si Nanowire Tunneling Field-Effect Transistor (TFET) has been conducted in this project. A device performance comparison was carried out between Double Gate (DG) Tunneling Field-Effect Transistor and Gate All Around Si Nanowire (GAA SiNW) Tunneling Field-Effect Transistor. The device physics and electrical characteristics of the GAA SiNW TFET are investigated for better performance of gate control and low power consumption for the future scaling applications. Due to the high electric filed generated under the gate bias GAA SiNW TFET has high Ion and steep subthreshold swing. It is shown for the first time that subthreshold swing S is proportional to the diameter of the SiNW TFET and decreasing the diameter will lead to a better Ion /Ioff ratio. Device design and physics detailing the impact of drain and source engineering was discussed for SiNW TFET for lower off-state leakage current and a higher Ion with a steeper subthreshold swing S. Lastly, we have also investigated the effect of using high-k dielectric material and shorter gate length for SiNW for the future device applications. I. INTRODUCTION gate modulation gives a better Subthreshold swing which is smaller than 60 mV/decade and Lower Ioff Leakage Current of 10-14 A/um.[1],[2] Apart from Tunneling Field-Effect Transistor (TFET), Si Nanowires MOSFETs have been considered as the novel channel materials for the next-generation FET-type devices due to their novel material having promising device performance and novel transport characteristics. The outstanding performance of Si NW MOSFET is already shown in terms of high Ion /Ioff ratio and good subthreshold swings.[3],[4] We would integrate the SiNW to the channel of the TFET to achieve a better performance. The structure of the Si gate all around (GAA) Nano-wire structure is shown in Fig. 2. The TFET devices can give lower Ioff leakage current comparing to C-MOSFET. In experiment, a low leakage current less than 10-14 A/um can be realized. The working principle of a TFET was shown in Fig. 3.

T

he ITRS "roadmap", describing forecasts and technology barriers to development for device sizes updated approximately annually. In the recent white paper, the ITRS shows that the semiconductor industry has entered the 65 nm scale in 2007 and the scale process and optimization of the Nano device is still a favorable issue for engineers. The Tunneling Field-Effect Transistor (TFET) is a new kind of electronic transistor that has been proposed in the recent years to overcome the limitation of increase drain current and lower the power consumption. A basic TFET device structure is shown in Fig. 1.

Fig. 3. Band diagrams for gate controlled band-to-band tunneling in TFET with 100 nm channel length. The n+ region is positive biased and the p+ region is grounded. The band diagrams are extracted along the cutline 2 nm away from the Si–SiO2 interface in a simulated 2-dimensional structure. Retrieved from P.-F. Wang et al. / Solid-State Electronics 48 (2004) 2281–2286.

Fig. 1. Schematic of structure of an n-channel Si or Ge TFET with a p+ source and n+ drain. Retrieved from: E.H Toh, et.al /Journal of Applied physics, Vol. 103.Pp:104504/1-5.

Fig. 2. Structure of SiNW MOSFET Retrieved from: Gengchiau, Liang, IEEE Electronic Device, p129, 2007

Experimental results of tunneling field effect transistor TFETs has shown the excellent channel control through the

When a negative gate voltage is applied, electrons can tunnel from the valence band (p+ doped) to the conduction band (n+ region) while the generated holes flow to the p+ drop region. A large current will be generated in this case. However, when the gate bias is zero, the large tunneling barrier will make it difficult for electrons to move from the p+ region to n+ region. This characteristic enables TFET possessing a very low sub-threshold leakage current. The sub-threshold swing (S) is the voltage required to increased or reduce Id by one decade. Various simulation studies on TFET have shown that the 60 mV/dec is not a limitation for sub-threshold swing. The lower leakage current and sub-threshold swing of TFET give rise to low power consumption and eventually benefit semiconductor industry which is an important issue for the integrated circuit today.

II. TFET SIMULATION STUDY A. Background TFET simulations and analysis have been done for SGTFET and MOSFET under the same device dimension. By vary the device parameters such as oxide thickness Tox and doping profile. We are aim to investigate the design and configuration for TFET device. The following features have been proved for TFET which has lower leakage current and lower Sub-threshold Swing S. B. SGTFET and MOSFET simulation The Conventional N-MOSFET and SG TFET devices need to be set up under same physical dimension. The MOSFET has an N-type doping concentration for source and drain of 1020 cm-3. Channel is P-type doped 5×1016 cm-3 with a 45 nm gate length is and 1nm thickness for SiO2 layer under gate. For SGTFET source doping is P-type 1020 cm-3 and drain doping has been modified as N-type 1019 cm-3 to achieve lower leakage current. 1) Device performance Fig. 4. shows the Id-Vg curve for both NMOSFET and SGTFET at VDS=1.2V:
MOSFET vs SGTFET
1. 00E- 02 1. 00E- 03 1. 00E- 04 1. 00E- 05 1. 00E- 06 1. 00E- 07 1. 00E- 08 1. 00E- 09 1. 00E- 10 1. 00E- 11 1. 00E- 12 1. 00E- 13 1. 00E- 14 1. 00E- 15 1. 00E- 16

Therefore, equation (1) can be expressed as:

q s (VGS ) ) (2) kT For very thin oxide and a non-degenerate doping for MOSFET, by the definition of subthreshold swing: I D C s (VGS ) 1/ 2 exp( kT ln10 q (3) Therefore, the limit for subthreshold swing S for MOSFET is 60 mV/dec.(at 300 K) S (d log Id / dVgs ) 1
In an band to band tunneling transistor, the drain current flows across a degenerately doped p+ or n+ tunnel junction, a transport mechanism that is particularly well described, in the reverse, Zener tunneling direction, by Sze:[6] b I aVeff exp (4) Veff where is the tunnel–junction bias, ξ is the electric field, a and b are coefficients determined by the materials’ properties of the junction and the cross-sectional area of the device A.
3

a

Aq3

2m */ Eg 4 22

b

Log Id (Amps/um)

, ,where m * is the carrier effective mass, Eg is the energy band gap, and  is Planck’s constant divided by 2π. This shows the tunneling current density is proportional to the magnitude of the electric field. The derivative of the tunneling current equation of (4) with respect to the gate-source voltage can be used to determine the expression for the subthreshold swing of a field-effect tunneling transistor.[5]
S ln10

4 m *Eg2 3q ,

NMOSFET SGTFET
- 0. 20 - 0. 15 - 0. 10 - 0. 05 0. 00 0. 05 0. 10 0. 15 0. 20 0. 25 0. 30 0. 35 0. 40 0. 45 0. 50 0. 55 0. 60 0. 65 0. 70 0. 75 0. 80 0. 85 0. 90 0. 95 1. 00 1. 05 1. 10 1. 15

V (Volts)

Fig. 4. Id-Vg curve for both NMOSFET and SGTFET at VDS=1.2V

The MOSFET has one order higher current at on state and 6 order higher leakage current than SGTFET. This proves the lower leakage for SGTFET. Moreover, SGTFET has a much steeper subthreshold swing of 32.6 mV/dec, while MOSFET keep a subthreshold swing of 75.7 mV/dec. 2) Results analysis In normal MOSFET, the current has two mechanisms which are draft and diffusion. However, subthreshold current is dominated only by diffusion, just like the bipolar transistor, which can be described in equation (1): dn n(0) n(L) ID qADn qADn (1) dx L ,where, q is the electron charge, A is the area of the channel, For quantum approximation:[5] q s

(5) This suggests transistor geometry with a thin and/or high-κ gate dielectric and an ultrathin body to assure that the gate field directly modulates the channel. The second term derivative of the junction electric field on the gate-source voltage should be maximized. In such a device, the gate-source voltage changes the tunneling width and increases the junction electric field.

1 dVeff Veff dVGS

1

b d 2 dVGS

III. SINW TFET SIMULATION STUDY By integrating GAA SiNW channel device with tunneling field effect transistor (TFET), we would like to compare the gate control with Double Gate TFET. Furthermore investigation on impact of SiNW dimension, S/D doping, High-k dielectric material and shrinking gate length was discussed for future application. A. DGTFET vs. GAA SiNW For both of the devices, source doping is P-type 1020 cm-3 and drain doping is N-type 1019 cm-3. Channel is P-type doped

q(

n(0) np0e kT
A W d2DEG

n(L) np0e kT W (2qN A q s s Vds ) kT

/ s)

1/ 2

5×1016 cm-3 with a 45 nm gate length is and 1nm thickness for oxide. We make the body thickness/diameter of 10 nm respectively for DGTFET and SiNW. 1) Device performance Fig. 5. shows the Id-Vg curve for both DGTFET and SiNW at VDS=1.2V:
SiNW vs DGTFET (10nm)
1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 1.00E-11 1.00E-12 1.00E-13 1.00E-14 1.00E-15 DG TFET D=10nm
-0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20

denoted the Zener tunneling current in equation (4). The tunneling current is proportional to the electric field along the tunneling direction. Hence, a higher electric field along the tunneling direction will lead to a higher Id. However slightly thinner tunneling barrier width WT gives out DGTFET a slightly better subthreshold swing S, as shown in Fig. 6: B. Dimension dependency of the SiNW TFETs In this part of the simulation, we set up the GAA SiNW devices and explore the dimension effect by changing the diameter of the SiNW while keep other device parameters constant. 1) Device performance Fig. 7. Shows the Id-Vg curve for SiNW TFET when diameter varies while keep other device parameters constant. The device operates at VDS = 1.2V
SiNW device at different diameter
1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 1.00E-11 1.00E-12 1.00E-13 1.00E-14 1.00E-15 1.00E-16
SiNW D=20nm SiNW D=10nm SiNW D=6nm

Log Id (Amps/um)

SiNW TFET D=10nm

Vg (Volts)

We abstract the data obtained from Fig. 5: DG TFET (10nm) Sub-threshold Swing S 33.785 (mV/dec) Ioff (Vg=0v) (amps/um) 9.02E-16 Ion (Vg=1.2v) (amps/um) 2.37E-05 Ion/ Ioff ratio 2.63 E10

SiNW (10nm) 35.030 3.67E-15 3.70E-05 1.01 E10

Log Id (Apms/um)

Fig. 5. Id-Vg curve for 10nm body thickness DGTFET and 10nm diameter SiNW TFET when same device physics are used. The device operates at VDS=1.2V

SiNW has higher Id, means both on state current and off state leakage current are higher than DG TFET. The Id (SiNW) is 1.5 times of Id (DGTFET) at on state Vg = 1.20V and 4 times of Id (DGTFET) at off state Vg = 0V. SiNW has a very similar but slight bigger Sub-threshold Swing than DG TFET. 2) Results analysis
1. 5 1

Fig. 7. Id-Vg curve for 45nm channel length device of SiNW TFET with different diameters. The device operates at VDS = 1.2V

The decrease in SiNW diameter will increase the on state drain current. Smaller diameter also leads to a higher band to band tunneling rate GBTBT and steeper Sub-threshold Swing S 2) Results analysis In order to prove the above statement, we need to draw the band diagram for the three devices to verify above relationship between the SiNW diameter and tunneling width WT. A comparison between band diagram along source to drain direction for 6nm 10 nm 20nm SiNW at depth of 1.5 nm was draw. SiNW Diameter 6nm 10nm 20nm

Par t i al Band di agr am of Si NW and DG TFET ( Vd=Vg=1. 2V)
Ev Ec Ev Ec Si N W Si N W D TFET G D TFET G

El ect r on Pot ent i al ( eV)

0. 5 0
0. 0300 0. 0319 0. 0335 0. 0349 0. 0360 0. 0370 0. 0378 0. 0385 0. 0391 0. 0396 0. 0400 0. 0404 0. 0408 0. 0412 0. 0415 0. 0419 0. 0422 0. 0425 0. 0428

0. 0431

0. 0434

0. 0436

- 0. 5 -1 - 1. 5 -2

0. 0439

Tunneling width WT

X( M cr ons) i

Fig. 6. Zoom in band diagram of tunneling barrier between source and channel at VDS=VGS=1.2V

Comparing the total electric filed along the current, the SiNW has bigger area of high electric field. As we have

As we decrease the diameter of SiNW, the tunneling barrier width also decreased, therefore thinner tunneling barrier would enable easier tunneling and smaller Sub-threshold Swing. Therefore, we concluded that the smaller the diameter of SiNW the smaller Sub-threshold Swing S. However, if we increase the diameter beyond the boundary of 20 nm, SiNW will enter the state of surface inversion and cause the saturation for Sub-threshold Swing. Fig. 8. Shows the diameter dependence of the Sub-threshold Swing S.

-0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15
Vg (Volts)

3.6 nm

4.9 nm

5.7 nm

Diameter dependence for S
90
1.0000E-12
Leakage current (Amps/um)

leakage current vs Drain doping

Subthreshold Swing S

80 70 60 50 40 30 20 10 0 6nm 10nm Diameter 20nm 14.497 35.030 68.326

76.460

1.994E-13 1.0000E-13

1.0000E-14 3.674E-15 1.0000E-15 3.204E-16 1.0000E-16 5.264E-16 leakage current 2.00E+20

GAA SiNW

30nm

1.00E+17

1.00E+18 1.00E+19 Drain doping (cm-3)

Fig.8. Diameter dependence of the Sub-threshold Swing S for SiNW.

Fig. 10. The impact on the leakage current by varying drain doping concentration ND

C. S/D doping of the SiNW TFETs 1) Drain doping engineering In this part of the simulation, GAA SiNW diameter is 10nm. We fixed the source doping concentration at 1E20 cm-3 and vary the drain doping concentration. In order to achieve low tunneling leakage current, the drain should be modified in such way that lower leakage current is achieved while not affecting the on drain current.[7]
Id Vg at Different Drain doping
1.0000E-03 1.0000E-04 1.0000E-05 1.0000E-06

2) Source doping engineering In this part of the simulation, GAA SiNW device has diameter of 10nm. We fixed the drain doping concentration at 1E19 cm-3 and vary the source doping concentration. The device performance at different source doping was shown below in Fig. 11.
IdVg at Different Source doping
1.00E-03 1.00E-04 1.00E-05 1.00E-06

Log Id (Amps/um)

1.00E-07 1.00E-08 1.00E-09 1.00E-10 1.00E-11 1.00E-12 1.00E-13 1.00E-14 1.00E-15 Ns=1E19 Ns=5E19 Ns=1E20 Ns=5E20

Log Id(Amps/um)

1.0000E-07 1.0000E-08 1.0000E-09 1.0000E-10 1.0000E-11 1.0000E-12 1.0000E-13 1.0000E-14 1.0000E-15 1.0000E-16
-0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20

Drain doping = 1E18 Drain doping = 1E19 Drain doping = 2E20

Vg (Volts)

Fig. 11. Id-Vg curve of SiNW at different source doping at VDS =1.2V

Fig. 9. Id-Vg curve of SiNW at different drain doping at VDS=1.2V

The data obtained from Fig. 11.
Sub-threshold Swing S Ioff (VGS = 0 v) (amps/um) Ion (VGS =1.2 v) (amps/um) Ion/ Ioff ratio SiNW (NS =1E19) 62.902 (mv/dec) 1.21E-15 4.74E-08 3.92 E07 SiNW (NS =1E20) 35.030 (mv/dec) 3.67E-15 5.89E-05 1.60 E10 SiNW (NS =5E20) 24.696 (mv/dec) 2.27E-13 3.77E-04 1.66 E09

There is one order increase for leakage current when we increase the drain doping by one order. However, the on state drain current is not affected much by the change of drain doping. All the doping concentration profile has the very similar drain current for Ion. The reason is lower drain doping concentration will affect the electric field at the drain junction and results in an increase in tunneling barrier width leading to the reduced off-state leakage current. Thus, drain engineering is the key to optimal TFET device performance. We have plotted the off-state leakage current Ioff as a function of drain doping concentration ND in Fig. 10. With lower ND, Ioff is substantially reduced, meeting the low power specifications of logic devices. There is an exponential increase for Ioff when higher ND was doped.

The Ion/Ioff ratio improves when we increase the doping concentration of source. Higher source doping concentration leads to a higher on state drain current and the smaller Sub-threshold Swing S. We have draw Fig. 11 and Fig. 12 to show the impact on Ion and subthreshold swing S by various source doping concentration.

-0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15
Vg (Volts)

Ion at various source doping
1.00E-03
3.77E-04

Different oxide material
1.00E-03 1.00E-04 1.00E-05 1.00E-06

Log Id(Amps/um)

1.00E-04
5.89E-05

1.00E-07
Log Id (Amps/um)

1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E+19
4.74E-08

1.00E-08 1.00E-09 1.00E-10 1.00E-11 Hfo2 SiO2

4.34E-06

On current 5.00E+19 1.00E+20 Source doping (cm-3) 5.00E+20

1.00E-12 1.00E-13 1.00E-14 1.00E-15
-0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20

Fig. 11. The impact on Ion by varying source doping concentration at VGS= VDS=1.2V
Sub-threshold Swing S dependence on Source doping
70

Vg (Volts)

Fig. 13. Id-Vg curve for 45nm channel length device of SiNW TFET with 1nm thickness of HfO2. The device operates at VDS = 1.2V.

Sub-threshold Swing S (mV/decade)

60 50 40 30 20 10 0 1.00E+19 5.00E+19 1.00E+20 Source doping (cm-3) 5.00E+20 62.901

40.610 35.030 32.369 GAA SiNW

Fig. 12 The impact on Subthreshold swing S by varying source doping concentration

As shown in Fig. 11, Ion as a function of NS, increases four orders of magnitude for source doping from 1E19 cm-3 to 1E20 cm-3 for NS. We could see that the increase in Ion is exponential first. For NS beyond 1E20 cm-3, Ion starts to saturate. Basically, higher the source doping concentration leads to higher the on state current. In Fig. 12. We could see that the decrease in Subthreshold swing S is exponential first. For NS beyond 1E20 cm-3, the decrease of Subthreshold swing S starts to saturate. The overall impact is the higher the source doping concentration NS the smaller Sub-threshold Swing S. Higher source doping NS results in more BGN. Thus, the higher built-in field exists and BGN effect contributes to a narrower WT. The narrower WT, contributes to a higher on current and much steeper S. D. Different gate dielectric material for SiNW TFETs 1) High k dielectric HfO2 under same physical thickness In this part of the simulation, we set up the GAA SiNW devices 10 nm diameter as same as pervious chapter, while keeping the doping profile as constant. We changed the oxide material from SiO2 to HfO2 and keep the physical thickness of the oxide Tox = 1nm. Fig. 13. shows Id-Vg curve for SiNW TFET when oxide material changed to high k dielectric material HfO2, while keep the same physical oxide thickness. The device operates at VDS = 1.2V.

The high k dielectric material HfO2 has almost one order higher Ion and one order lower Ioff than SiO2. A better Ion/ Ioff ratio was also present in the device simulation results for HfO2.As shown in Fig. 13, the high k dielectric material HfO2 also improves Sub-threshold Swing S. We could explain this by gate capacitance. It is known that when the insulator has the same physical thickness, higher – k value will lead to higher permittivity, therefore larger capacitance. When the same amount gate voltage is applied, the device with lager capacitance will have larger magnitude of charge changing, that is, the more electrons will be attracted under gate and thus stronger depletion layer will be formed. This heavy electron concentration under gate will help to pull down the potential band diagram near source side and thus thin the tunneling barrier is obtained higher drain current and smaller Subthreshold swing S. 2) HfO2 with same Equivalent Oxide Thickness EOT The EOT has been kept at 1nm in simulation, that is, for SiO2 based insulator layer the physical thickness is 1nm. For the purpose of keeping same capacitance for different dielectric materials, the physical thickness for HfO2 can be calculated by using formula: A A C TSiO2 THfO2 For dielectric constant of SiO2 is 3.9, HfO2 is 21. Therefore: T (Hfo2) = 5.38nm Fig. 14. shows the Id-Vg curve for SiNW TFET when oxide material changed to high k dielectric material HfO2, with the same equivalent oxide thickness (EOT). The device operates at VDS = 1.2V. As we seen from the figure, the high k dielectric material HfO2 with same equivalent thickness (EOT) has very similar Ion and Ioff with SiO2. However, for HfO2 Ion is lower than SiO2 which is out of our expectation. The high k dielectric material HfO2 under same (EOT) does not improve the Sub-threshold Swing S.

IdVg at different gate length
1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07
Log Id (Amps/um)

1.00E-08 1.00E-09 1.00E-10 1.00E-11 1.00E-12 1.00E-13 1.00E-14 1.00E-15
-0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15

Lg = 45nm Lg = 32nm Lg = 22nm Lg = 16nm

Vg (Volts)

Fig. 14. The Id-Vg curve for 45nm channel length device of SiNW TFET with same equivalent thickness (EOT) of HfO2. The device operates at VDS = 1.2V.

Fig. 15. The Id-Vg curve of SiNW TFET with various gate length, device operates at VDS = 1.2V.

Data obtained from Fig. 15.
SiNW

When the insulator material has the same equivalent oxide thickness (EOT), theoretically, the capacitance is the same for different dielectric material devices at the same EOT, that is, the same Id-Vg curve is expected. However, in Fig . 14. We could find that the Id (HfO2) with higher – k is slightly lower than the Id (SiO2 ) in both cases where the devices possess the same EOT at 1nm. We would like to explain the above contradictory by considering the fringing field effect at the gate edge where the fringing field capacitance induced during device operation.[8] For the same EOT devices with different dielectric material, the insulator capacitance under gate is same, whereas the insulator physical thickness for HfO2 (t = 5.38nm) is much larger than that for SiO2 (t = 1nm). The total capacitance will be denote as: C Total = C Fringing + C Gate , since CFringing is higher in device with SiO2 than that in HfO2 due to a smaller physical thickness. The CGate is same for same EOT devices regardless of material. Therefore, overall gate capacitance is higher for SiO2. As we discussed before, the larger capacitance is, the thinner tunneling barrier will be obtained and thus give us higher drain current. E. Shrinking gate length for SiNW TFETs We follow the chain of 45 nm, 35nm, 22nm, 16nm gate length. In this part of the simulation, while keeping other device parameters constant. We vary the gate length to check the device performance. The device specification is: Diameter = 10 nm Tox = 1nm Source doping concentration=1020 cm-3 Drain doping concentration =1019 cm-3 Channel doping concentration =5×1016 cm-3 Fig. 15. Shows the Id-Vg curve of SiNW TFET with various gate length, device operates at VDS = 1.2V.

LG

45 nm 35.030 3.67E-15 5.89E-05 1.60 E10

35 nm 75.273 2.72E-13 2.46E-05 9.04E07

22 nm 87.829 4.73E-12 2.94E-05 6.22E06

16 nm 108.802 9.78E-11 4.26E-05 4.32E05

Sub-threshold Swing S Ioff (VGS = 0 v) (amps/um) Ion (VGS =1.2 v) (amps/um) Ion/ Ioff ratio

The device performances become worse when we decrease the length of the gate, as we observed from Fig 4.26. Sub-threshold Swing S increases when we decrease the gate length. The Ioff also increases by four orders when we decrease the gate length from 45nm to 16nm. The on state current Ion does not show liner relation with the gate length.This is because the 45nm SiNW TFET device is already well established, while other devices need further optimization. Theoretically, the shorter the gate length, the stronger the electric field would apply on the channel. More channel inversion will cause effectively BGN to pull down the energy band. Therefore, more electrons would tunneling through and we will have a higher Ion and steeper Subthreshold swing S. For the leakage current we still need to find the reason for the four orders increase when shorter gate length was used. We have to draw the energy band diagram to show the gate control of SiNW device. For an easy observation, we draw the band diagram for gate length of 45nm and 16nm for comparison. As we can see from Fig. 16 since the gate length is big, the energy band under gate region has a better ability to prevent the channel-drain junction band downwards from the influence of drain bias. The leakage current needs to tunnel through a big barrier width under zero gate bias. Therefore, the leakage current is suppressed by big tunneling barrier the channel-drain junction.

through applying various gate voltages, we have proved the TFET’s improved short channel characteristics and a significantly smaller static leakage current compared to the standard MOSFET. In Section III, the Si Nanowire TFET has been introduced to our simulation. Specifically, by constructing the 1D Gate All Around Si Nanowire (GAA SiNW) and comparing with Double gate DG TFET in terms of leakage current, Ion/I off ratio and Sub-threshold Swing, we have progressively investigate the gate effect of SiNWs TFETs. Besides, device physic design guideline investigation has been done for SiNWs. We have find out the some key device optimal parameters such as diameter dependence, S/D doping, different oxide thickness and materials and gate length. Due to time limit, the design physic of SiNW study still need further investigation such as the oxide thickness and materials and gate length optimization. ACKNOWLEDGMENT The author would like to express his sincere appreciation to the following people in the Department of Electrical and Computer Engineering, National University of Singapore. Thanks Professor Geng-Chiau, Albert Liang and Samudra Ganesh Shankar, who is my FYP co-supervisor, for their support and guide when I am facing difficulties. Dr.Zhao Hui and Ms Fan Lu, thanks for their helps on simulation. Mr. Kai Tai Lam, thanks for his lecture for our FYP group meeting and technical support on simulation. Thank all of them.
Fig. 17. Energy band diagram along the source-to-channel direction for SiNW 16 nm gate length at VDS =1.2 V.

Fig. 16. Energy band diagram along the source-to-channel direction for SiNW 45 nm gate length at VDS =1.2 V.

REFERENCES
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As shown in Fig. 17. the band under gate region is much shorter for 16 nm gate length device. There is huge band bending in the channel-drain junction caused by the drain bias. This phenomenon actually reduces the control ability of the gate to withhold the energy band towards drain bias and results in a thin tunneling barrier in the channel-drain junction. Therefore, bigger leakage current was present for shorter gate length devices. We could propose some methods to overcome the above problems to improve the short gate length device performance. Firstly, we can reduce the oxide thickness or change to some high-k dielectric materials to enhance the gate control to be able hold the energy band in channel region. Alternatively, as we have discussed in section B, we could reduce the diameter of the SiNW to have the same effect. This could be further done in the future. IV. CONCLUSION In Section II of this project, we are interested in investigating characteristic of Nano scale TFET. Both conventional MOSFET and TFET were constructed under the same physical design. By comparing the device characteristics

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