INTEGRATED CIRCUITS

DATA SHEET

PCD8544 48 × 84 pixels matrix LCD controller/driver
Product specification File under Integrated Circuits, IC17 1999 Apr 12

Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
CONTENTS 1 2 3 4 5 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.7.1 7.8 FEATURES GENERAL DESCRIPTION APPLICATIONS ORDERING INFORMATION BLOCK DIAGRAM PINNING Pin functions R0 to R47 row driver outputs C0 to C83 column driver outputs VSS1, VSS2: negative power supply rails VDD1, VDD2: positive power supply rails VLCD1, VLCD2: LCD power supply T1, T2, T3 and T4: test pads SDIN: serial data line SCLK: serial clock line D/C: mode select SCE: chip enable OSC: oscillator RES: reset FUNCTIONAL DESCRIPTION Oscillator Address Counter (AC) Display Data RAM (DDRAM) Timing generator Display address counter LCD row and column drivers Addressing Data structure Temperature compensation 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 8.4.1 8.5 8.6 8.7 8.8 8.9 9 10 11 12 12.1 12.2 13 14 14.1 14.2 15 16 17 INSTRUCTIONS Initialization Reset function Function set Bit PD Bit V Bit H Display control Bits D and E Set Y address of RAM Set X address of RAM Temperature control Bias value Set VOP value LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS Serial interface Reset

PCD8544

APPLICATION INFORMATION BONDING PAD LOCATIONS Bonding pad information Bonding pad location TRAY INFORMATION DEFINITIONS LIFE SUPPORT APPLICATIONS

1999 Apr 12

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Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
1 FEATURES 2 GENERAL DESCRIPTION

PCD8544

• Single chip LCD controller/driver • 48 row, 84 column outputs • Display data RAM 48 × 84 bits • On-chip: – Generation of LCD supply voltage (external supply also possible) – Generation of intermediate LCD bias voltages – Oscillator requires no external components (external clock also possible). • External RES (reset) input pin • Serial interface maximum 4.0 Mbits/s • CMOS compatible inputs • Mux rate: 48 • Logic supply voltage range VDD to VSS: 2.7 to 3.3 V • Display supply voltage range VLCD to VSS – 6.0 to 8.5 V with LCD voltage internally generated (voltage generator enabled) – 6.0 to 9.0 V with LCD voltage externally supplied (voltage generator switched-off). • Low power consumption, suitable for battery operated systems • Temperature compensation of VLCD • Temperature range: −25 to +70 °C. 4 ORDERING INFORMATION

The PCD8544 is a low power CMOS LCD controller/driver, designed to drive a graphic display of 48 rows and 84 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCD8544 interfaces to microcontrollers through a serial bus interface. The PCD8544 is manufactured in n-well CMOS technology. 3 APPLICATIONS

• Telecommunications equipment.

PACKAGE TYPE NUMBER NAME PCD8544U − DESCRIPTION chip with bumps in tray; 168 bonding pads + 4 dummy pads VERSION −

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Product specification

48 × 84 pixels matrix LCD controller/driver
5 BLOCK DIAGRAM

PCD8544

handbook, full pagewidth

C1 to C83

R0 to R47

COLUMN DRIVERS VLCD2 BIAS VOLTAGE GENERATOR DATA LATCHES

ROW DRIVERS

SHIFT REGISTER RESET

RES

VLCD1

VLCD GENERATOR DISPLAY DATA RAM (DDRAM) 48 × 84

OSCILLATOR

OSC

VDD1 to VDD2 VSS1 to VSS2 ADDRESS COUNTER

TIMING GENERATOR

T1 T2 T3 T4

DISPLAY ADDRESS COUNTER

DATA REGISTER

PCD8544

I/O BUFFER

MGL629

SDIN

SCLK

D/C

SCE

Fig.1 Block diagram.

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Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
6 PINNING SYMBOL R0 to R47 C0 to C83 VSS1, VSS2 VDD1, VDD2 VLCD1, VLCD2 T1 T2 T3 T4 SDIN SCLK D/C SCE OSC RES DESCRIPTION LCD row driver outputs LCD column driver outputs ground supply voltage LCD supply voltage test 1 input test 2 output test 3 input/output test 4 input serial data input serial clock input data/command chip enable oscillator external reset input 6.1.8 SCLK: SERIAL CLOCK LINE 6.1.7 SDIN: SERIAL DATA LINE Input for the data line. 6.1.5

PCD8544
VLCD1, VLCD2: LCD POWER SUPPLY

Positive power supply for the liquid crystal display. Supply rails VLCD1 and VLCD2 must be connected together. 6.1.6 T1, T2, T3 AND T4: TEST PADS

T1, T3 and T4 must be connected to VSS, T2 is to be left open. Not accessible to user.

Input for the clock signal: 0.0 to 4.0 Mbits/s. 6.1.9 D/C: MODE SELECT

Input to select either command/address or data input. 6.1.10 SCE: CHIP ENABLE

dummy1, 2, 3, 4 not connected Note 1. For further details, see Fig.18 and Table 7. 6.1 6.1.1 Pin functions R0 TO R47 ROW DRIVER OUTPUTS

The enable pin allows data to be clocked in. The signal is active LOW. 6.1.11 OSC: OSCILLATOR

These pads output the row signals. 6.1.2 C0 TO C83 COLUMN DRIVER OUTPUTS

When the on-chip oscillator is used, this input must be connected to VDD. An external clock signal, if used, is connected to this input. If the oscillator and external clock are both inhibited by connecting the OSC pin to VSS, the display is not clocked and may be left in a DC state. To avoid this, the chip should always be put into Power-down mode before stopping the clock. 6.1.12 RES: RESET

These pads output the column signals. 6.1.3 VSS1, VSS2: NEGATIVE POWER SUPPLY RAILS

Supply rails VSS1 and VSS2 must be connected together. 6.1.4 VDD1, VDD2: POSITIVE POWER SUPPLY RAILS

This signal will reset the device and must be applied to properly initialize the chip. The signal is active LOW.

Supply rails VDD1 and VDD2 must be connected together.

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Product specification

48 × 84 pixels matrix LCD controller/driver
7 7.1 FUNCTIONAL DESCRIPTION Oscillator 7.4 Timing generator

PCD8544

The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input. 7.2 Address Counter (AC)

The timing generator produces the various signals required to drive the internal circuits. Internal chip operation is not affected by operations on the data buses. 7.5 Display address counter

The address counter assigns addresses to the display data RAM for writing. The X-address X6 to X0 and the Y-address Y2 to Y0 are set separately. After a write operation, the address counter is automatically incremented by 1, according to the V flag. 7.3 Display Data RAM (DDRAM)

The display is generated by continuously shifting rows of RAM data to the dot matrix LCD through the column outputs. The display status (all dots on/off and normal/inverse video) is set by bits E and D in the ‘display control’ command. 7.6 LCD row and column drivers

The DDRAM is a 48 × 84 bit static RAM which stores the display data. The RAM is divided into six banks of 84 bytes (6 × 8 × 84 bits). During RAM access, data is transferred to the RAM through the serial interface. There is a direct correspondence between the X-address and the column output number.

The PCD8544 contains 48 row and 84 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected.

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Product specification

48 × 84 pixels matrix LCD controller/driver

PCD8544

frame n VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS

frame n + 1 Vstate1(t) Vstate2(t)

ROW 0 R0 (t)

ROW 1 R1 (t)

COL 0 C0 (t)

COL 1 C1 (t)

VLCD V3 - VSS VLCD - V2 Vstate1(t) 0V V3 - V2 V4 - V5 0V VSS - V5 V4 - VLCD −VLCD VLCD V3 - VSS VLCD - V2 Vstate2(t) 0V V3 - V2 V4 - V5 0V VSS - V5 V4 - VLCD −VLCD
01 2 3 45 6 7 8 ... 47 0 1 2 3 4 5 6 7 8 ... 47

MGL637

Vstate1(t) = C1(t) - R0(t). Vstate2(t) = C1(t) - R1(t).

Fig.2 Typical LCD driver waveforms.

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Product specification

48 × 84 pixels matrix LCD controller/driver

PCD8544

DDRAM bank 0 top of LCD R0

bank 1

R8

bank 2

R16

LCD bank 3

R24

bank 4

R32

bank 5

R40

R47
MGL636

Fig.3 DDRAM to display mapping.

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Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
7.7 Addressing

PCD8544

Data is downloaded in bytes into the 48 by 84 bits RAM data display matrix of PCD8544, as indicated in Figs. 3, 4, 5 and 6. The columns are addressed by the address pointer. The address ranges are: X 0 to 83 (1010011), Y 0 to 5 (101). Addresses outside these ranges are not allowed. In the vertical addressing mode (V = 1), the Y address increments after each byte (see 7.7.1 DATA STRUCTURE

Fig.5). After the last Y address (Y = 5), Y wraps around to 0 and X increments to address the next column. In the horizontal addressing mode (V = 0), the X address increments after each byte (see Fig.6). After the last X address (X = 83), X wraps around to 0 and Y increments to address the next row. After the very last address (X = 83 and Y = 5), the address pointers wrap around to address (X = 0 and Y = 0).

LSB handbook, full pagewidth 0

Y-address MSB 5 0 X-address 83
MGL638

Fig.4 RAM format, addressing.

handbook, halfpage

0 1 2

6 7

0

Y-address 3 4 5 0 X-address 503 83
MGL639

5

Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).

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Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver

PCD8544

handbook, halfpage

0

1

2

0

84 85 86 168 169 170 Y-address 252 253 254 336 337 338 420 421 422 0 X-address 503 83
MGL640

5

Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).

7.8

Temperature compensation

Due to the temperature dependency of the liquid crystals’ viscosity, the LCD controlling voltage VLCD must be increased at lower temperatures to maintain optimum

contrast. Figure 7 shows VLCD for high multiplex rates. In the PCD8544, the temperature coefficient of VLCD, can be selected from four values (see Table 2) by setting bits TC1 and TC0.

VLCD handbook, halfpage

(1) (2) (3) (4)

0 °C

temperature
MGL641

(1) Upper limit. (2) Typical curve. (3) Temperature coefficient of IC. (4) Lower limit.

Fig.7 VLCD as function of liquid crystal temperature (typical values).

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Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
8 INSTRUCTIONS

PCD8544

The instruction format is divided into two modes: If D/C (mode select) is set LOW, the current byte is interpreted as command byte (see Table 1). Figure 8 shows an example of a serial data stream for initializing the chip. If D/C is set HIGH, the following bytes are stored in the display data RAM. After every data byte, the address counter is incremented automatically. The level of the D/C signal is read during the last bit of data byte.

Each instruction can be sent in any order to the PCD8544. The MSB of a byte is transmitted first. Figure 9 shows one possible command stream, used to set up the LCD driver. The serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no effect and no power is consumed by the serial interface. A negative edge on SCE enables the serial interface and indicates the start of a data transmission.

handbook, halfpage MSB (DB7)

LSB (DB0) data
MGL666

data

Fig.8 General format of data stream.

handbook, full pagewidth

function set (H = 1)

bias system

set VOP

temperature control

function set (H = 0)

display control

Y address

X address
MGL642

Fig.9 Serial data stream, example.

Figures 10 and 11 show the serial bus protocol. • When SCE is HIGH, SCLK clock signals are ignored; during the HIGH time of SCE, the serial interface is initialized (see Fig.12) • SDIN is sampled at the positive edge of SCLK • D/C indicates whether the byte is a command (D/C = 0) or RAM data (D/C = 1); it is read with the eighth SCLK pulse

• If SCE stays LOW after the last bit of a command/data byte, the serial interface expects bit 7 of the next byte at the next positive edge of SCLK (see Fig.12) • A reset pulse with RES interrupts the transmission. No data is written into the RAM. The registers are cleared. If SCE is LOW after the positive edge of RES, the serial interface is ready to receive bit 7 of a command/data byte (see Fig.13).

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Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver

PCD8544

handbook, full pagewidth

SCE

D/C

SCLK

SDIN

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
MGL630

Fig.10 Serial bus protocol - transmission of one byte.

handbook, full pagewidth

SCE

D/C

SCLK

SDIN

DB7 DB6

DB5 DB4

DB3 DB2

DB1 DB0

DB7 DB6 DB5

DB4

DB3

DB2 DB1

DB0

DB7 DB6

DB5
MGL631

Fig.11 Serial bus protocol - transmission of several bytes.

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Product specification

48 × 84 pixels matrix LCD controller/driver

PCD8544

handbook, full pagewidth

SCE

D/C

RES

SCLK

SDIN

DB7 DB6

DB5 DB4

DB3 DB2

DB1 DB0

DB7 DB6 DB5

DB4

DB3

DB2 DB1

DB0

DB7 DB6

DB5
MGL632

Fig.12 Serial bus reset function (SCE).

handbook, full pagewidth

SCE

RES

D/C

SCLK

SDIN

DB7 DB6

DB5 DB4

DB3

DB7

DB6 DB5 DB4

DB3

DB2

DB1 DB0

DB7

DB6 DB5

DB4
MGL633

Fig.13 Serial bus reset function (RES).

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Product specification

48 × 84 pixels matrix LCD controller/driver
Table 1 Instruction set D/C COMMAND BYTE DB7 0 0 DB6 0 0 DB5 0 1 DB4 0 0 DB3 0 0 DB2 0 PD DB1 0 V DB0 0 H

PCD8544

INSTRUCTION (H = 0 or 1) NOP Function set 0 0

DESCRIPTION

Write data (H = 0) Reserved Display control Reserved Set Y address of RAM Set X address of RAM (H = 1) Reserved Temperature control Reserved Bias system Reserved Set VOP Table 2

1 0 0 0 0 0

D7 0 0 0 0 1

D6 0 0 0 1 X6

D5 0 0 0 0 X5

D4 0 0 1 0 X4

D3 0 1 X 0 X3

D2 1 D X Y2 X2

D1 X 0 X Y1 X1

D0 X E X Y0 X0

no operation power down control; entry mode; extended instruction set control (H) writes data to display RAM do not use sets display configuration do not use sets Y-address of RAM; 0≤Y≤5 sets X-address part of RAM; 0 ≤ X ≤ 83 do not use do not use set Temperature Coefficient (TCx) do not use set Bias System (BSx) do not use write VOP to register

0 0 0 0 0 0 0

0 0 0 0 0 0 1

0 0 0 0 0 1 VOP6

0 0 0 0 0 X VOP5

0 0 0 0 1 X VOP4

0 0 0 1 0 X VOP3

0 0 1 X BS2 X VOP2

0 1 TC1 X BS1 X VOP1

1 X TC0 X BS0 X VOP0

Explanations of symbols in Table 1 BIT 0 chip is active horizontal addressing use basic instruction set display blank normal mode all display segments on inverse video mode VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3 1 chip is in Power-down mode vertical addressing use extended instruction set

PD V H D and E 00 10 01 11 TC1 and TC0 00 01 10 11

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Product specification

48 × 84 pixels matrix LCD controller/driver
8.1 Initialization 8.3.3 BIT H

PCD8544

Immediately following power-on, the contents of all internal registers and of the RAM are undefined. A RES pulse must be applied. Attention should be paid to the possibility that the device may be damaged if not properly reset. All internal registers are reset by applying an external RES pulse (active LOW) at pad 31, within the specified time. However, the RAM contents are still undefined. The state after reset is described in Section 8.2. The RES input must be ≤0.3VDD when VDD reaches VDDmin (or higher) within a maximum time of 100 ms after VDD goes HIGH (see Fig.16). 8.2 Reset function

When H = 0 the commands ‘display control’, ‘set Y address’ and ‘set X address’ can be performed; when H = 1, the others can be executed. The ‘write data’ and ‘function set’ commands can be executed in both cases. 8.4 8.4.1 Display control BITS D AND E

Bits D and E select the display mode (see Table 2). 8.5 Set Y address of RAM

Yn defines the Y vector addressing of the display RAM. Table 3 Y2 0 0 0 0 1 1 8.6 Y vector addressing Y1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 BANK 0 1 2 3 4 5

After reset, the LCD driver has the following state: • Power-down mode (bit PD = 1) • Horizontal addressing (bit V = 0) normal instruction set (bit H = 0) • Display blank (bit E = D = 0) • Address counter X6 to X0 = 0; Y2 to Y0 = 0 • Temperature control mode (TC1 TC0 = 0) • Bias system (BS2 to BS0 = 0) • VLCD is equal to 0, the HV generator is switched off (VOP6 to VOP0 = 0) • After power-on, the RAM contents are undefined. 8.3 8.3.1 Function set BIT PD

Set X address of RAM

The X address points to the columns. The range of X is 0 to 83 (53H). 8.7 Temperature control

• All LCD outputs at VSS (display off) • Bias generator and VLCD generator off, VLCD can be disconnected • Oscillator off (external clock possible) • Serial bus, command, etc. function • Before entering Power-down mode, the RAM needs to be filled with ‘0’s to ensure the specified current consumption. 8.3.2 BIT V

The temperature coefficient of VLCD is selected by bits TC1 and TC0. 8.8 Bias value

The bias voltage levels are set in the ratio of R - R - nR - R - R, giving a 1/(n + 4) bias system. Different multiplex rates require different factors n (see Table 4). This is programmed by BS2 to BS0. For Mux 1 : 48, the optimum bias value n, resulting in 1/8 bias, is given by: n = 48 – 3 = 3.928 = 4 (1)

When V = 0, the horizontal addressing is selected. The data is written into the DDRAM as shown in Fig.6. When V = 1, the vertical addressing is selected. The data is written into the DDRAM, as shown in Fig.5.

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Product specification

48 × 84 pixels matrix LCD controller/driver
Table 4 Programming the required bias system BS2 0 0 0 0 1 1 1 1 Table 5 LCD bias voltage BIAS VOLTAGES VLCD (n + 3)/(n + 4) (n + 2)/(n + 4) 2/(n + 4) 1/(n + 4) VSS
7⁄ 6⁄ 2⁄ 1⁄ 8 8 8 8

PCD8544

BS1 0 0 1 1 0 0 1 1

BS0 0 1 0 1 0 1 0 1

n 7 6 5 4 3 2 1 0

RECOMMENDED MUX RATE 1 : 100 1 : 80 1 : 65/1 : 65 1 : 48 1 : 40/1 : 34 1 : 24 1 : 18/1 : 16 1 : 10/1 : 9/1 : 8

SYMBOL V1 V2 V3 V4 V5 V6 8.9 Set VOP value

BIAS VOLTAGE FOR 1⁄8 BIAS VLCD × VLCD × VLCD × VLCD × VLCD VSS

The operation voltage VLCD can be set by software. The values are dependent on the liquid crystal selected. VLCD = a + (VOP6 to VOP0) × b [V]. In the PCD8544, a = 3.06 and b = 0.06 giving a program range of 3.00 to 10.68 at room temperature. Note that the charge pump is turned off if VOP6 to VOP0 is set to zero. For Mux 1 : 48, the optimum operation voltage of the liquid can be calculated as: 1 + 48 V LCD = -------------------------------------- ⋅ V th = 6.06 ⋅ V th 1  1 – ----------  2⋅  48  where Vth is the threshold voltage of the liquid crystal material used. Caution, as VOP increases with lower temperatures, care must be taken not to set a VOP that will exceed the maximum of 8.5 V when operating at −25 °C. (2)

VLCD handbook, halfpage

b

a

00 01 02 03 04 05 06 07 08 09 0A ...
MGL643

a = 3.06. b = 0.06. VOP6 to VOP0 (programmed) [00 to 7FH].

Fig.14 VOP programming.

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Product specification

48 × 84 pixels matrix LCD controller/driver
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); see notes 1 and 2. SYMBOL VDD VLCD Vi ISS II, IO Ptot PO Tamb Tj Tstg Notes 1. Stresses above those listed under limiting values may cause permanent damage to the device. PARAMETER supply voltage supply voltage LCD all input voltages ground supply current DC input or output current total power dissipation power dissipation per output operating ambient temperature operating junction temperature storage temperature CONDITIONS note 3 note 4 MIN. −0.5 −0.5 −0.5 −50 −10 − − −25 −65 −65 +7 +10 VDD + 0.5 +50 +10 300 30 +70 +150 +150 MAX.

PCD8544

UNIT V V V mA mA mW mW °C °C °C

2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. With external LCD supply voltage externally supplied (voltage generator disabled). VDDmax = 5 V if LCD supply voltage is internally generated (voltage generator enabled). 4. When setting VLCD by software, take care not to set a VOP that will exceed the maximum of 8.5 V when operating at −25 °C, see Caution in Section 8.9. 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).

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Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
11 DC CHARACTERISTICS VDD = 2.7 to 3.3 V; VSS = 0 V; VLCD = 6.0 to 9.0 V; Tamb = −25 to +70 °C; unless otherwise specified. SYMBOL VDD1 PARAMETER supply voltage 1 CONDITIONS LCD voltage externally supplied (voltage generator disabled) LCD voltage internally generated (voltage generator enabled) LCD voltage externally supplied (voltage generator disabled) LCD voltage internally generated (voltage generator enabled); note 1 MIN. 2.7 − TYP.

PCD8544

MAX. 3.3 V

UNIT

VDD2

supply voltage 2

2.7

−

3.3

V

VLCD1

LCD supply voltage

6.0

−

9.0

V

VLCD2

LCD supply voltage

6.0

−

8.5

V

IDD1

supply current 1 (normal mode) for internal VLCD supply current 2 (normal mode) for internal VLCD supply current 3 (Power-down mode) supply current external VLCD supply current external VLCD

VDD = 2.85 V; VLCD = 7.0 V; − fSCLK = 0; Tamb = 25 °C; display load = 10 µA; note 2 VDD = 2.70 V; VLCD = 7.0 V; − fSCLK = 0; Tamb = 25 °C; display load = 10 µA; note 2 with internal or external LCD − supply voltage; note 3 VDD = 2.85 V; VLCD = 9.0 V; fSCLK = 0; notes 2 and 4 VDD = 2.7 V; VLCD = 7.0 V; fSCLK = 0; T = 25 °C; display load = 10 µA; notes 2 and 4 − −

240

300

µA

IDD2

−

320

µA

IDD3 IDD4 ILCD

1.5 25 42

− − −

µA µA µA

Logic VIL VIH IL Ro(C) Ro(R) Vbias(tol) LOW level input voltage HIGH level input voltage leakage current VI = VDD or VSS VSS 0.7VDD −1 − − −100 − − − 0.3VDD VDD +1 V V µA

Column and row outputs column output resistance C0 to C83 row output resistance R0 to R47 bias voltage tolerance on C0 to C83 and R0 to R47 12 12 0 20 20 +100 kΩ kΩ mV

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Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
SYMBOL PARAMETER CONDITIONS VDD = 2.85 V; VLCD = 7.0 V; − fSCLK = 0; display load = 10 µA; note 5 VDD = 2.85 V; VLCD = 7.0 V; fSCLK = 0; display load = 10 µA VDD = 2.85 V; VLCD = 7.0 V; fSCLK = 0; display load = 10 µA VDD = 2.85 V; VLCD = 7.0 V; fSCLK = 0; display load = 10 µA VDD = 2.85 V; VLCD = 7.0 V; fSCLK = 0; display load = 10 µA − MIN. TYP.

PCD8544

MAX.

UNIT

LCD supply voltage generator VLCD VLCD tolerance internally generated VLCD temperature coefficient 0 0 300 mV

TC0

1

−

mV/K

TC1

VLCD temperature coefficient 1

−

9

−

mV/K

TC2

VLCD temperature coefficient 2

−

17

−

mV/K

TC3

VLCD temperature coefficient 3

−

24

−

mV/K

Notes 1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Internal clock. 3. RAM contents equal ‘0’. During power-down, all static currents are switched off. 4. If external VLCD, the display load current is not transmitted to IDD. 5. Tolerance depends on the temperature (typically zero at 27 °C, maximum tolerance values are measured at the temperate range limit).

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Product specification

48 × 84 pixels matrix LCD controller/driver
12 AC CHARACTERISTICS SYMBOL fOSC fclk(ext) fframe tVHRL tWL(RES) fSCLK Tcy tWH1 tWL1 tsu2 th2 tWH2 th5 tsu3 th3 tsu4 th4 Notes 1. f clk ( ext ) T frame = ------------------480 PARAMETER oscillator frequency external clock frequency frame frequency VDD to RES LOW RES LOW pulse width fOSC or fclk(ext) = 32 kHz; note 1 Fig.16 Fig.16 VDD = 3.0 V ±10% All signal timing is based on 20% to 80% of VDD and maximum rise and fall times of 10 ns CONDITIONS MIN. 20 10 − 0(2) 100 TYP. 34 32 67 − − − − − − − − − − − − − −

PCD8544

MAX. 65 100 − 30 −

UNIT kHz kHz Hz ms ns

Serial bus timing characteristics clock frequency clock cycle SCLK SCLK pulse width HIGH SCLK pulse width LOW SCE set-up time SCE hold time SCE min. HIGH time SCE start hold time; note 3 D/C set-up time D/C hold time SDIN set-up time SDIN hold time 0 250 100 100 60 100 100 100 100 100 100 100 4.00 − − − − − − − − − − − MHz ns ns ns ns ns ns ns ns ns ns ns

2. RES may be LOW before VDD goes HIGH. 3. th5 is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE (see Fig.15).

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Product specification

48 × 84 pixels matrix LCD controller/driver
12.1 Serial interface

PCD8544

handbook, full pagewidth

tsu2 SCE tsu3 th3 D/C tWL1 tWH1 SCLK tsu4 th4 SDIN

th2

tWH2

th5

th5

tsu2 Tcy

MGL644

Fig.15 Serial interface timing.

12.2

Reset

handbook, full pagewidth V

DD tWL(RES)

RES

tRW
MGL645

Fig.16 Reset timing.

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Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
13 APPLICATION INFORMATION Table 6 STEP D/C 1 2 start 0 0 0 1 0 0 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Programming example SERIAL BUS BYTE DISPLAY

PCD8544

OPERATION SCE is going LOW function set PD = 0 and V = 0, select extended instruction set (H = 1 mode) set VOP; VOP is set to a +16 × b [V] function set PD = 0 and V = 0, select normal instruction set (H = 0 mode) display control set normal mode (D = 1 and E = 0) data write Y and X are initialized to 0 by default, so they are not set here

3 4

0 0

1 0

0 0

0 1

1 0

0 0

0 0

0 0

0 0

5

0

0

0

0

0

1

1

0

0

6

1

0

0

0

1

1

1

1

1

MGL673

7

1

0

0

0

0

0

1

0

1

data write

MGL674

8

1

0

0

0

0

0

1

1

1

data write

MGL675

9

1

0

0

0

0

0

0

0

0

data write

MGL675

10

1

0

0

0

1

1

1

1

1

data write

MGL676

1999 Apr 12

22

Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
SERIAL BUS BYTE STEP D/C 11 1 DB7 DB6 DB5 DB4 DB3 0 0 0 0 0 DB2 DB1 DB0 1 0 0 DISPLAY

PCD8544

OPERATION data write

MGL677

12

1

0

0

0

1

1

1

1

1

data write

MGL678

13

0

0

0

0

0

1

1

0

1

display control; set inverse video mode (D = 1 and E = 1)
MGL679

14

0

1

0

0

0

0

0

0

0

set X address of RAM; set address to ‘0000000’

MGL679

15

1

0

0

0

0

0

0

0

0

data write

MGL680

The pinning is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 48 × 84 pixels. The required minimum value for the external capacitors is: Cext = 1.0 µF. handbook, halfpage

DISPLAY 48 × 84 pixels

Higher capacitor values are recommended for ripple reduction.
24

24

84

14 BONDING PAD LOCATIONS 14.1 Bonding pad information (see Fig.18) PARAMETER SIZE min. 100 µm 80 × 100 µm 59 × 89 × 17.5 (±5) µm max. 380 µm

PCD8544
8 Cext I/O VDD VSS VLCD
MGL635

Pad pitch Pad size, aluminium Bump dimensions Wafer thickness

Fig.17 Application diagram.

1999 Apr 12

23

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Apr 12
12.97 mm
PCD8544-1

14.2

Philips Semiconductors

handbook, full pagewidth

48 × 84 pixels matrix LCD controller/driver

Bonding pad location

2.5 mm

pitch y

x

62

61 60 59 58 57 56 55 54 53 52 51 50

49

48

47

46

45

44

43 42 41 40

39

38 37 36 35 34

33

32

31

30

29

28

27

26 25 24

23 22 21 20 19

18 17 16 15 14

13 12 11 10 9 8 7 6 5 4 3 2

1

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103

104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131

132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159

160 161 162 163 164 165 166 167 168 169 170 171

12.97 mm
MGR935

172

63

64 65 66 67 68 69 70 71 72 73 74 75

24 y PCD8544-1

2.5 mm

x 0 0

Product specification

PCD8544

Fig.18 Bonding pad locations.

Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
Table 7 Bonding pad locations (dimensions in µm). All X/Y coordinates are referenced to the centre of chip (see Fig.18) PAD NAME dummy1 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 SCLK SDIN D/C SCE RES OSC T3 VSS2 VSS2 VSS2 VSS2 VSS2 x +5932 +5704 +5604 +5504 +5404 +5304 +5204 +5104 +5004 +4904 +4804 +4704 +4604 +4330 +4230 +4130 +4030 +3930 +3750 +3650 +3550 +3450 +3350 +3250 +3150 +3050 +2590 +2090 +1090 +90 −910 −1410 −1826 −2068 −2168 −2268 −2368 −2468 y +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 25 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 PAD PAD NAME T4 VSS1 VSS1 VSS1 VSS1 T1 VLCD2 VLCD2 VLCD1 VLCD1 T2 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 dummy2 dummy3 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 C0 x −2709 −2876 −2976 −3076 −3176 −3337 −3629 −3789 −4231 −4391 −4633 −4894 −4994 −5094 −5194 −5294 −5394 −5494 −5594 −5694 −5794 −5894 −5994 −6222 −6238 −5979 −5879 −5779 −5679 −5579 −5479 −5379 −5279 −5179 −5079 −4979 −4879 −4646

PCD8544

PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 1999 Apr 12

y +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1085 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 +1060 −738 −738 −738 −738 −738 −738 −738 −738 −738 −738 −738 −738 −738 −746

Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
PAD 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 1999 Apr 12 PAD NAME C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 x −4546 −4446 −4346 −4246 −4146 −4046 −3946 −3846 −3746 −3646 −3546 −3446 −3346 −3246 −3146 −3046 −2946 −2846 −2746 −2646 −2546 −2446 −2346 −2246 −2146 −2046 −1946 −1696 −1596 −1496 −1396 −1296 −1196 −1096 −996 −896 −796 −696 −596 −496 −396 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 26 y 118 119 120 121 122 123 124 125 126 127 128 139 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 PAD PAD NAME C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 −296 −196 −96 +4 +104 +204 +304 +404 +504 +604 +704 +804 +904 +1004 +1254 +1354 +1454 +1554 +1654 +1754 +1854 +1954 +2054 +2154 +2254 +2354 +2454 +2554 +2654 +2754 +2854 +2954 +3054 +3154 +3254 +3354 +3454 +3554 +3654 +3754 +3854 x

PCD8544

y −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746 −746

Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
PAD 159 160 161 162 163 164 165 166 167 168 169 170 171 172 PAD NAME C83 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 R25 R24 dummy4 x +3954 +4328 +4428 +4528 +4628 +4728 +4828 +4928 +5028 +5128 +5228 +5328 +5428 +5694 −746 −738 −738 −738 −738 −738 −738 −738 −738 −738 −738 −738 −738 −738 y

PCD8544

1999 Apr 12

27

Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver

PCD8544

handbook, full pagewidth

VDD SUPPLY VDD1, VDD2

LCD O/Ps VLCD2

VSS1

VLCD SUPPLY VLCD1, VLCD2 T2, T3 VSS1

VSS1

VDD2

INPUT PINS VDD1 VSS1 SCLK, SDIN, OSC, RES, D/C, SCE, T1, T4 VSS1 VSS1

VSS2

VLCD2 VSS1 VDD1 VSS1

VLCD1

VSS2
MGL634

Fig.19 Device protection diagram.

1999 Apr 12

28

Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
15 TRAY INFORMATION

PCD8544

handbook, full pagewidth

x

A

C D

y

B F

E
MGL646

For the dimensions of x, y and A to F, see Table 8.

Fig.20 Tray details.

Table 8 DIM. A handbook, halfpage
PCD8544-1

Dimensions DESCRIPTION pocket pitch, in the x direction pocket pitch, in the y direction pocket width, in the x direction pocket width, in the y direction tray width, in the x direction tray width, in the y direction no. of pockets in the x direction no. of pockets in the y direction VALUE 14.82 mm 4.39 mm 13.27 mm 2.8 mm 50.67 mm 50.67 mm 3 11

B C D E F
MGL647

x y

The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientation and position of the type name on the die surface.

Fig.21 Tray alignment.

1999 Apr 12

29

Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values

PCD8544

This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1999 Apr 12

30

Philips Semiconductors

Product specification

48 × 84 pixels matrix LCD controller/driver
NOTES

PCD8544

1999 Apr 12

31

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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 © Philips Electronics N.V. 1999

Internet: http://www.semiconductors.philips.com

SCA63

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

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465008/750/01/pp32

Date of release: 1999 Apr 12

Document order number:

9397 750 05024