1a) Assume that the total number of instructions = 100
Based on the information given in the question, there will be 3.6 instructions of store(1.0) and load(2.6) for every 100 instructions.
As per the code sequence for calculating the effective address, there will be one ADD instruction with each and every LW instruction.
In the new method of calculating effective address, we are modifying the given code sequence form in such a way that there will be only one instruction instead of two instructions(ADD and LW). This results in decrease in 3.6 in the instruction count.
So, the instruction count new will be 100-3.6 = 96.4
So, the ratio of instruction count (enhanced MIPS) to the instruction count (original MIPS) is 96.4/100 = 0.964
1b)
speedup …show more content…
2d) It takes 6clockcycles for executing an instruction from the moment it enters to the moment it leaves the pipeline
2e)
For N instructions the execution time for an unpipelined processor is 3.8N
For each instruction it takes 3.8Clockcycles
2f) The pipelining pays off because we achieved a speedup of 3.8 and the average CPI is also decreased because of pipelining.
3)
a) The data dependencies in the given code sequence are
R1 from LD to DADDI
R1 from DADDI to SD
R2 from DADDI to DSUB
R4 from DSUB to BNEZ
There exist 4 data dependencies in the code sequence given in the question

b) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
LD R1, 0(R2) IF ID EX MEM …show more content…
J k Issue Read Operands Execution complete Write result
L.D F2, 0 +R2 1 2 3 4
L.D F4, 100 +R3 5 6 7 8
ADD.D F8, F2, F2 6 7 11 12
MUL.D F6, F4, F8 7
SUB.D F6, F2, F4

Functional unit status
Name Busy Op Fi Fj Fk Qj Qk Rj Rk
Integer ALU
Fp Mult1 Yes MUL.D F6 F4 F8 FP Add Yes No
FpMult2
FpAdd Yes ADD.D F8 F2 F2 Yes Yes
FpDivide

Register Result Status F1 F2 F3 F4 F5 F6 F7 F8
Functional unit FP mult1 FP add

Cycle-13
Instruction status J k Issue Read Operands Execution complete Write result
L.D F2, 0 +R2 1 2 3 4
L.D F4, 100 +R3 5 6 7 8
ADD.D F8, F2, F2 6 7 11 12
MUL.D F6, F4, F8 7 13
SUB.D F6, F2, F4

Functional unit status
Name Busy Op Fi Fj Fk Qj Qk Rj Rk
Integer ALU
Fp Mult1 Yes MUL.D F6 F4 F8 Yes Yes
FpMult2
FpAdd
FpDivide

Register Result Status F1 F2 F3 F4 F5 F6 F7 F8
Functional unit FP mult1

Cycle-14
Instruction status J k Issue Read Operands Execution complete Write result
L.D F2, 0 +R2 1 2 3 4
L.D F4, 100 +R3 5 6 7 8
ADD.D F8, F2, F2 6 7 11 12
MUL.D F6, F4, F8 7 13
SUB.D F6, F2, F4

Functional unit status
Name Busy Op Fi Fj Fk Qj Qk Rj