CSE 6421 Research Assignment Explain how each architecture handles instruction fetch. ALPHA 21264: The instruction fetch is the stage 0 in Alpha 21264 instruction pipeline. It can fetch four instructions each cycle. It includes a branch predictor, two Mux for decode and validity check, a line/set prediction and an instruction cache. The branch prediction and the line/set prediction are used to increase fetch efficiency. The line and set prediction, associated with each instruction block, guides the professor to find the next instruction to fetch. The instruction cache is 64-Kbytes and two-way. Compared with Alpha 21164(8-Kbytes and direct-mapped), the hit rates increase significantly. Itanium 2: The instructions are fetched by the front-end structures. The instruction pointer is chosen from next linear IP, branch prediction resteer pointers or branch misprediction and instruction exception steer pointers by the front end and then presents to the instruction cache and translation look-aside buffer. The processor then uses prevalidated tags to decide to deliver instructions to which caches. In prevalidated tags design, the cache tags store the virtual address and compare with the identifier entry to find match line. It is faster to find out the cache hit address. MIPS R10000: The R10000 processor fetches …show more content…
The processor has branch history storage of two levels. The first level is connected to L1 instruction cache. It uses Yeh-Patt algorithm with branch taken history to determine the branch taken/not taken or trigger. It can be executed in one cycle. If the branch misses from L1I, the second level storage could revisit the branch history and trigger, which is saved in a 24000-entry L2 branch cache. It uses three address-based hashing functions to determine the prediction for L2 cache. An 8-entry return stack buffer is used to provide the predictions for all return