Now a days IC’s such as highly integrated multi-layer boards with fine pitch IC are impossible to accessible physically for testing and that require more power. Functional test, only accesses the board's primary I/O s, providing limited coverage and poor diagnostics for board-network fault includes to traditional board test methods. Another traditional test method works by physically accessing each wire on the board via costly "bed of nails" probes and testers in circuit testing. A research has been conducted to verify the VLSI testing and to reduce the equipment cost. The major problems to identify so far are as follows: Problems on test generation and Gate to I/O pin ratio
• Test Generation Problems…show more content… As years goes on ,the numbers of test patterns are becoming too large to be handled by an external tester and this has resulted in high computation costs and more power consumption and has exceeds reasonable available time to production testing.
• The Gate to I/O Pin Ratio Problem
As gate counts are increase in ICs, the gate nodes are access directly by one of the package pins that to be no longer true. It is very difficult to test internal nodes as they could neither no longer be easily controlled by signal from an input pin (controllability) nor easily the pins of the output have been monitor or tested at (observability). And pin counts are slow than gate counts, which worsens the controllability and observe capability of internal gate
