Techniques for copying with soft errors

Ushna Asif
Computer Science
Bahria University Karachi campus
Karachi, Pakistan ushnaasif99@gmail.com hajra masood
Computer Science
Bahria University Karachi campus
Karachi, Pakistan
Hajra.cs@gmail.com

Aniqa Naeem
Computer Science
Bahria University Karachi campus
Karachi, Pakistan
Aniqanaeem@yahoo.com

Abstract—This electronic document is a “live” template and already defines the components of your paper [title, text, heads, etc.] in its style sheet. *CRITICAL: Do Not Use Symbols, Special Characters, or Math in Paper Title or Abstract. (Abstract)

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Introduction

There are many different kind of fault tolerance in computer architecture like failure in operating system and other hardware issues raised in our daily lives among them there is a soft error issues which is also called as semiconductor transient faults. This fault occurred by the cosmic rays or substrate alpha particle that can also have possibly corrupt the user data. A soft error event causes enough of a charge disturbance to reverse or flip the data state of a memory cell, register, latch, or flip-flop. [1] The error is called “soft” because the circuit/device itself is not permanently damaged by the radiation; if new data are written to the bit, the device will store it correctly. The soft error is also often referred to as a single event upset(SEU). If the radiation event is of a very high energy, more than a single bit maybe affected, creating a multi-bit upset (MBU) as opposed to the more likely single bit upset[2]

background

1 Alpha particles and cosmic rays

Alpha particles are emitted by the reaction of trace uranium and thorium impurities are added into the materials and shown cause of soft errors in DRAM devices. Alpha particle consist of two neutrons and two protons. The most natural source of containing alpha particle is 238U, 235U, and 232Th.[3] Cosmic rays are produced by neutrons reach on the ground of earth. The heavy nuclei produced by a nuclear reaction between a neutron and a silicon nucleus deposit huge amount of energy that brings about a single event upset. Thus, about 99% of soft-errors by secondary cosmic-rays are caused by cosmic-ray neutrons.[4]
[pic]

Figure 1 Fission of 10B induced by the capture of a neutron[5]

2 Single event upset(SEU)

The SEU can be defined as
“Radiation-induced errors in microelectronic circuits caused when charged particles (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs”. - - - NASA Thesaurus[5]

3 soft error circuits

A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. Soft error in electronic device are major issues and they occur due to radiation induced when the logical value of circuit node is alters and particles impact in circuit. Sift registers are mainly used in applications like digital filtering and alignment of signals for communication in receivers [6].

related work

|Author name and year |Techniques for|Copying |Correcting |SEU and MEU|
| |Detecting soft|soft error |Hardware | |
| |errors | |overhead | |
|Decimal Hamming: A |( |( |( |( |
|Software-Implemented | | | | |
|Technique to Cope with| | | | |
|Soft Errors (2011) [7]| | | | |
|An Efficient technique|( |( |( |( |
|to Protect Serial | | | | |
|Shift Registers | | | | |
|Against Soft Errors | | | | |
|(2013) [8] | | | | |
|A Study of Soft Error |( |( |( |( |
|Consequences in Hard | | | | |
|Disk Drives ( 2012)[9]| | | | |
|Exploiting replicated |( |( |( |( |
|Checkpoints for Soft | | | | |
|Error Detection and | | | | |
|Correction (2013)[10] | | | | |

In this paper they describe the used the overhead technique to detect and correct the soft errors by their proposed algorithm hamming codes are applied to decimal addition with the combination of different data structures like heap , linked list. Then combined overhead performance of decimal hamming of both the data structure. There result shows that decimal hamming is better than binary hamming and other checkpoints technique for detecting and correcting the error soft error.[7]

They proposed the method in which two copies of shift register for input and output. The input one copy is encoded in input phase and other in output phase. After that this copies generated an error pattern at output side which helped in distinguishing the copy in error and the correct error using output from other copy. Through this technique they showed that how to protect from soft errors caused by radiation in devices.[8]

As we all know there are various layers in hard disk for preventing data on the fault occurrence. They proposed that detect soft errors using hard error algorithms and setting a threshold which arise the alarm and user can safe their data to safe location. They compare many soft error on hard error algorithm but most of them generated false alarm. After changes threshold of the soft error occur generates better but it lots of time to compute. In the end they concluded that having large data cause computation power but generates efficient results.[9]

In this paper they remove soft error in superscalar microprocessors but using pervious designed processor that takes the copy of RAT(register alias table that holds current location of value to the register) at each instruction to recover from the error occurred. The proposed the technique of detecting and correcting the same RAT checkpoints from the same and pervious checkpoints. They showed the comparison between the 2006 benchmark that shows average RAT 25% and average checkpoints 5.66% and there result shows average RAT 41.5% . by this technique small energy consumption and less overhead in hardware.[10]

Soft errors are the system malfunctions generated due to collision of alpha particles with ICs ;this event is referred as single transient event (STE). Soft error coping techniques can based on “tolerance ” or “mitigation” .previous work mostly focus on synchronous processors but now focus is shifting towards asynchronous(of quasi-delay-insensitive (QDI) processor) .In error tolerance Triple error modular redundancy is implemented on C element or muller C gate is used to produce appropriate output wrt input in less time (robustness ) .another tolerance approach is halting based test generation method .In soft error mitigation gates of circuits are chosen by 3 strategies for soft error reduction .

1. Individual gates,

2. complete cones of state/output logic

3. partial cones of state/output logic

for soft error susceptibility assessment we implement asynchronous-circuit fault simulator[11]

Soft error in stochastic logic circuits can result greater malfunction (stochastic logic is implemented for complex computations by simple bit-wise operations on the streams.)Error analysis in stochastic logic for RESc architecture is performed in 3 steps

1. Approximation(Bernstein approximation)

2. Quantization

3. random fluctuations( randomizer generate stochastic bit streams )

In this new model of stochastic circuits computation in deterministic Boolean domain are transformed into arithmetic computation with probability . Thus it is more fault tolerant but their accuracy depends on statistical distribution of random bits[12]

Complex ,multicore and fabricated processors are more prone to transient errors. In this paper online error detection is performed. Error comes before fault so monitoring errors may help detecting faults. Error: “A difference…between a computed result and the correct result” :Fault: “An incorrect step, process, or data definition in a computer program” (IEEE610.12-90)Online Error Detection focus on Anomaly detection in which errors(anomalous behavior) are monitored to predict faults. Online Error Recovery and Repair: can be done by forward error recovery (detect and correct the errors by using redundancy ) and backward error recovery (correct the errors by switching to previous correct state which are saved periodically). Fault Detection: is done by analyzing errors ,Fault Diagnosis identify the root cause of error and then recovery is performed (forward or backward)[13]

Nano technology combined with multicore processors have increased the chances of system hardware to produce faults. The occurrence of faults is controlled by applying redundancy in information, spatial or temporal domain. Correcting Codes (ECC) are introduced for transient bit flips ; in correcting codes information redundancy is applied to mitigate soft error but it is costly in terms of power .A single event upset may result in loss of control and system failure. When alpha particle strikes with silicon chip it generates charge which can result in bit flip in memory or transient pulse in logic. Soft error mitigation defines error as “if the primary component have error which is not present in redundant component” . False errors are controlled by time and spatial redundancy. Soft error detection and recovery data is latched in registers and then comparison is performed to detect soft errors. Fault tolerance is performed with SEM cells (soft error mitigation) which deal with soft errors of high strike rate.[14]

References

1. Zhang, W., et al. An analysis of microarchitecture vulnerability to soft errors on simultaneous multithreaded architectures. in Performance Analysis of Systems & Software, 2007. ISPASS 2007. IEEE International Symposium on. 2007. IEEE.
2. Baumann, R.C., Radiation-induced soft errors in advanced semiconductor technologies. Device and Materials Reliability, IEEE Transactions on, 2005. 5(3): p. 305-316.
3. Kobayashi, H., et al., Evaluation of LSI soft errors induced by terrestrial cosmic rays and alpha particles. 2001, Technical report, Sony Corporation and RCNP Osaka University.
4. Sawamura, H., T. Hand, and T. Iguchi, Soft errors of semiconductors caused by secondary cosmic-ray neutrons. 2003.
5. Wang, F. and V.D. Agrawal. Single event upset: An embedded tutorial. in VLSI Design, 2008. VLSID 2008. 21st International Conference on. 2008. IEEE.
6. Hatamian, M., et al. Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers. in Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998. 1998.
7. Argyrides, C., et al. Decimal Hamming: A software-implemented technique to cope with soft errors. in Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on. 2011. IEEE.
8. Reviriego, P., et al., An Efficient Technique to Protect Serial Shift Registers Against Soft Errors. Circuits and Systems II: Express Briefs, IEEE Transactions on, 2013. 60(8): p. 512-516.
9. Tsai, T., N. Theera-Ampornpunt, and S. Bagchi. A study of soft error consequences in hard disk drives. in Dependable Systems and Networks (DSN), 2012 42nd Annual IEEE/IFIP International Conference on. 2012. IEEE.
10. Koc, F., et al. Exploiting replicated checkpoints for soft error detection and correction. in Proceedings of the Conference on Design, Automation and Test in Europe. 2013. EDA Consortium.
11. Almukhaizim, S., et al., Soft-error tolerance and mitigation in asynchronous burst-mode circuits. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2009. 17(7): p. 869-882.
12. Qian, W., et al., An architecture for fault-tolerant computation with stochastic logic. Computers, IEEE Transactions on, 2011. 60(1): p. 93-105.
13. Gizopoulos, D., et al. Architectures for online error detection and recovery in multicore processors. in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011. 2011. IEEE.
14. Avirneni, N.D.P. and A.K. Somani, Low overhead soft error mitigation techniques for high-performance and aggressive designs. Computers, IEEE Transactions on, 2012. 61(4): p. 488-501.