National Aviation University
Computer Systems and Networks Department

Term Project on Basics of Computer Aided Design

Performed by : group FCS-405
Checked by:
Nadtochiy V.I.

Kyiv 2011
Contents
Introduction 2 1. Description of the work process of the device “Automobile guard with alarm system” 4 1.1. Description of the input and output values of the device 4 1.2. States of the system : 4 2. Design of a finite state machine 5 3. State diagram design 6 4. State table design 6 5. Design of the full – adder 7 5.1. Creation of project in Quartus II 8 5.2. Creation of a block diagram file in Quartus II 11 5.3. Compiling and simulating of our design in Quartus II 17 5.4. Design of full adder on VHDL 21 Conclusions 24 Reference list 25 Appendix 1 : VHDL-code for full-adder 26 Appendix 2 : VHDL-code for test bench of full-adder program 27

Introduction
This year we’ve started studing the new course,that’s named “Basics of Computer Aided Design”.Actually,I find this discipline really interesting and useful to learn.That’s really pity that we don’t have much time for being able to study the designing of the computer devices more precisely.
In my term work I’m going to try describing few first steps in designing the own project of a device.We don’t have the possibility to realise our projects on the hardware,but still I think that the process of imagining its work is already quite exciting : defining the states of working of the device,its principle of work,thinking of the approximate look of the device.
I’ve decided to investigate the process of building the automobile guard,because nowadays lots of people use automobiles ,but it’s not too safe to leave them on the streets without watching after them,so to prevent happening of any non-pleasant accidents the special device that can notify the owner, if some other person makes any attempts of opening the doors of the car,by means of executing the loud alarm signal.
That’s really wonderful,because from the nature we don’t have any magic abilities of being in one place and watching what’s happening in another place,but with the help of electronic computer devices we can create some special “abilities” to make our life more comfortable.I have one friend who studies Computer Engineering in university in South Korea,he works really hard.Once I’ve asked him why he used to choose such major to learn.His answer has actually surprised me a lot,because I didn’t expect the person could be so immersed into his major.So,he said to me that being a computer engineer was his dream since childhood.He described the computer engineer as a person, who’s kind of a hero, who makes people’s life more happy and convenient. Well I agree with him in some points. Before I’ve started learning CAD I hardly could imagine the process of creation of electronic devices so now I’m really happy to being able to try performing some steps of designing the device by myself.

1. Description of the work process of the device “Automobile guard with alarm system”
This automobile guard is used to protect the car from being damaged.It consists of the remote control device and of the contacts sensors(door switchers) that can be installed on the doors,and the door switchers also are installed in parallel on the door of the hood and on the tailgate.To put the system into the guarding statement we have to turn on the toggle switch that’s hidden inside the automobile’s salon.The time interval between the moment of turning on the system and the turning on the guard is about 1 minute.During that 1 minute all the doors,hood and tailgate must be closed by the owner.If one of the doors is still opened after that 1 minute the system resets.
When one of the closed before doors is opened when the guard was already successfully turned on then the alarm signal starts being executed.If the owner can’t turn off the alarm during 5 seconds,then the alarm signal continues for 20 seconds more.After these 20 seconds pass the system returns to the guard statement.If the door that was opened hasn’t been closed after these 20 seconds then the system continues repeating the alarm signal. 2.1. Description of the input and output values of the device

Input values :
DC – all the doors are closed
DO – at least one of the doors is opened

Output values :
GO – guard-on;
GOF – guard-off;
AL – alarm signal is executing. 2.2. States of the system :

State0 – the initial state when the guard is off and the doors are opened;
State1 – normal condition when the guard is on and the doors are already closed;
State2 – reset of the system after the attempt of turning on the guard while not all the doors are closed;
State3 – If the door is opened while the system is in the State1 the alarm signal appears;
State4 – If the door is still opened after the signal ,then the alarm continues playing;
State5 – If the door is closed after the signal then the system returns to the guard –on statement;
State 6 – If the doors are closed when the system is in the guard-on regime then it remains in the guard-on regime till it won’t be reset. 2. Design of a finite state machine

The circuit that is used in creation of our device is a sequential circuit, to describe the work of such circuit we should use several flip-flops and combinational logic. Such circuits are named the finite state machines.
So, here goes the finite state machine representation of the system “Automobile guard with alarm system”. Fig 2.1 “Finite state machine for automobile guard with alarm system “ 3. State diagram design
Let’s set up some particular states to describe the transitions from one state to another.
We assign A value to the state “guard on”,B value to the state “guard off” and C – to the “alarm”.
Then W = 0 and W = 1 will be ”doors are closed” and “doors are opened” correspondently.
Initially,the system is in the statement B.Then we make the W = 0 to put it to the statement A.If the output is W = 1 doors aren’t closed yet,then we remain the B state of the system.After we finally obtain the W = 0 as output the system is in the statement A.If one then we receive W = 1 then then the statement C follows.To stop the C statement and to pass to the A back,we need W = 0.If we want to turn the guard off and to turn off the alarm simultaneously,we can just press RESET to come back to the B statement.

Fig 3.1 “State diagram of the automobile guard with alarm system “ 4. State table design
The state table is the same as the excitation table of a flip-flop, i.e. what inputs need to be applied to get the required output. In other words this table gives the inputs required to produce the specific outputs.[1]
A state table is the sequential analog of a truth table. It shows inputs and current states on the left, and outputs and next states on the right.[1]
Based on the state diagram we create the state table.Let’s recall the variables of input and output :
A – guard on
B – guard off
C – alarm

W = 0 – doors are closed
W = 1 – doors are opened Present State | Next State | Output | | W = 0 | W = 1 | | B | A | B | 1 | A | A | C | 0 | C | A | C | 1 |
Table 4.1 “State table of the automobile guard with alarm system “ 5. Design of the full – adder
To perfrom a combinational logic functions in our sequentional circuit we are going to use the full – adder(FA). Adder is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic unit(s), but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar.[2]
A one-bit full adder is a device with three single bit binary inputs (A, B, Cin) and two single bit binary outputs (Sum, C-out). Having both carry in and carry out capabilities, the full adder is highly scalable and found in many cascaded circuit implementations.
The basic logic functions of the full adder can be summarized in the truth table (Table 5.1). From the truth table it can be seen that the full adder can be trivially constructed with two half adders. A FA consists of two half adders (HA) and one OR gate as described in the Fig 5.1 .

Fig 5.1 “Logical scheme of the full-adder”
The truth table for such circuit will be :

Table 5.1 “Truth table for the FA circuit” 6.3. Creation of project in Quartus II
First,we need to create the new project file in Quartus.For that purpose,run the Quartus software and choose the option File New Project in there(Fig 5.1.1).

Fig 5.1.2 “File menu”

Then you’ll receive such window (Fig 5.1.2) where you need to specify the directory and the name of the project:

Fig 5.1.2 “New Project’s Name”

The next window is very important(Fig 5.1.3). This is where we specify which chip we're using.
We’re going to select he MAX II chip in there .

Fig 5.1.3 “Choosing the chip”
Click Next in the next window(Fig 5.1.4).

Fig 5.1.4 “Other tools”
Then click “Finish” to create the project(Fig 5.1.5).

Fig 5.1.5 “Finish of creating of project” 6.4. Creation of a block diagram file in Quartus II
We begin by opening a blank block diagram file.To do this we need to click “File” New to get the side-menu(Fig 5.2.1).

Fig 5.2.1 “Side menu bar”
Click on the option that says “Block Diagram/Schematic File” (highlighted in Fig 5.2.1). This will give us a blank page filled with dots(Fig 5.2.2). This blank page will be our canvas for connecting logic gates (and larger circuits) together.

Fig 5.2.2 “Blank block diagram file”
Now we are going to start designing the adder. Double-click anywhere on the blank surface to bring up a menu of logic gates called the “Symbol Tool”(Fig 5.2.3).

Fig 5.2.3 “Symbol Tool menu”
The symbol tool menu is where basic (or predefined) logic gates are selected. Click the + sign next to the directory shown under “libraries”.We should not see 3 sub-menus called “mega functions”,“others”,and”primitives”.Click on the + sign next to primitives to reveal several more sub-menus. Click the + sign next to “logic”. This will reveal a list of basic logic gates you can select. Scroll down until you see “xor”. When you click on the xor gate, it a preview of it should appear to the box on the right (Fig 5.2.4). Click “OK” to select this gate.

Fig 5.2.4 “Placement of a symbol”
The xor gate should now be under the control of your mouse cursor. Click anywhere on the black space to place it down. We have placed our first logic gate on our design.Then we have to add another xor gate to our design. We can see the result further (Fig 5.2.5).

Fig 5.2.5 “BDF file with two OR gates “
The final component needed for our full adder is a 2-to-1 multiplexer. Although we can create this manually, it would be easier to use one already created by quartus. Specifically, we will tell Quartus to give us a multiplexer with parameters specified by us. This called an LPM muduel (Library of Parameterized Modules).Open the symbol tool box again. This time, click on the folder megafunctions > gates > lpm_mux to bring up a menu similar to that in Fig 5.2.6. This is called the megawizard plug-in manager.

Fig 5.2.6 “Mega Wizard Plug-In Manager.Select output type” This will simply be a series of menus where we select the parameters we want for our multiplexer. Click “Next” to get the menu in Fig 5.2.7.

Fig 5.2.7 “Mega Wizard Plug-In Manager.Select input and output parameters”
In the menu shown in Fig 5.2.7, make sure you select 2 data inputs and a 1-bit wide bus.That’s it! Click “Finish” twice. Your mouse cursor should now have control over the 2-to-1 multiplexer. Place it down anywhere(Fig 5.2.8).

Fig 5.2.8 “Two xor gates and 2-to-1 multiplexer”
Although we have the logic gates we need for our adder, we are missing input and output pins. These pins can be reffered to in simulations to find the values of an output given some programmed input. Input/Output pins are found in the symbol toolbox under primitives > pin. We will need 3 input and 2 output pins(Fig 5.2.9).

Fig 5.2.9 “Input/Output pins”
Now that our 3 logic gates are placed down, they must be connected together(Fig 5.2.10). To do this, we need to place our mouse cursor on the output edge of one gate, and click and hold the left mouse button. Drag the wire to the input edge of another gate, and release when a small box is drawn around the cursor indicating a clean connection. Make sure there are no wires hanging around that are connected to nothing. If we mess up, we can click a wire to highlight it, and press DELETE on the keyboard to delete it.

Fig 5.2.10 “Clean connections” If to look carefully, the names of the pins are given automatically, such as “pin_name”, “pin_name2”, etc. It is very nice of Quartus to name our pins for us. However, this makes analyzing simulations difficult. To change the name of a pin, double-click it and change the name in the box that appears. When we are done, we click “OK”. Our full-adder is now complete! 6.5. Compiling and simulating of our design in Quartus II
Compiling

To compile the design, we simply need to click on Processing=>Start compilation. If our design has no loose wires or incorrect inputs, all the bars under the status menu on the left side will reach 100%. Simulating

Now that we have compiled, we are ready to simulate. First, click on File > New. In the box that appears, look under “verification/debugging files” and select “vector waveform file”. A new screen will appear on top of our design.Then we need to right click on the left area of the window. In the menu that appears, we click “Insert node or bus”. We will see the following box(Fig 5.3.1).

Fig 5.3.1 “Insert node or bus”
After clicking “Insert node or bus”, a menu will appear asking which pins to analyze in the simulation. Refering to the Fig 5.3.2, click “List” to list the nodes that are available (Fig 5.3.3).

Fig 5.3.2 “Node Finder”

Fig 5.3.3 “List of the available nodes”
After listing the available nodes, click the double right arrow “>>” to move them to the Selected Nodes list(Fig 5.3.4). Click “OK” to go back to the “Insert Node or Bus” menu. Click “OK” again.

Fig 5.3.4 “Moving of the nodes in the list”

Now we’re back to the original vector waveform file screen. To simulate, we need to give all the inputs initial values. Right click on the first input and select “Value”. From the menu that appears, click on “Random Values”. On the box that appears, click “OK” without changing the selected parameter. Next, do the same with the second input, as well as the carry in. This will give different input test values (because they are random).
Now, we can simulate. Click on Processing > Simulator Tool. This will bring up the menu in Fig 5.3.5 below called the “Simulator Tool”.

Fig 5.3.5 “Simulator Tool window”
In the simulator tool we click the dropdown menu that says “Timing” next to “Simulation mode” and change it to functional. Then we have to click “Generate Functional Simulation Netlist”. What we just did is change the simulation mode to be pure logic and have no reports of time delay that each transistor produces.

Next we click “Start” in the lower left corner of the Simulator Tool to start the simulation. Assuming the progress hits 100% need to click “Report” to view the simulation results. We should see a waveform(Fig 5.3.6).

Fig 5.3.6 “Simulated waveform based on full-adder”
Analyze the simulation waveform. All the inputs should add correctly, giving the correct sum and carry out result. For example, refering to the Fig 5.3.6, at time 27.45ns, we have A=1, B=0, and Cin=0 for our input values. The simulated output values are Cout=0 and Sum=1. In other words, 1+0+0 = 01, which is binary for 1. This is a correct result. 6.6. Design of full adder on VHDL
VHDL is a hardware description language. This is different than the C++ and Java languages you may have seen. While C++ and Java are used for software development, VHDL is used purely to describe hardware. This greatly simplifies the hardware design process, as you can design a circuit without knowing the exact logic gates inside. A circuit can be designed purely based on its behavior.An example code for VHDL is shown below.

LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; entity one_bit_adder is port( I1, I2, Cin : in STD_LOGIC; Sum, Cout : out STD_LOGIC ); end one_bit_adder; architecture arch of one_bit_adder is begin Sum <= (not I1 and not I2 and Cin) or
(not I1 and I2 and not Cin) or
(I1 and not I2 and not Cin) or
(I1 and I2 and Cin);
Cout <= (not I1 and I2 and Cin) or
(I1 and not I2 and Cin) or
(I1 and I2 and not Cin) or
(I1 and I2 and Cin); end arch;

The code above describes a one-bit adder functionally similar to the one we created using a blockdiagram file. However, the hardware used to describe it is based on the image in Fig 5.4.1.

Fig 5.4.1 “Schematic of one-bit adder described on the VHDL code “one_bit_adder.vhd””
VHDL is separated into two main parts; They are the entity and the architecture. Looking at the code in the previous page, the following entity is seen.

entity one_bit_adder is port( I1, I2, Cin : in STD_LOGIC; Sum, Cout : out STD_LOGIC ); end one_bit_adder;

The entity describes a black box representation of our design. It only describes the inputs and outputs. In the case of the above adder, there are 3 inputs (I1, I2, Cin) and 2 outputs (Sum, Cout).
The architecture describes what is inside your black box. It shows how our design works and what it does. In the case of the adder in figure 18, the VHDL code given above gives a dataflow style description of the one-bit adder. This means each gate is described in the architecture, with its corresponding connections.

To create our full adder on VHDL we should click New > VHDL File to bring up a blank text document in Quartus. Then type the code that’s provided in Appendix 1.Compile and Simulate. Compare the simulated results with the simulation from the block diagram file. Make sure the file is called “full_adder.vhd” or you will get an error. The name of the entity must always be the same as the name of the file.
Then we need to create the testbench file to verify the correctness of our design.This file will have the name “tb_full_adder.vhd” and its code also can be found in Appendix 2 of this project work.

Conclusions
So,now we’ve finally got to the end of creating of our term project.I really enjoyed doing it,because I’ve got to discover lots of things connected to the design of computer devices.I’ve gone through the first steps of their creation,got acquinted with creating the projects in the special software from ALTERA Quartus II and simulating of the work of the created circuit.So I can approximately conclude that if I had a possibility to implement the final state of programming the device on the real physical microchip then maybe it will even work correctly and would be able to be used in the future.But unfortunately we don’t have such possibility and we don’t have too much time to study the course of CAD more precisely.
After trying the software Quartus to create the project and simulate it in there,I’ve understood that it’s really very convenient to do such things in there.We used to study MaxPlus before starting performing the labworks on Quartus,and honestly I think it would be really more useful for students to know how to work in Quartus and how to write at least simple programs on VHDL or Verilog languages,though even these are purely hardware describing languages,still for a person who maybe wants to connect his future with inventing some new computer technologies they can be really very useful to know and even required to know.
In that work I’ve tried using two ways of creating the design of devices : creation of the block diagram file and the programming way with the use of VHDL.Actually,I would like to say that I liked the block diagram desgning way the best.Because I think it’s more fast and convenient.And also we can receive the probability of receiving the successful compilation of a BDF projects seems to be higher than the one after compiling the VHDL or Verilog written program.That’s why I would recommend such method of designing the device.

Reference list

1. Brown S. Vranesic Z. “Fundamentals of Digital Logic with VHDL” (2nd)(Chapter 8,10) 2. http://en.wikipedia.org/wiki/Adder_(electronics) 3. Randy H. Katz ,“Contemporary Logic Design “,University of California,Benjamin Cummings/Addison Wesley Publishing Company,1993 4. Charles H.Roth “Digital Systems Design Using VHDL”,1998

Appendix 1 : VHDL-code for full-adder

library ieee; use ieee.std_logic_1164.ALL; -- can be different dependent on tool used. use ieee.std_logic_unsigned.ALL; -- can be different dependent on tool used.

entity fa is port (a : in std_logic; b : in std_logic; c_in : in std_logic; sum : out std_logic; -- sum out of X+Y c_out : out std_logic -- carry out ); end fa;
-- =============================================================================
-- ============================================================================= architecture rtl of fa is -- Define internal signals signal sum_low : std_logic; signal c_low : std_logic; signal c_high : std_logic;

-- Define the entity of the half adder to instansiate component ha -- "ha" must be same name as used in the entity for the file port (X : in std_logic; Y : in std_logic; Z : out std_logic; -- sum out of X+Y C : out std_logic -- carry out ); end component; --------- end of entity for ha ----------
-- =========================================================================== begin ha_low : ha port map ( -- ha-side fa-side X => a, Y => b, Z => sum_low, C => c_low ); --------- end of port map for "ha_low" ----------

ha_high : ha port map ( -- ha-side fa-side X => sum_low, Y => c_in, Z => sum, C => c_high ); --------- end of port map for "ha_high" ----------

c_out <= (c_low OR c_high);

end rtl;
Appendix 2 : VHDL-code for test bench of full-adder program

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity tb_fa is end tb_fa;

architecture test of tb_fa is

type oper_test_type is (initialization, test_fa, end_test );

signal OPER_TEST : oper_test_type;

constant CLOCKCYCLE : time := 100 ns;

-- =============================================================================
-- ==== start of signals in file "tb_fa.vhd" (connected to entity "fa.vhd" ===
-- =============================================================================

signal A_in : std_logic; signal B_in : std_logic; signal C_in : std_logic; signal carry : std_logic; signal sum : std_logic;

-- =============================================================================
-- ====== end of signal in file "tb_fa.vhd (connected to entity "fa.vhd" ======
-- =============================================================================

component fa port (a : in std_logic; b : in std_logic; c_in : in std_logic; sum : out std_logic; -- sum out of X+Y c_out : out std_logic -- carry out ); end component; --------- end of entity for fa ----------

begin
-- =============================================================================
-- ============================================================================= main:process begin OPER_TEST <= initialization; A_in<='0'; B_in<='0'; C_in<='0'; wait for 1*CLOCKCYCLE;

-- ============================================================================= OPER_TEST <= test_fa; wait for 1*CLOCKCYCLE; -- sum=0, c_out=0

A_in<='1'; B_in<='0'; C_in<='0'; wait for 1*CLOCKCYCLE; -- sum=1, c_out=0

A_in<='0'; B_in<='1'; C_in<='0'; wait for 1*CLOCKCYCLE; -- sum=1, c_out=0

A_in<='1'; B_in<='1'; C_in<='0'; wait for 1*CLOCKCYCLE; -- sum=0, c_out=1

A_in<='0'; B_in<='0'; C_in<='1'; wait for 1*CLOCKCYCLE; -- sum=1, c_out=0

A_in<='1'; B_in<='0'; C_in<='1'; wait for 1*CLOCKCYCLE; -- sum=0, c_out=1

A_in<='0'; B_in<='1'; C_in<='1'; wait for 1*CLOCKCYCLE; -- sum=0, c_out=1

A_in<='1'; B_in<='1'; C_in<='1'; wait for 1*CLOCKCYCLE; -- sum=1, c_out=1 A_in<='0'; B_in<='0'; C_in<='0';
-- =============================================================================
-- End test OPER_TEST <= end_test;

wait; --forever end process main;
-- =============================================================================
-- =============================================================================

fa_u : fa port map (
-- fa testbench a => A_in, b => B_in, c_in => C_in, sum => sum, c_out => carry ); --------- end of port map for "fa_u" ----------

-- ============================================================================= end test ;