Assignment 1 (Computer Networking)
Question 25
Assume you wish to transfer an n-byte file along a path composed of the source, destination, seven point-to-point links, and five switches. Suppose each link has a propagation delay of 2us, bandwidth of 4Mbps, and that the switches support both circuit and packet switching. Thus you can either break the file up into 1-kB packets, or set-up a circuit through the switches and send the file as one contiguous bit stream. Suppose that packets have 24 bytes of packet header information and 1000 bytes of payload, that store-and-forward packet processing at each switch incurs at 1-ms delay after the packet has been completely received, that packets may be sent continuously without waiting for acknowledgements, and that circuit setup requires a 1-kB message to make one-round trip on the path incurring a 1-ms delay at each switch after their message has been completely received. Assume switches introduce no-delay to data traversing a circuit. You may also assume that file size is a multiple at 1000 bytes. a) For what file size n bytes if the total number of bytes sent access the network less for circuit than for packets ?

source destination S1

S2

S3
S4

S5
1

2

3

4

5

6

Consider the 5 switches corresponds to 6 links below :

Packet switching, Number of bytes transferred = no. of packets x Header size + data size = n1000×24 bytes+n = 1.024n Circuit switching, Number of bytes transferred = file size + 2 packets = (1kB + 1kB) +n = 2048 + n byte To make circuit switching more efficient 1.024n >2048+n 1.024n-n >2048 0.024n >2048 n >85333 Since the file size need to be multiple 1000 bytes, n ≥86000 bytes b) For what file size n bytes is the total latency incurred before the entire file arrives at the destination less for circuits than for packets? In circuit switching, the transfer time let be T T = 2 (Packet time) + transmission delay = 2 (5 switch delay + 6 link delay + 6 packet delay) + ( 6 link delay + transmission) Transmit time = File sizeBandwidth =nB4Mbps=2nμs T = 2(5(1) + 6(2) + 6(2.048) + (6(2) + 2nus) = 70.58ms + 2nus For the condition that : Packet size >circuit size 27.24+2.048nus>70.58ms+2nus 2.048-2nus>70.58-27.24ms 0.048nus>43.33ms n> 43.33×10-30.048×10-6=902833.3 Since the file size need to be multiple 1000bytes, n>903000 bytes c) How sensitive are these results to the number of switches along the path? To the bandwidth of the links ? To the ratio of packet size to packet header size ? To determine sensitivity, Let the packet size as p, let ratio of header size h, Then the header size = p x h File size in packet switching = [n/(p-p x h)] x p x h + n File size in circuit switching = 2p + n Then, let the switch number as k, and bandwidth as b * Duration by packet switching = 5 packet delay + 6 link delay + 5 switch delay + transmit time Packet delay = Packet sizeBandwidth= pb T = k+ pb+ k+1link delay+k switch delay+(n1-hb)

* Duration by circuit switching T = 2(5 switching delay + 6 link delay + 6 packet delay) + (6 link delay + transmit time) T = 2(k switch delay) + 2(k+1) link delay + 2(k+1). pb + (k+1) link delay + nb T = 2k switch delay + (k+1) link delay + 2(k+1) pb+nb Below is the table summarize the relationship of three factors : k, b, h * PS : Packet Switching CS : Circuit Switching Parameters | Effect on Required Traffic | Effect on Obtained Delay | Number of switch (k) | PS : No effect CS : No effect | PS : bigger k cause bigger delay CS : bigger k cause bigger delay | Average link bandwidth (b) | PS : No effect CS : No effect | PS : bigger b cause smaller delay CS : bigger b cause smaller delay | Header ratio to packet size (h) | PS : bigger a cause more traffic CS : No effect | PS : bigger cause bigger delay CS: No effect | d) How accurate do you think this model of the relative merits of circuits and packets is? Does it ignore important considerations that discredit one or the other approach? If so, what are they? The model in this question can reflect the main advantages and disadvantages of PS and CS.
There are some issues ignored, for example: i. the storage and processing ability of switches, which may cause much minor delay ii. the complex network topology, which may bring multiple paths for PS.