Through Silicon-Via (TSV) Technology

Abstract
Increasing demands for electronic devices with superior performance and functionality with longer battery life while reducing their sizes, weights and energy consumption has driven the semiconductor industry to develop more advanced packaging technologies. Among all different types of packaging technologies proposed, three-dimensional (3D) vertical integration (3D stacking of chips) using through silicon via (TSV) copper interconnect is currently considered one of the most advanced technologies in the semiconductor industry. The co-efficient of thermal expansion of copper is 5-6 times more than that of silicon. This leads to thermal stresses in the via. These stresses are analyzed in this paper. Also, these stresses lead to a change in carrier mobility. This leads to formation of keep out zones (KOZ) in surrounding silicon. The various factors affecting the size of the KOZs are also considered.

1

1

Introduction

A via (Latin for path or way) is an electrical connection between layers in a physical electronic circuit that goes through the plane of one or more adjacent layers. A through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. This is an interconnection method in which holes are drilled through active chips, after which they are filled with an interconnect material. Different tiers of chips are then stacked on each other by CuCu bonding or by the use of micro-bumps [1]
Even though there are many interconnect materials that are currently used for the filling of TSVs, copper (Cu-TSV) is the most preferred. This is because of its high electrical conductivity, relatively well-known deposition process and high resistance to electromigration which results in a large current-carrying capacity.
TSVs are a high performance technique used to create 3D packages and 3D integrated circuits, compared to alternatives such as package-on-package, because the density of the vias is substantially higher, and because the length of the connections is shorter. The TSV technique results in high chip performance since it yields high interconnect density and decreases signal delays and capacitance as it reduces the length of the electrical path. Through-silicon metal connectivity enables electrical and thermal performance advantages, back-side connectivity for two-sided semiconductor wafer and chip-level testing, as well as vertical interconnections for 3D IC stacking and microand opto-electronics. TSV enables the formation of higher density and higher aspect ratio connections, allowing this way the integration of multichip systems entirely within the silicon with a better packing density than traditional 3D packaging methods. TSV can eliminate the need for wire bonding. It has the ability of providing short connections, as short as the chip thickness, reducing significantly the distance of information flow on a chip (by up to 1000x). Because the connections are not limited just to the periphery of the dies, as would be the case with wire bonding, additional pathways and channels can be obtained (up to 100x more than 2D chips).
3D stacking with TSV electrodes can overcome the limitation of traditional 3D packaging methods.
TSV interconnect technology has recently gained a lot of interest in the semiconductor industry due to its advantages over traditional interconnect technologies such as smaller package size-tofunction ratio, higher operating performance, lower packaging cost and reduced power consumption. It has a wide area of applicability, ranging from imaging products and memory to high-speed logic and processing applications.
The following problems present process challenges: metal voiding during filling, uniform via wall material deposition, and active IC surface connectivity to name a few. Copper vias fabricated in a silicon wafer impose, at high temperatures, tensile stresses in silicon. The situation might be aggravated by the stress fields due to numerous vias and, if the vias are placed too close to each other, the thermally induced stresses might lead to cracking of the silicon wafer. In addition, the vias experience compressive ’hoop’ stresses. These stresses could lead to the via buckling.

2

2

Through Silicon Via (TSV) Process

This section gives a brief description of the TSV process. There are two main different approaches to vertical integration, that is vertical stacking of chips, using TSV technology, that have been adopted for 3D chip stacking: via first and via last. Both of these approaches are explained in brief below. Figure 1: Blind-via filling before wafer thinning [1]
1. Via first:
In the via first approach, TSV holes are made in the basic silicon wafer prior to front-end semiconductor processing. As presented in Figure 1, the vias are filled from the front side of the silicon wafers, similar to the copper damascene applications. After via filling, the wafer is thinned, exposing the TSV electrodes.

Figure 2: Through-via filling after wafer thinning [1]
2. Via last:
In this hole formation and plating processes are performed from the backside surface of the finished wafer. The filling of vias is performed after the wafer was thinned, as shown in
Figure 2.
3

3

Thermal Stress Analysis

The co-efficient of thermal expansion of copper is 5-6 times more than that of silicon. Due to the unique feature of TSV structure and the high mismatch in the coefficient of thermal expansion
(CTE) between silicon substrate, dielectric layer material and metal core, large stress may develop, and these stresses may lead to various reliability issues, such as cohesive cracking and/or interfacial delamination. Large thermomechanical stresses are generated at the copper-silicon interface.
To study these stresses, a large array of filled TSVs were subjected to XRD analysis using Cu-K as the characteristic XRD source, at different temperatures ranging from 25 ◦ C to 425 ◦ C in steps of 25 ◦ C [2]. The temperature change led to strain and stress in the TSV structure. In the X-Ray stress measurement, the strain is detected by a shift in the 2θ peak at the different temperatures of measurement. A monotonic peak shift downwards with increasing temperature was detected for each Cu peak of the XRD spectra.
From the measured 2θ change at different temperatures, we can use the following equation to determine the stress in the TSV. σ= E cot(θ)∆2θ x
×
2ν y (1)

where σ is stress, E is the Young’s modulus and ν is the Poisson’s ratio.
Figure 3 shows the peak shift at different temperatures in the X ray diffraction measurement.

Figure 3: XRD pattern (near 2θ=89.933) for Cu at different temperatures [2]
Using the above formula, stress in the TSV is calculated at different temperatures. This is shown on Figure 4. From this graph it is seen that plastic deformation of copper begins at temperatures as low as 100 ◦ C.

4

Figure 4: Stress in TSVs at different temperatures [2]
But this analysis considers only the average stress and not the stress distribution. To evaluate the thermal stresses within silicon, a plane strain analytical solution, Lame stress solution can be used.
Consider an infinitely long TSV embedded in an infinite matrix. The stress field in the matrix induced by a differential thermal load can be expressed as: m m σxx = −σyy = −

r2 B∆α∆T (x2 − y 2 )
2(x2 + y 2 )2

(2)

m m where σxx and σyy are inplane stresses, B is modulus, ∆α∆T is the thermal mismatch strain and r is TSV radius.

The elastic mismatch between TSV and the silicon matrix is neglected. These stresses can be adjusted for a TSV array as:
∗
∗ θ2 = θ1 ×

1
D∗2
= ∗ ×
∗
1 − RV S
H
1−

π
4

1
1
× (S ∗ +1)2

(3)

where D is the TSV diameter, H is the TSV height and S is the spacing of the TSV array.
The von Mises stress and normal stress distribution [3] are plotted schematically in Figure 5(a) and 5(b), respectively. In both cases, stresses are intensified along the x- and y- directions but suppressed along the diagonal directions. The major difference between Figure 6(a) and 6(b) is the stress distribution characteristic. In a Cartesian coordinate system, the distribution of von
Mises stress around an isolated TSV is axially symmetric, just like the radial stress distribution in a cylindrical coordinate system. In an infinite square TSV array, the distribution of von Mises stress is of four-fold rotational symmetry due to the stress interaction between adjacent TSVs. On the other hand, the normal stress distribution is of two-fold rotational symmetry with tensile stress concentrated on one axis and compressive stress concentrated on the other axis. According to the
5

stress analysis, the keep-away-zone may not be axially symmetric around each TSV due to the stress interaction between TSVs.

Figure 5: FEA simulation of a 2x2 TSV array [3]
Figure 6 shows the calculated normal and shear stress distribution around an isolated, 10µm radius copper TSV in a Cartesian coordinate system, under a -175 ◦ C of thermal load. It is seen that tensile and compressive stresses are concentrated along mutually perpendicular directions around the TSV. The stress distribution exhibits similar two-fold rotational symmetry as shown previously in Figure 5(b).

Figure 6: Thermal stress approximation around single TSV [3]
In 3-D integration, the interaction of the stress field between the TSVs has to be taken into account in assessing the keep-away-zone. The stress interaction coming from adjacent TSVs were deduced using a linear superposition of the analytical solution. Figure 8 shows the stress interaction between two TSVs in a Cartesian coordinate system. When two TSVs are aligned along the y- direction, the normal stress is intensified and the shear stress is suppressed in the space between TSVs, as shown in Figure 7(a) and 7(b). In contrast, the normal stress is suppressed and the shear stress is intensified while two TSVs are aligned in the diagonal direction, as shown in Figure 7(c) and 7(d).
It suggests that the stress interaction between TSVs is directional dependent, and the TSV arrays can be arranged accordingly to minimize the thermal stresses.
There exist stress-free points in the space between two TSVs as a result of destructive stress interaction. Figure 8 shows the von Mises stress distribution surrounding two TSVs under a -175C of
6

Figure 7: Thermal stress interaction between two TSVs [3] thermal load. Provided that two TSVs are located at the diagonal corners of a square, the other two corners of the square come out as stress-free points. The radial stress from one TSV is canceled by the hoop stress from the other TSV at stress-free points, and all other stress components are also zero. The stress-free points exist regardless of the array orientation, as illustrated in Figure 8(a) and 8(b). Similar stress characteristics can be found in a rectangular TSV array. In Figure 5(a), the low stress trough in the center region of the array is formed by the stress cancellation of the nearby
TSV pairs.

Figure 8: Stress-free points between two TSVs [3]
A sample was heated from a stress free temperature of 50C to a temperature of 300C. For the through-via, the distribution of the various stresses components as well as von Mises stress are shown in Figure 9, which indicate that Cu tends to expand more than the surrounding Si. Therefore, the axial stress σyy for most of the the via is compressive. Similarly, the radial stress σxx for Cu is mostly compressive. The shear stresses dominate near the corners of Cu/SiO2 interface.
7

Figure 9: Stresses in through-via at 300 ◦ C (deformation scale factor × 50) [2]
The via layout is periodic in nature, and one can determine an average magnitude of stress in Cu over a given planar area of the structure. Thus, when the simulated stress results averaged over a given area for a given depth of the sample, it is seen that the simulated stress magnitude is of the same order as measured by the XRD. Such a comparison provides a preliminary experimental validation of the models. The plot of equivalent plastic strain (Figure 10) indicates that Cu yielding occurs along the Cu/SiO2 interface near the Cu pad corner.

Figure 10: Equivalent plastic strain at 300 ◦ C (deformation scale factor × 50) [2]
Furthermore, when the vias are cooled to -50 , the results also show that those corner locations are highly stressed.
8

4

Keep Out Zones (KOZ)

As seen in the previous section, thermal stresses are induced in the TSV structures which can affect the device performance by degrading carrier mobility and raise serious reliability concerns. Keep
Out Zone (KOZ) is a conservative way to prevent any devices/cells from being impacted by the
TSV-induced stress. The factors affecting the size of KOZ are:
1. Stresses : The stress distribution due to TSVs and their interaction described in the previous section affects carrier mobility induced by piezoresistivity. This in turn, affects the KOZ.
The effect of stress interaction and the shape of the KOZs for an n-type MOSFET and a p-type MOSFET is shown in Figure 11.

Figure 11: Effect of stress interaction (p/D = 3) on Keep-Out Zone (KOZ) for (a) n-type MOSFET with [100] alignment and (b) p-type MOSFET [110] alignment, where dashed lines indicate the
5% mobility change [4]
2. Device Alignment : As the material properties of Si are anisotropic, the mobility change depends on device orientation.
3. TSV Dimensions : KOZ increases with increasing via diameter. The relation between the via diameter and KOZ and also he effect of wafer thickness is shown in Figure 12.
4. Cu Plasticity : During fabrication of TSV structures, annealing at high temperatures may develop plasticity in the copper vias. The effect of Cu plasticity on KOZ with varying yiel strength and thermal load is shown in Figure 13.

5

Conclusion

In this paper, we saw how integrated circuits can be packaged in 3D by stacking individual chips one over the other and joining them by through silicon vias (TSV). Thermal stresses generated due to difference in co-efficient of thermal expansion of copper and silicon were also studied. Various factors affecting the keep-out-zone(KOZ) in surrounding silicon were also considered.

9

Figure 12: Effect of via dimensions on KOZ for n-type Si with [100] device alignment and p-type
Si with [110] device alignment (∆T = 250 ◦ C). (a) Effect of via diameter (H = 200 µm). (b) Effect of wafer thickness (D = 10 µm) [4]

Figure 13: Effect of Cu plasticity on keep-out zone size (D = 10 µm and H = 200 µm). (a) KOZ for different yield strengths with ∆T = 250 ◦ C. (b) KOZ size calculated by the elastic and plastic models for different thermal loads (σy = 200 MPa) [4]

References
[1] R. Beica, C. Sharbono, and Tom Ritzdorf. “Through silicon via copper electrodeposition for
3D integration”. In: Electronic Components and Technology Conference, 2008. ECTC 2008.
58th. May 2008, pp. 577–583. DOI: 10.1109/ECTC.2008.4550031.
[2] Xi Liu et al. “Failure mechanisms and optimum design for electroplated copper ThroughSilicon Vias (TSV)”. In: Electronic Components and Technology Conference, 2009. ECTC
2009. 59th. May 2009, pp. 624–629. DOI: 10.1109/ECTC.2009.5074078.
[3] K.H. Lu et al. “Thermo-mechanical reliability of 3-D ICs containing through silicon vias”.
In: Electronic Components and Technology Conference, 2009. ECTC 2009. 59th. May 2009, pp. 630–634. DOI: 10.1109/ECTC.2009.5074079.
[4] Suk-Kyu Ryu et al. “Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone
Around Through-Silicon Vias for 3-D Integration”. In: Device and Materials Reliability,
IEEE Transactions on 12.2 (June 2012), pp. 255–262. ISSN: 1530-4388. DOI: 10.1109/
TDMR.2012.2194784.

10