What is Drain Induced Barrier Lowering?
Ideally, drain current Ids should be constant i.e. independent of Vds in saturation region. In reality, Ids increases with Vds in saturation region because of the following two regions: 1) Channel length modulation: As Vds increases, length Leff decreases, hence current increases. 2) Drain Induced Barrier Lowering: As Vds increases, Vt decreases, hence current increases.

Drain Induced Barrier Lowering (DIBL) is a decrease in threshold voltage of the transistor at higher drain voltages. This decrease is the result of charge neutrality. The three electrode charges of the device viz. the gate, the source and the drain balance the combined charge in the depletion. As the drain voltage is increased, the depletion region of the p-n junction between the drain and body increases in size and extends under the gate, so the drain assumes the greater portion of the burden of balancing depletion region charge, leaving a smaller burden for the gate. As a result, charge present on the gate retains charge balance by attracting more carriers into the channel, which leads to lowering the threshold voltage of the device. The channel becomes more attractive for electrons or in other words the potential energy barrier for electrons in the channel is lowered. Hence the term “barrier lowering” is used.
DIBL increases as the channel length is reduced because the source and drain form pn junctions with the body, and so has associated built-in depletion layers associated with them that become significant partners in charge balance at short lengths even with no reverse bias applied to increase depletion widths.

What is Hot carrier effect?
It refers to an effect in MOSFETs , where a carrier is injected from the conducting channel in the silicon substrate to the gate dielectric. To become ‘hot’ and enter the conduction band of the gate dielectric which is usually SiO2 , an electron must gain a kinetic energy of ~3.2eV. For holes, it is ~4.6eV.
The term ‘hot electrons’ encompasses electron distributions that possess energy much above the band gap with an elevated effective temperature. This elevated energy affects the mobility of charge carriers and as a consequence affects how they travel through a semiconductor device. Hot electrons can tunnel out of the semiconductor material instead of recombining with a hole. Consequently, this effect results in heating of the device and increased leakage current. In MOSFETs , the hot electrons may jump from the channel region or from the drain, for instance and into the gate or the substrate.

Strained silicon
It is a layer of silicon in which the silicon atoms are stretched beyond their normal interatomic distance. This can be accomplished by putting the layer of silicon over a substrate of silicon germanium(SiGe). As the atoms in the silicon layer align with the atoms of the underlying silicon germanium layer, the links between the silicon atoms become stretched-thereby leading to strained silicon.
This reduces the atomic forces that interfere the movement of electrons through the transistors and thus better mobility, resulting in better chip performance and lower energy consumption.

These electrons can move 70% faster allowing strained silicon transistors to switch 35% faster

Impact Ionization
It is a process in a material by which one energetic charge carrier can lose energy by the creation of other carriers. E.g: in a semiconductor, an electron or hole with enough kinetic energy can knock a bound electron out of its bound state and promote it to a state in the conduction band, creating a electron-hole pair.
DUAL MATERIAL GATE MOSFET
Scaling has been a major concern in the development of MOSFETS with t he advancement in technology. We know that MOSFET is a symmetric device in the sense that the source and drain are interchangeable.They are identified by the operating bias. But as the gate length becomes small, the device operation becomes asymmetrical. This asymmetrical operation results in short-channel Effects (SCEs), such as drain induced barrier lowering as well as hot carrier effects that limit the scaling. As the conventional scaling limit is approached, new structures employing asymmetrical architecture must be developed. This requires new techniques to be developed.
*The problems associated with short channel effects degrade the performance of scaled MOS devices and these problems are addressed by the recently proposed dual-material gate field-effect transistor(DMGFET)*.
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BRIEF DESCRIPTION OF DMGFET

The DMGFET has a gate comprising two laterally contacting materials with different work functions. For both a n-channel fet and a p-channel fet, this gate structure takes advantage of a material work function difference.
For a n-channel FET, the threshold voltage near the source is more positive than that near the drain. Utilization of this material work function difference results in a more rapid acceleration of the charge carriers in the channel and a screening effect to suppress the short channel effects.

Structural Description
In DMG structure, the threshold voltage modulation is produced by choosing the gate electrode consisting of two materials with different work functions to introduce a step in the surface potential in the channel region. The gate with higher work function is termed as the control gate and plays major role in determining the threshold voltage of the device. On the other hand, the gate with the lower work function is called the screen gate which shields the control gate through its step function like shape by absorbing ay detrimental drain to source voltage(Vds) variation. In such a gate structure, the redistribution of electric field in the channel region may result in an enhanced average carrier velocity along the channel. Further the peak electric field at the drain end is observed to be lower whereas the average electric field under the gates is higher in the DMG structures than the conventional SOI MOSFETs. This implies that the hot electron effects and the avalanche multiplications at the drain side of the DMG MOSFETs are inherently smaller than the conventional CMOS devices. The field distribution also enables the device to minimize the ability of the localized charges to raise the drain resistance.
How DMSG can be further improved?
Locally raising the channel doping next to the drain or drain/source can improve MOSFET’s performance.[4]

References
[1]. Narain Arora. MOSFET Modeling for VLSI Simulation: Theory and Practice
[2]. Dual-material gate (DMG) field effect transistor. Long, W.
[3]. A novel hetero-material gate(HMG) MOSFET for deep submicron ULSI technology, Xing Zhou [4]. Dual Material Gate SOI MOSFET with a single halo
[5] Hot-Electron Effect in Superconductors and Its Applications for Radiation Sensors". LLE Review
[6]. Strained Silicon , http://www.belford-research.com/