AMIBIOS8™ Check Point and Beep Code List

Version 2.0 – June 10, 2008

American Megatrends, Inc. Checkpoint & Beep Code List 2.0
Copyright (c) 2008 American Megatrends, Inc. All Rights Reserved. American Megatrends, Inc. 5555 Oakbrook Parkway Suite 200 Norcross, GA 30093 (USA) This publication contains proprietary information which is protected by copyright. No part of this publication may be reproduced, transcribed, stored in a retrieval system, translated into any language or computer language, or transmitted in any form whatsoever without the prior written consent of the publisher, American Megatrends, Inc. American Megatrends, Inc. retains the right to update, change, modify this publication at any time, without notice. For Additional Information Call American Megatrends BIOS Sales Department at 1-800-828-9264 for additional information. Limitations of Liability In no event shall American Megatrends be held liable for any loss, expenses, or damages of any kind whatsoever, whether direct, indirect, incidental, or consequential, arising from the design or use of this product or the support materials provided with the product. Limited Warranty No warranties are made, either express or implied, with regard to the contents of this work, its merchantability, or fitness for a particular use. American Megatrends assumes no responsibility for errors and omissions or for the uses made of the material contained herein or reader decisions based on such use. Trademark and Copyright Acknowledgments All product names used in this publication are for identification purposes only and are trademarks of their respective Companies.

Revision Information
Date 7 May 2002 8 May 2002 1 Oct 2002 24 Mar 2003 9 July 2003 10 July 1003 24 Jan 2004 6 Dec 2004 June 7, 2005 May 17, 2006 Oct 11, 2007 2008-06-10 Rev 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.71 1.8 1.9 2.0 Description of Changes First Public Release for AMIBIOS8 Added beep code troubleshooting information. Added CPU and ACPI POST codes Fixed spelling errors. Changed copyrights to 2003. Added notes concerning checkpoints for specific platforms, option ROMS & other undocumented checkpoints. Remove duplicate definition of E9 & EA. Define ranges for OEM checkpoints. Expanded beep code listing. Removed unused checkpoints, included new checkpoints and corrected checkpoint definitions. Reformatted Template Removed unused POST(2,4,5,9,10,11) and Boot Block(8,9) beep codes. Boot block beep codes are not just for floppy drive. Removed Boot Block beep code 6 and corrected POST beep code 6 to “Keyboard controller BAT command failed” Updated address. Updated to documentation standards.

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0

Table of Contents
1 INTRODUCTION ..........................................................................................................4
1.1 1.2 1.3 About This Document ....................................................................................................4 Checkpoints and Beep Codes.......................................................................................4 Viewing BIOS Checkpoints............................................................................................4

2 3 4 5 6 7 8

BOOTBLOCK INITIALIZATION CODE CHECKPOINTS.............................................5 BOOTBLOCK RECOVERY CODE CHECKPOINTS....................................................7 POST CODE CHECKPOINTS......................................................................................8 OEM POST ERROR CHECKPOINTS ........................................................................11 DIM CODE CHECKPOINTS .......................................................................................12 ACPI RUNTIME CHECKPOINTS ...............................................................................14 BEEP CODES ............................................................................................................15
8.1 8.2 Boot Block Beep Codes...............................................................................................15 POST BIOS Beep Codes ..............................................................................................15

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0

1 Introduction
1.1 About This Document
This document lists checkpoints and beep codes generated by AMIBIOS. This document was last revised at the release of AMIBIOS8 Core 8.00.04. This covers AMIBIOS products released before May 2002. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.

1.2 Checkpoints and Beep Codes
A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process. Beep codes are used by the BIOS to indicate a serious or fatal error to the end user. Beep codes are used when an error occurs before the system video has been initialized. Beep codes will be generated by the system board speaker, commonly referred to as the “PC speaker.”

1.3 Viewing BIOS Checkpoints
Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These are ISA or PCI add-in cards that show the value of I/O port 80h on a LED display. Checkpoint cards are available through a variety of computer mail-order outlets. Some computers using AMIBIOS display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated. Keep in mind that not all computers using AMIBIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMIBIOS checkpoints.

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0

2 Bootblock Initialization Code Checkpoints
The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS 1 :
Checkpoint Before D0 D0 Description If boot block debugger is enabled, CPU cache-as-RAM functionality is enabled at this point. Stack will be enabled from this point. Early Boot Strap Processor (BSP) initialization like microcode update, frequency and other CPU critical initialization. Early chipset initialization is done. Early super I/O initialization is done including RTC and keyboard controller. Serial port is enabled at this point if needed for debugging. NMI is disabled. Perform keyboard controller BAT test. Save power-on CPUID value in scratch CMOS. Go to flat mode with 4GB limit and GA20 enabled. Verify the boot block checksum. System will hang here if checksum is bad. Disable CACHE before memory detection. Execute full memory sizing module. If memory sizing module not executed, start memory refresh and do memory sizing in Boot block code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled. Test base 512KB memory. Adjust policies and cache first 8MB. Set stack. Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM. Copies compressed boot block code to memory in right segments. Copies BIOS from ROM to RAM for faster access. Performs main BIOS checksum and updates recovery status accordingly. Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If BIOS recovery is necessary, control flows to checkpoint E0. See Bootblock Recovery Code Checkpoints section of document for more information. Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash. The Runtime module is uncompressed into memory. CPUID information is stored in memory. Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM. Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See POST Code Checkpoints section of document for more information. System is waking from ACPI S3 state

D1

D2 D3

D4 D5

D6

D7

D8 D9

DA

DC

1

Please note that checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0 E1-E8 EC-EE OEM memory detection/configuration error. This range is reserved for chipset vendors & system manufacturers. The error associated with this value may be different from one platform to the next.

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0

3 Bootblock Recovery Code Checkpoints
The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS 2 :
Checkpoint E0 Description Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled. Set up floppy controller and data. Attempt to read from floppy. Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM. Disable ATAPI hardware. Jump back to checkpoint E9. Read error occurred on media. Jump back to checkpoint EB. Search for pre-defined recovery file name in root directory. Recovery file not found. Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file. Start reading the recovery file cluster by cluster. Disable L1 cache. Check the validity of the recovery file configuration to the current configuration of the flash part. Make flash write enabled through chipset and OEM specific method. Detect proper flash part. Verify that the found flash part size equals the recovery file size. The recovery file size does not equal the found flash part size. Erase the flash part. Program the flash part. The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h.

E9 EA EB EF F0 F1 F2 F3 F5 FA FB

F4 FC FD FF

2

Please note that checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0

4 POST Code Checkpoints
The POST code checkpoints are the largest set of checkpoints during the BIOS preboot process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS 3 :
Checkpoint 03 Description Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags." Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table. Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock." Fixes CPU POST interface calling pointer. Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5. Early CPU Init Start -- Disable Cache – Init Local APIC Set up boot strap processor Information Set up boot strap processor for POST Enumerate and set up application processors Re-enable cache for boot strap processor Early CPU Init Exit Initializes the 8042 compatible Key Board Controller. Detects the presence of PS/2 mouse. Detects the presence of Keyboard in KBC port. Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules. Early POST initialization of chipset registers. Relocate System Management Interrupt vector for all CPU in the system. Uncompress and initialize any platform specific BIOS modules. GPNV is

04

05 06

07 08

C0 C1 C2 C5 C6 C7 0A 0B 0C 0E

13 20 24

3

Please note that checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0 initialized at this checkpoint. Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs. Initializes all the output devices. Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module. Initializes the silent boot module. Set the window for displaying text information. Displaying sign-on message, CPU information, setup key message, and any OEM specific information. Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. USB controllers are initialized at this point. Initializes DMAC-1 & DMAC-2. Initialize RTC date/time. Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system. Mid POST initialization of chipset registers. Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, … etc.) successfully installed in the system and update the BDA, EBDA…etc. Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory. Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed. Initializes NUM-LOCK status and programs the KBD typematic rate. Initialize Int-13 and prepare for IPL detection. Initializes IPL devices controlled by BIOS and option ROMs. Generate and write contents of ESCD in NVRam. Log errors encountered during POST. Display errors to the user and gets the user response for error. Execute BIOS setup if needed / requested. Check boot password if installed. Late POST initialization of chipset registers. Build ACPI tables (if ACPI is supported) Program the peripheral parameters. Enable/Disable NMI as selected Initialization of system management interrupt by invoking all handlers. Please note this checkpoint comes right after checkpoint 20h Clean-up work needed before booting to OS. Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed. Initialize runtime language module. Display boot option popup menu. Displays the system configuration screen if enabled. Initialize the CPU’s before boot, which includes the programming of the MTRR’s.

2A 2C 2E 31

33 37 38

39 3A 3B 3C 40

52

60 75 78 7C 84 85 87 8C 8D 8E 90 A1 A2

A4 A7

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0 A9 AA AB AC B1 00 Wait for user input at config display if needed. Uninstall POST INT1Ch vector and INT09h vector. Prepare BBS for Int 19 boot. Init MP tables. End of POST initialization of chipset registers. De-initializes the ADM module. Save system context for ACPI. Prepare CPU for OS boot including final MTRR values. Passes control to OS Loader (typically INT19h).

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0

5 OEM POST Error Checkpoints
Checkpoints from the range 61h to 70h are reserved for chipset vendors & system manufacturers. The error associated with this value may be different from one platform to the next.

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0

6 DIM Code Checkpoints
The Device Initialization Manager (DIM) gets control at various times during BIOS POST to initialize different system busses. The following table describes the main checkpoints where the DIM module is accessed 4 :
Checkpoint 2A Description Initialize different buses and perform the following functions: Reset, Detect, and Disable (function 0); Static Device Initialization (function 1); Boot Output Device Initialization (function 2). Function 0 disables all device nodes, PCI devices, and PnP ISA cards. It also assigns PCI bus numbers. Function 1 initializes all static devices that include manual configured onboard peripherals, memory and I/O decode windows in PCIPCI bridges, and noncompliant PCI devices. Static resources are also reserved. Function 2 searches for and initializes any PnP, PCI, or AGP video devices. Initialize different buses and perform the following functions: Boot Input Device Initialization (function 3); IPL Device Initialization (function 4); General Device Initialization (function 5). Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller. Function 4 searches for and configures all PnP and PCI boot devices. Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices.

38

While control is in the different functions, additional checkpoints are output to port 80h as a word value to identify the routines under execution. The low byte value indicates the main POST Code Checkpoint. The high byte is divided into two nibbles and contains two fields. The details of the high byte of these checkpoints are as follows: HIGH BYTE XY The upper nibble 'X' indicates the function number that is being executed. 'X' can be from 0 to 7. 0 = func#0, disable all devices on the BUS concerned. 1 = func#1, static devices initialization on the BUS concerned. 2 = func#2, output device initialization on the BUS concerned. 3 = func#3, input device initialization on the BUS concerned. 4 = func#4, IPL device initialization on the BUS concerned.

4

Please note that checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0

5 = func#5, general device initialization on the BUS concerned. 6 = func#6, error reporting for the BUS concerned. 7 = func#7, add-on ROM initialization for all BUSes. 8 = func#8, BBS ROM initialization for all BUSes. The lower nibble 'Y' indicates the BUS on which the different routines are being executed. 'Y' can be from 0 to 5. 0 = Generic DIM (Device Initialization Manager). 1 = On-board System devices. 2 = ISA devices. 3 = EISA devices. 4 = ISA PnP devices. 5 = PCI devices.

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0

7 ACPI Runtime Checkpoints
ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state. The following table describes the type of checkpoints that may occur during ACPI sleep or wake events 5 :
Checkpoint AC AA 01, 02, 03, 04, 05 10, 20, 30, 40, 50 Description First ASL check point. Indicates the system is running in ACPI mode. System is running in APIC mode. Entering sleep state S1, S2, S3, S4, or S5. Waking from sleep state S1, S2, S3, S4, or S5.

5

Please note that checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.

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American Megatrends, Inc. Checkpoint & Beep Code List 2.0

8 Beep Codes
8.1 Boot Block Beep Codes
Number of Beeps 1 2 3 4 5 7 10 11 12 13 Description No media present. (Insert diskette in floppy drive A:) ‘AMIBOOT.ROM’ file not found in root directory of diskette in A: Insert next diskette if multiple diskettes are used for recovery Flash Programming successful File read error No Flash EPROM detected Flash Erase error Flash Program error ‘AMIBOOT.ROM’ file size error BIOS ROM image mismatch (file layout does not match image present in flash device) Description Memory refresh timer error. Base memory read/write test error Keyboard controller BAT command failed General exception error (processor exception interrupt error) Display memory error (system video adapter) Troubleshooting Action Reseat the memory, or replace with known good modules. Fatal error indicating a serious problem with the system. Consult your system manufacturer. Before declaring the motherboard beyond all hope, eliminate the possibility of interference by a malfunctioning add-in card. Remove all expansion cards except the video adapter.

8.2 POST BIOS Beep Codes
Number of Beeps 1 3 6 7 8 Number of Beeps 1, 3 6, 7

8.2.1 Troubleshooting POST BIOS Beep Codes

• •

If beep codes are generated when all other expansion cards are absent, consult your system manufacturer’s technical support.

8

If beep codes are not generated when all other expansion cards are absent, one of the add-in cards is causing the malfunction. Insert the cards back into the system one at a time until the problem happens again. This will reveal the malfunctioning card. If the system video adapter is an add-in card, replace or reseat the video adapter. If the video adapter is an integrated part of the system board, the board may be faulty.

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