UNIVERSITI TEKNIKAL MALAYSIA MELAKA

FACULTY OF ELECTRONIC & COMPUTER ENGINEERING

BENU 2002
ELECTRONIC ENGINEERING PRACTICE

MODULE: MINI PROJECT (BENC)

TIMER & COUNTER FOR LIGHT EMITTING DIODES

PREPARED BY:
COMPUTER ENGINEERING DEPARTMENT, FKEKK
SEMESTER 3 SESSION 2012/2013

1.0 OBJECTIVE * To study the structure of the basic electronic components and functionality of the timer 555 with some basic application in electronics circuit. * To provide practical experience in PCB making, soldering, trouble-shooting and applying the components.

2.0 COMPONENTS/MATERIALS * Soldering Tools-(Solder iron, solder wire, sucker) * Power supply DC 9V (or batteries) * Oscilloscope * Digital Multimeter * Resistors: 4.7 Ω, 2 Unit * Resistor 1K Ω, 2 Unit * Resistor 390 Ω, 1 Unit * Variable resistor: 500k Ω to 2MΩ, 1 Unit (Preset) * Capacitors : 10nF ceramic, 1 Unit * Capacitors: 10μF , 25 volt Electrolytes, 1 Unit * Light Emitting Diodes 8 Units * CMOS 4017, 1 Unit * 555 timer 1C, 1 Unit * 8-pin DIL socket for 1C, 1 Unit * 16-pin DIL socket for 1C, 1 Unit * ON/OFF switch, 1 Unit * Printed Circuit Board, 1 Unit

3.0 THEORY
The Light Emitting Diodes circuit in Figure 1, controls 8 Light Emitting Diodes. The timing sequence is generated using a CMOS 4017 decade counter and a 555 timer. The Light Emitting Diodes will be on. The complete cycle time can be adjusted with variable resistor.
The 555/556 timer is one of the most versatile and popular chips made. It is very inexpensive and easy to use. There are two basic modes of operation. 1: Monostable Mode and 2: Astable Mode. In the monostable mode the 555 timer acts as a "one - shot". It would be used for the purpose of obtaining a one pulse of variable length. In the astable mode the 555 will retrigger itself to output a stream of pulses of variable length. Basic information about the 555 timer is shown in Figure 2.

Figure 1

(b)
(a)

Figure 2: (a) Pin outlines; (b) Internal block diagram
In monostable mode, the timing interval, t, is set by a single resistor and capacitor, as shown in Figure 3. Both the threshold input and the discharge transistor (pins 6 & 7) are connected directly to the capacitor, while the trigger input is held at +VCC through a resistor. In the absence of any input, the output at pin 3 remains low and the discharge transistor prevents capacitor C from charging. The timer will be triggered by applying a negative pulse to pin 2. That will cause the output of the timer to output a pulse on pin 3 for a time period determined by the values of R and C in the circuit below. The supply voltage has no effect on the length of the pulse. The formula to determine the duration of the output pulse is as follows: t = 1.1RC. (a) (b)
Figure 3: (a) Monostable Mode for 555 timer; (b) Time delay of timer
In the astable mode of operation pin 2 and 6 are tied together to cause the timer to retrigger itself. The output pulse is on pin 3. The output pulse is shown in the Figure 4. The chart below is used to figure out the relation between (R1 + 2R2), C and frequency. The T1 time (output high) is determined by T1 =0.693(R1 + R2)C1 and T2 time (output low) ,T2 =0.693( R1 x C1 ). The frequency of the output, f = 1.44 / (R1 + 2R2)C1. (a) (b)
Figure 4: (a) Astable Mode for 555 timer; (b) Free running frequency

Figure 5 shows the pin outlines of CMOS 4017 decade counter. The count advances as the clock input becomes high (on the rising-edge). Each output Q0-Q9 goes high in turn as counting advances. For some functions (such as flash sequences) outputs may be combined using diodes. The reset input should be low (0V) for normal operation (counting 0-9). When high it resets the count to zero (Q0 high). This can be done manually with a switch between reset and +Vs and a 10k resistor between reset and 0V. Counting to less than 9 is achieved by connecting the relevant output (Q0-Q9) to reset, for example to count 0,1,2,3 connect Q4 to reset. The disable input should be low (0V) for normal operation. When high it disables counting so that clock pulses are ignored and the count is kept constant. The ÷10 output is high for counts 0-4 and low for 5-9, so it provides an output at 1/10 of the clock frequency. It can be used to drive the clock input of another 4017 (to count the tens).

Figure 5: Pin outlines of CMOS 4017

4.0 PROCEDURES 1. Design the circuit in Figure 1 using PROTEUS and fabricate the circuit using printed circuit board (PCB). 2. Observe the output of circuit (LED) by adjusting the variable resistor, VR1. Comment your result. 3. Compare the running frequency of 555 timer between measurement and calculation. Comment your result. 4. Observe the voltage output across capacitor, C2 and output of 555 timer. Comment your result.

5.0 SAFETY GUIDE 1. Before making any connections to your circuit, always make sure that the power supply is turned off. 2. Ensure that the circuit “Ground” and “Power” connections are correct first before making any other connections. 3. Keep your working area clean and organized. Store away all unused components or equipment in their proper places.

6.0 RESULT
Attach the all results including tables, figures (completely labels), schematic diagram and any related calculations and simulations.

7.0 DISCUSSION
Discuss and analyzed your results including comparison, problem, suggestion. Every figure must be explained clearly.

8.0 QUESTION
1. Which Light Emitting Diodes (LED) light on for the beginning? Explain
2. Light Emitting Diodes (LED) light on from first count to the end in a circle time. Please state the IC pin number from first count to the end.
3. If variable resistor was adjusted to increase the resistant, observe the effect to LED. Explain.
4. What type of mode of 555 timer in your circuit design. Explain.

9.0 REPORT GUIDELINE

1. Short report must be in hand writing – results (simulation output vs measurement output) and questions.
2. Student must demo their project to the lecturer (circuit functionality &testing procedure) and show your project evaluation rubric during the demonstration.
3. Student must submit short report (maximum 5 pages), PCB design and project evaluation rubric. Due date on 6 September 2013.
4. Final report (combine with other modules)- objectives, introduction (Extended Theory) , apparatus (equipment), experiment’s Procedure), results (calculation, simulation and measurement), project methodology (process of circuit design), discussion of results and questions, conclusion, appendix and references.

ELECTRONIC ENGINEERING PRACTICE (BENU 2002) | PROJECT EVALUATION RUBRIC (MINI PROJECT) | ** Student Section (fill all the information below) | | | | | | | | | | STUDENT NAME: | | | | | | | | | COURSE: | | | | | | | | | | GROUP: | | | | | | | | | | PROJECT: | | | | | | | | | | | | | | | | | | | | ASSESSMENT SCALE: | | | | | | | | | 5: Outstanding: Your work demonstrates excellence in this portion of the activity. | | 4: Highly Competent: Your work fulfills all of the objectives of this portion of the activity. | 3: Competent: Your work is acceptable, but needs minor revisions. | | | 2: Not yet Competent: Your work is acceptable but requires major revisions. | | | 1: Not Achieved: Your work is incomplete. | | | | | | 0: Not submitted. | | | | | | | | | | | | | | | | | | | 1. Functionality of Circuit & Testing (30%) | | | | Scale | Score | | (a) Circuit was working properly. (20%) | | | | | | | (b) Ability to use the equipments during circuit testing. (10%) | | | | | | | | | | | | | | | 2. PCB Design (20%) | | | | | | | | | (a) Design optimizes available space on PCB. (5%) | | | | | | (b) Holes accurately drilled. (5%) | | | | | (c) Modifications & Cleanliness of PCB. (5%) | | | | | (d) Show the complete information’s (name, course, group) on PCB. (5%) | | | | | | | | | 3. Soldering (15%) | | (a) Sufficient amount of solder used on all connections. (5%) | | | | | | | | (b) Components leads and wires neatly trimmed. (5%) | | | | | | | | (c) Uniformity of solder connections. (5%) | | | | | | | | | | | | | | 4. Results (20%) | | | | | | | | | (a) Simulation | | | | | (b) Measurement | | | | | | | | | 5. Questions (15%) | | | | | | | | | | | | | | | | | | | | | | TOTAL (100%) | | | | | | | | | | | | | | | | | | | OVERALL (40%) | | | |