Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms
Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms
Abstract
Adding more processor core can help in the improvement of a computer performance. As a result in the number of high specification application being run on the computer, it reduces the processing ratio of processor core. This journal focuses on how the system resources is being shared. It also explains how an algorithm is being use to share, map and schedule task for more processor cores. At the end of the research, the algorithm states how the processor core are being improved greatly by 64.77% . with the speed up ratio of 43.55 can be obtained if 48 process unit is employed and are all activated and 10% will be the performance ratio.
Introduction
Demand for high definition image of modern images made the computation working application much higher. To achieve efficiency improvements were needed on the system architecture. The frequency of single core processors could not have any impact on the processor cores even when the frequency is increased, as a result processors with higher computation power were employed. Today a number of parallel image processing algorithms with emphasis in manipulating the arithmetical level ignoring the limitation of hardware in a many processor core machine and are also developed for many core system. In other to know how to utilize the said algorithm, a dedicated (special) hardware structure must be put in place since a special communication channel is needed for the data to be transmitted through the memory interface.
A machine with many processor core are seen as the same for different application. The two system resources that are shared is the physical and memory controller with the processor core. In a situation whereby many processor cores tries to access s system resource, all of the system resources cannot be granted at the same time, some of the already running process has to be put on hold for a system with an higher priority to use the process/resources. The method usually reduces the performance of the processor cores. To ensure that such issues never raise again, similar scheduling task and management of the space in the memory must be tackled.
Because of the complexity of image integrity, inputting method for image-based integrity protocol algorithm is utilized. The computation methods is being imported to the memory mapping and another section of the input goes into the scheduling task algorithm.
To derive the actual scheduling task and memory mapping result, is gotten from TILE64 processor cores and also improves the performance result. The derived result of the result conducted proves that propound algorithm can have a great impact on the processor core speed rotation up to 43.55x if 48 processors bit is employed and they are all activated. This simply means that the improved performance detolorate ratio will be less than 10% based on the research conducted, a conclusion was drawn that the computation methods is in urgent issue to the performance of the system. When insufficient computation method is used, it will increase the performance loss ratio of 50% despite the fact that task scheduling and memory mapping are not initialized. This is how this journal is structured. Section 2 talks about the problem of task scheduling and memory mapping in a more processing core machine. The inputting method for an image based integrity processing algorithms are introduced in section 3. Section 4 talks about the problem of task and memory mapping and how to go about solving the above problem. Section 5 talks about the structure of TILE64 hardware and the number of processing core involves. Section 6 talks about the research result and section 7 talks about the conclusion drawn from the whole section.
Motivation:
Machine with many processor cores usually comes with a dedicated system cache resources. This cache resources are ……. To individual cores of the processor. The sharing takes place from interface down to the main memory. This rely on the amount of processing cores and the amount of memory bandwidth that required to carry out the operation and it’s sometimes requires one or more memory module controller to be employed. Let take TILE64 processor core for instance, DDR2 memory x4 controllers is made available to enhance the bandwidth of 25.6GB/s. In accordance to the structure, individual memory controller may utilize among a set of processor cores or all of the cores. For individual controller, a queue for memory is requested and maintained for the cores that is making the request and it also service such request. Individual memory controller has the capability of accessing a special (dedicated) physical memory address and is also capable of treating a memory request one after another.
Mostly, the amount of memory controllers is almost lower than the amount of processor cores in the system. The amount of request generated can be treated in parallel and always restricted. When a proper checks and balances is not put in place, task that require more memory will eat up the system resources, this can resolve to reduction in the performance. All the supported memory space is mostly independent, this is done to abstain from problems. To make optimum use of the system resources made available, memory address must be supported by an entirely different memory controller. The diagram in figure 1 shows the importance of how to judiciously manage a memory, the impact on performance and scheduling task in a multi core processor machine.

Figure 1(a) shows a machine that has four processor cores and two main memory controller. All the four cores and two main memory controller. All the four processor cores is being utilized by the main memory controller. This means that each individual cores is permitted to use any one of the core two main memory controllers. The physical memory space on 1 and the physical memory space on 2 are being supported by the memory controller in 1 and memory controller in 2. Figure 2b shows a graph that illustrated two types of task, the load () and the proc () are put into consideration. The load () a task operation load () can operate in parallel if the data that the computation is to be performed on resides in a different physical memory address. The task proc() operation simply means that the data to which the computation is to be performed resides on a local cache. A, B, C, D is use to represent to represent the data state in the example above. Because data depends on their self, it has to follow the A, B, C, D order.
The explanations below shows that main memory mapping and scheduling task are put into consideration.
Figure 1c above shows that the data object (A, B) and (C, D) is pointed to the physical memory address of I and II. The job of loading (B) and loading (D) are made available to the task load (A) and load (C). This simply means that the appointment of load () operation does not know about the reliance of proc () operation. For instance, if each proc () operation allows 1X unit. For the above example, the operation execution of proc (A) is shifted to the five times unit because the load (A) operation is not successful until the execution of the fourth unit. All the amount of time needed to fully accomplish the load () and proc () operation is 8X.
The task of scheduling load () operation must be adjusted before the execution of proc (A) operation will be allowed.
Figure 1d shows that load (A) and load(C) are appointed for the operation of load (B), load (D). The example means that the execution of proc (A) operation will commence in 3X unit. Thus the running of proc (B) operation will be moved for just a time unit as a result of load (B) operation. The overall amount of time needed to fully execute both load () and proc () operation is 7X.
Figure 1(e) shows that memory mapping and scheduling task issue is addressed. Pointing the data A, B object to a physical memory address allows by all the different memory controllers. The operation of loading (A) and the load (B) can be executed in parallel.
In the process of scheduling, load (A) and (B) will be the 2nd unit, the running of proc (A) operation without any delay. The overall amount of time needed to execute all load () operation and proc () operation is improved greatly by 6X of the unit. With this example, we can conclude that if memory mapping and task scheduling is not put into consideration, it will lead to a great loss of the processor core performance. The issue tends to increase when the number of processor cores is more. This paper illustrated the mapping skeleton and task scheduling for image recycling and it also prove the impact of TILE64 on a processor with many cores irrespective of the platform.
Section II Proposed computation method for image integrity on many core machine.
Softwares that require high graphic image processing, pixel plays a vey important role and it has some standard rules to abide by. For instance, if p(x,y) represent the image pixel at a particular point in time, say (x,y). The end result of p(x-1,y) and p(x,y-1) will be derived when p(x,y) is used. 1. Calculation of image integral.
The calculation of image integral is as shown below:
If we use a pixel with an integral of (x,y) is represented as II(x,y). we can sum it up as a pixel inside of a rectangle by using (o,o) and (x,y). The description of (xy) II can be seen as equation (i).
II(x, y) =
To make optimum use of image integral calculation, an algorithm was developed to do the computation by Jones and Viola. The algorithms is as shown below.

In the equation above, C(x, y) represent cumulative row sum at a particular point in time let’s say (x,y). If the size of an image is WxH, then 2 has to be added to the belonging of computation like this 2xWxH. 2. Simultaneous computation method for integral image on processor with many cores.
In other to run different processes simultaneously on a processor with many cores using a process unit. The image is executed by a dedicated processor core unit. It inputting method is explained in the rest of the passage below.

i. Divide and update inputting method: Data dependent and data independent part is used as computation in the divide and update method. The calculation in data independent is achieved simultaneously, after that, the end result of individual sub image is moved and mixed to a new update stage. The data dependent is done in the update stage. The inputting of individual sub image result is been updated based on the data that was transferred and the aim here is to satisfy the data dependency. Thus, the inputting of divide and update computation methods let some of the input to be done simultaneously without any reliance, although, additional inputting total is added to the update stage. The inputting of integral image with divide and update method is shown in figure 2. In figure 2(a) , the figure is sub divided into sub figures ao and a1 using a row based division method. Each sub image can be inputted individually. If II, (x, y) represent the integral image of image I: at the address of (x,y). With proper explanations, IIo (x, y) is inputted as the end result of all of the pixel in the image. II0(x, yo) is equal to II all(X and yo).
The overall steps in shown in figure 3. For instance, if we use a system that has n as the processor unit. Here Pi, represent the processor cores in units and figure is as shown below. Iii with image integral is inputted first. The boundary for the update of I1-1 and is represented as Bi-1 is gotten for Pi-1. If we use h, h represent the sun image height. The equation below shows how to work with the update boundary.

Conclusion:

This paper shows how the techniques user for task scheduling and memory mapping works in the performance of processors with many cores. The computation method used for the processing of images with the help of the said algorithm. The research was conducted and TILE64 processor core is used as a case study. Pipelining and the divide and update can be greatly improved by 39.86% and 32.55%. If memory mapping and task scheduling are methods are utilized, the pipeline and divide and update performance will be greatly improved by 72.13% and 57.42%.It was noticed that the features of computation method is important. The rate of loss in performance is 10%. The rate of loss ratio is larger than 50% when divide and update computation is used either task scheduling and memory technique.

References:

Ang-Chih Hsieh, Yi-Ta Wu, Shau- Yin Tseng, and TingTing Hwang‡ Information and Communication Research Laboratories, Industrial Technology Research Institute Department of Computer Science, National Tsing Hua University
{achsieh, yitawu, tseng}@itri.org.tw; tingting@cs.nthu.edu.tw