Objective To implement the Product of Sums (POS) of a Boolean expression.
Components
ICs: NOT (7404), 2-input AND (7408), 2-input OR (7432) Lab equipment: breadboard, power supply, multimeter.
Problem
Derive the Product of Sums (POS) expression from the equation provided below.

Y = A’B + B’C’D’ + BCD + AB’CD Note that gates with large number of inputs can be constructed from gates with less number of inputs.
Introduction
The equation Y=A’B+B’C’D’+BCD+AB’CD needs to be rearranged using a Karnaugh map to support the product of sums circuit. The truth table for the previous experiment, Lab 2 SOP Implementation of Boolean Expressions, is used for the Karnaugh map. IC 7408 and 7432 only has 2 inputs for each gate, so an extra pair is needed to be able to manage the amount of OR gates required.
Prelab
In order to simplify the equation, the truth table needed to be solved for Y = A’B + B’C’D’ + BCD + AB’CD and converted using a Karnaugh map. During simplification, the coordinates at the 0’s that are grouped up horizontally and vertically, in groups of two, and are divided. When searching for the product of sums the 1’s turn to 0’s, and is a commonly missed error. After simplifying the expression, the schematic was drawn to map out the 2 input gate structure of the ICs: 7404, 7408, and 7432.

Truth Table for Y = A’B + B’C’D’ + BCD + AB’CD A’ | B’ | C’ | D’ | A | B | C | D | A’B | B’C’D’ | BCD | AB’CD | Y | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 |

Karnaugh Map

AB/CD | 00 | 01 | 11 | 10 | 00 | 1 | 0 | 0 | 0 | 01 | 1 | 0 | 1 | 0 | 11 | 0 | 0 | 1 | 0 | 10 | 1 | 1 | 1 | 1 |

Simplification

Boolean Expression

In the Lab The connections were mapped out on a piece of paper to keep track of what was next. IC 7404 is the main chip giving off the NOT gates, and was aligned first on the board, starting at row 5. IC 7432 is composed of OR gates, and IC 7408 contains the AND gates. By looking at the full equation the circuit needed eight OR gates, six NOT gates, and only three AND gates. After the IC 7404 chip, two IC 7432s were aligned at row 17 and row 30. The circuit only needed one IC 7408 at row 40 to prove the product of sums. Green wires were used for power and grounding. Black wires were inputs, and red wires were outputs. Beginning at IC 7404 we connected all the inputs of the first four gates to represent the A, B, C, and D in the equation. The first connection wrote down was from IC 7404 pin 2 to IC 7432(1) pin 1. The second connection was from IC 7404 pin 4 to IC 7432(1) pin 2. The output of IC 7432(1) pin 3 went down onto pin 4. The third connection was from IC 7404 pin 5 to IC 7432(1) pin 5. This should give A’+B’+C as an output for IC 7432(1) pin 6. The fourth connection starts from IC 7404 pin 1 and ends at IC 7432(1) pin 13. The fifth connection starts from IC 7404 pin 5 and ends at IC 7432(1) pin 12. The output A+C is moved down one from IC 7432(1) pin 11 onto IC 7432(1) pin 10. The sixth connection starts from IC 7404 pin 12 to IC 7432(1) pin 9. This should give A+C+D’ as an output for IC 7432(1) pin 8. The seventh connection starts at IC 7404 pin 1 and ends at IC 7432(2) pin 1. The eighth connections starts at IC 7404 pin 3 and ends at IC 7432(2) pin 2. The output for IC 7432(2) pin 3, A+B, is moved down onto pin 4. The ninth connection starts at IC 7404 pin 6 and ends at IC 7432(2) pin 5. This should give an output of A+B+C’ for IC 7432(2) pin 6. The tenth connection starts at IC 7404 pin 4 and ends at IC 7432(2) pin 13. The eleventh connection starts from IC 7404 pin 6 and ends IC 7432(2) pin 12. This should give an output of B’+C’ at IC 7432(2) pin 11. The output for IC 7432(2) pin 11 is moved down onto pin 10. The twelfth connection starts at IC 7404 pin 13 and ends at IC 7432(2) pin 9. The output for IC 7432(2) pin 8 should be B’+C’+D. The outputs for IC 7432(1) pin 6 and pin 8 are moved into IC 7408 pins 1 and 2. IC 7408 pin 3 should have an output of (A’+B’+C)(A+C+D’). The output for IC 7432(2) pin 6 and pin 8 are moved in IC 7408 pins 4 and 5. IC 7408 pin 6 should have an output of (A+B+C’)(B’+C’+D). Finally the outputs for IC 7408 pin 3 and pin 6 are moved into IC 7408 pins 13 and 12. The output for IC 7408 pin 11 can be measured using a multimeter and 5V from this point on flawlessly. To track the connections it is necessary to write them down.

Breadboard Configuration
IC 7404 NOT gate | Pin Number | Pin Number | | A | 1 | 14 | Voltage | A’ | 2 | 13 | D | B | 3 | 12 | D’ | B’ | 4 | 11 | | C | 5 | 10 | | C’ | 6 | 9 | | Ground | 7 | 8 | |

IC 7432 (1) OR gate | Pin Number | Pin Number | | A | 1 | 14 | Voltage | B’ | 2 | 13 | A | A’+ B’ | 3 | 12 | C | A’+ B’ | 4 | 11 | A+C | C | 5 | 10 | A+C | A’ + B’ + C | 6 | 9 | D’ | Ground | 7 | 8 | A + C + D’ |

IC 7432 (2) OR gate | Pin Number | Pin Number | | A | 1 | 14 | Voltage | B | 2 | 13 | B’ | A+B | 3 | 12 | C’ | A + B | 4 | 11 | B’ + C’ | C’ | 5 | 10 | B’ + C’ | A + B + C’ | 6 | 9 | D | Ground | 7 | 8 | B’ + C’ + D |

IC 7408 AND gate | Pin Number | Pin Number | | A’+B’+C | 1 | 14 | Voltage | A+C+D’ | 2 | 13 | (A’+B’+C)(A+C+D’) | (A’+B’+C)(A+C+D’) | 3 | 12 | (A+B+C’)(B’+C’+D | A+B+C’ | 4 | 11 | (A’+B’+C)(A+C+D’)(A+B+C’)(B’+C’+D) | B’+C’+D | 5 | 10 | | (A+B+C’)(B’+C’+D) | 6 | 9 | | Ground | 7 | 8 | |

Conclusion This lab experiment taught us the transition you take from sum of products to a product of sums equation. Before we came to the lab, we had no idea what a Karnaugh map was. The Karnaugh map taught us how to make a product of sums equation out of the truth table for the sum of products. In our pre-lab I assumed the equation Y = A’B + B’C’D’ + BCD + AB’CD was flipped as Y = AB’+ BCD + B’C’D’ + A’BC’D’, but I was wrong and was quick to learn why. After finding out about how the Karnaugh map works, I began deriving all the max terms and double checked to make sure every 1 was considered a compliment of its variable. The Karnaugh map is used to find equations out of truth tables that don’t have any expressions to represent what it shows. To find the sum of products using a Karnaugh map all you do is group up the 1s, and then find their min terms. To find the product of sums using a Karnaugh map all we did was group the 0s, and find the max terms for those cells. When grouping the 0s though, a common error made is not changing the 1s into 0s to represent the correct variables for simplification.