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MODERN CHIP COMPONENTS
The four most important concepts in microprocessor architectures are functional units, pipelines, caches, and buses. These factors determine how fast a processor will run and how efficiently it will communicate with the outside world. Functional units are subsystems of logic circuits that carry out a program’s instructions. Different types of functional units handle different instructions. Integer units handle fixed-point arithmetic and Boolean logic. Floating-point units handle more complex arithmetic operations, involving noninteger values. Load/store units load data from and store data to memory. Pipelines work like factory assembly lines. Each stage of the pipeline handles one relatively small and simple task that comprises part of the work needed to execute one computer instruction. A simple pipeline has four stages: fetch (retrieve an instruction from cache); decode (figure out what the instruction does); execute (carry out the instruction); and write back (store the result). Each pipeline stage usually takes one clock cycle. Most modern processors have superscalar pipelines, which are two or more pipelines arranged in parallel. That way, the processor can issue and complete multiple instructions in each clock cycle. The processor may also rearrange the instructions at execution time to put them in a more efficient order. This procedure is called dynamic execution. Modern processors can operate at speeds above 1 GHz. To maintain this rate, the processor must fetch a new instruction every nanosecond. Unfortunately, the main memory system that holds the computer program needs as much as 70 nanoseconds to pull an instruction out of its memory banks and send it to the processor. Caches provide a solution to this speed mismatch. Caches are blocks of fast memory that temporarily hold instructions and data. The processor’s fastest cache is called the primary or Level 1 (L1) cache and usually is integrated on the chip. L1 caches usually range from about 4 kilobytes to 128 kilobytes in size. Whenever the processor needs instructions and data, it looks in the L1 cache first. If it cannot find what it needs in the L1 cache, it looks in the secondary or Level 2 (L2) cache. Secondary caches are much larger than primary caches, but not as fast. When a processor cannot find the instructions and data it needs in either the L1 or L2 caches, it looks at main memory (dynamic random access memory). A system bus (frontside bus) is the chip’s interface to external devices. (The L2 cache bus is called the backside bus.) A bus is a physical channel through which data are transmitted from one part of the computer to another. All buses consist of two parts: a data bus, which transfers data, and an address bus, which transfers information about where the data should go. The peak capacity of a bus depends on its width and its clock frequency. A wider bus can transmit more bits per clock cycle. Higher clock frequencies transmit more bits in a given amount of time. A processor’s peak bus bandwidth is the product of the width of its bus (measured in bytes) times the frequency at which the bus transfers data (measured in megahertz). For example, Intel’s Pentium 4 processor uses a 64-bit bus that runs at 400 MHz, giving the processor a peak bandwidth of 3.2 Gbps.

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CPU OPERATIONS

The execution of machine-level instructions is composed of the instruction phase and the execution phase, each phase having two processes. The time it takes to perform the instruction phase is called the instruction time (I-time) and the time it takes to perform the execution phase is called the execution time (E-time). Each instruction must go through both phases. The two phases, taken together, constitute a machine cycle. The control unit directs the phases of the machine cycle through microcode. Microcode is composed of predefined circuits that the processor performs when it executes an instruction. Microcode is literally software instructions that have been implemented as hardware circuits.

Instruction Phase
Process 1—Fetch instruction. The control unit accesses the instruction to be executed from memory. Process 2—The control unit decodes the instruction so the central processor knows what is to be done, necessary data are moved from memory to the registers, and the next instruction is identified.

Execution Phase
Process 3—Execute the instruction. The ALU does what it is instructed to do, either a mathematical operation or a logical comparison. Process 4—Store the results. The results are stored in the registers or in memory.

PROCESSOR BENCHMARKS

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The iCOMP (Intel Comparative Microprocessor Performance) Index from Intel provides a simple, relative measure of microprocessor performance. It is not a benchmark, but a collection of benchmarks that take into account typical processing needs, including the increasing use of 3D, multimedia, and Internet technology and software. The higher the iCOMP rating, the higher the relative performance of a processor. For example, an Intel Pentium III processor running at 933 MHz has an iCOMP rating of 3100; and an Intel Pentium III processor running at 1.0 GHz has an iCOMP rating of 3280. There are other chip benchmarks, which include the CPUmark, WinTune Integer Test, and SPECint. There are also benchmarks for specific applications, such as: • Productivity software benchmarks (word processing, presentation, personal finance) (SYSmark* 2001, SPECint* 2000) • Multimedia benchmarks (Video*2000-Performance, Video*2000-MPEG2 Encoding) • *3D/Floating-point benchmarks (3D WinBench* 2000-Processor Test, SPECfp* 2000) • Internet technology benchmarks (WebMark* 2001) Popular PC magazines (e.g., PC Magazine, PC World, Computer Shopper) provide less technical measures of processor performance, such as price, performance, reliability, services, and other factors.

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MICROPROCESSOR ARCHITECTURES
Complex instruction set computing (CISC), the oldest approach to microprocessor design, appears most notably in Intel’s x86 series. CISC first appeared in 1978 with the 8086 chip. CISC architectures attempted to use the smallest amount of system memory, which was then both expensive and slow. Mainframes then contained a few megabytes of memory, and early desktop systems had only a few kilobytes. Manufacturing processes severely limited the number of transistors that could fit on a chip. (The 8086 had 29,000 transistors compared with about 42 million in a Pentium 4.) As a result, Intel made compromises in the 1970s that continue to affect the x86 today: a small set of registers, variable-length instructions, and highly complex instructions that take a long time to execute. These CISC architectures can address only 4 GB of main memory, which is already a limitation in high-end computers. Reduced instruction set computing (RISC) uses simple, fixed-length instructions that execute quickly. Grouped together, several instructions perform the same actions as one CISC instruction. RISC processors include a large number of available registers. Very long instruction word (VLIW) architectures take a different approach to processor organization. CISC and RISC approaches use on-chip hardware resources to make complex decisions about scheduling machine-level instructions within a program, where VLIW architectures make these decisions when a program is compiled. This approach transfers complexity from hardware to software and makes the processor easier to design and more efficient because it uses software instead of hardware to handle these difficult scheduling tasks. In practice, creating compilers that optimize code performance for VLIW architectures has been difficult. VLIW architectures have proven well suited to performing multimedia operations and scientific/engineering programs. Explicitly parallel instruction computing (EPIC), the newest microprocessor architecture, combines the RISC and VLIW concepts. The EPIC approach embeds in the instruction stream explicit information that tells the processor which program instructions to execute in parallel. Intel’s Pentium 4 is the first implementation of EPIC architecture.

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ADVANCED CHIP TECHNOLOGIES The Crusoe Chip by Transmeta
Transmeta designed its Crusoe microprocessor (chip) largely for portable devices that will supplement desktop PCs as a common means of connecting to the Internet. The Crusoe chip was built for mobile applications, and Transmeta claims that the processor can efficiently run software programs designed for larger Pentium chips (e.g., Windows or Linux), while consuming less electricity and generating less heat. In January 2001, Transmeta introduced three types of Crusoe chip, the TM3200, the TM5400, and the TM5600. The smallest (TM3200) is designed for handheld devices such as smart phones and pocket computers. The larger and faster TM5400 and TM5600 are designed to run Linux or Windows on notebook computers. The Crusoe chip has its own instruction-set architecture, based on Transmeta’s proprietary 128-bit VLIW (very long instruction word) architecture and design. The Transmeta design does have advantages over traditional microprocessors. The VLIW instruction set is smaller and lacks many of the specialized instructions that Intel has added to the Pentium series to optimize it for specific tasks like streaming multimedia. That lowers the overall transistor count, reducing power consumption and generating

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Computer Hardware less heat. A TM5400 chip in an idle personal computer consumes about 16 percent of the power used by an Intel Mobile Pentium III in the same personal computer. For Web browsing and playing DVDs and MP3s, the TM5400 consumes between 20 and 30 percent of the power that the Mobile Pentium III does. Software written for Intel x86 chips will not run directly on Crusoe chips. Instead, Crusoe chips run one custom software program, written by Transmeta. This program dynamically translates x86 instructions into Crusoe instructions, then executes them. Transmeta calls this process “code morphing.” The code-morphing software is stored on a reprogrammable Flash ROM chip, making it easy to upgrade the software without having to buy replacement hardware. The Crusoe chip executes the entire range of x86 instructions by using its codemorphing software. For example, the code-morphing software might need to translate one complex Pentium instruction into 15 VLIW instructions. However, most of the time, there is a one-to-one correspondence between x86 instructions and VLIW instructions. In fact, the Crusoe chip can outperform this one-to-one ratio. With simple x86 instructions, the code-morphing software can put four of Intel’s 32-bit x86 instructions into a single 128-bit VLIW instruction and execute them simultaneously. Therefore, the Crusoe chip might be slower with a few complex instructions, but it makes up for lost time with simpler instructions. (Source: Red Herring, March 2000; Red Herring, October 30, 2000; Red Herring, February 13, 2001; MIT Technology Review, November/December 2000.)

DNA Chips
DNA microarrays or DNA chips appeared in 1996 when Affymetrix introduced the first commercial version, which the company called GeneChip. Affymetrix used lightsensitive chemical reactions to grow a grid-like pattern of as many as 400,000 short DNA strands, called probes, on a glass wafer. Since each probe can bind to a different gene sequence in a sample of DNA, the chips allow researchers to perform what once would have been thousands of separate experiments all at the same time. DNA chips open up new possibilities: new understanding of the role genes play in heart disease or antibiotic resistance; tools for prenatal or infection diagnosis that incorporate all the genes of interest on a single chip; and massive-scale automated screening of potential drugs. Advantages of DNA chips include: • They work in parallel, processing all possible answers at the same time. • They are fast. • They are energy-efficient. Conventional chips waste about a billion times more energy per operation than do DNA chips. • They have a huge storage capacity. One gram of DNA can hold the data of a trillion CDs. Example of How DNA Chips Work: 1. Start with a group of patients, some of whom have one type of cancer and some of whom have another. 2. For each patient, take a sample of cancer cells and isolate all the genes that are active in those cells. Make copies of those genes, incorporating some special nucleotides, or DNA letters (DNA bases), that have a fluorescent dye attached to them.

Chapter 3 3. Put the new gene copies onto a DNA microarray, a chip covered with a grid of several thousand probes—short stretches of DNA that each bind to a unique gene sequence. 4. When a probe matches one of the genes that are active in the cancer cells, it binds to the copy of that gene. Once binding takes place, wash away the extra free-floating DNA. 5. Put the DNA chip into the chip scanner. There, a laser shines light on the chip and causes the fluorescent dye to glow, making a pattern of light spots where labeled gene copies are bound to probes and dark spots where there are unbound probes. The scanner detects the fluorescence and records an image of the grid of light and dark. 6. Using a computer that has been fed a map of where each probe is on the microarray, you can determine which genes are active in each sample. Careful analysis of these results can allow you to pinpoint small sets of genes that are active in one cancer but not the other. In the future, these genes could become targets for new drugs, or could be the basis for new, highly specific diagnostic tests.

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Optical Computing
In today’s chips, data move on pathways made of very thin strands of metal (aluminum or copper). In the very near future, the most critical of those pathways could be replaced with fiber circuits carrying tiny pulses of laser light. It may even be possible to dispense with some of the fibers and wires altogether and move laser light through open circuits within the chip. This change could be critical. The speed of computer chips could reach an absolute barrier in the next decade. The barrier will vary because how much data a wire can transmit is determined by a ratio of wire length and thickness. If a wire is too long or thin, the bandwidth will be low. Part of the problem is the physical properties of metal. Metal interconnects can allow data to move only so fast. Optical interconnects may then have to take the place of metal ones wherever bottlenecks may occur. In effect, researchers want to add optical express lanes to conventional chips. Electricity moves slower through a metal wire than light moves through the air or an optical fiber. That is because electrical properties such as resistance limit the throughput of metal wires and also produce a lot of heat. Light has another key advantage: Many different frequencies of light can be sent down the same fiber. Such multiplexing, which is done routinely in telecommunications, could allow several metal wires to be replaced by just one fiber that can transmit just as much data. In optical systems, laser light pulses carry data. Researchers want to develop a silicon laser that can be integrated within the chip and be flicked on and off to produce these pulses. Researchers in Europe and the United States have recently discovered techniques to get silicon to amplify light and then emit it with some efficiency, key steps toward a silicon laser. Another problem is that silicon lasers must be powered by electricity coming from other parts of the chip, a problem that has not been solved. Further, a way to route data within an optical chip is, as yet, unknown. In traditional chips, the flow of current around the circuits is governed by the transistors, which are tiny switches. Making analogous optical devices on the tiny scale demanded by chip-making is a breakthrough waiting to be achieved.

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Reconfigurable Processors
So far, no one has figured out how to produce a chip that meets all the criteria for the ultimate consumer device. Such a chip would have to have flexibility, high performance, low power consumption, and low cost, and would need to get to the market quickly before the multiple features it supported became outdated. Now a new kind of chip may reshape the semiconductor arena. The chip adapts to any programming task by effectively erasing its hardware design and regenerating new hardware that is perfectly suited to run the software at hand. These chips, referred to as reconfigurable processors, could tilt the balance of power that has preserved a decade-long standoff between programmable chips and hard-wired custom chips. These new chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the utmost speed. If silicon can become dynamic, then so will the devices. No longer will you have to buy a camera and a tape recorder. You could just buy one device and then download a new function for it when you want to take some pictures or make a recording. These chips are programmable logic devices with hardware that can be rewritten hundreds of times a second. Each has two parts: one that serves as a quickly accessible library, or cache, for hardware components, and another that is like a blank chalkboard. As needed, the chip takes a hardware component from the library and places it onto the blank chalkboard. There, the component executes the software running at the moment. When it is finished, the hardware component is erased, and a new component is placed in to process the next piece of software. It takes complex scheduling to map the right piece of hardware into the chalkboard at exactly the right time. But the advantages are potentially huge. The chip can be smaller because its chalkboard allows it to fetch hardware components from memory, meaning that it does not use valuable chip space to store the entire library of hardware components, as a microprocessor does. Without such a chalkboard, a microprocessor has the whole library in place and drawing electricity at all times, even though only 1 to 5 percent is being used at any given time. By contrast, a reconfigurable chip uses only the piece of hardware that it needs at any one time, and it uses power only for the active function.

Molecular Computing
In this new field—which merges the technologies of electrical engineering and the materials of physical chemistry—individual molecules take the place of switches etched on silicon wafers. Because the molecules are roughly one-millionth the size of today’s silicon switches, computing could be performed in tiny spaces using far less power. Molecular switches are easily grown in mass quantities, require very little power, and are relatively cheap. Silicon switches are expensive, larger, slower to produce, and require much power.

Intelligent Random Access Memory (IRAM)
This advance in chip design combines a microprocessor and a memory chip on a single silicon wafer. University of California at Berkeley Professor Dave Patterson invented the chip, and IBM will fabricate the prototype. The plan was to begin testing the prototype at the end of 2001 in applications such as multimedia and portable systems. The chip may accelerate the market for a new generation of handheld computers that would combine wireless communications, television, speech recognition, graphics, and video games. One application is to leverage IRAM so that a handheld like the Palm can be used as a tape recorder with speech recognition and file-index capabilities.

Chapter 3 IRAM has the potential for removing the bottleneck that has restrained processing speeds in microprocessors. Over the last two decades, the speed of microprocessors has increased more than 100 times. But, while memory chips (DRAMs) have kept pace in terms of capacity, their speed has increased by only a factor of ten. As a result, microprocessors spend more time waiting for data and less time doing valuable computations. As the gap between speeds widens, methods to help alleviate the problem, like memory caching, are becoming less useful.

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HARD DISK DRIVES
In 1956, IBM released the first disk drive. The 350 Ramac, a 50-disk storage unit, was a huge device that leased for $3,200 a month and stored 5 megabytes. In 1980, IBM produced the first storage system that could hold 1 billion bytes of data. Known as the 3380 disk drive, it cost $40,000, stood as tall as a refrigerator, and weighed 550 pounds. In 2000, IBM released the Microdrive, with a capacity of 1 gigabyte, a cost of $499, the size of a matchbook, and a weight of less than one ounce. By the end of 2001, the Microdrive will have a capacity of 2 GB—enough printed material to fill two pickup trucks. Hard disk drive technologies may be distinguished by several characteristics, which include the size of the unit, the areal density, and the speed of data access. By the second quarter of 2001, hard disk drives are 3.5-inch fixed head/disk assembly, 1.6 inches tall (known as half-height), and house 12 platters and 24 read/write heads with a capacity of 180 GB. The most common metric of storage technology is areal density, generally expressed as megabits per square inch. IBM researchers have exceeded the superparamagnetic limit—a point at which the tiny magnetic areas that store ones and zeros on the rotating platters used in hard disks become unstable. As a result, by the first quarter of 2001, IBM was shipping commercial products with areal densities as high as 25.7 billion bits (3.26 GB) per square inch. Many researchers say that with current technologies, the practical limit to areal or storage density may be as high as 100 billion bits (12.5 GB) per square inch. Therefore, it will be possible to build desktop drives capable of storing 400 GB of data and portable drives capable of storing 200 GB of data. Such a portable drive could hold the equivalent of 42 DVDs or 300 CDs’ worth of data. Storage density is increasing at nearly 100 percent per year, outpacing the rate that Moore’s Law predicted for semiconductors. The higher the density, the greater the capacity of a storage medium. Recall that, to access a given piece of data, read/write heads pivot across the rotating disks to locate the right track, calculated from an index table, and the head then waits as the disk rotates until the right sector is underneath it. Disk drives rotate at a constant speed, called the rotational speed. The speed at which hard disks rotate is significant because it determines how long it takes for the requested data to come into position under the read/write head. This delay is referred to as rotational latency time and on average is equal statistically to one-half of a disk revolution. In September 2000, the average high-performance disk rotated at 10,000 rpm. Early in 2000, Seagate Technology introduced its Cheetah X15 drive with a rotational speed of 15,000 rpm. Another element that affects a drive’s performance is seek time, which is the time it takes for the read/write heads to move into position to read the data. The final element that affects a drive’s performance is the transfer rate, measured in bits per second, which indicates the speed at which the read/write heads can transfer the data from the rotating disks.

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OTHER INTERFACES TO STORAGE SYSTEMS

Fibre channel, a high-speed interface, serves as a host to connect storage systems and servers and has become a foundation technology for SANs (discussed in the body of the chapter). Originally, the technology was used exclusively with fiber optic cable, but now fibre channel can also be used with copper cabling. Firewire, developed by Apple, is a high-speed interface that supports high-volume data transfers. Firewire is currently in limited use (on digital cameras, set-top boxes, printers, camcorders, and high-end computer systems), but is expected to become more widely available in consumer electronics devices and PCs sold to consumers. Infiniband offers a new high-speed interconnection to storage systems. Intended primarily as a next-generation replacement for communication between processors and storage devices, Infiniband offers very high-volume interconnection speeds over fiber and copper. The universal serial bus (USB) was originally developed as a means of replacing the serial and parallel ports that have historically been used to connect low-speed peripheral devices to PCs. (These devices include the keyboard and mouse, printers, scanners, and docking cradles for personal digital assistants.) USB 2.0 supports a broader range of I/O devices, including the full range of disk storage devices as well as digital video. USB 2.0 also has the ability to connect new devices without rebooting the system, a capability called hot plugging.

ADVANCED STORAGE TECHNOLOGIES Holographic Optical Storage

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Three-dimensional holographic storage promises to provide smaller storage devices, higher storage capacities, and faster data transfer rates. IBM labs anticipate that the first generation of these devices could store 125 GB of information on a removable 5.25-inch holographic disk. The potential exists to store one terabyte of data on one 5.25-inch disk. In addition, holographic storage has the possibility of reading and writing data one million bits at a time, instead of one by one as with magnetic storage. This means that you could duplicate an entire DVD movie in a few seconds. Holographic storage relies mainly on laser light and a photosensitive material— usually a crystal or a polymer—to save data. It works by splitting a laser beam in two. One beam contains the data and is referred to as the object beam. The other holds the location of the data and is called the reference beam. The two beams intersect to create an intricate pattern of light and dark bands. A replica of this interference pattern is engraved three-dimensionally into the photosensitive material and becomes the hologram. To retrieve the stored data, the reference beam is shone into the hologram, which refracts the light to replicate the data beam.

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ENTERPRISE STORAGE SYSTEMS
Enterprise storage systems are built around a high-speed interconnect (shared bus or switched fabric) that uses technology proprietary to the manufacturer. The system then is linked to the host via a fibre channel interface. Enterprise storage systems are designed to be modular so the customer can add storage incrementally after purchase. A number of characteristics distinguish enterprise storage from server-based storage: • Multiple heterogeneous host support. Enterprise storage must have the ability to access a common storage resource from hosts and servers of various types and must be able to run various operating systems. • Data sharing. Enterprise storage must allow multiple servers that handle different parts of the same application to use the same data files. When multiple systems share access to the same files, the data must be protected so multiple users or applications do not try to update the same data at the same time. • High performance. Enterprise storage must be able to deal with the quantity and variety of transactions requested of it without unacceptable degradation of performance. Because storage access requests may be coming from distant, diverse locations, an additional goal is to provide a uniform performance to the remote user population. • High availability. Enterprise systems are synonymous with worldwide operation and no allowance for downtime. These systems must have integrated fault tolerance and be able to perform both scheduled and unscheduled maintenance without disrupting business. • Disaster tolerance. Most disasters are unpredictable and unavoidable. Regardless of the cause or location, disasters should not result in an enterprise environment being down for more than a matter of minutes at most. Recovery of critical systems must be part of the business plan, which means having redundant backup hardware, software, and current data files. • Storage management and optimization. For the enterprise, this term means centralized management with decentralized access and control. • Numerous integrated technologies. Enterprise storage is not just for disk storage—it also relates to tape and other removable media types as well as to the libraries that manage them. • Scalable resources, function, and performance. All systems must be expandable online, and this expansion must be seamless and easy to maintain.

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SUPERCOMPUTERS
There are two types of supercomputer architectures: vector processors and massively parallel processing (MPP). Vector processing supercomputers, such as Cray T90 and NEC’s SX-5, use a small number of (as few as four) powerful vector processors. Vector processing performs operations on vectors, which are ordered collections of individual data elements. This approach is in contrast to scalar processing, which processes one data element at a time. Whole vectors are fed into the pipeline (in contrast to the loading of individual elements on a scalar processor), and the same operation is performed on each element of the vector. This approach, referred to as single instruction, multiple data (SIMD) technology, is also being built into microprocessors. Because of the small

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Computer Hardware number of processors, it is easy for the operating systems to divide tasks among processors, and the overhead associated with interprocessor communications is relatively low. A key aspect of vector computing has been the development of memory systems that allow the data to be streamed fast enough to the processor so operations can be performed without time lost waiting for vectorized data. A supercomputer is considered to be a massively parallel processor (MPP) if it operates with at least 64 processors, but MPP supercomputers can operate with thousands of processors. Examples of MPP supercomputers include Cray’s T3E (up to 2,048 processors) and IBM’s RS/6000 SP. Vendors of MPP systems typically use commodity microprocessors from Intel or one of the RISC vendors rather than the special kind found in vector systems. The processors usually are grouped into nodes—each node typically consists of several processors in SMP architecture, sharing memory and a memory bus. Each node might consist of 4, 8, or 16 processors that present a single-system image to the application, share a single memory bus, and have their own local shared memory resources. The nodes are then linked via a high-speed interconnect. One benefit of an MPP system is the greatly reduced contention for memory resources as compared to a shared-memory SMP system with the same number of processors. Because each node has its own memory and memory bus, contention among nodes for memory resources can be eliminated to the extent that an application can be partitioned and made parallel successfully. Unfortunately, the multiple nodes of an MPP system do not look like a single system to the application. Instead, each node must run its own copy of the program instructions (called the code segment), making memory management complex and resulting in slower access to memory. A significant repercussion of this issue is that applications must be written specifically or modified for an MPP environment, which has greatly slowed the adoption of massively parallel architectures. In addition, a large number of nodes increases the overhead associated with interprocessor communications. Supercomputing has evolved through three eras. The first era is best represented by the Cray 1 and offered performance by building fast processors. The second era, dominated by SMP and MPP systems, sought performance through thousands of processors. In the third era (just begun), organizations are coupling very large numbers of heterogeneous computers on networks to create virtual supercomputers. This trend builds on an effort known as the Beowulf Project that began trying to build a supercomputer by linking together multiple commodity systems in 1994. There are, however, new systems under development that will redefine the rules of high-capacity computing. Cray currently is developing the Cray SV2 system, which will be the first system to offer both vector and MPP capabilities in a single architecture. (The new systems should ship in the second half of 2002.) Supercomputers always have been reserved for a small number of select applications, and their greatest impact is probably in their use as a proving ground for new technology, rather than as a general commercial platform. For example, the U.S. government’s $2.5 billion ASCI project is designed to simulate the aging of nuclear weapons beyond their designated shelf life. In December 1999, IBM announced plans to build a 1 petaflops supercomputer. This system, known as Blue Gene because it will be used to study the structure of proteins, will be based on a highly optimized MPP architecture capable of automatically detecting and overcoming failures of individual processors and computing threads. IBM calls the architecture SMASH, for “Simple, Many, and Self-Healing.” Blue Gene will consist of more than 1 million processors, each capable of 1 Gflops performance. The processors themselves will be based on a simplified RISC architecture, with fewer

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than 60 instructions in its instruction set, compared with 200 for most current RISC architectures. If successful, the same technology then could be applied to commercial scientific and engineering applications as well as to memory-intensive applications such as data warehouses.

MAINFRAMES
The current version of IBM’s mainframe architecture is the zSeries 900, replacing the earlier S/390 line. Most mainframes today run on OS/390 or IBM’s new 64-bit z/OS, which was introduced in October 2000. Comfortable with mainframe scalability, security, availability, and manageability, companies continue to add significant processing power to S/390 systems and consider a migration to IBM’s zSeries, whose 64-bit addressing provides the necessary capacity for unpredictable workloads and growing enterprise applications. IBM’s eServer zSeries 900 was designed with flexibility in mind. The system’s intelligent Resource Director feature automatically reallocates I/O paths and other resources on the fly to varying application workloads as needed. This reallocation enables applications to expand and contract their resource use. Mainframes can communicate on TCP/IP networks, and modern tools make it a good platform for building Web-enabled applications. One significant factor in the reemergence of the mainframe has been UNIX compatibility as well as support for Internet technologies. For example, mainframes can host e-commerce servers and Web application servers. Also of note is increased support for Java and Linux, making mainframes more suitable as application development and integration platforms. (In May 2000, IBM announced mainframe support for Linux.) In 1994, IBM moved to CMOS (complementary metal-oxide semiconductor) technology in its mainframes. This technology means that mainframes use less energy, run cooler, take up less space, and cost less than the previously dominant emitter-coupled logic (ECL) technology. As of October 2000, the zSeries 900 had 250 uniprocessor MIPs, 2,500 total estimated MIPs, and 16 CPU engines. The 16-way model has 20 CPUs (four CPUs are reserved for handling I/O functions). The zSeries can be configured in numerous ways and can operate independently or as part of a Parallel Sysplex 32-way cluster of servers with as many as 640 processors.

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