ENGR 852

Fall 2013

San Francisco State University School of Engineering ENGR 852: Advanced Digital Design (3 units)

Course Objective: This course is designed to teach students advanced topics in digital design, from high level system description down to ASIC implementation. The course begins with a review of the digital design flow and fundamentals of digital design and then moves towards the system level design of digital systems. The design at the system level is done using Verilog hard-ware description language. The students will experience HDL description of digital systems, synthesis, and optimization to gatelevel. The main objectives of the course is   To prepare the student to be an entry-level industrial standard cell ASIC or FPGA designer. To give the student an understanding of issues and tools related to ASIC/FPGA design and implementation including timing, performance and power optimization, verification and manufacturing test.

Specific Learning Outcomes: Students completing the course successfully will       explain a modern digital design flow describe a digital system in Verilog HDL perform design optimization and synthesis to gate-level use model EDA (Electronic Design Automation) tools for simulation, verification, and synthesis of digital design perform post-synthesis design validation implement complex digital systems from high-level HDL description down to ASIC implementation

Prerequisites:    For undergrads, grade of C- or better in ENGR 356 or equivalent Basic knowledge of digital design, including combinational logic gates, sequential logic gates, timing design, finite state machine, etc. Familiarity with HDL preferred, but not required

ENGR 852 Fall 2013 Instructor: Xiaorong Zhang, Ph.D. Office: SCI 170A Office Hours: T,Th: 3:00-4:30 pm or by appointment E-mail: xrzhang@sfsu.edu Phone: (415)338-3946 Course Website: https://ilearn.sfsu.edu (All lecture slides, supplementary materials, and assignments are posted on iLearn.)
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ENGR 852 Reference Materials:

Fall 2013

Purchase is optional. Main 1. M.D. Ciletti, “Advanced Digital Design with the Verilog HDL (2nd Edition),” (Prentice Hall), 2010. ISBN 0136019285. 2. D.R. Smith and P.D. Franzon, "Verilog Styles for Synthesis," (Pearson Education [Prentice Hall]), 2000.ISBN. 0201618605. Additional 1. Thomas and Moorby, ``The Verilog Hardware Description Language'', 3rd edition, Kluwer Academic. ISBN 0-7923-9723-1. 2. S. Sutherland, S. Davidman, P. Flake, “System Verilog for Design” (Kluwer), 2004, ISBN 1-4020-7350-8. 3. H. Bhatnagar, “Advanced ASIC Chip Synthesis Using Synopsys Design Compiler, Physical Compiler, and PrimeTime”, ISBN 0-7923-7644-7. Class Schedule ENGR 852: Location: Topics:            Introduction to ASIC design Review of combinational and sequential logic design fundamentals Timing design Design of digital hardware using Verilog HDL Design of complex systems Hierarchy and Partitioning Finite State Machines Test benches and verification Low power design Design for test Introduction to FPGAs Monday 6:10pm-8:55pm TH 210

Tentative Weekly Schedule Week 1 2 3 4 5 6 Date 8/26 9/2 9/9 9/16 9/23 9/30 Topics Course overview; Introduction to ASIC Design No Class (Labor Day) Review of combinational sequential logic design; Timing Design; Design of digital hardware using Verilog HDL I Design of digital hardware using
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Due

and Homework 1

ENGR 852

Fall 2013

Verilog HDL II 7 8 9 10 11 12 13 14 15 16 17 17 10/7 10/14 10/21 10/28 11/4 11/11 11/18 11/25 12/2 12/9 12/16 12/21 TBD TBD TBD TBD TBD No class (Veteran's Day) TBD Fall semester break TBD TBD Oral project presentation Final Exam Midterm exam (first half of the class meeting) Preliminary project report

18 12/23 Final project report Note: This schedule is to be completed and subject to change based on the "reality" of the class performance. Information given in class supersedes this schedule. Important Dates Last day to add/drop: Sept. 9, 2013 Last day to withdraw: Nov. 22, 2013 (Please read the last page of the syllabus for more information) Grading Policy: Grades will be based on total points earned through the following activities: Homework Midterm Exam Project Final Exam Total Important Dates:      Preliminary project report due: Midterm exam: Oral project presentation: Final exam: Final project report due: Mon Nov 4th Mon Oct 28th (first half of the class meeting) Mon Dec 16th Sat Dec 21st, 6:10pm-8:55pm, TH 210 Mon Dec 23th 20% 15% 40% 25% 100%

Notes on grading:  Both the midterm and the final exams will be comprehensive, open-book, open-notes exams. You may NOT use computers, mobile phones, or PDAs during the exams. Generally, there will be no make-up exam and no incomplete grades given. If you miss
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ENGR 852

Fall 2013

an exam, you must notify the instructor before the exam or, if physically impossible, soon after. If you have an acceptable, documented excuse, you may be given a make-up exam. If you do not have an acceptable reason for missing the exam, you will receive zero points for the exam.  Though you can collaborate during homeworks, direct copying of solutions, in part or in whole, is not permitted. All code required for the homeworks should be individually designed and developed.  A fixed project will be published in the class. The project will be done by the students in pairs. You will be evaluated as a pair. Policies on Plagiarism Plagiarism is defined as using someone else’s ideas or work as one’s own without giving proper credit to the source. The source include public (books, journals, magazines, newspapers, internet, etc.) as well as private (unpublished reports, internal documents, personal work, etc.) materials. The instructor will not accept excuses such as “I forgot to give credit to …,” “It’s an oversight,” or “It’s a clerical error.” Students are solely responsible for materials submitted for the course so “My roommate must have done that without my knowledge” is not an acceptable excuse either. That is, no excuses will be accepted if plagiarism is discovered. If a submitted work is found to contain plagiarized material, the work will receive zero credit and the student may be reported to the Student Judiciary Affairs for disciplinary actions. Cheating on tests will also be reported to the Student Judiciary Affairs. Disciplinary actions may include disqualification from the university. Disability Policy Statement Students with disabilities who need reasonable accommodations are encouraged to contact the instructor. The Disability Programs and Resource Center (DPRC) is available to facilitate the reasonable accommodations process. The DPRC is located in the Student Service Building and can be reached by telephone (voice/TTY 415-338-2472) or by email (dprc@sfsu.edu). (http://www.sfsu.edu/~dprc/facultyfaq.html#1) Policy on observance of religious holidays If a student wishes to observe religious holidays and such observances require the student to be absent from class activities, it is the responsibility of the student to inform the instructor, in writing, about such holidays during the first two weeks of the class each semester. If such holidays occur during the first two weeks of the semester, the student must notify the instructor, in writing, at least three days before the date that he/she will be absent.

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