Advanced Source/Drain Technologies for Nanoscale CMOS by Pankaj Kalra

B. Tech. (Banaras Hindu University) 2003 A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering – Electrical Engineering and Computer Sciences in the GRADUATE DIVISION of the UNIVERSITY OF CALIFORNIA, BERKELEY

Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Chenming Hu Professor Eugene E. Haller

Fall 2008

The dissertation of Pankaj Kalra is approved:

Professor Tsu-Jae King Liu, Chair

Date

Professor Chenming Hu

Date

Professor Eugene E. Haller

Date

University of California, Berkeley

Fall 2008

Advanced Source/Drain Technologies for Nanoscale CMOS Copyright © 2008 by Pankaj Kalra

Abstract Advanced Source/Drain Technologies for Nanoscale CMOS by Pankaj Kalra Doctor of Philosophy in Engineering – Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair

Transistor scaling has been the driving force for technology advancements in the semiconductor industry over the last few decades. In order to mitigate short channel effects, the gate-oxide thickness and source/drain junction depth have been scaled along with the gate length. Recently, however, gate-oxide thickness scaling has slowed, as evidenced by the fact that an equivalent oxide thickness (EOT) of ~1 nm has been used for the past 2-3 generations of CMOS technology. Although significant progress has been made in the development of high-permittivity (high-κ) gate-dielectric materials and metal gate technology in recent years, it will be difficult to scale EOT well below 1 nm. This makes junction-depth scaling even more pressing for continued transistor scaling. Furthermore, as the dimensions of MOSFETs are scaled down, the contact resistance of silicide-to-source/drain regions increasingly limits transistor performance. This is because the on-state resistance of a MOSFET drops with transistor scaling, whereas contact resistance increases with contact area scaling. Contact resistance increases exponentially 1

with Schottky barrier height (SBH) of the silicide-to-semiconductor contact. Thus, lower values of SBH will be needed in order to achieve substantial performance improvements with transistor scaling in the future. In practice, fermi- level pinning makes it especially difficult to attain low values of SBH for metal (silicide) contact to n-type silicon. This dissertation addresses the aforementioned scaling challenges associated with the design of source/drain structures for sub-45 nm CMOS generations. Firstly, the progress made towards the formation of ultra-shallow junctions with the help of advanced annealing techniques, low-energy implants, and GCIB doping is presented. The experimental results obtained with flash annealing indicate that it is possible to achieve sub-15 nm junctions with lower sheet resistance (~1000 Ω/ ), adequate for 32 nm CMOS technology. Since high- κ/metal-gate stacks are already used in the most advanced 45 nm CMOS technology today, i is important to assess the compatibility of flash annealing t with high- κ/metal- gate stacks. The process integration of high-κ/metal-gate stacks with flash annealing is discussed next. It is shown that the flash annealing process has minimal effects on gate stack properties and is found to be compatible with the high- κ/metal- gate stacks. However, it results in degraded interface quality which is improved by using a post-metallization anneal. To reduce the effective SBH of silicide-to-semiconductor contact, various species (nitrogen, fluorine, sulfur and selenium) are studied. These species were implanted into the semiconductor, and then “piled up” at the silicide-semiconductor interface during the silicidation process. It is shown that significant SBH lowering (by as much as 0.37 eV) can be achieved on n-type silicon using nitrogen. The impact of this process on the

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properties of NiSi is assessed and the mechanism of SBH reduction is explained. Encouraging results are also obtained with sulfur and selenium, and a comparison of effective SBH reduction is made for all studied species. Finally, material properties of nickel germanide formed on epi Ge on Si substrate are studied to form low-resistance and thermally stable contact material for realizing highly-scaled high-performance technology based on Ge-channel MOSFETs.

_________________________________ Professor Tsu-Jae King Liu, Chair

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To my parents, for their love, support and encouragement

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Table of Contents

Chapter 1: Introduction ................................................................................................... 1 1.1. MOSFET Scaling Benefits...................................................................................... 1 1.2. Bulk Si MOSFET Scaling Challenges..................................................................... 3 1.3. Emerging CMOS Technology Roadmap ................................................................. 5 1.4. Challenges of Source/Drain Design for Nanoscale CMOS..................................... 8 1.5. Dissertation Objectives and Outline ...................................................................... 13 1.6. References .............................................................................................................. 14 Chapter 2: Formation of Ultra-Shallow Junctions (USJs).......................................... 20 2.1. Introduction............................................................................................................ 20 2.2. State-of-the-art Junction Technology..................................................................... 25 2.3. Alternate Doping and Annealing Techniques........................................................ 28 2.4. Junction Metrology ................................................................................................ 32 2.5. Experimental Results with Spike Anneal .............................................................. 36 2.6. Experimental Results with Laser Anneal............................................................... 40 2.7. Experimental Results with Flash Anneal............................................................... 42 2.8. Experimental Results with Infusion (GCIB) Doping............................................. 54 2.9. Summary................................................................................................................ 59 2.10. References............................................................................................................ 60

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Chapter 3: Process Integration of High-k /Metal-Gate with Flash Anneal................ 66 3.1. Introduction............................................................................................................ 66 3.2. Advanced Gate Stacks ........................................................................................... 68 3.3. Device Fabrication ................................................................................................. 71 3.4. Device Characterization......................................................................................... 72 3.4.1. SCE Control................................................................................................ 72 3.4.2. Gate Stack Integrity .................................................................................... 74 3.4.3. MOSFET Performance ............................................................................... 81 3.4.4. Effects of Post-Metallization Anneal.......................................................... 87 3.4.5. Challenges with Flash Anneal.................................................................... 89 3.5. Summary................................................................................................................ 91 3.6. References .............................................................................................................. 92 Chapter 4: Low Barrier Height Contact Technology................................................ 101 4.1. Introduction.......................................................................................................... 101 4.2. Approaches to Reduce Barrier Height................................................................. 107 4.2.1. Bandgap Engineering................................................................................ 108 4.2.2. Dual Silicide Technology ......................................................................... 110 4.2.3. Interface Passivation................................................................................. 110 4.2.4. Image- force Induced Barrier Lowering .................................................... 112 4.2.5. Workfunction Engineering........................................................................ 113 4.3. Experimental Details............................................................................................ 115 4.4. Results and Discussion........................................................................................ 117 4.4.1. Effects of Nitrogen Implantation .............................................................. 118

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4.4.2. Effects of Fluorine Implantation............................................................... 126 4.4.3. Effects of Selenium and Sulfur Implantation............................................ 128 4.5. Summary.............................................................................................................. 131 4.6. References ............................................................................................................ 132 Chapter 5: Contact Material for Ge MOSFETs ........................................................ 137 5.1. Introduction.......................................................................................................... 137 5.2. Heteroepitaxial Growth of Ge on Silicon ............................................................ 140 5.3. Metal Germanides ................................................................................................ 142 5.4. Experimental Details............................................................................................ 143 5.5. Physical Analysis ................................................................................................. 145 5.6. Wet Chemical Reaction ....................................................................................... 147 5.7. Summary.............................................................................................................. 149 5.8. References ............................................................................................................ 150 Chapter 6: Conclusions ................................................................................................ 154 6.1. Summary.............................................................................................................. 154 6.2. Contributions ........................................................................................................ 155 6.3. Recommendations for Future Research ............................................................... 159 6.4. References ............................................................................................................ 160

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Acknowledgements

I am very grateful to so many people for their help and support given to me along the entire course of my graduate study. Without their help, this thesis would not have been possible. First of all, I would like to express my sincere gratitude to my advisor Professor Tsu-Jae King Liu, for her inspiring guidance and constant encouragement through out this work. Her vast knowledge and strong technical expertise have helped me in getting an excellent background in the semiconductor device technology, identifying the opportunities in this field and preparing for the challenges. I am thankful for the rewarding learning experience that her mentorship has produced. I would like to thank Professor Chenming Hu and Professor Eugene Haller for serving on my dissertation committee. I would also like to thank Professor Nathan Cheung for being on my qualifying examination committee. Special thanks go to Dr. Hsing-Huang Tseng and Dr. Prashant Majhi at SEMATECH, Austin for providing me the opportunity to be part of their team and to gain valuable industrial experience. In particular, I would like to thank Prashant for being an excellent mentor during my internship, and for his support and friendship. I would also like to thank Dr. Raj Jammy, Dr. Muhammad Mustafa Hussain, Dr. Rusty Harris, Nikhil Vora, Dr. P. Y. Hung, Dr. Dawei Heh, Dr. Gennadi Bersuker, Dr. Chadwin Young, Dr. Jungwoo Oh, Dr. Huang-Chun Wen, Joel Barnett and Barry Sassman. Additionally, I benefited greatly from the fruitful research collaborations with Dr. Michael Current (Frontier Semiconductor) for non-contact sheet resistance measurements, Steve McCoy (Mattson Technology) for flash annealing, Dr. John Hautala (Epion-TEL) v

for GCIB doping and Professor Hyunsang Hwang (GIST, Korea) for post- metallization anneal. Their contributions became the essential part of various research projects. I would like to express my warmest appreciation for Hideki Takeuchi who generously helped me with various fabrication tools in Microlab. His invaluable experience and critical feedback helped me to gain better insight into the nuances of the nanoscale device fabrication. I would also like to acknowledge the following current or former members of device group that have helped me to get through the initial learning curve as a new graduate student and microlab user: Sriram Balasubramanian, Joanna Lai, Vidya Vardarajan, Mohan Dunga, Hiu Yung Wong, Carrie Low and Daewon Ha. I must thank the visiting fellows to the Device Group, Akira Hokazono, Takuro Matsutoya, Yuri Yasuda, Koichi Fukuda, Taro Osabe, Si-Woo Lee and Woo Young Choi for sharing their experience s. The administrative and technical staffs at Microlab and ATDF, Austin deserve sincere thanks for their hard work to keep the fabrication facilities functional. I would also like to thank the wonderful EE Graduate Student Affairs staff, Ruth Gjerde and Mary Byrnes for giving countless hours of service to the graduate students. Thanks to Linda Manly, Charlotte Jones, Misty Kiuchi and Sim Kallan for being very helpful with monetary matters. Much needed financial support by MARCO Materials, Structures and Devices (MSD) Center, UC Discovery Grant, Intel, Infineon, Applied Materials Fellowship and SEMATECH is gratefully acknowledged. My heartfelt thanks to my friends Akira, Alvaro, Anshul, Arka, Bala, Blake, Chung-Hsun, Darsen, Donovan, Drew, Dunga, Gaurav, Gautam, Huang-Chun, Joanna, Kaushik , Kinyip , Koichi, Krish, Marie, Nikhil, Noel, Rahul, Sriram, Steve, Takuro, Taro,

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Vidya, Vishnu, Woo Young, Yung, Yuri and many others for their friendship and support. Mere words are not enough to express the gratitude I feel for my family. I cherish our times together.

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Chapter 1

Introduction

1.1 MOSFET Scaling Benefits
First stated in 1965, Moore’s law describes the unparalleled technology advancement over the past 40 years which has allowed the number of transistors on a chip to double about every two years [1]. This pheno menal progress has been made possible by continual downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) to smaller physical dimensions. MOSFETs have the remarkable feature that as they become smaller they also become cheaper, consume less power, become faster, and enable more functions per unit area of silicon. As a result, denser silicon integrated circuits (ICs) can be realized, offering superior performance at reduced cost per function as shown in Figure 1.1 and 1.2.

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Figure 1.1. Number of transistors on a chip, as a function of the first year of production [2].

Figure 1.2. The increase in chip performance, measured in millions of instructions per second (MIPS), as a consequence of scaling [2].

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1.2 Bulk Si-MOSFET Scaling Challenges
Figure 1.3 shows the schematic of the conventional planar bulk Si-MOSFET, the basic building block of an integrated circuit. As the gate length (Lg ) of a MOSFET decreases, the capacitive coupling of the channel potential to the source and the drain terminals increases with respect to the capacitive coupling to the gate terminal, resulting in short channel effects (SCE), such as threshold voltage (V TH) roll-off? smaller VTH at shorter Lg , and drain- induced barrier lowering (DIBL)? smaller V TH at higher drain voltage (V DS ) due to reduction of the source-channel potential barrier by the drain voltage. V TH roll-off and DIBL manifest into increased off-state transistor leakage (Ioff). Ioff is becoming a severe concern for high-performance logic technologies that may hinder CMOS scaling because of significant passive power consumption as shown in Figure 1.4 [2, 3].

Lg Tox

Gate Source
Xj

Drain

Substrate
Figure 1.3. Schematic diagram of the bulk Si MOSFET.

Therefore, careful device design is required so that SCE do not prevent the use of a minimum Lg MOSFET. For bulk MOSFETs, a minimum Lg must be ~5l, where l is the characteristic length and is given by [4]: 3

2 l = 0.1 X j Tox Tdep

(

)

(1.1)

where X j is the source/drain extension junction depth, Tox is the gate dielectric (SiO 2) thickness and Tdep is the channel depletion depth. According to Eq. (1.1), vertical dimensions ( ox , Xj, Tdep) must be scaled together with Lg to suppress SCE in bulk T MOSFETs.

Figure 1.4. The trend in active and leakage power of microprocessors as a consequence of scaling [2]. The leakage power is approaching ~50% of the total power in a modernday microprocessor. This scaling methodology has worked very well for several decades, but as silicon CMOS technology advances into the nanometer regime, fundamental and practical limits impede the traditional scaling of transistors as discussed next. Historically, the gate dielectric thickness has been the single most important dimension to enable device scaling. Scaling down of the gate dielectric not only increases capacitive coupling of the gate to the channel but also leads to increased on-state transistor drive current (Ion ).

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However, the thickness of SiO 2 -based gate dielectrics is approaching physical limits (2008, Rseries is expected to be ~20% of the total Ron , a significant fraction, yet no known solutions are

Source

Gate

Drain

R

R ch

R

Rseries = 2 R Ron = Rch + Rseries

Figure 1.8. Schematic representation of the channel resistance (Rch ) and the parasitic S/D series resistance (R series). The total on-resistance (Ron ) of the MOSFET is the summation of Rch and Rseries.

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available to meet or limit these projections. Therefore, Rseries reduction presents one of the biggest challenges for continued aggressive CMOS scaling.

Figure 1.9. Historic scaling trends for Ron and Rseries (or Rext) of high-performance nMOSFETs [26].
1200 ITRS 2005 1000 25

Physical Gate Length (nm)

Resistance (Ω-µm)

Lgate 800 600 400 200 0 2007 2008 Rseries 2009 2010 2011 2012 RON

20

15

10 solutions exist solutions NOT known

5

0

Year of Production
Figure 1.10. Scaling projections of Ron and Rseries for high-performance bulk nMOSFETs [27]. Ron is calculated using the projected values of drive current and power supply so that the 17% per year device performance improvement targets are met for a given technology year. The red region indicates that the solutions to achieve these projections are not known.

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As shown in Figure 1.11, Rseries can be divided into the four components : (i) extension-to-gate overlap resistance (Rov ); (ii) S/D extension resistance (Rext); (iii) deep S/D resistance (RS/D); and (iv) contact resistance at the silicide-silicon interface (Rco ). A simple first order estimation of these components is presented next to understand their dependence on device and process parameters. The overlap resistance (Rov) is a strong function of doping concentration in the overlap region and the lateral abruptness of the overlap doping profile. These two factors govern the accumulation carrier density and the current spreading. Increased lateral abruptness is needed for improved SCE, reduced spreading resistance and reduced accumulation resistance.

Rov = f ( Abruptness , N ext , Rch )

(1.2)

where N ext is the peak dopant concentration in the extension region and Rch is the channel resistance.

Lext Rch Rov Rext

LS/D

Lcont tSi Silicide

`

RS/D Xj Rco S/D extension Xj,S/D Deep S/D

Figure 1.11. Schematic representation of various components of S/D series resistance.

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Assuming an ideal box- like profile, the S/D extension resistance (Rext) can be written as:

Rext =

ρ ext Lext WXj

(1.3)

where ρ ext is the resistivity of the extension region, Lext is the extension length, W is the channel width and X j is its junction depth. Similarly, the deep S/D resistance (RS/D) equals:

RS / D =

ρ S / D LS / D W (X j ,S / D − t Si )

(1.4)

where ρ S/D is the resistivity of the deep S/D region, LS/D is the lateral diffused length of deep junction, X j,S/D is its junction depth and tSi is the thickness of silicon consumed during silicidation. The summation of Rext and RS/D is commonly referred as the spreading resistance under the sidewall spacer (R spr). The contact resistance (Rco) is defined as the resistance between the silicide and the Si underneath the silicide and is expressed as:

Rco =

ρc W Lcont

(1.5)

where ρ c is the specific contact resistivity of the silicide-silicon interface and is determined by the active dopant concentration and Schottky barrier height at the interface. Lcont is the length of the silicide region. Rco has another sub-component due to an additional current path at the sidewall of recessed contact region, which is a strong function of the silicon recess (t Si). For successful optimization of the source/drain design for lower Rseries, it is important to first understand the relative contribution of its components. Figure 1.12 shows the results of an advanced series resistance model for sub-100 nm bulk-Si

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technologies [28, 29 ]. The series resistance trend versus technology scaling predicts that Rspr and Rco are the dominant components and account for >85% of the total series resistance for all technologies studied. Furthermore, the contribution of Rco increases as the technology scales. This is not unexpected because of the requirement of shallower junctions for SCE control and the scaling of Lcont, which shrinks by a factor of ~0.7× every node. Shallow junction depth and smaller Lcont degrades Rext and Rco , respectively. A similar trend is seen for 90 nm SOI technology [30]. The extracted series resistance breakdown indicates that the contribution of Rspr and Rco is ~95% as seen in Figure 1.13. It has been reported that the contact resistance between the silicide and Si- fin will be a serious challenge to MuGFET structures as well [31, 32]. To summarize, the source/drain design for future nanoscale CMOS devices requires reduced Rext and Rco. However, ultra-shallow junctions are a key requirement to suppress short channel effects, but this leads to higher Rext. Therefore, very high active
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Relative Contribution (%)

60 50 40 30 20 10 0

NMOS

Rco

Rspr

Rov
32 nm 53 nm 70 nm 100 nm

Technology
Figure 1.12. The relative contribution of the various components of the series resistance for different technology nodes. The device parameters for each technology are scaled down according to ITRS (Source: Prof. Jason Woo, UCLA).

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Figure 1.13. The extracted series resistance and the contributions of its components for 90 nm SOI CMOS technology [30].

dopant concentration levels and abruptness are required for these junc tions. To limit the impact of Rco, lower ρ c is desirable. Since ρ c decreases exponentially with decreasing Schottky barrier height (SBH) of the silicide-Si contact, a lower SBH will be needed.

1.5 Dissertation Objectives and Outline
In this dissertation, some of the aforementioned source/drain engineering issues are addressed, with the aim of minimizing the impact of parasitic series resistance on device performance. The process solutions presented here are applicable not only to the bulk-Si MOSFET but also to advanced transistor structures. A systematic study to meet the stringent junction requirements for future CMOS generations using conventional and/or advanced processing methods is presented in Chapter 2. In Chapter 3, the compatibility of millisecond flash annealing with advanced gate stacks in a “gate- first” CMOS process flow is addressed. The evaluation of the flash 13

annealed devices is presented to understand the impact of flash annealing on highκ/metal- gate device performance and reliability. Chapter 4 focuses on reducing the Schottky barrier height of a silicide to n-type Si contact by introducing impurities into the silicon via ion implantation. These impurities are then piled up at the silicide-semiconductor interface during silicidation. Various impurity species are studied using this process, and comprehensive electrical and physical analyses are performed on the bulk silicide and silicide-Si interface. Chapter 5 presents a brief introduction to epi-Ge MOSFETs. To fully exploit the superior carrier transport properties of Ge, low-resistance, thermally-stable, and selfaligned contact material with low formation temperature is needed. Nickel germanide is investigated as the choice of germanide for source/drain contact in epi- Ge MOSFETs. Chapter 6 summarizes the key contributions of this research and provides suggestions for future research directions.

1.6 References
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(http://www.public.itrs.net/).

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[28] S. -D. Kim, C. -M. Park, and J. C. S. Woo, "Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime—Part I: Theoretical Derivation", IEEE Transactions on Electron Devices, vol. 49, no. 3, pp. 457-466, 2002. [29] S. -D. Kim, C. -M. Park, and J. C. S. Woo, "Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime—Part II: Quantitative Analysis", IEEE Transactions on Electron Devices, vol. 49, no. 3, pp. 467-472, 2002. [30] S. D. Kim, S. Narasimha, and K. Rim, "An Integrated Methodology for Accurate Extraction of S/D Series Resistance Components in Nanoscale MOSFETs," IEEE IEDM Tech. Digest, pp. 149-152, 2005. [31] H. Kam, L. Chang and T. -J. King, "Impact of Source-Drain Doping Profiles and Contact Schemes on FinFET Performance in the Nanoscale Regime," IEEE Silicon Nanoelectronics Workshop Proc., pp. 9-10, 2004. [32] A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. De Meyer, " Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs", IEEE Transactions on Electron Devices, vol. 52, no. 6, pp. 1132-1140, 2005.

19

Chapter 2

Formation of Ultra-Shallow Junctions (USJs)

2.1 Introduction
Current trends of complementary metal oxide semiconductor (CMOS) technology scaling are diversified in many ways to meet the historical pace of intrinsic transistor performance improvement by about 17% per year. At each node there always existed severe skepticism of the ability to realize future generations by simply scaling the geometry of the devices. However, the technologists almost always managed to scale the devices with minimal change to the conventional CMOS process flow. The biggest scaling challenge is to keep the short-channel effects (SCE) under control which manifests into degraded device performance. SCE is the decrease of MOSFET threshold voltage (V TH) as physical gate length (Lg) is reduced. Figure 2.1 highlights the short-channel VTH roll-off against Lg . The decrease in V TH with decreasing 20

Lg can be explained by significant capacitive coupling of other MOSFET terminals (source and drain) with respect to control terminal (gate) in short-channel devices. SCEs are more pronounced when high voltage bias is applied to the drain terminal of MOSFET. High drain bias reduces the potential barrier at the source end of the channel for carriers to flow into the channel, resulting in further reduction of V TH. This effect is also known as drain- induced barrier lowering (DIBL). Figure 2.2 shows the measured IdV g characteristics of long-channel (Lg = 1.0µm) and short-channel (Lg = 0.175µm) devices at different drain biases. For a long-channel device, subthreshold current is independent of drain bias. However, for a short-channel device, V TH is reduced for high drain bias condition, resulting in higher off-state leakage.
0.70

Threshold Voltage, VTH (V)

0.65

0.60

0.55

0.2

0.4

0.6

0.8

1.0

Physical gate length, Lg (µ m)
Figure 2.1 Linear VTH roll-off characteristics for nMOSFETs with varying physical gate length. V TH was extracted by peak G m method using Id-V g measured at V d = 50mV (details of MOSFET fabrication are discussed in section 3.4). EOT=1.15 nm. When V TH drops too much, off-state leakage becomes too large for that channel length, which is unacceptable. Thus, careful device design is needed so that VTH roll-off and DIBL do not prevent the use of minimum physical gate length MOSFET. Using

21

1x10

-2

Vd= VDD Vd= 50mV
ΔV
T

Drain Current, I d (A)

1x10 1x10 1x10 1x10 1x10 1x10 1x10 1x10

-3

-4

-5

-6

Lg = 0.175 µm Lg = 1.0 µm

-7

-8

-9

-10

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Gate Voltage, Vg (V)
Figure 2.2 Subthreshold characteristics of a long-channel (Lg = 1.0µm) and short-channel (Lg = 0.175µm) nMOSFET. Id -V g was measured at V d = 50mV and Vd = 1.2 V. DIBL for short-channel MOSFET is 100mV/V whereas DIBL for long-channel MOSFET is very small (10mV/V). EOT=1.15 nm. Voltage-Doping Transformation, the shrinkage in MOSFET geometry can be correlated to VTH roll-off and DIBL according to following equation [1] ?
2 ε Si  X j  Tox Tdep 1+  V bi ε ox  L2  Lel Lel  el  2 ε Si  X j 1+ ε ox  L2  el

SCE =

(2.1)

DIBL =

 Tox Tdep  V  Lel Lel d 

where Lel is the electrical channel length, X j is the source/drain extension depth, Tox is the gate dielectric thickness, Tdep is the depletion depth, ε Si is the dielectric constant of silicon, εox is the dielectric constant of gate dielectric, V bi is the built- in potential, and Vd is the drain bias. Figure 2.3 shows the schematic cross-sectional of a MOSFET with abovementioned device dimensions.

22

Tox Wdep Xj

Figure 2.3 Cross-section of a MOSFET. Eqn. (2.1) indicates that to avoid excessive SCE, vertical dimensions (Tox , Tdep , X j) must be reduced to support the gate length shrink. Reducing Tox increases gate-to-channel capacitive coupling. Historically in bulk Si MOSFETs, thinning down the gate dielectric has been the key enabler to minimize SCE (and to improve drive current), as Tox has been scaled by ~0.75× in each technology generation every three years as shown in Figure 2.4 [2]. However, recently the thickness of gate oxide has scaled more slowly than the historical pace and an equivalent oxide thickness (EOT) of ~1nm has been used for the past 2-3 generations, signaling the advent of new era where further scaling must be realized mainly by new materials. Nearly a decade of research and development has been conducted, by various groups, on high-permittivity (high- κ) gate dielectrics to potentially replace the conventional gate dielectric, SiO x N y , for future generations of CMOS. There has been excellent progress in recent years in demonstrating high-performance devices with hafnium-based high-κ dielectric and metal gate electrode [3]. Introduction of metal gates mitigates problems associated with conventional poly-silicon gate electrodes. While the introduction of high- κ/metal gates have extended effective gate oxide thickness scaling for better gate control, it will be difficult to scale EOT well below 1 nm. 23

Figure 2.4 Published and projected scaling trend of equivalent gate oxide thickness (EOT) [2].

Reducing Tdep helps to eliminate leakage paths far from the dielectric-channel interface. Tdep can be reduced by increasing channel doping concentration but it also results in decrease carrier mobility due to enhanced impurity scattering degrading onstate performance. For current and near- future technology nodes, channel doping is ~46×1018 cm-3 , which is already too high [4]. Tox and Tdep are clearly reaching fundamental physical limitations, which necessitates more aggressive junction depth scaling in order to control short channel effects. Figure 2.5 shows the X j requirements for a given gate length for past and future technology generations to keep pace with historical improvement in high per formance logic devices [4, 5]. In the 2005 edition, the International Technology Roadmap for Semiconductors (ITRS) model for X j was ~0.36×Lg . However, introduction of high-

24

κ/metal gate and offset spacers has relaxed this requirement and ITRS 2007 edition modifies it to be ~0.50×Lg . Nevertheless, future CMOS generations 32nm and beyond will have source/drain extensions few nm deep (~10nm), yet will require sheet resistance of the order of ~1000Ω/ . The aforementioned junction requirements may appear to be too aggressive for realistic implementation in nanoscale devices, yet they stress upon the need to form ultrashallow junctions (USJs) to keep short channel effects and total parasitic resistance of the device within acceptable degree of tolerance. The goal of this study is to systematically investigate the possibility of achieving shallower junctions with lower sheet resistance by conventional and/or advanced processing methods.

Physical Lg, S/D Extension Xj (nm)

100 Lg Xj =0.33 Lg (ITRS 05) Xj =0.50 Lg (ITRS 07)

10

1 2004

2006

2008

2010

2012

Year
Figure 2.5 Scaling trend of physical gate length and source/drain extension as reported in ITRS.

2.2 State-of-the-art Junction Technology
In recent years, the formation of shallow junctions has seen a rise in advanced processes, at the cost of added process complexity, that accompany the conventional 25

method of dopant incorporation (by ion implantation) and dopant activation with implant damage annihilation (by rapid-thermal processing). Particularly, requirements for p+/n shallow junctions are difficult to meet as compared to n+/p junctions because of an extended tail of the boron (p-type impurity) profile due to ion channeling. Preamorphization implants (PAIs) such as germanium or silicon are primarily used to minimize ion channeling. If silicon is amorphized during implantation, extended defects are formed upon annealing. These defects a commonly known as end-of-range (EOR) re defects and are located just below the interface between the amorphized and crystalline substrate. EOR defects are typically {311} rod- like defects or dislocation loops, formed by excess silicon interstitials (Sii). If the EOR damage layer lies within the depletion width, junction leakage is increased. Hence, the amorphized silicon depth should be carefully controlled to avoid the presence of EOR damage within the depletion width (which depends upon source/drain extension and halo doping). Since boron diffuses in silicon by interstitial mechanism, excess Sii concentration leads to an enhanced diffusion of boron commonly known as transient enhanced diffusion (TED) [6]. While the dopant profile may be shallow after implantation, upon annealing the profile can diffuse several nanometers into the bulk substrate resulting in undesired deep junctions. Hence, the control of junction depth for a given technology node is limited by TED. It has been demonstrated that co- implantation of carbon and fluorine can be a very effective method to reduce TED of boron atoms [7, 8]. These co-implanted species form complexes with Sii, which reduces [Sii] to near-equilibrium values, reducing B-Sii interaction for diffusion Best results are obtained when projected range (Rp ) of co. implanted species is close to the amorphous (a-Si) /crystalline (c-Si) interface generated by

26

pre-amorphization as shown in Figure 2.6, preventing the arrival of Sii in the boron-doped region. This results in a twofold advantage – shallower junctions due to lesser boron TED and stabilization against deactivation caused by interstitial-driven boron clustering [9, 10]. Thus, there is a strong interdependence between the depth of amorphized silicon region and co- implanted species profile. Therefore both – PAI which determines the depth of amorphized silicon and co-implanted species’ implanted profile need careful investigation to achieve optimum junction depth. In addition to carbon and fluorine, there are also reports of the use of nitrogen as a co- implant species to control boron TED [11, 12]. ln [C] Implanted Boron co-implanted species profile a-Si/c-Si interface

EOR damage

Depth Figure 2.6 To mitigate boron TED, co- implanted species energy is chosen in a way so that the projected range of co- implantation lies in-between the implanted boron profile and a-Si/c-Si interface. EOR damage layer is located beneath this interface. To further reduce the impact of TED, it is necessary to anneal at the highest temperature possible while limiting the total thermal budget for dopant diffusion. Consequently, spike annealing with soak time less than 1 second has been developed. Fast-ramp spike annealing along with low-energy dopant implants with co- implantation (for boron) is currently in practice to satisfy the shallow junction requirements for nodes down to 65 and 45 nm.

27

2.3 Alternate Doping and Annealing Techniques
The demand for low-energy implantation will be increasingly difficult to meet for 32 nm nodes and below because throughput is limited by low beam current from the ion source to wafers. To address the issue of decreased productivity at low energies, decel mode is used. The ions are extracted at higher energies to draw high beam current and then decelerated before they reach the wafer targets. However, some of the dopant ions are neutralized by charge exchange with the background gas prior to deceleration. These neutrals will not be decelerated and therefore reach the wafer at higher than desired energies. This effect is known as energy contamination and leads to a deeper than desired dopant depth profile. In decel mode operation, beam spreading becomes a problem because of increased coulomb repulsion due to decreased ion velocities for low energy implants. These two effects are shown in Figure 2.7 [13].

B+ + (gas)0

B0 + (gas)+
Neutrals are not decelerated

Ions are neutralized by interaction with background gas

Energy contamination

Ion Beam

V

Deceleration causes beam spread

Figure 2.7 Mechanism of energy contamination in decel mode ion implanter. Energy contamination causes implanted profile to be deeper than desired.

28

Various doping techniques such as Plasma doping, Infusion doping, and Molecular implants have been proposed to counter the limitations of beam line implantation. In the PLAsma Doping (PLAD) technique, the wafer is placed in a vacuum chamber filled with process gas (BF 3 , AsH3, PH3). Application of negative voltage to the wafer ionizes the gas and attracts these ions toward the wafer, resulting in ion implantation. In PLAD, all ionized species present in the plasma will be implanted into the wafer, causing the risk of contamination and etching. To minimize these effects, a series of voltage pulses is applied to the wafer such that plasma is present only during the implant time. This modified process is called Pulsed PLAsma Doping (P2 LAD) [14]. Within-wafer and wafer-to-wafer uniformity are important issues for PLAD because implanted ions have a range of energies rather than a specific energy [15]. Infusion doping utilizes gas cluster ion beam (GCIB) for shallow doping applications [16, 17]. GCIB processing uses clusters (>5000 atoms) consisting of Ar or He and B containing molecules such as B H6 and BF 3 . After adiabatic expansion that 2 causes cluster formation, clusters are ionized and accelerated to the substrate. Upon impact, the cluster energy is transferred to the substrate surface causing rapi heating and d dissociation of molecules into its atoms. The gas atoms (Ar, He, H) leave the surface and soluble species intermix or are infused in the substrate. Although the clusters have higher total energy, the energy/atom is very low (~10eV) and hence intermixing occurs in very shallow depths. Infusion doping is mass independent because the intermixing depth i s determined by the collective energy of the cluster. Extreme abruptness and lack of channeling or energy contamination are the main features of infusion doping.

29

The aforementioned doping techniques are promising for shallow junction applications but require in-depth research on various aspects of device performance before they can be implemented in production. Furthermore, they have to be costeffective and should obtain same or better process control as achieved by conventional method of doping – beam- line implantation. Thus alternative methods are being explored to extend conventional beam- line implantation to several more generations. Molecular implants such as B10 H14 and B18 H22 are well suited for direct replacement of monoatomic ion species for low-energy implantation providing improved throughput while retaining the precision of ion dose, repeatability, uniformity and angle control of ion implantation [18, 19]. Rapid thermal processing is also facing contrasting challenges of dopant movement during annealing and limited electrical activation because of solid solubility limits. A higher anneal temperature is desirable but with current RTA tools, the annealing time at these elevated temperatures are too long to cause significant dopant diffusion, resulting in deeper junctions. Figure 2.8 indicates that in order to limit diffusion to 1250o C. A spike anneal with a very high ramp rate has been used to meet 45 nm CMOS technology requirements for shallow junctions. But in order to meet the requirements for sub-45 nm technologies, spike annealing will not be adequate; especially, boron TED will still pose great challenges for ultra-shallow junction formation. Flash annealing and laser annealing are two prime candidates for possible replacement of spike annealing and are often regarded as “diffusion-less” annealing techniques. Flash annealing uses an array of flash lamps ignited by high voltage pulses to achieve annealing times in the range of

30

milli-seconds [20, 21 ]. Laser annealing is a metastable process lasting few microseconds to nanosceconds in which dopants can be frozen in the lattice sites well above the solid solubility limit [22], but equipment maturity is the main challenge for its adoption. Both annealing techniques are capable of heating a silicon substrate to very high temperature. Figure 2.9 exhibits the differences in annealing temperature and time for conventional anneals (furnace, RTP, spike) and advanced anneals (flash and laser). With advanced annealing techniques, it is possible to achieve higher temperature (>1200o C) for increased dopant activation while keeping the anneal time short for restricted dopant diffusion. Another primary dif ference is that advanced annealing techniques heat up only the device side of the wafer, unlike conventional annealing techniques for in which the bulk of the wafer is subjected to thermal treatment.
10
6

10

4

Time (s)

10

0

10

-2

10

-4

600

ms anneal

RTP

10

2

Diffusion Length = 20 nm 10 nm 5 nm 2 nm 1 nm

Furnace
800

1000 o 1200

1400

Temperature ( C)
Figure 2.8 Thermal budget criteria for different B diffusion lengths ( √Dt). High2 temperature milli-second anneals can provide for higher dopant activation without significant diffusion. Solid phase epitaxial regrowth is another potential candidate to achieve shallow junctions. The main advantage is above-equilibrium dopant activation, good control over

31

junction depth and lower temperature requirement (~650o C) [23]. The main drawback is relative high density of residual defects after annealing which leads to very high junction leakage.

Surface Heating
1400

Bulk Heating

Anneal Temperature ( C)

o

1200

Laser
1000 800

Spike

Flash
600

RTP

Furnace

More Activation
400

Less Diffusion
200 -7 10 1x10
-5

10

-3

10

-1

10

1

10

3

10

5

Anneal Time (s)
Figure 2 Temperature-time ranges of various conventional and advanced annealing .9 techniques.

2.4 Junction Metrology
In this work, Secondary Ion Mass Spectroscopy (SIMS) was used to measure the junction depth (X j). The analyses were performed on the Physical Electronics ADEPT 1010. B was monitored as a positive ion under 500-650eV O2 + bombardment incident at 45°. The analysis chamber was backfilled with a high partial pressure of O 2 to reduce ion intensity fluctuations at the beginning of the profile. As was monitored as the molecular secondary ion As+Si under 500eV Cs+ bombardment at 60°. Secondary ions were 32

collected from the center 10% of a 400 µm x 400 µm rastered area. 1-cm2 pieces were taken from the center of each wafer. Stylus profilometry was used to determine the depth of the craters and calibrate the depth scale. B and As concentrations were calculated using relative sensitivity factors (RSFs) determined from standard samples. Accurate sheet resistance (Rs ) measurement is critical for assessing USJ formation processes. The conventional method, four-point probe (FPP), is used to measure sheet resistance. However, a mechanical load is used to push the probes against the sample, which causes probe penetration and leaves a footprint behind because of silicon fracture. This probe-tip penetration can be deeper than Xj for USJs as shown in Figure 2.10(a). Figures 2.10 (b) & (c) are atomic force microscopy (AFM) topographic images of samples probed using two FPP tools [24]. It is clear that both tools penetrate significantly into the silicon surface; the largest penetration depth is 30-130 nm.

Xj~30 nm Substrate (a) (b) (c)

Figure 2.10 (a) Probe-tip penetration for junctions shallower than 30nm in FPP method (Source: Dr. M. Current). (b), (c) AFM images of the probe imprints of FPP SSM 240 (image size 5 µm) and FPP Veeco 5000 (image size 50 µm), respectively. The z ranges are 100 and 500 nm [24]. Sheet resistance was also measured by a non-contact method for improved accuracy. The measurement is based on the monitoring of junction photo- voltage at a transparent electrode at the center of the probe (V in ) and second electrode (V out) some

33

small distance away as shown in Figure 2.11 [25, 26]. Free carriers are created in the depletion region by illuminated light. These carriers, then, get separated at the junction boundary. The charge in the surface junction induces a charge at the central electrode. This is the junction photo -voltage ( JPV) signal. Carriers created in the junction spread out from the illuminated area and a JPV signal is detected by the outer electrode. The ratio and phase of the JPV signals, V in /Vout is used to determine Rs.

Vin

Modulated LED Beam

Vout

---Carrier spreading Carrier recombination in depletion layer

++++ ----

p+

n

Figure 2 .11 Non-contact method of measuring sheet resistance and leakage of a p/n junction [25].

The n on-contact method can also be used to measure junction leakage. Carriers which drift into the depletion layer can recombine at defect sites. This recombination reduces the charge in the surface junction and JPV signal. Analysis of the JPV signal at different modulation frequencies allows for determination of junction recombination current density.

34

Variability for Rs measurements using the non-contact method is 0.05% as shown in Figure 2.12 (a) [27]. The other advantage of the non-contact method is that whole wafer mapping can be done ve ry quickly (~1,000 pt in 25nm. Thus, spike annealing results in junctions that are too deep for sub-45nm nodes.
10
22

PAI Ge + BF2 (0.5 keV)
21

[B] (atoms/cm )

3

10

as implanted spike annealed

10

20

1019
18

10

10

17

0

10

20

30

40

Depth (nm)
Figure 2.16 B SIMS profiles of as-implanted and spike-annealed for BF2 implant (0.5keV, 5×1014 cm-2 ). Significant dopant diffusion is seen for the spike anneal. Junction depth is taken at [B] = 5×1018 cm-3.
10
22

Arsenic (0.5keV)
21

[As] (atoms/cm )

10

as implanted spike annealed

3

10

20

10

19

10

18

10

17

0

10

20

30

40

Depth (nm)
Figure 2.17 As SIMS profiles of as- implanted and spike-annealed As implant (0.5keV, 1015cm-2 ). Spike annealing results in much deeper junctions (X j>25nm). 38

Co-implanted species interact with excess Si interstitials generated during implantation and thus mitigate boron TED. Figures 2.18 & Figure 2.19 highlight the impact of F and N co-implantation, respectively, for different implanted boron energies.
PAI Ge + BF2 (0.5keV) Spike annealed

[B] (atoms/cm )

10

20

3

10

19

10

18

w/o F I.I. w/ F I.I. 10
17

0

10

20

30

40

50

Depth (nm)
Figure 2.18 SIMS profiles of spike annealed BF 2 implant (0.8keV, 5×1014 cm-2 ) without and with F co-implantation.
PAI Ge + B (0.2keV) Spike annealed

[B] (atoms/cm )

3

10

20

10

19

1018

w/o N I.I. w/ N I.I.

10

17

0

10

20

30

40

50

Depth (nm)
Figure 2.19 N co-implantation helps to reduce Xj, as seen in the SIMS profiles of spike annealed B (0.2keV, 5×1014 cm-2 ).

39

The total change observed in junction depth ( X j) is 3-10nm for all studied coΔ implantation conditions. Therefore, co-implantation helps to reduce Xj, but this reduction is not enough to meet ITRS specifications for highly scaled CMOS technologies.

Sheet Resistance, Rs (kΩ/sq.)

5 spike annealed 4

3

2

1

0

0

10

20

30

40

Junction Depth, X j @5E18 cm (nm)
Figure 2.20 Sheet resistance (Rs ) determined by non-contact method vs. junction depth (X j) for p+/n junctions formed by spike a nnealing (1070 o C). Figure 2.20 summarizes the experimental results obtained with spike annealing with and without co- implantation for p+/n junctions. These results indicate that it may be possible to achieve junction depths of ~20nm, but it comes at the expense of higher sheet resistance. Furthermore, it will be increasingly difficult to meet ultra-shallow junction requirements below 20nm with spike annealing while maintaining low sheet resistance.

-3

50

2.6 Experimental Results with Laser Anneal
The substrate used in this study was n-type (100) silicon. The samples were first pre-amorphized using Ge implantation, which resulted in 36 nm of a-Si. Subsequently, BF 2 implant was carried out at 0.5 keV with a dose of 5×1014 cm-2 and angle of 7o . A pulsed XeCl excimer laser anneal (ELA) with λ=308nm was used to activate dopants. 40

The ELA pulse was of very short duration, approximately 30ns. Three different l ser a fluences were chosen in this experiment: 450 mJ/cm2 , 500mJ/cm2 , and 550mJ /cm2 . SIMS results obtained are summarized in Figure 2.21.
10
21

[B] (atoms/cm )

10

3

20

PAI Ge + BF2 (0.5keV) as-implanted 2 fluence = 450mJ/cm 2 fluence = 500mJ/cm 2 fluence = 550mJ/cm Laser annealed

10

19

10

18

10

17

0

10

20

30

40

50

Depth (nm)
Figure 2.21 SIMS profiles of BF2 (0.5keV, 5×1014 cm-2 ) implant before and after laser anneal. Laser fluence of 450 mJ/cm2 , 500mJ/cm2 , or 550mJ/cm2 was used to activate dopants. ELA has near- zero thermal budget, but as shown in Figure 2.21, it results in deeper junctions (Xj > 20nm), and shows no significant benefit over spike annealing for this particular experiment. This anomaly can be attributed to the chosen laser fluence and depth of pre-amorphization, as discussed next. The laser fluence needed to melt any material is defined as the melt-threshold of that material. Hence, laser annealing processes generally fall into two categories: melt or non-melt. Dopant diffusivity in molten silicon is about 8 orders of magnitude higher than that in solid-phase silicon. Therefore, dopants will diffuse very rapidly in molten silicon but slowly in solid-phase silicon, resulting in a step- like profile [28]. The melt-threshold also depends on the crystalline state since amorphized material has lower melting point as

41

compared to crystalline material. Hence, the melt-threshold of a-Si is much lower than cSi. In the experiments discussed above, the amorphized silicon depth is 36 nm and the chosen laser fluence is higher than the melt-threshold of a-Si but not enough to melt c-Si. Therefore, the laser pulse melts ~36nm of silicon and a step-like gradient is observed near 36 nm for all studied conditions. This observation indicates that the depth of pre-amorphizated silicon can set the junction depth and shallow junctions can be achieved by picking a lower PAI Ge energy as reported in [29].

2.7 Experimental Results with Flash Anneal
USJ studies were done using lightly doped (~1015 cm-3 ) n- or p-type Si (100) wafer substrates with 2 nm-thick thermal oxide as capping layer. For n+/p junctions, As implantation at 0.5-1.0 keV with 10 15 -2.5×1015 cm-2 dose and 7o tilt was performed. p+/n junctions were formed by BF2 implantation (0.8-1.0keV, 5×1014 -2.5×1015 cm-2 , 7 o ). 36 nm of silicon was pre-amorphized prior to BF 2 implantation by Ge implant (20 keV, 1015 cm-2). Figure 2.22(a) highlights the features of the flash annealing process used in this work. In a flash annealing process, the bulk of the wafer is first heated up to an intermediate temperature (Tint), and then a millisecond flash is applied to heat the device side of the wafer to the peak temperature (Tpeak ). Once the flash lamps are turned off, the bulk acts as a thermal sink to cool the device side very rapidly, and finally radiative cooling to ambient temperature occurs. Large heating and cooling rates (~106 o C/s) can be achieved using flash anneal. Figure 2.22(b) shows a typical heating cycle for a flash

42

anneal. High speed pyrometers are used to the monitor temperatures of the top and bottom sur faces of the wafer [30].

T T int

T peak

t

(a)

(b)

Figure 2.22 (a) Device (top) side temperature-vs.-time profile for flash annealing. The wafer temperature is first ramped up to an intermediate temperature (Tint ), and then the device side of the wafer is heated to the peak temperature (Tpeak ). (b) Measured temperatures at the top and bottom surfaces of a wafer during flash annealing. SIMS analyses of boron (BF 2=0.5 keV) and arsenic (As=0.5 keV) implanted samples before and after flash anneal are shown in Figure 2.23 and Figure 2.24, respectively. Spike annealed profiles are also plotted on the same scale for reference. Negligible dopant movement is observed for flash annealed samples compared to spike annealed samples. Clearly, flash annealing reduces dopant diffusion as compared with spike annealing and is a promising approach for ultra-shallow junctions formation for sub-45nm nodes. These results are consistent with those of other studies [31, 32].

43

10

22

PAI Ge + BF2 (0.5 keV) as implanted spike annealed spike annealed w/ co-implantation flash annealed

[B] (atoms/cm )

10

21

3

10

20

10

19

10

18

10

17

0

10

20

30

40

Depth (nm)
Figure 2.23 SIMS analyses of samples which received low-energy boron (0.5keV) implant. Negligible diffusion is observed for flash annealed samples compared to spike annealed samples (with or without co-implantation).
10
22

Arsenic (0.5keV) as implanted spike annealed flash annealed

[As] (atoms/cm )

3

10 10

21

20

10

19

10 10

18

17

0

10

20

30

40

Depth (nm)
Figure 2.24 SIMS analysis for as- implanted, spike annealed and flash annealed samples implanted with As (0.5keV). Flash annealing results in restricted dopant movement as compared with spike annealing. Various combinations of flash anneal parameters (Tint, Tpeak , and n, where n is number of flash shots) were also included in the study to elucidate interdependencies.

44

The time between flash anneals was relatively long, for the samples which received multiple flash anneals, as illustrated in Figure 2.25. Figures 2.26-2.31 exhibit the effects of Tint, Tpeak, and n on sheet resistance (Rs) and junction depth (Xj). T peak T int
Large t Large t

T

….

t Figure 2.25 Temperature-vs.-time profile for multiple-shot flash annealing with relatively long time intervals in between. Figures 2.26 & 2.27 show the impact of Tint for two different values of Tpeak , for single-shot flash annealing. For both 1250o C and 1300 o C peak temperature, Tint = 700oC results in shallower X j and lower Rs. Thus, 700o C is preferred over 800o C for the intermediate temperature.
10
22 o o

10

21

[B] (atoms/cm )

Tint=700 C, Rs=1714Ω/sq. o Tint=800 C, Rs=1996Ω/sq.

Tint=700 C, Rs=1381Ω/sq. o Tint=800 C, Rs=1470Ω/sq.

3

10

20

10

19

10

18

(a) Tpeak = 1250 C 10
17

o

(b) Tpeak = 1300 C 15 20 0 5 10 15 20

o

0

5

10

Depth (nm)

Depth (nm)

Figure 2 SIMS profiles of samples implanted with BF 2 (0.8keV, 10 15 cm-2 ) flash .26 annealed at various Tint with (a) Tpeak = 1250o C, (b) Tpeak = 1300oC.

45

Sheet Resistance, Rs (Ω/sq.)

3000 2800 2600 2400 2200

Solid: 1250 C, n=1; Open: 1300 C, n=1 14

o

o

15

Junction Depth, Xj (nm)

13 12 11

2000 1800 1600 1400 1200 700 750 800 o 10 9 8 7

Intermediate Temperature, T int ( C)
Figure 2 .27 Measured Rs and X j as a function of Tint . Solid symbols are for Tpeak = o 1250 C and n = 1. Open symbols are for Tpeak = 1300oC and n = 1. Figures 2.28 & 2.29 show the impact of Tpeak. Significant reduction in Rs (26% for Tint = 700oC and 20% for Tint = 800o C) is observed when Tpeak is increased from 1250o C to 1300o C. However, the reduction in Rs comes at the expense of a small

increase in X j (40nm) whereas flash annealing causes little dopant movement as earlier observed for conventional ion implantation.
10
22

B Infusion (3 kV, 10 cm ) 10
21

14

-2

[B] (atoms/cm )

as-doped spike annealed flash annealed

3

10

20

10

19

10

18

10

17

0

10

20

30

40

50

60

Depth (nm)
Figure 2.40 SIMS analyses of samples doped with B Infusion process (3k V, 10 14 cm-2 ). Negligible diffusion is observed for the flash annealed samples compared to the spike annealed samples. 55

Figures 2.41-2.43 summarize the effects of various flash anneal parameters investigated in this study. Figure 2.41 shows the impact of Tint for two different infusion process conditions. R s is reduced considerably when Tint is changed from 800o C to 700o C for both 1250o C and 1300o C peak temperature. A small change in X j is also observed, however this difference is within the depth resolution of SIMS. Thus, 700o C is preferred over 800oC for the intermediate temperature to achieve higher dopant activation.
3500

Sheet Resistance, Rs (Ω/sq.)

B Infusion 3 kV B Infusion 5 kV 3000 2500 2000 1500 1000 500 1250 C o 1300 C 700 750 800 o o

Intermediate Temperature, Tint ( C)
Figure 2.41 Measured sheet resistance as a function of Tint for two different peak temperatures. Figure 2.42 illustrates the effect of Tpeak for two different values of Tint. As seen from the reduction in Rs, Tpeak =1300oC appears to be better choice for peak temperature. 1300o C also caused more dopant diffusion (ΔX j ~0.5nm), but this change may be attributed to the SIMS depth resolution limitation. The combination of 700o C intermediate temperature with 1300 o C as peak temperature is found to be optimal in this study. Figure 2.43 shows the impact of carrying out multiple shots of flash annealing. 40-

56

45% decrease in Rs is observed as the number of shots, n, is increased from 1 to 3. However, the junction depth is also increased (ΔXj ~4.5nm).

Sheet Resistance, R s (Ω/sq.)

3500

Tint=800 C 3000 B Infusion 3 kV Tint=700 C o o

2500

2000

1500 B Infusion 5 kV 1000 1250 1300 o Peak Temperature, Tpeak ( C)
Figure 2.42 Measured sheet resistance as a function of Tpeak.
1500 20 B infusion 3 kV, B infusion 5 kV 18

Sheet Resistance, Rs (Ω/sq.)

Junction Depth, Xj (nm)

1250

16 1000

14 750 o o

12 Tint=800 C, Tpeak =1300 C 1 2 3

500

10

Number of shots, n
Figure 2.43 Measured sheet resistance and junction depth as a function of n for Tint = 800oC and Tpeak = 1300o C.

57

Rs-X j summary of flash annealed p+/n junctions formed by infusion doping is shown in Figure 2.44. Clearly, 32nm node USJ requirements are met (X j~12-15nm, Rs~1kΩ/ ) with infusion doped, flash annealed junctions.

Sheet Resistance, Rs (kΩ/sq.)

5 flash annealed 4

3

2

1

ITRS Target
0 5 10 15 20

0

Junction Depth, Xj @5E18 cm (nm)
Figure 2.44 Sheet resistance (Rs) determined by non-contact method vs. junction depth (X j) for p+/n junctions formed by infusion doping and flash annealing. To keep pace with high drive current requirement for future CMOS generations, (110) pMOSFET has been proposed as a potential solution because of its higher hole mobility as compared with (100) oriented silicon [33]. However because of wider channels in (110) oriented crystal shown in Figure 2.45, ion channeling is a big concern as. This will result in large X j making suppression of short channel effects difficult in (110) oriented pMOSFETs. Infusion doping does not suffer from the problem of ion channeling as reported earlier in Figure 2.39. This feature of Infusion doping can be used to overcome the limitation of ion implantation. Figure 2.46 shows SIMS results obtained with (110) and (100) oriented silicon substrates before and after flash annealing. There appears to be

-3

25

30

58

very small difference in the SIMS profiles obtained for both substrates, but this difference can be attributed to the SIMS depth resolution limitation. These results indicated that infusion doping is orientation independent and thus can be used for making ultra-shallow junctions for (110) pMOSFETs, if channeling is the limiting factor. (a) (b)

Figure 2.45 Atomic lattice of Si as viewed in the (a) and (b) directions.
10
22

[B] (atoms/cm )

10

21

(100) Substarte (110) Substrate

3

10

20

10

19

flash annealed

10

18

as doped

10

17

0

10

20

30

40

Depth (nm)
Figure 2.46 SIMS profiles of as doped and flash annealed (Tint = 800o C, Tpeak = 1300oC, n=3) doped with boron infusion process (5kV, 1014 cm-2 ) for (100) and (110) substrate orientations.

2.9 Summary
Ultra-shallow junction (USJ) requirements for sub-45 nm CMOS genera tions and associated challenges are reviewed in this chapter. Flash annealing appears to be a 59

promising candidate to replace conventional spike annealing. A detailed investigation is carried out to investigate the effects of flash anneal parameters. Best results are obtained with Tint = 700oC and Tpeak = 1300o C. Multiple shots of flash annealing further lower Rs, with a trade-off in X j. Non-contact method is employed for accurate R s measurements. Furthermore, it is demonstrated that F co-implantation helps to reduce the junction leakage, so that the limitation of ms-anneals’ efficacy to annihilate implant damage can be overcome with appropriate choice of F dose and energy. Advantages of Infusion doping over ion implantation are discussed and it appears very promising for (110) oriented substrate. Because of lack of channeling for the infusion process, its incorporation in CMOS process flow will help to eliminate the need for PAI, and eliminate the associated EOR defects, which are formed upon annealing amorphized silicon. Hence, leakage of thus ly formed junctions can be minimized. This study indicates that to realize shallow junctions for future nanoscale CMOS nodes, the use of millisecond annealing will be imperative. However, the use of advanced doping techniques (e.g. plasma, infusion) may be delayed in high- volume manufacturing because of superior process control and in-depth understanding of ion implantation. Molecular implants will more likely be well suited for extending ion implantation for shallow doping applications.

2.10 References
[1] T. Skotnicki, "Heading for Decananometer CMOS – Is Navigation Among Icebergs Still a Viable Strategy? " ESSDERC Proc., pp. 19-33, 2000. [2] B. H. Lee, J. Oh, H. -H. Tseng, R. Jammy, and H. Huff, " Gate Stack Technology for Nanoscale Devices", Materials Today, vol. 9, no. 6, pp. 32-40, 2006. 60

[3]

K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. -H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. Mclntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, " A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb- free Packaging," IEEE IEDM Tech. Digest , pp. 247–250, 2007.

[4]

International

Technology

Roadmap

for

Semiconductors,

2007

Edition,

(http://www.public.itrs.net/). [5] International Technolo gy Roadmap for Semiconductors, 2005 Edition,

(http://www.public.itrs.net/). [6] P. A. Stolk, H. -J. Gossmann, D. J. Eaglesham, D. C. Jacobson, C. S. Rafferty, G. H. Gilmer, M. Jaraíz, J. M. Poate, H. S. Luftman, and T. E. Haynes, "Physical Mechanisms of Transient Enhanced Dopant Diffusion in Ion-Implanted Silicon," J. Applied Physics, vol. 81, no. 9, pp.6031-6050, 1997. [7] P. -S. Chen, T. E. Hsieh, and C. -H. Chu, "Removal of End-of-range Defects in Ge+-pre-amorphized Si by Carbon Ion Implantation," J. Applied Physics, vol. 85, no. 6, pp. 3114-3119, 1999.

61

[8]

H. Graoui, M. Hilkene, B. McComb, M. Castle, S. Felch, N. E. B. Cowern, A. AlBayati, A. Tjandra, and M. A. Foad , "Optimization of Fluorine Co-implantation for PMOS Source and Drain Extension Formation for 65nm Technology Node," Mat. Res. Soc. Symp. Proc., vol. 810, pp. 247-252, 2004.

[9]

S. Nishikawa, A. Tanaka, and T. Yamaji, "Reduction of Transient Boron Diffusion in Preamorphized Si by Carbon Implantation," Applied Physics Letters, vol. 60, no. 18, pp. 2270-2272, 1992.

[10] N. E. B. Cowern, B. Colombeau, J. Benson, A. J. Smith, W. Lerch, S. Paul, T. Graf, F. Cristiano, X. Hebras, and D. Bolze, "Mechanisms of B deactivation control by F co-implantation", Applied Physics Letters, vol. 86, no. 10, pp. 101905, 2005. [11] T. Murakami, T. Kuroi, Y. Kawasaki, M. Inuishi, Y. Matsui, and Akihiko Yasuoka, "Application of nitrogen implantation to ULSI," Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, vol. 121, no. 1-4, pp. 257-261, 1997. [12] S. B. Felch, B. S. Lee, S. L. Daryanani, D. F. Downey, and R. J. Matyi, "Characterization of Ultra-shallow p+/n junctions Formed by Plasma Doping with BF 3 and N 2 Plasmas," Materials Chemistry and Physics, vol. 53, pp. 37-43, 1998. [13] M. Kase, "Ultra-Shallow Junction Formation," IEEE VLSI Technology Short Course, 2006. [14] R. B. Liebert, S. R. Walther, S. B. Felch, Z. Fang, B. O. Pedersen, and D. Hacker, " Plasma doping system for 200 and 300 mm wafers", Int. Conf. Ion Implantation Technology Proc., pp. 472 - 475, 2000.

62

[15] J. T. Scheuer, D. Lenoble, J. -P. Reynard, F. Lallement, A. Grouillet, A. Arevalo, D. Distaso, D. Downey, Z. Fang, L. Godet, B. W. Koo, T. Miller, and J. Weeman, "USJ formation using pulsed plasma doping," Surface Coatings & Technology, vol. 186, pp. 57-61, 2004. [16] J. Hautala, J. Borland, M. Tabat, and W. Skinner, "Infusion Doping for USJ Formation," Int. Workshop Junction Technology, pp. 50-53, 2004. [17] J. Hautala, M. Gwinn, W. Skinner, and Y. Shao, "Productivity Enhancements for Shallow Junctions and DRAM Applications using Infusion Doping," Int. Conf. Ion Implantation Technology Proc., pp. 174-177, 2006. [18] W. Krull, B. Haslam, T. Horsky, K. Verheyden, and K. Funk, " Simplifying the 45nm SDE Process with ClusterBoron® and ClusterCarbon™ Implantation," Int. Conf. Ion Implantation Technology Proc., pp. 182-185, 2006. [19] L. M. Rubin, M. S. Ameen, M. A. Harris, and H. Chuong, "Molecular Implants for Advanced Devices," Int. Workshop Junction Technology, pp. 113-118, 2007. [20] T. Ito, T. Iinuma, A. Murakoshi, H. Akutsu, K. Suguro, T. Arikado, K. Okumura, M. Yoshioka, T. Owada, Y. Imaoka, H. Murayama, and T. Kusuda, “Flash Lamp Anneal Technology for Effectively Activating Ion Implanted Si,” Ext. Abs. SSDM, pp. 182–183, 2001 [21] T. Gebel, M. Voelskow, W. Skorupa, G. Mannino, V. Priviter, F. Priolo, E. Napolitani, and A. Carnera, "Flash Lamp Annealing with Millisecond Pulses for Ultra-shallow Boron Profiles in Silicon," Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, vol. 186, no. 1-4, pp. 287-291, 2002.

63

[22] B. J. Cho, D. Poon, L. S. Tan, M. Bhat and A. See, "Multiple-Pulse Laser Annealing of Boron -Implanted Preamorphized Silicon and the Process

Optimization," Int. Workshop Junction Technology, pp. 22-26, 2004. [23] R. Lindsay, K. Henson, W. Vandervorst, K. Maex, B. J. Pawlak, R. Duffy, R. Surdeanu, P. Stolk, J. A. Kittla, S. Giangrandi, X. Pages, and K. van der Jeugd, " Leakage Optimization of Ultra-shallow Junctions Formed by Solid Phase Epitaxial Regrowth," J. Vac. Sci. Technol. B, vol. 22, no. 1, pp. 306-311, 2004. [24] T. Clarysse, D. Vanhaeren, and W. Vandervorst, "Impact of Probe Penetration on the Electrical Characterization of Sub-50 nm Profiles," J. Vac. Sci. Technol. B, vol. 20, no. 1, pp. 459-466, 2002. [25] V. N. Faifer, M. I. Current, T. Nguyen, T. M. H. Wong, V. V. Souchkov, "Noncontact Measurement of Sheet Resistance and Leakage Current: Applications for USJ-SDE/Halo Junctions," Int. Workshop Junction Technology, pp. 45-48, 2005. [26] V. N. Faifer, M. I. Current, T. M. H. Wong, and V. V. Souchkov, "Noncontact sheet resistance and leakage current mapping for ultra-shallow junctions," J. Vac. Sci. Technol. B, vol. 24, no. 1, pp. 414-420, 2006. [27] V. N. Faifer, M. I. Current, W. Walecki, V. Souchkov, G. Mikhaylov, P. Van, T. Wong, T. Nguyen, J. Lu, S. H. Lau, and A. Koo, "Non-Contact Electrical Measurements of Sheet Resistance and Leakage Current Density for Ultra-Sha llow (and Other) Junctions," Mat. Res. Soc. Symp. Proc., vol. 810, pp. 475-480, 2004. [28] C. H. Poon, B. J. Cho, Y. F. Lu, M. Bhat, and A. See, "Multiple-pulse Laser Annealing of Preamorphized Silicon for Ultrashallow Boron Junction Formation," J. Vac. Sci. Technol. B, vol. 21, no. 2, pp. 706-709, 2003.

64

[29] A. Shima, H. Ashihara, T. Mine, Y. Goto, M. Horiuchi, Y. Wang, S. Talwar and A. Hiraiwa, "Self- limiting Laser Thermal Process for Ultra-shallow Junction Formation of 50-nm Gate CMOS," IEEE IEDM Tech. Digest, pp. 493–496, 2003. [30] P. Timans, J. Gelpey, S. McCoy, W. Lerch, and S. Paul, "Millisecond Annealing: Past, Present and Future," Mat. Res. Soc. Symp. Proc., vol. 912, pp. 3-14, 2006. [31] T. Ito, K. Suguro, T. Itani, K. Nishinohm, K. Matsuo, and T. Saito, "Improvement of Threshold Voltage Roll-of by Ultra-Shallow Junction Formed by Flash Lamp Annealing," IEEE VLSI Technology Symp. Tech. Digest, pp. 53-54, 2003. [32] K. Adachi, K. Ohuchi, N. Aoki, H. Tusjii, T. Ito, H. Itokawa, K. Matsuo, K. Suguro, Y. Honguh, N. Tamaoki, K. Ishimaru, and H. Ishiuchi, "Issues and Optimization of Milisecond Anneal Process for 45 nm node and Beyond," IEEE VLSI Technology Symp. Tech. Digest, pp. 142-143, 2005. [33] M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D’Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, and H. Ng, “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” IEEE IEDM Tech. Digest , pp. 453-456, 2003.

65

Chapter 3

Process Integration of High-k /Metal-Gate with Flash Anneal

3.1 Introduction
Poly-Si gate and SiO 2 gate dielectric have been used as the standard gate stack in CMOS technologies over the years, until recently. The use of thermally grown SiO2 offers a thermally and electrically stable high-quality Si/SiO 2 interface. Indeed, the key enabler of successful MOSFET scaling has been the thinning of SiO 2 with every generation for increased gate control. The gate dielectric thickness has shrunk from ~100 nm in early generations to a few atomics layers (~1-2 nm) in current technology nodes. However, as SiO 2 is scaled below 2 nm in thickness, it starts to conduct a significant amount of current due to the quantum mechanical tunneling of electrons or holes, as shown in Figure 3.1 [1]. High gate leakage increases power consumption and dielectric reliability becomes a major concern for such an ultra-thin SiO 2 gate oxide. Furthermore, 66

boron can diffuse rapidly from a poly-Si gate to channel through a sub-2 nm oxide during high-temperature process steps, causing the threshold voltage to shift.

Figure 3.1 Measured and simulated direct tunneling gate current of nMOSFETs with ultra-thin SiO 2 dielectric [1]. The solution for avoiding undesired effects of ultra-thin gate dielectric is to replace SiO 2 with higher permittivity material. The equivalent oxide thickness (EOT) of a dielectric with relative permittivity κ and thickness t phys is given as –

EOT =

3 .9 t phys κ

(3.1)

where 3.9 is the relative permittivity for SiO 2 . From a device operation point of view, a physically thicker higher-κ gate dielectric is equivalent to SiO 2 with a thickness given by the EOT value. The addition of N to SiO 2 reduces boron diffusion through the dielectric and also provides for reduced leakage because the dielectric can be made slightly thicker for a given EOT. However, nitrided oxide provides only a near-term solution and its scaling is

67

limited to ~1.3 nm [ An alternate dielectric material with higher κ will be needed to 2]. replace silicon oxide/nitrided oxide for a long-term solution. Another major problem with a conventional poly-Si/SiO 2 gate stack is the poly-Si depletion near the gate dielectric interface. The result is a ~3-4 Å thick parasitic dielectric layer which adds substantially to EOT for sub-2 nm gate stacks. Metal gates offer a potential solution to the poly-Si depletion problem. The current status of replacing the conventional gate stack with an advanced gate stack is discussed in the next section.

3.2 Advanced Gate Stacks
Many materials properties need to be considered to determine the best high-κ candidate to replace SiO2 . The material must offer a significant barrier against carrier tunneling because leakage current increases exponentially with decreasing barrier height. Thus, high-κ material must have sufficient conduction- and valence-band offsets with respect to the silicon substrate and gate material. Additionally, high κ material must be thermodynamically stable on silicon, must provide high-quality interface with silicon channel, and must remain in an amorphous state (to minimize leakage current) at high temperatures commonly used in CMOS processing. Several high-κ materials have been investigated as a gate dielectric to replace SiO 2, such as TiO 2 [3-5], Ta 2O5 [6-8], La2 O3 [9], Y2 O3 [10], SrTiO 3 [11], Al2 O3 [12-14], HfO2 [15, 16], and ZrO2 [17-19]. Table 3.1 lists the most commonly studied high-κ candidates and their corresponding dielectric constants, bandgaps (Eg ), conduction band offsets (ΔE c), merits, and drawbacks [ 20]. TiO 2 , Ta2 O5 , and SrTiO 3 have very low ΔEc and are not thermodynamically stable on silicon. In addition, TiO2 has a low

68

crystallization temperature (~400oC). Y2 O3 and La 2 O3 have large Eg and ΔE c, but Y2 O3 crystallizes at ~400o C, and chemical instability due to reaction with moisture is a serious issue for La2O 3 . Al2 O 3 has many favorable properties including a large Eg , and is amorphous and thermodynamically stable on silicon up to high temperatures. However, Al2 O3 has κ value of only ~10 and has a large fixed charge density. Thus, Al2 O3 will not be a viable candidate to replace SiO 2 as a long-term solution. ZrO 2 is a potentially attractive candidate, but it forms detrimental silicide when in contact with poly-Si gate. Table 3.1 Comparison of various characteristics and main features of existing and candidate high- κ gate dielectrics [20].

Research on high-κ dielectrics has converged on HfO 2 -based dielectrics because they show much promise in overall materials properties to replace SiO 2 . However, typical dopant activation anneal temperatures (~1000o C) used in CMOS processing are much higher than the crystallization temperature of HfO2 . The addition of Si [21] and N [22] to HfO2 increases thermal stability significantly. Improved thermal stability also minimizes the interfacial layer thickness. However, N induces a fixed oxide charge and tends to pile

69

up at the interface, which can lead to lower mobility. Furthermore, the addition of Si reduces the dielectric constant of the gate dielectric. Therefore, careful optimization of Si and N content and profile is needed to fully realize the scaling benefits of HfO 2. Despite the growing understanding of Hf-based dielectrics, potential roadblocks remain for the successful integration of poly-Si and Hf-based dielectrics. An unfavorable increase in threshold voltage has been observed for PMOS devices with poly-Si/high-κ stack [23]. This is primarily due to Fermi- level pinning because the gate work function for a poly-Si/high- κ gate stack is determined by Si-Hf bonding instead of the Fermi level of the poly-Si gate. The pinning location is believed to be just below the Si conduction band edge [ 4]. Additionally, the poly-Si electrode suffers from a number of other 2 drawbacks such as gate depletion and boron penetration. Therefore, research on the use of a metal gate electrode to replace conventional poly-Si has gained momentum. A HfSiON gate dielectric with metal gate has been shown to meet 45 nm node requirements with EOT scalable to 1 nm and carrier mobilities comparable to that of nitrided oxide [25]. Intel has implemented high-κ/metal-gate technology in 45 nm CMOS generation using a high-κ first, gate- last process integration approach [26]. It is well recognized that one of the major issues for nano-scale MOSFET source/drain design is the formation of ultra-shallow junctions (USJs). In chapter 2, it is shown that to achieve USJ requirements for the 32 nm generation and beyond, advanced anneal techniques such as flash anneal will be needed. Since high-κ/metal- gate technology is already being implemented at the 45 nm node, it becomes very important to understand the integration challenges of flash anneal with a high- κ/metal-gate. There are reports of using laser anneal and flash anneal on poly-Si/silicon oxide-based gate stack, 70

but very little is reported about their impact on high-κ/metal gate stacks [27-32]. In this chapter, a detailed investigation of the effects of flash annealing on MOSFETs with Hf based dielectric and metal gate is presented.

3.3 Device Fabrication
A conventional gate-first CMOS process flow was used to fabricate sub-100 nm gate length devices on p-type (100) silicon wafers with a 5 µm epi- layer of doping density ~3×1017 cm-3 as shown in Figure 3.2. After a shallow trench isolation (STI) process, n-wells and p-wells were formed for p-MOS and n-MOS devices respectively. After a pre-gate clean and an ozone treatment that produces ~1 nm interfacial SiO x, a 3nm thick HfSiO film was grown by atomic layer deposition using pulses of tetrakis(ethylmethylamino)hafnium (TEMAHf) and tetrakis(ethylmethylamino)silicon (TEMASi) [33]. Ozone was the oxidizing ambient. The composition was determined to be Si/(Si+Hf)~0.20. Afterwards, wafers received a post-high-κ deposition anneal (PDA) in ammonia (NH3 ) at 700°C and 30 Torr for 60 seconds. Resultant N content in HfSiON was estimated to be ~7 at. % by X-ray photoelectron spectroscopy (XPS) [34]. For the gate electrode, 10 nm TiN was deposited by ALD, and capped by 100 nm thick LPCVD poly-Si for ease of process integration. S/D extensions (SDE) and halo implants were done next, followed by spacer and deep S/D formation. For n-SDE, As was implanted at 0.5keV, 10 15 cm-2 with 7o tilt. A pre-amorphization implant (Ge: 10 keV, 1015 cm-2) followed by B implant (0.8 keV, 5×1014 cm-2 , 7o ) were used to form p-SDE. A spike anneal (1070oC) or flash anneal (Tint=800 o C, Tpeak=1300oC) was used to activate implanted source/drain dopants, followed by a two-step cobalt-salicidation process done

71

at 550o C and 750oC for 30 seconds in N2 ambient. After metallization, forming gas anneal (FGA) was done last in H2 /N 2 at 480oC for 30 minutes. STI and Well Formation Gate Stack Formation (ALD HfSiO + ALD TiN) Shallow Extensions and Halo I/I Spacer Formation Deep Source/Drain I/I Dopant Activation Anneal Spike (1070o C) vs. Flash (1300o C, ms) Salicidation Metallization Figure 3.2 Gate- first CMOS process flow used to evaluate the impact of flash annealing on high- κ/metal- gate stacks.

3.4 Device Characterization
3.4.1 SCE Control
Well-behaved transistor characteristics are obtained from the fabricated MOSFETs. Figure 3.3 shows the measured IDS -VGS characteristics of spike annealed and lash annealed MOSFETs (Lg = 1.0 µm & 0.1 µm) at VDS =50 mV and 1.2 V.
1x10-1 (a) Lg = 1.0 µm 1x10 1x10 1x10
-3

VDS = 1.2V

Drain Current, IDS (A)

-5

VDS = 50mV

-7

1x10-9 1x10 -11 1x10
-13

solid line : spike annealed dashed line : flash annealed

-0.5

0.0

0.5

1.0

1.5

2.0

Gate Voltage, V GS (V)

72

1x10-1 (b) Lg = 0.1 µ m

VDS = 1.2V VD S = 50mV

Drain Current, I DS (A)

1x10-3 1x10 1x10
-5

-7

1x10-9

1x10 -11 1x10
-13

solid line : spike annealed dashed line : flash annealed

-0.5

0.0

0.5

1.0

1.5

2.0

Gate Voltage, VGS (V) Figure 3.3 Id -Vg of spike annealed and flash annealed nMOSFETs ? (a) long-channel (Lg = 1.0 µm) and (b) short-channel (Lg = 0.1 µm) ? measured at Vd = 50 mV and V d = 1.2 V.
Subthreshold Slope (mV/decade)
150 EOT = 1.15nm, W=10 µm spike annealed flash annealed 120

Shallower X j
90

60

0.1

300 250

Gate Length, Lg (µm)

1

EOT = 1.15nm, W=10µ m spike annealed flash annealed

DIBL (mV/V)

200 150 100 50 0 0.1

Shallower Xj

Gate Length, Lg (µ m) Figure 3.4 Measured SS and DIBL values for nMOSFETs fabricated using either spike or flash annealing to activate the implanted S/D dopants.

1

73

The subthreshold slope (SS) and drain- induced barrier lowering (DIBL) of the transistors with different gate lengths are shown in Figure 3.4. It can be seen that the short-channel effects (SCE) are well controlled down to 100 nm gate length for flash annealed MOSFETs as compared with spike annealed MOSFETs. The improved SCE can be attributed to shallower junction depth (X j) achieved in flash annealed devices f or identical source/drain-extension ion implantation conditions. However, SS for MOSFETs with L >0.15 µm is worse for flash annealed devices as compared with spike annealed g devices. This observation is explained in section 3.4.3.

3.4.2 Gate Stack Integrity
The physical structure of gate stack after S/D activation anneal is analyzed using transmission electron spectroscopy (TEM). Figure 3.5 shows cross-sectional bright field TEM (BFTEM) and high resolution TEM (HRTEM) images for spike annealed and flash annealed gate stacks. These images illustrate that there is negligible difference in the physical thicknesses of HfSiON film and interfacial oxide layer for spike vs. flash annealed gate stacks. Measured thicknesses for HfSiON and SiOx are ~3 nm and ~1 nm, respectively. The HfSiON layer is observed to be amorphous after spike (or flash) anneal, based on the evidence provided by the HRTEM images. The HfSiON/SiO x interface appears to be slightly rougher in the flash annealed sample. High angle annular dark- field scanning Transmission Electron Microscopy (HAADF-STEM) using energy-dispersive X-ray spectroscopy (EDXS) and electron energy loss spectra (EELS) is used to compare chemical profiles after S/D activation anneal as shown in Figure 3.6. EELS and EDXS data were acquired across the high- κ/ metal- gate stack. EDXS and EELS profiles relate data with different intensity scales, 74

(a) (b)

TiN High-κ SiOx

20 nm
Image: 'E2323 070517007_6080231_15_AK6_rot.dm3' MAG: 115kX PCL: 070517007

5 nm
Image: 'E2333 070517007_6080231_15_AK6.Ed_rot.dm3' MAG: 590kX PCL: 070517007

(c)

(d)

TiN High-κ SiOx

20 nm
Image: 'E1875 070424017_6080231AB_18_AK6_rot.dm3' MAG: 115kX PCL: 070424017

5 nm
Image: 'E1886 070424017_6080231AB_18_AK6.Ed_rot.dm3' MAG: 590kX PCL: 070424017

Figure 3.5 Cross-sectional bright field TEM (BFTEM) and high resolution TEM (HRTEM) images of high- κ/metal gate stacks after S/D activation anneal. (a), (c) ? BFTEM; (b), (d) ? HRTEM. (a), (b) ? spike anneal (1070o C); (c), (d) ? flash anneal (Tint=800o C, Tpeak =1300o C) The thickness of the TiN, the HfSiO N film and the interfacial oxide layer are approximately 9.7 nm, 3 nm and 0.9 nm, respectively, for both spike and flash annealed devices.. The HfSiON layer was observed to be amorphous, based on the evidence provided by the HRTEM images.

75

(a) Hf EDX Ti Si O

1

Intensity (a.u.)

N

5 nm

0

5

10

15

Depth (nm)
(b) Si Hf EDX Ti

1

Intensity (a.u.)

O N

5 nm

0

5

Depth (nm)

10

15

Figure 3.6 High angle annular dark- field scanning TEM (HAADF-STEM) micrograph of the sample in cross-section with corresponding electron energy loss spectrometry (EELS) and energy dispersive X-ray spectroscopy (EDXS) scans acquired along the line from left to right as indicated by the arrow. (a) ? spike anneal (1070 o C); (b) ? flash anneal (Tint=800oC, Tpeak=1300oC)

but have been scaled to allow comparison on one plot. Figure 3.6 suggests that there is no noticeable difference in the chemical profiles for gate stacks which underwent flash annealing vs. spike annealing.

76

Capacitance- voltage ( -V) measurements were done next on high-κ/metal- gate C MOS capacitors (A=5×10-5 cm2 ). Figure 3.7 shows the well-behaved high- frequency (f = 100 kHz) C-V curve for nMOS capacitors. The equivalent oxide thickness (EOT ) and the flatband voltage (VFB ) were extracted using the NCSU CVC program [35]. Comparable extracted EOT (~1.15 nm) and V FB (~-0.52 V) values are seen for the gate stacks exposed to flash vs. spike anneals. pMOS capacitors exhibit similar features as shown in Figure 3.8 and negligible difference in extracted EOT and V FB is observed.
1.5

EOT (nm)

100

A = 5E-5cm , f = 100kHz flash annealed spike annealed

2

1.0 0.5 0.0 Spike Flash

Capacitance (pF)

80

60

-0.6 40

20

VFB (V)
0 1

-0.4 -0.2 0.0 Spike Flash

0 -1

Gate Voltage (V)

Figure 3.7 Comparison of C-V curves for nMOS capacitors fabricated with spike or flash annealing (f = 100 kHz). Comparable EOT and VFB values are seen (right).

As shown in Figure 3.9, no frequency dispersion is seen in the multi- frequency CV measurements for the flash annealed gate stacks as frequency is increased from 10 kHz to 250 kHz. The C-V hysteresis measured using bidirectional voltage sweeps is negligible at a measurement frequency of 100 kHz.

77

EOT (nm)

100

A = 5E-5cm , f = 100kHz 1.0 0.5 0.0 0.6

2

1.5

Capacitance (pF)

80

flash annealed spike annealed

60

Spike Flash

40

20

V FB (V)
0 1

0.4 0.2 0.0

0 -1

Gate Voltage (V)

Spike Flash

Figure 3.8 Measured high- frequency (f = 100 kHz) C-V curves for high-κ/metal- gate pMOS capacitors after either spike or flash annealing. Similar EOT (~1.15 nm) and V FB (~0.45 V) values are achieved as shown on the right.
120 A = 5E-5 cm 100
2

forward Sweep backward Sweep

Capacitance (pF)

80

250 kHz 100 kHz 10 kHz

60 A = 5E-5 cm f = 100kHz
2

40

20 0 -1

0

1 -1

0

1

Gate Voltage (V)
Figure 3.9 C-V curves for pMOS capacitors fabricated with flash annealing. No frequency dispersion or hysteresis is observed for flash annealed gate stacks. The accumulation gate leakage current of capacitors (A=5×10-5 cm2 ) fabricated with spike or flash annealing is shown in Figure 3.10. The leakage current of the flash annealed gate stack is comparable to that of the spike annealed gate stack at a bias of V GS78

V FB =1 V (Jg = 0.5 A/cm2 ). The time-zero breakdown (TZBD) voltage for flash -annealed gate stacks is higher than that for spike-annealed gate stacks. This might be due to small differences in the crystalline structure of the high- κ films subjected to annealing with rather different peak temperatures and thermal budgets.
10 10
3

A=5E-5 cm

2

1

Jg (A/cm )

2

10 10

-1

-3

spike annealed flash annealed

1x10 10

-5

-7

10-9

0

-1

-2

-3

-4

-5

VGS - VFB (V)
Figure 3.10 Accumulation Jg for both spike and flash annealed gate stacks. Time- zero breakdown (TZBD) voltage is observed to increase for flash annealed gate stacks vs. spike annealed gate stacks.
3

Jg (-A/cm ) @ VFB-1

10

Poly-Si/SiO2 10
2

spike annealed flash annealed >500x

2

10

1

10

0

10

-1

1.0

1.1

1.2

1.3

EOT(nm)
Figure 3.11 Jg,accumulation vs. EOT for HfSiON/TiN capacitors fabricated with spike or flash annealing. Leakage current density is on par with the historical high- κ trend line. Spike annealed data is taken from [36].

79

Figure 3.11 shows the relationship between gate current density at V GS = V FB−1 V and EOT. For reference, the SiO 2 /poly-Si model is shown. The flash annealed HfSiON/TiN gate stack data point is in agreement with the trendline for spike annealed gate stacks, and >500× leakage reduction versus SiO 2 /poly-Si is achieved at 1.15 nm EOT. Fast transient charging (FTC) in high- κ dielectrics is one of the major high-κ process integration issues. FTC has been shown to be a major contributor to low mobility, poor reliability and V TH instability [37-41]. The use of HfSiON is shown to reduce the charge trapping effects [25]. In order to study the impact of flash annealing on charge trapping, single pulse IDS -VGS measurements were done on transistors with W/L=10 µm/1 µm. Figure 3.12 shows the normalized drain current (IDS ) as a function of time when a trapezoidal pulse is applied to the gate for pulse duration of 200 µs with t r = tf =100 ns.

spike annealed 1.0 1.0

Normalized IDS

Normalized IDS

0.8

flash annealed 0.8

0.6

VGate = -1 to 2V PW = 200µs tr = tf = 100ns tr tf

0.6

0.4

0.4 0.2

200 (µs)
Figure 3.12 Single pulse IDS-V GS measurements show insignificant Δ IDS for both spike and flash annealed gate stacks, indicating negligible fast transient charge trapping. PW, t r, and tf correspond to the pulse width, pulse rise, and fall times, respectively.

80

Monitoring the IDS during the flat pulsewidth portion of the IDS -time plot, minimal IDS drop over the entire pulse duration is observed for the flash annealed sample, indicating negligib le charge trapping. This was further confirmed by long-time positive bias temperature instability (PBTI) measurements under different stress voltage biases (V GSV TH = 1.2 V, 1.4 V). The results indicate negligible PBTI variation with annealing techniques, as shown in Figure 3.13.

125 C, 10 µm x 1µm nMOSFET 0.1

o

ΔVTH (V)

VGS-VTH= 1.4V

VGS-VTH= 1.2V

spike annealed flash annealed 10
3

10

1

10

2

Time (s)

10

4

Figure 3.13 Comparison of VTH shift for PBTI stresses at various voltages, for spike vs. flash annealed gate stacks. Therefore, it can be concluded that flash annealing process has minimal effects on the gate stack properties such as EOT, V FB , and leakage, and it appears compatible with high- κ/metal- gate stacks. Furthermore, it is evident that bulk charge trapping in high-κ is not an issue with flash annealing.

3.4.3 MOSFET Performance
Linear peak transconductance (Gm ) as a function of gate length for spike and flash annealed nMOSFETs (W=10 µm) is shown in Figure 3.14. Significant degaradation in 81

the peak G m value is observed for flash annealed FETs as the gate length is scaled down to 100 nm; ~1.8× reduction is seen at Lg = 100 nm.
2.0

Linear peak Gm (mS)

1.5

spike annealed flash annealed

1.0

0.5

0.0 0.0

0.2

0.4

0.6

0.8

1.0

Lg (µm)
Figure 3.14 Effect of S/D activation anneal technique on Gm , plotted as a function of gate length, Lg. (W =10 µm, VDS =50 mV).

The effective electron mobility was extracted next using drain conductance (gd) determined at low drain bias and carrier density (N inv ) determined by split C-V measurement. This extraction was further confirmed by using the NCSU MOB2D model [42]. However, for identical S/D implantation conditions, shallower junction depth and higher dopant activation is achieved for flash annealed MOSFETs as compared to spike annealed MOSFETs. Therefore, different S/D parasitic resistance ( sd ) is expected for R flash and spike annealed devices. To decouple the impact of Rsd on device performance, drain conductance was corrected for Rsd ?

g d (Rsd ) =

gd 0 1+ g d 0 Rsd

(3.2)

82

where gd0 is drain conductance without Rsd and gd (R sd) is drain conductance with Rsd . DC IDS -VGS measurements were done on 10×1 µm2 nMOSFETs to determine gd (Rsd ). Rsd was extracted by channel-resistance method. gd0 was calculated using eqn. (3.2).

Effective Mobility (cm /V-s)

300

10µm x 1µm nFET

2

200

100

Universal Spike (w/ Rsd correction) Flash (w/ Rsd correction)

0 0.0

5.0x10

5

1.0x10

6

1.5x10

6

2.0x10

6

Effective field (V/cm)
Figure 3.15 Extracted electron mobility vs. effective transverse electric field. Mobility is degraded for nMOSFET fabricated with flash annealing vs. spike annealing.

The extracted effective electron mobility using gd0 and N inv is shown in Figure 3.15. For reference, the universal electron mobility model is also shown. Both the peak and high-field mobility values are degraded for a flash-annealed gate stack. Clearly, the performance of flash annealed MOSFETs is degraded. Fixed amplitude charge pumping (CP) measurements were done on 10×1 µm2 nMOSFETs to understand the cause for the mobility degradation. A trapezoidal pulse of amplitude = 1.4 V is applied to the gate with t r = t f =10 ns. Interface traps fill from the S/D regions into the channel during t r and empty into substrate during t f. Charge pumping current (Icp ) is given by (3.3)

Icp = q fANit
83

where f is the frequency, A is the channel area, and N it is the interface trap density. Due to high gate leakage current (EOT is ~1.15 nm), measured charge pumping current was corrected with low frequency Icp (1 kHz) [43]. Figure 3.16 compares the N it values for devices that underwent flash and spike annealing. Significantly higher Nit value is observed in the stacks that received flash annealing, which is 3-4× higher versus spike annealed gate stacks.
10 f = 1MHz

Nit (x10 /cm -eV)

8

Spike annealed Flash annealed

2 10

6

4

2 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0

Voltage(V)
Figure 3.16 Charge pumping (1 MHz) comparison of the two S/D activation annealing methods.

IL

Low f CP probing region

High-κ High f CP probing region

Figure 3.17 Energy band diagram for charge pumping measurements done at different frequencies. 84

For further investigation, the quality of the interfacial oxide is compared using the charge pumping method at various frequencies, which allows for spatial probing of the interfacial SiO x layer and high- κ/SiO x interface as shown in Figure 3.17 [44].
40 35 spike annealed flash annealed

Nit (x10 /cm eV)

.

2 10

30 25 20 15 10 5 10 100 1000

Frequency (kHz)
Figure 3.18 Charge pumping measurements of interface trap density (N it) at various frequencies. Higher N it and a significant difference in trap profile are observed for the flash annealed gate stacks as compared to the spike annealed gate stacks. Figure 3.18 shows measured Nit vs. frequency for 10×1 µm2 nMOSFET. The density of traps at high frequencies, which correspond to the trap location near the interface with the substrate, is higher in the flash annealed sample. A higher slope of the N it is also observed for flash annealed gate stacks at lower frequencies, indicating higher trap density towards the HfSiON/SiO x interface. Hence, the likely cause of the mobility loss seen in the flash -annealed gate stack is a higher interface state density. This is consistent with the degraded negative bias temperature instability (NBTI) characteristics (Figure 3.19) and higher SS seen for long channel MOSFETs (Figure 3.4).

85

125 C, 10µm x 1µm pMOSFET flash annealed

o

Δ VTH (V)

0.1

spike annealed

VGS-VTh = -1.2V VGS-VTh = -1.4V
3

10

2

10

10

4

Time (s)
Figure 3.19 NBTI comparison. Degraded characteristics are seen for flash annealed gate stack. This difference is primarily attributed to the degraded Si interface. To explain the origin of higher N it, wafer-bow measurements were performed before and after the flash-annealing. The radius of curvature measurements are summarized in Table 3.2. A large change in wafer radius of curvature is observed, indicating wafer- level stress after flash annealing. Negative (positive) radius of curvature values correspond to compressive (tensile) stress. This is not unexpected, because only the device side of the wafer is heated to very high temperature, so that there is a large thermal gradient through the thickness of the wafer, during flash annealing. Similar stress behavior has been reported for a pulsed laser annealing process [31]. Table 3.2 Radius of curvature for the wafers before and after the flash annealing. Negative and positive curvatures correspond to compressive and tensile stress in the wafer, respectively.
Wafer ID 109-02 (before flash anneal) 109-13 (after flash anneal) 109-14 (after flash anneal) Radius of curvature [m] -471.32 10.32 9.6 Stress C T T

86

As has been shown earlier via simulations, CP measurements in the frequency range down to a few kHz may access traps located primarily within the SiO x interfacial layer and at the high- κ/SiO x interface [44]. Greater N it change with decreasing CP frequency in the flash annealed devices (seen in Figure 3.18) is thus indicative of structural modification in the SiOx interfacial layer. At high CP frequencies (1 MHz), when the dielectric is probed in the vicinity of its interface with the substrate, the observed N it increase is probably caused by the thermal-stress- induced defects (broken bonds) at the Si/SiO x interface. A higher slope of the N it vs. frequency trend at lower frequencies corresponding to deeper probing into the gate dielectric indicates a higher density of high- κ induced traps in SiO x [45]. These defects, which are likely to be oxygen vacancies generated in the SiO x interfacial layer due to high- κ-driven O outdiffusion [45], can be expected to be created more efficiently during the high-temperature (~1300o C) flash annealing.

3.4.4 Effects of Post-Metallization Anneal
As discussed earlier, flash annealing appears to be compatible with high- κ/metalgate stacks, but degraded Si interface is seen for flash annealed FETs, resulting in mobility loss. This mobility degradation is a major roadblock for the adoption of flash annealing. In this section, the effects of a post- metallization annealing process on interface properties of fabricated MOSFETs which received flash annealing as S/D activation anneal are presented. After the conventional forming gas anneal discussed in section 3.4, a high-

pressure (10 atm) anneal was performed in pure (100%) deuterium (D2 ) ambient for 30 minutes at 400o C [46]. Linear drain current (IDS ) and transconductance (Gm ) versus gate 87

voltage (VGS ) of 10 µm ×1 µm nMOSFET before and after high-pressure (H.P.) anneal are shown in Figure 3.20. Measurements were taken for V DS=50 mV. After the H.P. anneal, ~7-8% improvement is observed in IDS and G m.
160 10µm x 1µm nFET, VDS = 50mV 300

Transconductance, Gm (µS)

Drain Current, I (µA)

120

DS

after H.P. anneal before H.P. anneal

250 200

80

150 100

40 50 0 0.0 0 2.0

0.5

1.0

1.5

Gate Voltage, VGS (V)
Figure 3.20 Samples annealed in the high-pressure (H.P.) D2 ambient show improved linear drain current and transconductance (VDS =50 mV). Capacitance- voltage (C-V) measurements were done next on small-area MOS capacitors (A=5×10-5 cm2 ), and no discernible difference in EOT and V FB is seen in C-V curves before and after H.P. anneal as shown in Figure 3.21.
100 A = 5E-5cm , f = 100kHz
2

Capacitance (pF)

80 after H.P. anneal before H.P. anneal

60

40

20

0 -1.0

-0.5

0.0

0.5

1.0

Gate Voltage (V)
Figure 3.21 Measured high-frequency (f = 100 kHz) C-V curves for nMOS capacitors before and after H.P. annealing. 88

DC IDS-VGS measurements shown in Figure 3.20 were further corrected for series resistance (Rsd ) and using NCSU MOB2D model, effective electron mobility was extracted. It is found that high-pressure anneal is effective for recovering mobility loss as shown in Figure 3.22. Significant improvement is seen for peak field mobility, which is governed by interface quality. Improved interface is further evidenced by lower subthreshold slope (S.S.) for a 10×1 µm2 nMOSFET as shown in the Figure 3.20 inset. Thus mobility recovery is attributed to reduction in interface trap density. However, at a higher electric field, mobility gain diminishes, which indicates that H.P. anneal helps to recover mobility loss due to surface roughness scattering, but does not recover it fully. Further optimization of anneal conditions will be needed for further gains.

Effective Mobility (cm /V-s)

85

300 10µm x 1µm nFET, Flash annealed

SS (mV/dec.)

80 75 70

2

200

Before

After

100

Universal before H.P. anneal after H.P. anneal

0 0.0

5.0x10

5

1.0x10

6

1.5x10

6

2.0x10

6

Effective field (V/cm)
Figure 3.22 Mobility in a flash-annealed device is improved by H.P. anneal. S.S. value is also lowered for 10 µm × 1 µm nMOSFET.

3.4.5 Challenges with Flash Anneal
Flash anneal is a millisecond anneal process. Therefore, its efficacy to annihilate implantation damage is a primary concern because of the shorter anneals time. Figure 3.23 shows the cumulative probability plot for the junction leakage of a n+/p diode of 89

area 10-6 cm2 . Comparing the 50% values for flash annealed and spike annealed diode, it is seen that flash annealed junctions leak more as compared to spike annealed junctions by ~10×. The junction leakage is a sensitive function of the location of residual effects with respect to the depletion region, which in turn depends on the S/D extension and halo implant profiles. Therefore, careful optimization of implantation conditions of S/D extension and halo are needed to reduce the junction leakage. In addition, F coimplantation as discussed in section 2.7 can be used to passivate the residual defects and thus reduce the junction leakage.
100

Cummulative Probability

A=10 cm 80

-6

2

1x10

-4

50% value

1x10 10 10

-5

60

-6

-7

40

Spike

Flash

spike annealed flash annealed 20

0 -6 10

Junction leakage (A/cm )

1x10

-4

10

-2

2

10

0

Figure 3.23 Junction leakage of n+/p diode after spike or flash anneal. Figure 3.24 shows the overlap capacitance ( ov ) for flash and spike annealed C devices. 20% reduction in Cov is seen for flash annealed devices. This reduction can be attributed to shorter anneal time used in flash anneal process. It has been reported that a minimum length of overlap region (Lov) is needed to avoid hot-carrier injection into the ungated region, which leads to reliability problems. Therefore, the small thermal budget of the flash anneal process may become an issue for highly- scaled CMOS devices

90

because it does not result in enough overlap of the source/drain region under the gate. To counter this problem, an additional low temperature anneal before flash anneal may be needed in conjunction with flash anneal, to provide enough thermal budget to satisfy the Lov requirement. The upper limit of the thermal budget for this anneal will be set by USJ requirements. This additional anneal can also help annihilate implant damage, reducing the higher junction leakage shown in Figure 3.23.
100

Cummulative Probability

50% value

spike annealed flash annealed

0.8 0.6 0.4 0.2 0.0 Spike Flash

80

60

40

20

0 0.00

0.25

0.50

0.75

1.00

Overlap Capacitance (fF/µm)
Figure 3.24 Overlap capacitance for flash and spike annealed devices.

3.5 Summary
The process integration of high-κ/metal-gate with flash anneal is presented in this chapter. The flash anneal process is found to be compatible with the high-κ/metal- gate stack in terms of gate stack integrity, and is effective to achieve the benefits of USJs. Generation of O vacancies within the interfacial SiOx layer due to thermal stress and high-temperature processing results in higher interface-state density and hence degraded mobility. An optimized post-metallization annealing process is shown to be effective for recovering device performance. 91

3.6 References
[1] S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum- mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-thin-oxide nMOSFETs," IEEE Electron Device Letters, vol. 18, no. 5, pp. 209 -211, 1997. [2] S. Song, W. S. Kim, J. S. Lee, T. H. Choe, J. K. Choi, M. S. Kang, U. I. Chung, N. I. Lee, K. Fujihara, H. K. Kang, S. I. Lee, and M. Y. Lee, "Design of sub-100 nm CMOSFETs: Gate Dielectrics and Channel Engineering," IEEE VLSI Technology Symp. Tech. Digest, pp. 190-191, 2000. [3] S. A. Campbell, D. C. Gilmer, X. C. Wang, M. T. Hsieh, H. S. Kim, W. Gladfelter, and J. Yan, "MOSFET Transistors Fabricated with High-permittivity TiO2 Dielectrics," IEEE Trans. Electron Devices, vol. 44, no. 1, pp. 104-109, 1997. [4] B. H. Lee, Y. Jeon, K. Zawadzki, W. Qi, and J. C. Lee, "Effects of Interfacial Layer Growth on The Electrical C haracteristics of Thin Titanium Oxide Films on Silicon," Applied Physics Letters, vol. 74, no, 21, pp. 3143-3145, 1999. [5] C. Hobbs, R. Hedge, B Maiti, H. Tseng, D. Gilmer, P. Toblin, O. Adetutu, F. . Huang, D. Weddington, R. Nagabushnam, D. O'Meara, K. Reid, L. La, L. Grove, M. Rossow, "Sub-quarter Micron CMOS Process for TiN-gate MOSFETs with TiO2 Gate Dielectric Formed by Titanium Oxidation," IEEE VLSI Technology Symp. Tech. Digest, pp. 133-134, 1999. [6] A. Chatterjee, R. A. Chapman, K. Joyner, M. Otobe, S. Hattangady, M. Bevan, G. A. Brown, H. Yang, Q. He, D. Rogers, S. J. Fang, R. Kraft, A. L. P. Rotondaro, M. Terry, K. Brennan, S. -W. Aur, J. C. Hu, H. -L. Tsai, P. Jones, G. Wilk, M. Aoki,

92

M. Rodder, and I. -C. Chen, "CMOS Metal Replacement Gate Transistors Using Tantalum Pentoxide Gate Insulator," IEEE IEDM Tech. Digest, pp. 777-780, 1998. [7] H. F. Luan, S. J. Lee, C. H. Lee, S. C. Song, Y. L. Mao, Y. Senzaki, D. Roberts, and D. L. Kwong, "High Quality Ta 2O 5 Gate Dielectrics with T