CHAPTER 6
6.4) John von Neumann, usually considered the developer of the computer as we know it today, set down a series of guidelines known as the von Neumann architecture for computers. The major guidelines include: Memory holds both programs and data which is known as the stored program concept. This allows programs to be changed easily. Memory is addressed linearly- there is a single sequential numeric address for each and every memory location. Memory is addressed by the location number without regard to the data contained within.
Using the Little Man Computer, it requires the use of a particular mailbox to store or to retrieve data (in the form of 3-digit numbers). When adding 2 numbers, the LMC will use the ADD instruction which allows the Little Man to go to the specific mailbox address given from the instruction, then grab that number in the mailbox, then go to the calculator to add the mailbox number to the number already stored in the calculator while the number in the mailbox is unchanged. These steps follow the guidelines of the von Neumann architecture in that it stores a number, goes to the specific mailbox address, and adds to the number stored in the calculator with the number in the mailbox being unchanged.
6.7)

CHAPTER 7
7.5) The fetch-execute cycle is the basis for every capability of the computer and as already seen from the Little Man Computer, the operation of every instruction is defined by its fetch-execution instruction cycle. Much of the cycle consists of copying data from one register to another and involves using steps:
Step 1: PC -> MAR (instruction being transferred from the specified memory location to the memory data register)
Step 2: MDR -> IR (transfer instruction to instruction register)
(remaining steps are instruction dependent)
[LOAD]
Step 3: IR[address] -> MAR (only address part of the contents of the instruction register transferred)
Step 4: MDR -> A (prepares memory module to read the actual data that will be copied into the accumulator [calculator])
Step 5: PC + 1 -> PC (CPU increments the program counter and the cycle is complete and ready to begin next instruction)
7.12) PC -> MAR MDR -> IR contents(IR[address1]) -> contents(IR[address2]) PC + 1 -> PC

CHAPTER 8
8.4) Pipelining, an assembly line technique, allows overlapping between the fetch-execute cycles of sequence of instructions which reduces the average time needed to complete an instruction. So, in the execution part of the fetch-execute cycle, pipelining speeds up the process by overlapping the instructions allowing a second instruction to begin executing before the first instruction is completed.
8.10) The use of cache memory has a profound effect on system performance. With its high speed and eliminating the use of the system bus, cache memory provides improvements in execution and process speeds of data and instructions as well as storing instructions, improving overall system speed. Caching is also useful in areas of system design as it is used to reduce the time necessary to access data from a disk.

CHAPTER 9
9.6) An interrupt vector is a method in which the address of the interrupting device is included as part of the interrupt which is a fast way of determining which device initiated the interrupt but requires additional hardware to implement.
9.10) Block-oriented devices, such as a hard disk, are used to store and load programs and data and are always transferred in blocks, not as individual bytes or words. They may operate at upwards of 100 megabytes per second and as storage devices, they must be capable of both input and output and also must be capable of transferring large amounts of data very quickly between the CPU and disk.
Devices, such as a keyboard and mouse, are character-based devices. Unlike block-oriented devices, character-based devices transfer data on a byte-by-byte basis so the data rate is obviously much slower. Since the use of a character-based device is dependent on the user, the data input is much slower than a block-oriented device where the CPU is more dependent. Since the keyboard and mouse are input devices, they may generate unexpected inputs that lead to slow data rates compared to its input and output block-oriented devices.

CHAPTER 10
10.3) a) The total capacity of this disk is 135168000000 bytes or 125.88 GB
b) The disk transfer rate is 171.8 MB/s.
c) The minimum latency time for this disk is 6.15 milliseconds and the maximum is 7.33 milliseconds. The average latency time for this disk is 6.67 milliseconds.
10.13) a) 640 x 480 x 3 = 9216000 pixels/s b) 1920 x 1080 x 60 = 124416000 pixels/s

CHAPTER 11
11.3) Bus interfaces, also known as expansion bus interfaces or bus bridges or bus controllers, expand the flexibility of the system bus architecture by converting the format of the bus signals from one bus to another so that different types of buses (PCI bus, ATA bus, etc.) can be used together. Using these different buses together allows the connection of different devices, such as disks or terminals, which makes it possible for the system-designer to optimize each I/O function to maximize the speed, flexibility, and overall system performance. Taking advantage of this opens up a wider market as the standardization of bus interfaces simplifies the purchase, setup, and proper operation of peripherals from multiple vendors.

CHAPTER 12
12.8) Due to the fact that the company has several buildings scattered around a town and are no more than a ¼ mile from one another, I would use a metropolitan area network (MAN). Since a MAN is generally used to connect several buildings in an area together within a range of 30 miles or less, it would be a perfectly suitable network for this company. Since a ¼ mile would be too large for strictly 1 LAN, it could be possible to implement a MAN almost entirely with a combination of LANs and one or more backbone networks, plus some easy-to-form of Internet access which eliminates the need of direct wire connections. One of the office buildings may be the one to host the Web service and through the use of switches and a point-to-point Metro Ethernet link connected to the main building, it could create a virtual network with all of the other buildings.

12.18) This is an important requirement for the operation of a router in a network because each is data being sent in the form of packets to various computers in the network which contain header information, destination, etc. and passes through layers. The physical addresses are associated with individual devices connected to a network and are needed by the data link and physical layers to identify which nodes they are connected which aid in devices being moved from one network to another and since IP addresses are converted to physical addresses, they can be assigned dynamically.

CHAPTER 13
13.9) Since IP addresses are usually divided into three levels, and in some cases 4 or more, the purpose of an IP address mask is to separate different parts of the address.
a) 222.44.66.88/24 Network Address: 222.44.66.0 Host Address: 222.44.66.88 Hosts: 254
b) 200.40.60.80/26 Network Address: 200.40.60.64 Host Address: 200.40.60.80 Hosts: 62
13.18) Using a satellite as a means of data communication (and to prevent a war) would be insecure as it is considered to be unguided. They can be received by any radio receiver tuned to the antenna so any means of security would be lost. Coaxial cables are also considered to be unguided as they carry an analog signal which can, again, be insecure due to the radio transmission and sine waves. For a guided communication, it limits to a specific path constrained to a cable of some sort so fiber optic would be more secure. Fiber optic cables are usually point-to-point because of the difficulty of tapping into one so it would be much more secure and since it carries digital signal, it is more immune to noise.