INTERRUPTS
• The difference between Hardware and Software Interrupts (eg. BIOS/DOS calls) is that an external device, not programmer, causes the hardware interrupt to occur. For eg. There is a keyboard interrupt which causes the PC to read a character typed. • Types of Interrupts and Priorities
– – – – – Reset (Highest Priority) Internal Interrupts and Exceptions Software Interrupts: SWI (INT #) NonMaskable Interrupts (NMI): External Hardware External (maskable) Hardware (Lowest Priority)

Interrupt Vectors
• All interrupts involve obtaining a vector (8 bit #) which is used by the MPU to fetch the address of the Interrupt Service Routine (ISR). • The address of the ISRs are in a table in memory beginning at 00h • Each entry (4B) in the table contains IP & CS of the corresponding ISR start address.

Interrupt Vector Table
Mem addr
Vector

Sys Services

70h*4

9*4 8*4

08 04 02 00

. . CS70h IP70h . . CS9 IP9 CS8 IP8 . . CS2 IP2 CS1 IP1 CS0 IP0

Vec 70h - CMOS Real Time Clock Vec 9 - PC Keyboard OR coprocessor seg overflow Vec 8 - PC Sys Timer OR interrupt table limit too small

Vec 2 - NMI Vec 1 - debug Vec 0 - divide error

Note: There is maximum of 256 vectors in Real Mode.

Hardware Requirements for Interrupts

RAM

ROM

INTR

INT

MPU INTA# reset NMI

Interrupt Controller IR7 IR0

io1 ...

io7

8259 Programmable Interrupt Controller (PIC)
• The 8259 PIC functions as overall mgr of an interrupt system environment. • Each PIC has up to 8 interrupt request (IR) inputs • Expandable up to 64 interrupt levels via cascading in a Primary Secondary environment. • Some Internal Registers are
– Interrupt Req. Reg (IRR): 8b reg storing 8 independent IRQs – In-Service Reg (SR): 8b reg storing interrupt levels which are being serviced – Interrupt Mask Reg (IMR): 8b reg storing interrupt levels to be masked. It operates on IRRs.

PIC Details
Interrupt Request to MPU Interrupt ACK from MPU Data Bus: interrupt vec, control, and status info sent on this bus Read Write Address: for selecting internal regs Chip Select Cascade: Output from Pri (goes to all Secs at same time); Input to Sec. Slave Prog/Enable Buffer INT INTA# D7-D0 RD# WR# A0 CS# CAS0 CAS1 CAS2 SP#/EN# IR0 IR1 Interrupt Requests . . .

8259 PIC

IR7

Programming the PIC
• Initialization Command Words (ICWs) – a series of initialization words in the order: ICW1, ICW2, [ICW3], [ICW4] • ICWs are identified as follows cs# A0 ICW 0 0 ICW1 0 1 ICW2, ICW3, ICW4 1 x PIC disabled • For eg. Master PIC in PC is at Port 20h. Thus addr of ICW1=20h; ICW2, …ICW3=21h

ICW1
• Indicates whether there’s more than one PIC and whether ICW4 is needed b7 0 b6 0 b5 0 b4 1 b3 ltim b2 0 b1 sngl bo icw4

• icw4=1==> ICW4 needed • sngl (single) = 1=> single 8259; =0 => multiple (cascade) • ltim (level timing) =1 => level input (IRi) to 8259; =0 => edge-triggered input. • B4=1 indicates ICW1

ICW2 (Interrupt Vector) b7 T7 b6 T6 b5 T5 b4 T4 b3 T3 b2 T2 b1 T1 bo T0

• • • • • •

T2 T1 T0 = 000 = Interrupt Vector for IR0. Interrupt Vectors for IR1, …, IR7 are derived automatically. For eg. That of IR7=111 Higher order bits (b7…b3)are fixed by programmer. In P/S mode, there is a separate ICW2 for Pri and Secondary using the same format. In current PCs IRQ0 (on Pri) is assigned vector= 08h, …irq7 vec=0fh Sec PIC's IRQs are irq8=ir0=70h, …, irq15=1R7=77h

ICW3 (Used in P/S Mode only)
• Separate ICW3 format for Pri and Sec. Master icw3 format follows b7 S7 • • b6 S6 b5 S5 b4 S4 b3 S3 b2 S2 b1 S1 bo S0

Si =1 => IRQi input has a secondary (slave) connected to it Secondary ICW3 format b7 0 b6 0 b5 0 b4 0 b3 0 b2 d2 b1 d1 bo d0

D2D1D0= ID# of Pri’s IR input Sec is connected to. =000 => slave ID =0, …, =111 => slave ID = 7.

PIC Configuration in typical PC
Vector in icw2 =08h IRQ0 IRQ1 IRQ3 IRQ7 . . Port A0h Vec 70h IRQ8 IRQ9 IRQ15 . . IR0 IR1 INT CAS0-2 Sec PIC INTA# IR7 Port 20h Vec 08h IR0 INT IR1 IR2 Pri PIC IR3 INTA# IR7 CAS0-2 SP#/EN# = Vcc=1 INTR MPU

LOGIC

SP#/EN# = 0

Examples
• In current PCs,
– edge triggered inputs – 2 cascaded PICs – ICW4 needed

• ICW1=00010001=11h mov al, 11h out 20h, al

• There is a single secondary connected to the Primary’s IR2 • Primary’s ICW3 = 00000100=04h • Secondary’s ICW3= 00000010=02h

ICW4 b7 T7 b6 T6 b5 T5 b4 b3 b2 MS b1 AEOI bo PM

SFNM BUF

1=Special Fully Nested Mode

0 X = nonbuffered 1 0 = buff mode sec 1 1 = buff mode pri

1=Auto EOI 0=Manual EOI Processor Mode: Must be = 1 for 386 and later

Note: There is a separate ICW4 for Pri and Sec using the same format

What is AutoEOI?

ICW4 (Buffered Mode and SFNM)
• BUF=1, Buffered Mode – Is used in large cascaded sys where data bus must be buffered and with a bi-directional bus – In this case BUF=1 means for PIC to send enable (EN#) signal on SP#/EN#. Thus EN#=L=0 whenever data is output from PIC to MPU – Because SP#/EN# is used as Pri/Sec selector in Non-buffered mode we have to find another way of specifying Pri/Sec in a buffered mode. • This is done in software by programming Bit2 • Bit2= MS = 0 for buffered mode Slave = 1 for Buffered Mode Master SFNM=1 is a SPECIAL FULLY NESTED MODE also used in cascaded systems. SFNM is enabled only for the Master and not Slaves. Details on this later.

•

Operation Command Words (OCWs)
• These words are sent to 8259 after ICWs have been sent. • OCWs do not have to be sent in sequence. • OCW Port Numbers
CS# A0 OCW 0 0 OCW2, OCW3 0 1 OCW1 Pri 20h 21h Sec a0h a1h

OCW1 (Setting Interrupt Mask)
• The bits go to the Interrupt Mask Register • The bits can also be Read to determine mask register contents. Thus it is a R/W reg. b7 M7 b6 M6 b5 M5 b4 M4 b3 M3 b2 M2 b1 M1 bo M0

Mi = 1 => Interrupt i is Masked. Ie. Not recognized by PIC

OCW2 (Assigns Specific Priority to IRQs and Used for Specifying EOIs)
Format Follows b7 R

: b5 EOI 0 b4 b3 0 b2 L2 b1 L1 bo L0

b6 SL

Rotation Specific Level End-Of-Interrupt

000 = Level 0 001 = Level 1 ... 111 = Level 7

OCW2 DETAILS
R 0 0 1 1 0 1 1 0 SL 0 1 0 0 0 1 1 1 EOI 1 1 1 0 0 1 0 0 Description Non specific EOI cmd *Specific EOI cmd Rotate on Nonspec EOI cmd Rotate in Auto EOI mode(set) Rotate in Auto EOI mode(clr) *Rotate on Specific EOI cmd *Set Priority cmd No Operation *: L2L1L0 are used

OCW3
• For reading Interrupt Request Reg (IRR) • For reading In-Service Register (ISReg) • For Issuing Poll Command • For Enable/Disable Special Mask Mode

OCW3 FORMAT b7 X b6 b5 b4 0 b3 1 b2 P b1 RR bo RIS

ESMM SMM

RST Special Mask = 10 Set Special Mask = 11 Poll/No Poll

0 x: No Action 1 0: Read IRR on nxt RD pulse 1 1: Read ISReg on nxt RD pulse

POLL WORD FORMAT b7 I b6 b4 0 b2 W2 b1 W1 bo W0

b5

b3 1

Interrupt Occurred

Code of Highest Priority Interrupt Req.

Note: Poll Word is issued by PIC in response to Poll from MPU via OCW3