LOSS COMPARISON OF TWO AND THREE-LEVEL
INVERTER TOPOLOGIES
G. I. Orfanoudakis*, S. M. Sharkh*, M. A. Yuratich† and M. A. Abusara*
* University of Southampton, UK, † TSL Technology, UK
G.I.Orfanoudakis@soton.ac.uk

Keywords: Inverter, DC-link capacitors, losses.

Abstract
This paper investigates semiconductor and DC-link capacitor losses in two two-level and two three-level voltage source inverters. The components of the four inverters are selected to have appropriate voltage and current ratings. Analytical expressions for semiconductor losses are reviewed and expressions for DC link capacitor losses are derived for all topologies. Three-level inverters are found to have lower semiconductor losses, but higher DC-link capacitor losses.
Overall, the three-level Neutral-Point-Clamped inverter proved to be the most efficient topology.

a.

1 Introduction
The process of selecting the topology, components and operating parameters (voltage, current and switching frequency) of an inverter is highly affected by the anticipated inverter losses. An accurate estimate of the losses occurring in each part of an inverter can significantly contribute to achieving an enhanced inverter design. This paper examines the semiconductor and DC-link capacitor losses of four voltage source inverter topologies: the conventional two-level inverter, the two-level two-channel interleaved inverter, the three-level Neutral-Point-Clamped (NPC) inverter and the three-level Cascaded H-Bridge inverter, shown in Figure 1.
Losses in two-level inverters have been reported extensively in the literature. Researchers have also investigated semiconductor losses in three-level inverters. Estimates of switching losses have been obtained using approximations of
IGBT and diode I-V switching characteristics [1, 4, 17, 18].
However, a more convenient approach based on calculating switching loss using the switching energy-current (Esw-I) characteristics, reveals that the switching losses of an IGBTdiode pair are approximately proportional to the switching voltage and current [12]. This observation can be verified based on IGBT-Diode module data sheets [8]. Analytical expressions for switching losses in a two-level inverter can be found in [7, 12]. For the two-level inverter, all continuous
PWM methods have the same switching losses, which are also independent of the load phase angle [9, 12].
Discontinuous strategies, however, can result in lower switching losses. Switching losses in a three-level NPC inverter have been investigated in [7], using a second order approximation of the IGBT and diode Esw-I characteristics.

b.

c.

d.
Figure 1: Circuit diagrams (one leg) of (a.) Two-level inverter, (b.) Two-channel two-level interleaved inverter, (c.)
Three-level NPC inverter and (d.) Three-level Cascaded HBridge inverter.

Expressions for the two-level inverter conduction losses can be found in [4, 12, 14]. The calculation of conduction losses is based on the linear I-V characteristics of the IGBT-diode modules. Unlike switching losses, two-level inverter conduction losses are affected by the selection of the PWM strategy and the load power factor. Expressions for the NPC inverter can be found in [7] as well as in [21] for a number of modulation strategies.
DC-link capacitor loss estimation is based on the rms value of the capacitor current. The derivation of the current rms expression for the two-level inverter has been presented in [8,
13, 19]. Capacitor loss estimations also appear for the twolevel two-channel interleaved and the three-level Cascaded HBridge inverters in [2] and [20], respectively. The DC-link of the three-level NPC inverter has only been studied in the literature with respect to its voltage and the capacitor balancing problem [5, 15, 16].
In this paper, expressions for switching and conduction losses in the four inverter topologies are reviewed. Analytical expression for DC-link capacitor losses are derived for the two-level interleaved and the three-level inverters. Unlike most studies that focus on a single inverter topology or loss type, the expressions for semiconductor and DC-link capacitor losses are used to compare the four examined topologies. Another significant contribution of the paper is that the comparison is based on a selection of inverter components from available commercial devices with appropriate voltage/current ratings and switching frequency.
This selection which is different for each topology, affects the resulting losses.

2 Selection of IGBT-Diode Modules
The four inverter topologies are compared on the basis of a common power output. Assuming a DC-link voltage Vdc of
2kV (1kV for the Cascaded H-Bridge inverter) and a nominal load peak current IM of 370A, the inverter power rating So is equal to 555kVA.
The switching voltage of the IGBT-diode modules in a threelevel inverter is half of that in a two-level inverter generating a voltage waveform with the same amplitude. The voltage rating of the IGBT-diode modules used in a three-level inverter therefore needs to be half that of an equivalent twolevel inverter. This difference in voltage rating has a very significant impact on switching and conduction loss parameters of the modules.
The current carried by each module is the same for all topologies except for the interleaved inverter in which each module carries half the current. The effect of the module current rating on switching loss parameters is insignificant, but conduction loss parameters are approximately doubled for the half current-rated modules.

Appropriate IGBT modules are selected for each topology.
The two-level inverter uses high-voltage high-current IGBTdiode modules (A), the interleaved inverter uses high-voltage low-current modules (B), while the three-level inverters uses the low-voltage high-current module (C). Table 1 lists the switching and conduction parameters of the selected modules.
Module A is the Eupec FZ800R33KL2C_B5 3.3kV – 800A
IGBT-diode module, Module B is the FZ400R33KL2C_B5
3.3kV – 400A IGBT-diode module, while Module C is the
FF800R17KE3 1.7kV – 800A module. Parameter values have been obtained from modules’ data sheets [8].
Parameter

Module
Module
Module
A
B
C
Vbase
1.8
1.8
0.9
V0,c
1.6
1.6
0.9
Rc
2.5
5
1.87
V0,d
1.7
1.7
1
Rd
1.25
2.5
1
ac
5.7
5.7
0.8
bc
50
50
40
ad
0.5
0.5
0.12
bd
150
150
60
Table 1: IGBT-Diode module parameters

Unit kV V mΩ V mΩ mJ/A mJ mJ/A mJ Parameters V0,c/d and Rc/d approximate the conduction I-V characteristics of IGBTs/diodes, respectively, according to:
(1)
V = V0,c / d + I ⋅ Rc / d
Parameters Vbase , ac/d and bc/d approximate the switching energy Esw-I characteristics according to:

E sw,c / d =

Vsw
(ac / d ⋅ I sw + bc / d )
Vbase

(2)

where Vsw and Isw are the instantaneous switching voltage and current, respectively.

3 Estimation of Inverter Semiconductor Losses
For a given switching frequency fs, the two-level inverter has the same switching losses for all continuous PWM methods.
Switching losses are also independent of the inverter modulation index M and the load power factor PF [12] but increase linearly with switching frequency. Conduction losses are not affected by fs but depend on the modulation strategy,
M and PF. For commonly used switching frequencies, conduction losses of the two-level inverter are significantly lower than corresponding switching losses.
The two-level two-channel interleaved inverter losses are examined under the assumption that the instantaneous current carried by each of the inverter channels is approximately half of the respective phase current. Leg (channel) inductors and sufficiently high switching frequencies are used to satisfy this requirement. Each module in this topology therefore carries half the current of a two-level inverter module. On the other hand, the number of modules in the interleaved inverter is twice that of the conventional two-level inverter.

Given that the expressions for switching and conduction losses in the conventional two-level inverter are (3) and (4), the expressions for the interleaved inverter losses can be proved to be (5) and (6), respectively. All equations refer to the three-phase inverters modulated by sinusoidal waveforms and their derivation is based on [12]. Parameters a and b represent the sums of ac, ad and bc, bd, respectively, of the module selected for each inverter.

Psw, 2 L = 6

Vdc  a b  IM +  fs
Vbase  π
2

(3)

2M
3
 2
Pcon , 2 L =  ( Rc + Rd ) +
( Rc − Rd ) cos φ  I M + π 4

(4)
3M
3

 π (Vc 0 + Vd 0 ) + 4 (Vc 0 − Vd 0 ) cos φ  I M


V a

(5)
Psw, 2 L − Int = 6 dc  I M + b  f s
Vbase  π

M
3
 2
Pcon , 2 L − Int =  ( Rc + Rd ) + ( Rc − Rd ) cos φ  I M + π 8

(6)
3M
3

 π (Vc 0 + Vd 0 ) + 4 (Vc 0 − Vd 0 ) cos φ  I M


The individual switching loss expressions for the three-level
NPC inverter modules given in [7], were revised assuming a linear dependence of the switching losses on the instantaneous current. Their summation yields Equation (7) for the total three-phase NPC inverter switching losses. The respective equation for conduction losses is (8). These expressions are applicable to any double carrier PWM methods with sinusoidal reference waveforms, such as threelevel PD and APOD/POD PWM, explained in [10].

Vdc  a b (7)
 IM +  fs
Vbase  π
2
4M
3
 2
( Rc − Rd ) cos φ  I M +
=  ( Rc + Rd ) +
2
π


(8)
3M
6

 π (Vc 0 + Vd 0 ) + 2 (Vc 0 − Vd 0 ) cos φ  I M



Psw,3 L = 3
Pcon ,3 L

Under the assumption of an equivalent modulation strategy as described in [10], the three-level Cascaded H-Bridge inverter can be shown to have the same semiconductor losses as the
NPC inverter. Equivalent strategies associate each IGBTdiode module of the NPC inverter to a module of the
Cascaded inverter. The losses on IGBTs are equal for respective modules, while losses on the NPC inverter’s clamping diodes are transferred to free-wheeling diodes of the
Cascaded inverter. The three-phase semiconductor losses for the Cascaded H-Bridge topology can also be calculated using
Equations (7) and (8).

4 DC-Link Capacitor RMS Current
In this paragraph, the method of [6], used for the derivation of the two-level inverter capacitor current rms expression, is applied to the three other inverter topologies. The method considers each inverter IGBT-diode module as a switch that, while on, carries the current of the respective phase. The sum of the currents through the upper switches of an inverter is id , as shown in Figure 1 for each of the four topologies. The DC component of this current is supplied by the inverter DC source, while the AC component is filtered, and hence carried by the DC-link capacitor. The rms value of the capacitor current, IC,rms, is calculated using the average (DC) and rms values of id, Id,,DC and Id,,rms, respectively:
2
2
2
2
2
I d ,rms = I d ,DC + I C ,rms ⇒ I C ,rms = I d ,rms − I d ,DC

(9)

According to [6], the calculation of current id average and rms values is based on the analysis of its transitions during a single switching period. If id is equal to id,int1 , id,int2 , ... during time intervals Tint1 , Tint2 , ... , respectively (with Tintk < Ts), then its average and rms value during a switching period Ts are given by Equations (10) and (11):


1
 ∑ Tint k ⋅ id ,int k  = ∑ δ int k ⋅ id ,int k
Ts  k
 k
1

2
2
2
id ,rms (θ ) =  ∑ Tint k ⋅ id ,int k  = ∑ δ int k ⋅ id ,int k
Ts  k
 k id , DC (θ ) =

(10)
(11)

The interval duty cycles δintk and respective currents id,intk are functions of θ, the angle of the voltage reference waveform for phase a. The average and rms values of id over a fundamental period are obtained using the following expressions: I d , DC

1
=
2π

I d ,rms =

2π

∫i

d , DC

(θ )dθ

(12)

0

1
2π

2π

∫i

2 d , rms

(θ )dθ

(13)

0

The expressions for δintk (θ) and id,intk (θ) may change during sectors of the fundamental cycle. In this case, the above expressions are written as sums of integrals for the different sectors. For example, for the derivation of the DC-link capacitor current rms expression of the two-level two-channel interleaved inverter, the fundamental cycle is divided into six sectors, each of which covers an angle of π/3. The inverter operation in these sectors is symmetric and hence only one sector needs to be analyzed. Sector I (0 – π/3) is divided into two sub-sectors, as described in Table 2. The table illustrates the duty cycles of the switching intervals and the corresponding values of current id as δintk → iintk . Angles θα, θb and θc, are equal to:

θ a = 0, θ b =

2π and
2π
θc = −
3
3

Sector I1
Sector I2
Duration (θ)
0 – π/6 π/6 – π/3
Ta / Ts δa δa
Tb / Ts δb δb
Tc / Ts δc δc
Interval 1
2(1-δc-δb) → -ib/2
2(1-δa-δb) → -ib/2
Interval 2
2(δc-δa) → (ic-ib)/2
2(δa-δc) → (ia-ib)/2
Interval 3
2(δa-1/2) → -ib
2(δc-1/2) → -ib
Table 2: Switching intervals for the two-level two-channel interleaved inverter
For two-level inverters:

δx =

1
(1 + M sin (θ + θ x ))
2

(14)

According to Table 2, for sector I1:

−i  id , DC , I 1, 2 L− Int (θ ) = 2 ⋅ (1 − δ c − δ b ) ⋅  b 
 2 
i −i 
+ 2 ⋅ (δ c − δ a ) ⋅  c b  + 2 ⋅ (δ a − 1 / 2 ) ⋅ (− ib )
 2 

(16)

(17)

Similarly, expressions can be derived for sector I2. The average (DC) and rms values of id are given by: π /6 π /3

3
 ∫ id , DC , I 1, 2 L− Int dθ + ∫ id , DC , I 2, 2 L− Int dθ  (18)

 π 0 π /6


3

π


π /6

∫
0

which result in:

I d , DC , 2 L− Int = MI M
I d ,rms , 2 L − Int = I M

π /3

2
2
id ,rms , I 1, 2 L − Int dθ + ∫ id ,rms , I 2, 2 L − Int dθ  (19)

π /6


π
4

cos(φ )

(20)


3M  3 − 1
3+2
+ cos 2 (φ ) (21)

6 π  24


The capacitor current rms expression for the two-level interleaved inverter will therefore be given by:

I C ,rms , 2 L − Int = I M


3M  3 − 1
3+2
+ cos 2 (φ )

6 π  24

−

π 2 M 2 cos 2 (φ )
16

(22)

(23)

According to Table 3, for sector I1:

id , DC , I 1, NPC (θ ) = δ c ⋅ (−ib ) + (δ a − δ c ) ⋅ ia
2
d , rms , I 1, NPC

(θ ) = δ c ⋅ (−ib ) + (δ a − δ c )⋅ i
2

2 a (24)
(25)

Similar expressions are derived for sectors I2 and I3. The DC and rms values of id for the NPC inverter are derived using equations similar to (18) and (19), which result in:

I d , DC , NPC =

2

i −i 
2
+ 2 ⋅ (δ c − δ a ) ⋅  c b  + 2 ⋅ (δ a − 1 / 2 ) ⋅ (− ib )
 2 

I d ,rms , 2 L − Int =

δ x = M sin (θ + θ x )

i

2

I d , DC , 2 L− Int =

Sector I1
Sector I2
Sector I3
Duration (θ) π/6 – π/3 π/3 – 2π/3 2π/3 – 5π/6
Ta / Ts δa δa δa Tb / Ts
0
0 δb Tc / Ts δc 0
0
Interval 1 δc → -ib δa → ia δb → -ic
Interval 2 δa-δc → ia δa-δb → ia
Table 3: Switching intervals for the three-level NPC inverter
For three-level inverters:

Assuming that the inverter load has a power factor cos(φ), the three-phase currents are given by:
(15)
i x = I M sin (θ + θ x − φ )

−i 
2
id ,rms , I 1, 2 L− Int (θ ) = 2 ⋅ (1 − δ c − δ b ) ⋅  b 
 2 

For the three-level NPC inverter, the three-phase voltage and current waveforms are divided into three sectors, covering an interval of 2π/3, each. Sector I is divided into three subsectors, as described in Table 3.

3
MI M cos φ
4

I d ,rms , NPC = I M

[

3M
1 + cos 2 (φ )
4π

(26)

]

(27)

Use of Equation (9) here gives the current rms expression for the upper capacitor of the three-level NPC inverter. Due to symmetry, the expression for the lower capacitor is identical:

I C ,rms , NPC = I M

M
2

 3 2 3 9  2 
+
− M  cos (φ ) (28)


8 
 2π  π





The derivation of the DC-link capacitor current rms for the three-phase Cascaded H-Bridge inverter is based on the analysis of a single H-Bridge, that of phase a. The current rms value of each capacitor in this topology is not affected by the switching operations of the other phases. The calculation of the capacitor rms current is based on the analysis of one out of two symmetrical sectors, covering an interval of π, each.
Duration (θ)
0–π
Τa / Ts δa Interval 1 δa → ia
Table 4: Switching intervals for phase a of the three-level
Cascaded H-Bridge inverter
According to Table 4:

id , DC ,Casc (θ ) = δ a ⋅ ia

2
2
id ,rms ,Casc (θ ) = δ a ⋅ ia

(29)
(30)

MI M cos(φ )
2
M (3 + cos(2φ ) )
= IM
3π

I d , DC ,Casc =

(31)

I d ,rms ,Casc

(32)

The capacitor current rms expression for this topology can be calculated using (9), (31) and (32) to be:

I C ,rms ,Casc = I M

M
[24 − 3Mπ + (8 − 3Mπ )cos(2φ )] (33)
24π

The DC-link capacitor current of a single-phase H-Bridge has been investigated in [20], deriving an expression for the rms value of high frequency capacitor current harmonics. This expression is equivalent to (33), which also incorporates the low-frequency harmonic of the Cascaded H-Bridge inverter
DC-link capacitor current. All the above derived capacitor current rms expressions were verified by inverter simulations in the SimPowerSystems toolbox of Matlab-Simulink.

5 Results
All inverters are assumed to supply a 3Ω impedance (Z) load with power factor equal to 0.9. Due to the increased switching losses of high-voltage IGBTs, however, two-level inverters are assumed to be switched at lower frequencies. The switching frequency fs is set to 1kHz for two-level and 2.5kHz for three-level inverters, respectively. Figure 2 plots the semiconductor losses against the inverter Modulation Index
M, according to Equations (3)-(8) and the values of Table 1.
An inspection of the plot indicates that the switching losses of the two-level inverters are significantly higher than that of the three-level inverters. Even though the switching frequencies of the two-level inverters are lower, three-level inverters exhibit a major advantage over switching losses, as a result of their decreased switching parameter values (ac/d and bc/d). The decreased number of output voltage levels and the lower switching frequencies also have a negative impact on the output harmonic performance of the two-level inverters, but this consideration is beyond the scope of this paper.
6000
2L Switching
3L Switching
2L Conduction
3L Conduction

Losses (W)

5000
4000

Interleaved

Conventional

2000
1000
0

0.2

0.4

0.6

0.8

M

Figure 2: Semiconductor losses vs M

The DC-link capacitors power losses are given by the following expression:
2
(34)
PC = N ⋅ RC ⋅ I C ,rms where N is the number of capacitors used in each topology and Rc represents the Equivalent Series Resistance (ESR) of each capacitor. As shown in Figure 1, N is equal to 2 for the two two-level and the three-level NPC inverters, and 3 for the
Cascaded H-Bridge inverter. Each capacitor (or capacitor bank) is assumed to have a nominal voltage of 1kV and an
ESR of 15mΩ.
1000
2L and 3L NPC
2L Interleaved
3L Cascaded

800
600
400
200
0

0

0.2

0.4

0.6

0.8

1

M

Figure 3: DC-link capacitor losses vs M
Figure 3 illustrates the variation of total DC-link capacitor losses with modulation index for the examined topologies. As shown in the figure, the two-level interleaved inverter has the lowest amount of DC-link capacitors losses. The capacitor losses in the conventional two-level inverter are higher and equal to the three-level NPC inverter losses. In fact, the expressions for the capacitor current rms values of these two topologies are identical. However, according to inverter simulations, their instantaneous capacitor currents and current spectra differ significantly. In contrast to the two-level inverter, the capacitor current of the three-level NPC inverter contains low-frequency harmonics. Low-frequency harmonics also appear in the capacitor current of the three-level
Cascaded H-Bridge inverter. This topology has the highest amount of capacitor losses, partially due to the fact that it uses three instead of two DC-link capacitors.
A fixed value of ESR was assumed for all DC-link capacitors.
In reality, the ESR of electrolytic capacitors that are commonly used for inverter DC-links, varies with the frequency of capacitor current harmonics. Its value for low frequencies, in the range of hundreds of Hz, is two to three times higher than it is for frequencies in the range of kHz.

3000

0

The conduction losses of the two two-level inverters are equal due to the values of conduction parameters Rc/d, which are half for the interleaved inverter modules (see Equations (4) and (6)). Conduction losses for three-level topologies are slightly higher.

Losses (W)

The average (DC) and rms values of current id for the
Cascaded H-Bridge inverter are calculated using Equations
(12) and (13), respectively, which result in:

1

Losses for the three-level inverters, whose capacitors carry low-frequency capacitor currents, will therefore be higher than predicted by (34). DC-link capacitor sizing for these topologies must consider this expected increment.
A final remark refers to the losses in two-level interleaved inverters. Results were presented assuming that all topologies supply the same current (with magnitude IM and phase φ) to the load, for the given DC-link voltages. However, the leg inductors of the interleaved inverter increase the apparent load inductance (by Lf /2), hence decreasing the load current and increasing the power angle φ. The inductance of the leg inductors was here assumed to be small compared to the load inductance. In practice, the DC-link voltage is increased to compensate for the inductor voltage drop.

[6]

[7]

[8]
[9]

[10]

6 Conclusion
The paper examined and compared the semiconductor and
DC-link capacitor losses of four inverter topologies. The semiconductor losses of the conventional and interleaved two-level inverters proved to be significantly higher than the respective losses of the NPC and Cascaded H-Bridge threelevel inverters. Switching losses that dominate in the twolevel inverters are increased even for low switching frequencies, due to the high-voltage IGBT-diode modules that these topologies use. The interleaved inverter has higher switching losses than the conventional two-level inverter.
Semiconductor losses for the three-level topologies are lower and equal for the NPC and Cascaded H-Bridge inverters, assuming an equivalence of their modulation strategies.
In terms of DC-link capacitor losses, the interleaved inverter can achieve better results than the conventional two-level inverter. Capacitor losses in the conventional two-level and three-level NPC inverters proved to be equal. The Cascaded
H-Bridge inverter, on the contrary, has significantly more capacitor losses than these two topologies. Lower DC-link capacitor losses of the two-level inverters cannot compensate for their increased semiconductor losses. Given the equality of three-level inverter semiconductor losses, the NPC inverter proved to be the most efficient between the four topologies.

[11]

[12]

[13]

[14]

[15]

[16]

[17]

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