TERM PAPER
NAND and NOR Flash Memory
-by
Shashank Chaudhay
2010EE10480

Abstract- This term paper is an introduction to the flash memory devices both NAND and NOR. This includes
- history of flash memory
- how it works
- NOR flash memory type
- NAND flash memory type
- differences between them
- limitations of flash memory
1. Introduction
Two main technologies dominate the non-volatile flash memory market today: NOR and NAND.
Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while working for Toshiba circa 1980. According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shōji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera. NOR flash was first introduced in market by Intel in 1988, revolutionizing a market that was then dominated by EPROM and EEPROM devices. NAND flash architecture was introduced in the market by Toshiba in 1989.Most hardware engineers are not familiar with the differences between these two technologies. In fact, they usually refer to NOR architecture as “flash”, unaware of NAND flash technology and its many benefits over NOR. This is mainly due to the fact that most flash devices are used to store and run code (usually small), for which NOR flash is the default choice.
Unlike Dynamic Random Access Memory (DRAM), Flash memory is non-volatile. Non-volatile memory retains data even without being powered-on. For example, when a computer is turned off all data that was in the computer’s DRAM memory is lost; however, when a Flash storage device is removed from a digital camera, all data (and pictures) remains saved on the Flash storage device. Flash memory is often used to hold control code such as the basic input/output system (BIOS) in a personal computer. When BIOS needs to be changed (rewritten), the flash memory can be written to in block (rather than byte) sizes, making it easy to update. On the other hand, flash memory is not useful as random access memory (RAM) because RAM needs to be addressable at the byte (not the block) level.
Flash memory gets its name because the microchip is organized so that a section of memory cells are erased in a single action or "flash." The erasure is caused by Fowler-Nordheim tunnelling in which electrons pierce through a thin dielectric material to remove an electronic charge from

a floating gate associated with each memory cell. Intel offers a form of flash memory that holds two bits (rather than one) in each memory cell, thus doubling the capacity of memory without a corresponding increase in price. Flash memory is used in digital cellular phones, digital cameras, LAN switches, PC Cards for notebook computers, digital set-up boxes, embedded controllers, and other devices.

Fig.1 A USB flash Drive (SanDisk Cruzer flash drive)

2. How It Works
The more common elementary flash cell consists of one transistor with a floating gate, similar to an EPROM cell. However, technology and geometry differences between flash devices and EPROMs exist. In particular, the gate oxide between the silicon and the floating gate is thinner for flash technology. Source and drain diffusions are also different. These differences allow the flash device to be programmed and erased electrically. Figures 2 and 3 shows a figurative difference between a flash memory cell and an EPROM cell from a same manufac-turer (AMD) with the same technol-ogy complexity.Fig. 4 shows a tabular comparison between a flash memory cell and an EPROM cell.
The cells look similar since the gate oxide thick-ness and the source/drain diffusion differences are not visible in the photographs. Fig. 2 EPROM MEMORY CELL

Fig.3 FLASH MEMORY CELL

Fig.4 FLASH CELL VS EPROM CELL

As with other semiconductors, the flash memory chip size is the major contributor to the cost of the device. For this reason, designers have developed alternative memory array architectures, yielding a trade-off between die size and speed. NOR, NAND, DINOR, and AND are the main architectures developed for flash memories.
Table 1 summarizes chip and cell sizes of some of the flash memories analyzed by ICE’s lab-oratory. Most of these are date coded 1994 but give a good idea of what is widely used in 1997.
All these memories use the NOR flash architecture.

Table 1. Flash Chip and Cell Size Comparison Floating gate transistor-
Flash memory stores information in an array of memory cells made from floating-gate transistors. In traditional single-level cell (SLC) devices, each cell stores only one bit of information. Some newer flash memory, known as multi-level cell (MLC) devices, can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells.The floating gate may be conductive (typically polysilicon in most kinds of flash memory) or non-conductive (as in SONOS flash memory).
In flash memory, each memory cell resembles a standard MOSFET, except the transistor has two gates instead of one. On top is the control gate (CG), as in other MOS transistors, but below this there is a floating gate (FG) insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, any electrons placed on it are trapped there and, under normal conditions, will not discharge for many years. When the FG holds a charge, it screens (partially cancels) the electric field from the CG, which modifies the threshold voltage (VT) of the cell. During read-out, a voltage intermediate between the possible threshold voltages is applied to the CG, and the MOSFET channel will become conducting or remain insulating, depending on the VT of the cell, which is in turn controlled by charge on the FG. The current flow through the MOSFET channel is sensed and forms a binary code, reproducing the stored data. In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.
Multiple floating input gate transistors
A Multiple-Input Floating Gate ( MIFG ) MOS Transistor is a floating gate transistor with mutiple control gate.
The sysytematic symbol and equivalent circuit are shown in the fig.6 (a) Systematic symbol (b) Equivalent Circuit Fig.6 The n input control gates are capacitively coupled to the floating gate. Let’s assume QFG is the net charge on the floating gate, VFG is the voltage of the floating gate, and Vgi is voltage of the ith control gate, thus where VFG=(QFG+CFGDVD+CFGSVS+CFGBVB+Σni=1CGiVGi)/ CTOTAL
Where

CTOTAL=CFGD+CFGS+CFGB+Σni=1CGi

Power supply Currently, flash power supplies range from 5V/12V down to 2V. Flash memory power supplies
Vary widely from vendor to vendor. There are two main reasons for this variation. First, flash
Cells need high voltage for programming. With different types of flash architectures and designs,
Different program/erase techniques (Fowler-Nordheim tunnelling or hot-electron injection) exist.
These architectures do not share the same voltage requirements. For example, high voltage with no current can be generated internally with a voltage pump. However the source/drain currentof hot-electron injection requires an external power supply.

3. NOR FLASH MEMORY

The NOR architecture is currently the most popular flash architecture. It is commonly used in EPROM and EEPROM designs. Aside from active transistors, the largest contributor to area in the cell array is the metal to diffusion contacts. NOR architecture requires one contact per two cells, which consumes the most area of all the flash architecture alternatives. Electron trapping in the floating gate is done by hot-electron injection. Electrons are removed by Fowler-Nordheim tunnelling. The world’s leading manufacturers of flash devices (Intel, AMD) use NOR cell configurations.
NOR Flash memory provides high-speed random-access capabilities, being able to read and write data in specific locations in the memory without having to access the memory in sequential mode. Unlike NAND Flash, NOR Flash allows the retrieval of data as small as a single byte. NOR Flash excels in applications where data is randomly retrieved or written. NOR is most often found built into cellular phones (to store the phone’s operating system) and PDAs and is also used in computers to store the BIOS program that runs to provide the start-up functionality.
To reduce cell area, the NAND configuration was developed. The NAND structure is considerably more compact. 4. NANDFLASH MEMORY NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors' VT) is the bit line pulled low. These groups are then connected via some additional transistors to a NOR-style bit line array.
To read, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.
Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistor below the size where they can be made reliably, to the size where further reductions would increase the number of faults faster than it would increase the total storage available.
NAND flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms the core of the removable USB storage devices known as USB flash drives, as well as most memory card formats and solid-state drives available today.
A drawback to the NAND configuration is that when a cell is read, the sense amplifier sees aweaker signal than that on a NOR configuration since several transistors are in series. The weak signal slows down the speed of the read circuitry, which can be overcome by operating in serial access mode. This memory will not be competitive for random access applications. 5. Comparison between NOR and NAND Gate Performance Wise Flash devices are divided into erase units, also called blocks. This division is necessary to reduce prices and overcome physical limitations. Writing information to a specific block, in any flash device, can only be performed if that block is empty / erased. In most cases, this means that an erase operation must precede a write operation. While in NAND devices an erase operation is straight forward, NOR does technology require all bytes in the block to be written with “zeros” before they can be erased. Since the size of erase blocks in NOR devices ranges from 64KByte to B128Kbytes (in NAND: 8KByte to 64KBytes), such a write/erase operation can take up to 4 seconds(!), In stark contrast, NAND performs the identical operation in 2msec maximum. The erase block size difference further increases the performance gap between NOR and NAND, as statistically more erase operations must be performed in NOR-based units per any given set of write operations (especially when updating small files).

Interface Difference NOR flash is very similar to a random access memory device (RAM). Is has enough address pins to map its entire media, allowing for easy access to each and every one of its bytes. NAND devices are interfaced serially via a rather complicated I/O interface, which may vary from one device to another or from vendor to vendor. The same eight pins convey control, address and data information. NAND is typically accessed in bursts of 512 bytes; i.e., 512 bytes can be read and written at a time (similar to hard drives). This makes NOR ideal for running code, while
NAND is best used as data storage device (hard drive/block device replacement). High-capacity NAND devices are now offer 2KByte pages in order to further improve cost and performance advantages
.
Ease Of Use Using a NOR-based flash is a straightforward process. Just connect it as you would connect other memory devices, and run your code directly from it (if you don’t mind the slow performance). Using NAND, on the other hand, is a tricky issue. NAND has an I/O interface and requires toggling the OLE, ALE, and CLE signals. Accessing one NAND from vendor A is not necessarily the same as accessing another NAND from vendor B. A driver MUST be written and used for performing any operation on a NAND device. Writing information to NAND is also tricky since you have to make sure you are not writing the information to a bad block. This means that virtual mapping MUST be implemented on NAND device at all times.

Software Difference Reading from NOR requires no driver.
Raw NAND has limited software support. TrueFFS is the flash management software chosen by all major vendors
TrueFFS supports NAND-based DiskOnChip, providing disk emulation and NAND flash management.

Reliability And Endurance NAND has more than 10 times the life span of NOR. All flash suffers from bit-flipping issues
NAND suffers more from bit-flipping and requires EDC/ECC.
NAND usually has some bad blocks randomly scattered throughout. NAND devices offer up to 10 times the life span of NOR devices. In fact, since the block size of a NAND device is usually about 8 times smaller than that of a NOR device, each NOR block will be erased relatively more times over a given period of time (especially significant when working with small files) than each NAND block, which further extends the gap in favour of NAND. In the Table. 7 the erase cycle limits of NOR and NAND are given

Table. 7 Erase cycle limits

Conclusion Use of NOR devices is widespread in the industry. They offer an easy memory interface and are suitable for code execution, making them ideal for devices that do not need data storage. Their architecture makes them a good alternative in the range of 1MB to 4MB. NOR offers good read performance but poor write and erase times, disqualifying it from being used as a data storage device. However, as today’s devices become more and more sophisticated, they are expected to offer more features, richer programs and store more information locally. This requires larger capacities, both for code and data storage, and considerably faster erase/write times. NAND offers all of this, plus better prices in capacities ranging from 8MB to512MB. However, most engineers are reluctant to use it due to its non-standard interface and complicated management.
Based on NAND architecture and combined with TrueFFS software, DiskOnChip offers all of NAND advantages without the hassle that goes with it. DiskOnChip includes a built-in
EDC/ECC mechanism (based on the Reed-Solomon algorithm) and a standard, memory-mapped SRAM interface. M-Systems TrueFFS software handles all of NAND’s shortcomings, featuring bad block handling, wear leveling, error correction, block device emulation and more. In addition, DiskOnChip offers an XIP boot block enabling it to function both as a boot device replacement (traditionally an EEPROM or a small NOR flash device), and as your system’s local storage device. This block can also be used to replace small serial EEPROMs or ROM.

6. Limitation of flash memory 1. One limitation of flash memory is that although it can be read or programmed a byte or a word at a time in a random access fashion, it can only be erased a "block" at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations, but cannot offer arbitrary random-access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over-written value's. For example, a nibble value may be erased to 1111, then written as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000. Essentially, erasure sets (all) bits, and programming can only clear bits. File systems designed for flash devices can make use of this capability to represent sector metadata. 2. Another limitation is that flash memory has a finite number of program-erase cycles (typically written as P/E cycles). Most commercially available flash products are guaranteed to withstand around 100,000 P/E cycles, before the wear begins to deteriorate the integrity of the storage. Micron Technology and Sun Microsystems announced an SLC NAND flash memory chip rated for 1,000,000 P/E cycles on December 17, 2008.
The guaranteed cycle count may apply only to block zero (as is the case with TSOP NAND devices), or to all blocks (as in NOR). This effect is partially offset in some chip firmware or file system drivers by counting the writes and dynamically remapping blocks in order to spread write operations between sectors; this technique is called wear leveling. Another approach is to perform write verification and remapping to spare sectors in case of write failure, a technique called Bad Block Management (BBM). For portable consumer devices, these wear out management techniques typically extend the life of the flash memory beyond the life of the device itself, and some data loss may be acceptable in these applications. For high reliability data storage, however, it is not advisable to use flash memory that would have to go through a large number of programming cycles. This limitation is meaningless for 'read-only' applications such as thin clients and routers, which are only programmed once or at most a few times during their lifetimes. 3. Another limitation is the method used to read NAND flash memory can cause other cells near the cell being read to change over time if the surrounding cells of the block are not rewritten. This is generally in the hundreds of thousands of reads without a rewrite of those cells. The error does not appear when reading the original cell, but rather shows up when finally reading one of the surrounding cells. If the flash controller does not track the total number of reads across the whole storage device and rewrite the surrounding data periodically as a precaution, a read disturb error will likely occur with data loss as a result.

7. References

1. Flash Memory Guide.pdf atkingston.com
2. The Inconvenient Truths of NAND Flash Memory
Jim Cooke (jcooke@micron.com)
Applications Engineering Director
Micron Technology, Inc.
3. NAND Flash Memory
MT29F2G08AABWP/MT29F2G16AABWP
MT29F4G08BABWP/MT29F4G16BABWP
MT29F8G08FABWP at micron.com
4. NAND vs. NOR Flash Memory
Technology Overview at Toshiba America electronics
5.FLASH MEMORY TECHNOLOGY pdf from internet source

6. Wiki page of Floating gate
7.Companion Website of the book
DIGITAL ELECTRONICS: PRINCIPLES, DEVICES AND APPLICATIONS
8.NAND versus NORBY MICHAEL SANTARINI • SENIOR EDITOR
9. Two Technologies Compared:NOR vs. NAND
White Paper
10. JULY 03
91-SR-012-04-8L, Rev 1.1
11. Floating Gate Techniques and Applications
12. Flash Memory with Nanoparticle Floating Gates
Sanjay Banerjee
Director, Microelectronics Research Centre
Cockrell Chair Professor of Electrical & Computer Engineering
University of Texas at Austin
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