3.5 Routing After placement of modules on to the chip, the routing determines the paths for wires on the chip layout to interconnect the pins on the design blocks or pads at the chip boundary. These paths must satisfy the DRC rules to ensure that the chip can be correctly manufactured. The main objective of routing step is to complete all the connections. If all the required connections are not completed then the chip would not function properly and may even get fail also. Routing should also satisfy other objectives like (1) reduce the wire-length between modules and
(2) ensure each net satisfy its required timing properties
Routing is basically a very complex process. To make it simpler, the routing process is divided in to two steps like global routing followed by detailed routing. In global routing the available routing region is divided into tiles and tile-to-tile paths. Then, in the detailed routing actual tracks and vias for nets are assigned. …show more content…
Figure 3.12b shows some global-routing paths. It first divides the routing region into tiles and then generates a temporary route for each connection by finding the tile-to-tile paths to connect corresponding pins and/or pads. Figure 3.12c shows a result of detailed routing, which defines the actual routing path.
3.6 Physical Verification After nano-routing, PnR tool should not give any DRC/LVS violations. However, the PnR tool deals only with abstract views which may not be able to generate DRC/LVS clean design. So, a specific physical verification tools are used for LVS and DRC checks. Some of these are Assura from Cadence, Hercules from Synopsys and Calibre from MentorGraphics.
The major checks are:
3.6.1