Table 5.3.1: External Interface of GPIO core
5.4 UART 16550 Core
The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities (the data format and transmission speeds (baud rate) are configurable) with a modem or other external devices using a serial cable and RS232 protocol. The UART core uses a shift register to convert between serial and parallel data. Using UART is advantageous as serial transmission of digital data through a single wire is less expensive than parallel transmission through multiple wires. The transmitting UART receives data from a controlling device like a CPU and transmits it in serial to the receiving UART, which then converts the serial data back into parallel data for the receiving …show more content…
Thus, it expects to find the program code at a specific address which usually points to a boot ROM. The first task of the bootloader is to map the RAM to predefined addresses. After RAM is mapped, the Stack Pointer is setup. This is the minimal setup required for the bootloader to start its work. Since it is the first software to run after power up or reset, it is highly processor and board specific. Also, the bootloader performs the necessary initializations to prepare the system for an operating system to boot.
5.8 SDRAM Controller Core
Dynamic memories are complicated to drive than static memories as rows, columns, banks and refresh cycles have to be taken care of. However, SDRAMs provide higher speed and lower cost per bit compared to their static counterparts. Therefore, we need an efficient way to access on-board SDRAM resources with ease. Thus, memory controllers are designed to serve as a translation layer, on one side, they provide end-users with an easy to use memory interface, and then do the dirty work to drive the real SDRAM signals. The figure 5.8.1 shows the state machine of an SDRAM