Premium Essay

Phase Lock Loop

In:

Submitted By sardar234
Words 336
Pages 2
STATISTICS I
EMGT 571

Assignment 1

Instructions: This assignment is designed to test your ability to work with SPSS and excel statistical software applications. Answer the following question using appropriate graphs and descriptive statistics generated from SPSS and/or excel.

The attached excel file (Social_Climbers.xls) contains data obtained from 274 couples regarding their education level, annual salary, the value of the cars that they own, the value of their homes, their total savings value (including stocks and bonds) and their social climber index (scale of 1-10, where 1 means very unconcerned about social status, 10 means very concerned). With this data and using SPSS and/or excel statistical functions, answer the following questions:

a) Generate box plots that illustrate education level versus salary, and social climber index versus salary. Briefly explain what you learn from these box plots with regards to salary vs. education level and salary vs. social climber index . b) Generate histograms and descriptive statistics for the following variables: salary, car value, home value and total savings. Be sure to identify median, mean, and standard deviation also identify any trends or abnormalities that are obvious. c) Generate histograms and descriptive statistics for the same variables in part b except segregate these by education level. (Essentially you will get 4 sets of descriptive statistics on salary, car value, home value and savings based on the four different education levels). Explain the difference in the variable means, median and mode, standard deviation between education levels. d) Based on the empirical data determine the following probabilities: i. Social climber index greater than or equal to 7 ii. Salaries less than or equal to $50K iii. Home values between $150K and

Similar Documents

Free Essay

Phase Locked Loop

...Xiao-Qiang GUO, Wei-Yang WU, He-Rong GU Yanshan University Phase locked loop and synchronization methods for gridinterfaced converters: a review Abstract. Phase locked loop and synchronization techniques are one of the most important issues for operating grid-interfaced converters in practical applications, which involve Distributed Power Generation Systems, Flexible AC Transmission Systems (FACTS), and High Voltage Direct Current (HVDC) Transmission, and so on. This paper presents a comprehensive review of the recently developed phase locked loop and synchronization methods, then a comparison and selection guide are provided. Finally, a list of more than 40 technical papers is also appended for a quick reference. Streszczenie. Techniki PLL i synchronizacji są ważnymi elementami przetworników w systemach sieciowych, takich jak: rozproszonych systemach mocy, FACTs czy HVDC. Artykuł przedstawia przegląd tego typu metod a następnie porównanie tych metod. Na końcu ponad 40 podstawowych artykułów z tej tematyki jest przedstawionych.(Metody synchronizacji i PLL w przetwornikach sieciowych – przegląd). Keywords: Grid-interfaced converters, phase locked loop, synchronization Słowa kluczowe: uchłady PLL, synchronizacja. Introduction The basic phase locked loop (PLL) concept was originally published by Appleton in 1923 and Bellescize in 1932, which was mainly used for synchronous reception of radio signals [1-2]. After that, PLL techniques were widely used in various industrial...

Words: 5211 - Pages: 21

Premium Essay

Dbms

...Notes on DBMS Internals Neil Conway neilc@samurai.com November 10, 2003 Preamble These notes were originally written for my own use while taking CISC-432, a course in DBMS design and implementation at Queen’s University. The textbook used by that class is Database Management Systems, 3rd Edition by Raghu Ramakrishnan and Johannes Gehkre; some of the material below may be specific to that text. This document is provided in the hope that it is useful, but I can’t provide any assurance that any information it contains is in any way accurate or complete. Corrections or additions are welcome. Distribution Terms: This document is released into the public domain. Query Evaluation External Sorting • A DBMS frequently needs to sort data (e.g. for a merge-join, ORDER BY, GROUP BY, etc.) that exceeds the amount of main memory available. In order to do this, an external sort algorithm is used. • 2-Way External Merge Sort: – In the first pass, each page of the input relation is read into memory, sorted, and written out to disk. This creates N runs of 1 page each. – In each successive pass, each run is read into memory and merged with another run, then written out to disk. Since the number of runs is halved with every pass, this requires log2 N passes. Since an additional initial pass is required and each pass requires 2N I/Os, the total cost is: 2N( log2 N + 1) – Thus, we can see that the number of passes we need to make is critical to the overall performance of the sort (since in...

Words: 12979 - Pages: 52

Free Essay

Single Loop vs Double Loop Learning

...Single loop learning is the most common type of learning and involves problem solving and improving the system but does not seek any answers as to why the problem arose. On the other hand Double loop learning uses feedback from past actions to restructure the set assumption patterns and seek alternative solutions. It is necessary for higher order problem solving and leadership. We see a series of such examples in our daily lives, which involve the use of single loop and double loop learning techniques. As a part of this study we will be analyzing the use of these learning techniques in the implementation of e-governance projects and try to overview whether the replacement of single loop learning with the double loop learning techniques in these mission mode projects yielded better outcomes and results. The study will try to hit the target by being very specific and studying the RajSWAN (Rajasthan State Wide Area Network) Project. The government’s aim behind the implementation of RajSWAN project was to establish an effective communication infrastructure and create a highway for electronic transfer of information in the form of voice, video and data between the various departments of the state machinery with an aim to improve the administrative efficiency and effectiveness of Government programmes and schemes thereby resulting in an improved quality of service to the citizen of this state. It also aims to strengthen the disaster management capacity. RajCOMP is a State designated...

Words: 1026 - Pages: 5

Premium Essay

Assignment

... A subquery can appear in many places in a SQL statement: • as part of a FROM clause, • to the right of a WHERE conditional expression, • to the right of the IN clause, • in a EXISTS operator, • to the right of a HAVING clause conditional operator, • in the attribute list of a SELECT clause. Examples of subqueries are: INSERT INTO PRODUCT SELECT * FROM P; DELETE FROM PRODUCT WHERE V_CODE IN (SELECT V_CODE FROM VENDOR WHERE V_AREACODE = ‘615’); SELECT V_CODE, V_NAME FROM VENDOR WHERE V_CODE NOT IN (SELECT V_CODE FROM PRODUCT); 2. What is a correlated subquery? Give an example. A correlated subquery is subquery that executes once for each row in the outer query. This process is similar to the typical nested loop in a programming language. Contrast this type of subquery to the typical subquery that will execute the innermost subquery first, and then the next outer query … until the last outer query is executed. That is, the typical subquery will execute in serial order, one after another, starting with the innermost subquery. In contrast, a correlated subquery will run the outer query first, and then it will run the inner subquery once for each row returned in the outer subquery. For example, the following subquery will list all the product line sales in which the “units sold” value is greater than the “average units...

Words: 1179 - Pages: 5

Premium Essay

Integrative Network Design

...Integrative Network Design NTC 362 Integrative Network Design This project will consist of five different phases totaling a timeline of six months. The first month will be the planning phase. This phase will have a deadline no longer than 30 days. After the first 30 days, the second phase will take into effect, which is the installation phase. This phase will also have a timeline of no more than 30 days. The Third Phase will be the longest phase of a timeline of 60 days. The third phase will be the testing phase. The testing phase is important because this is the troubleshooting phase. Troubleshooting is important to ensuring the new system is running up to optimal standards. The fourth phase will have a deadline of 30 days. The fourth phase is the Training Phase, and our trainers only need a month to convert the needed employees to the new system. The Fifth and Final Stage is our Final Evaluation/Lessons Learned Stage. At this point, the system is at full running operation, and for the last month the system will be ready for a full evaluation. Riordan Manufacturing is a fast growing business, and has grown into a large fortune 1000 company. As they grew into this large company they have been encountering problems with lost or misplaced material. As of now Riordan’s material is manually tracked by paper and pen by employees then entered into a database by an inventory clerk at the end of the day. This is causing them to misplace customer packages resulting in unhappy...

Words: 2910 - Pages: 12

Free Essay

My Paper

...1.5 user guide Table of Contents Chapter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Welcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Torq Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Decks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Main Waveform Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PFL/Headphone Cue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Browser/Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Effect Racks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Sampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Snapshots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Master Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Windows XP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Windows Vista . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Installation . . . . . . ...

Words: 33920 - Pages: 136

Free Essay

Modulation

...Chapter 5 Traditional Analog Modulation Techniques Mikael Olofsson — 2002–2007 Modulation techniques are mainly used to transmit information in a given frequency band. The reason for that may be that the channel is band-limited, or that we are assigned a certain frequency band and frequencies outside that band is supposed to be used by others. Therefore, we are interested in the spectral properties of various modulation techniques. The modulation techniques described here have a long history in radio applications. The information to be transmitted is normally an analog so called baseband signal. By that we understand a signal with the main part of its spectrum around zero. Especially, that means that the main part of the spectrum is below some frequency W , called the bandwidth of the signal. We also consider methods to demodulate the modulated signals, i.e. to regain the original signal from the modulated one. Noise added by the channel will necessarily affect the demodulated signal. We separate the analysis of those demodulation methods into one part where we assume an ideal channel that does not add any noise, and another part where we assume that the channel adds white Gaussian noise. 5.1 Amplitude Modulation Amplitude modulation, normally abbreviated AM, was the first modulation technique. The first radio broadcasts were done using this technique. The reason for that is that AM signals can be detected very easily. Essentially, all you need is a nonlinearity. Actually...

Words: 6411 - Pages: 26

Premium Essay

Deep'Z Studio.

...1 INTRODUCTION SQL is divided into the following  Data Definition Language (DDL)  Data Manipulation Language (DML)  Data Retrieval Language (DRL)  Transaction Control Language (TCL)  Data Control Language (DCL) DDL -- create, alter, drop, truncate, rename DML -- insert, update, delete DRL -- select TCL -- commit, rollback, savepoint DCL -- grant, revoke CREATE TABLE SYNTAX Create table (col1 datatype1, col2 datatype2 …coln datatypen); Ex: SQL> create table student (no number (2), name varchar (10), marks number (3)); INSERT This will be used to insert the records into table. We have two methods to insert.   a) By value method By address method USING VALUE METHOD Syntax: insert into (table_name) values (value1, value2, value3 …. Valuen); © Copy rights are reserved. 2 Ex: SQL> insert into student values (1, ’sudha’, 100); SQL> insert into student values (2, ’saketh’, 200); To insert a new record again you have to type entire insert command, if there are lot of records this will be difficult. This will be avoided by using address method. b) USING ADDRESS METHOD Syntax: insert into (table_name) values (&col1, &col2, &col3 …. &coln); This will prompt you for the values but for every insert you have to use forward slash. Ex: SQL> insert into student values (&no, '&name', &marks); Enter value for no: 1 Enter value for name: Jagan Enter value for marks: 300 old new ...

Words: 42387 - Pages: 170

Free Essay

A Survey of Checkpointing Strategies for Shared-Memory Hpc Applications

...A Survey of Checkpointing Strategies for Shared-Memory HPC Applications Ana Gainaru,Aparna Sasidharan,Jorge Mario Cara Carmona University of Illinois, Urbana-Champaign April 25, 2012 1 Introduction Fault tolerant protocols have always been a major research topic for the HPC community. Harnessing microprocessors to solve large computational problems has required the use of many microprocessors in a single system. Whereas today the large server machines in the business sector may have as many as 32 processors, large supercomputers can have thousands or tens of thousands of processors in a single machine. While this approach has proven itself to be highly effective in expanding the limits of computational capability, it has also brought to the foreground new challenges that did not arise in smaller systems. Fault tolerance is one such critical challenge.The problem of fault tolerance in modern systems arises from two important HPC trends. First is the rising frequency of faults in systems. Second is the increasing size and running times of applications running on these systems, making them more vulnerable to these faults. HPC systems are vulnerable to faults for three major reasons. First, whereas older machines were built from custommade,high-quality components, modern systems use commodity components that were designed and built for a less reliability-aware market. Second, as modern systems are made from more and more components, the probability of one of them failing...

Words: 7288 - Pages: 30

Free Essay

Dream Big

...vol. 1, 1 (2009), 11-20 Vernier’s Delay Line Time–to–Digital Converter G. S. Jovanovi´ , M. K. Stojˇ ev c c Abstract: This paper describes the architecture and performance of a high-resolution time–to– digital converter (TDC) based on a Vernier delay line. The TDC is used as a basic building block for time interval measurement in an ultrasonic liquid flowmeter. Operation of the TDC with 10ps LSB resolution and 1 ms input range has been simulated using library models for 1.2 µ m double–metal double–poly CMOS technology. The TDC operates at clock frequency of 200 MHz, and is composed of 500 delay–latch elements. The difference in delay between two chains, one for the start and the other for stop pulse, is controlled by the delay locked loop (DLL). Keywords: Time to digital conversion, Vernier delay line, DLL. 1 Introduction The precise measurement of the time interval between two events with very fine timing resolution is common challenge in the test and measurement instrumentation (logic analyzer, ATE system, nuclear instrumentation), industrial control (multichannel DAS, ultrasonic liquid flowmeters), electronic embedded control system (automotive controllers, medical devices avionics), etc. [1,2,3]. A time–to–digital converter (TDC) is one of the crucial building blocks installed into this type of equipment. High–resolution TDC is primarily used in application areas that require a resolution better than 10ps, low dead–time (minimum time between two measurement, less...

Words: 3304 - Pages: 14

Free Essay

Olympic 2012 Programme Baseline Report

...Learning legacy Lessons learned from the London 2012 Games construction project Programme Baseline Report Champion Products are examples of tools and formats used by the Olympic Delivery Authority (ODA) in executing its programme. The ODA is publishing these as part of its Learning Legacy in the anticipation that they may be of use to future projects seeking best practice examples of tools and templates that have been used successfully on a large, complex programme. Purpose of the document, description and how it was used The purpose of the Programme Baseline Report was to provide a comprehensive summary of the ODA’s Olympic Programme, detailing scope, programme, budget and risk against which performance could be measured both internally and externally. The scope defined in the report includes all works required regarding site platform and infrastructure, venues, transport, and legacy transformation. This document was used to present a comprehensive statement of the scope of works required and the necessary budget for delivery. Once the document was agreed at the commencement of the programme, delivery of the works was monitored against the baseline and change could be managed robustly. Olympic Delivery Authority Programme Baseline Report Summary November 2007 report The report was updated in 2009 reflecting the status of the programme two years after the original report and after substantial completion of the ODA’s Games-time...

Words: 37339 - Pages: 150

Free Essay

Accounting for Ngo in Bangladesh

...Installation, Operation and Maintenance Manual VLT® 6000 Series Adjustable Frequency Drive 12/01 Revision K 23-6108-00 Safety Guidelines ! DANGER 1. Rotating shafts and electrical equipment can be hazardous. Therefore, it is strongly recommended that all electrical work conform to National Electrical Code (NEC) and all local regulations. Installation, start-up and maintenance should be performed only by qualified personnel. Factory recommended procedures, included in this manual, should be followed. Always disconnect electrical power before working on the unit. 2. 3. 4. Warnings Against Unintended Start 1. Although shaft couplings or belt drives are generally not furnished by the manufacturer, rotating shafts, couplings and belts must be protected with securely mounted metal guards that are of sufficient thickness to provide protection against flying particles such as keys, bolts and coupling parts. Even when the motor is stopped, it should be considered “alive” as long as its controller is energized. Automatic circuits may start the motor at any time. Keep hands away from the output shaft until the motor has completely stopped and power is disconnected from the controller. Motor control equipment and electronic controls are connected to hazardous line voltages. When servicing drives and electronic controls, there will be exposed components at or above line potential. Extreme care should be taken to protect against shock. Stand on an insulating pad and make it a habit...

Words: 54111 - Pages: 217

Free Essay

Work

...This publication is available at Army Knowledge Online (www.us.army.mil) and General Dennis J. Reimer Training and Doctrine Digital Library at (http://www.train.army.mil). *TC 21-24 Training Circular No. TC 21-24 Headquarters Department of the Army Washington, DC, 9 January 2008 Rappelling Contents Page PREFACE..............................................................................................................vi Chapter 1 TOWER RAPPELLING ...................................................................................... 1-1 Section I - Personnel ........................................................................................ 1-1 Rappel Master .................................................................................................... 1-1 Rappel Safety Officer ......................................................................................... 1-2 Rappel Lane NCO .............................................................................................. 1-3 Rappeller ............................................................................................................ 1-3 Belayer................................................................................................................ 1-4 Belay Safety ....................................................................................................... 1-4 Section II - Preoperations Briefings and Safety Procedures ....................... 1-4 Safety......................

Words: 29104 - Pages: 117

Premium Essay

Analysis

...SEVENTH EDITION PROBLEM SOLVING AND PROGRAM DESIGN in C This page intentionally left blank SEVENTH EDITION PROBLEM SOLVING AND PROGRAM DESIGN in C Jeri R. Hanly, University of Wyoming Elliot B. Koffman, Temple University Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal Toronto Delhi Mexico City Sao Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo Editorial Director, ECS: Marcia Horton Editor-in-Chief: Michael Hirsch Senior Project Manager: Carole Snyder Director of Marketing: Patrice Jones Marketing Manager: Yezan Alayan Senior Marketing Coordinator: Kathryn Ferranti Director of Production: Vince O’Brien Managing Editor: Jeff Holcomb Associate Managing Editor: Robert Engelhardt Production Manager: Pat Brown Creative Director: Jayne Conte Designer: Suzanne Behnke Media Editor: Daniel Sandin Media Project Manager: John Cassar Cover Image: (c) michael Holcomb/Shutterstock.com Full-Service Project Management: Mohinder Singh/ Aptara®, Inc. Composition: Aptara®, Inc. Printer/Binder: Edwards Brothers Cover Printer: Lehigh-Phoenix Credits and acknowledgments borrowed from other sources and reproduced, with permission, in this textbook appear on appropriate page within text. Photo Credits: Page 4: Fig. 0.1: akg-images/Paul Almasy/Newscom. Page 11: Fig. 0.4: © 2008 IEEE/Journal of Microelectromechanical Systems (2006). Page 15:...

Words: 158087 - Pages: 633

Free Essay

Life, Death, and the Critical Transistion

...Life, Death, and the Critical Transition: Finding Liveness Bugs in Systems Code Charles Killian, James W. Anderson, Ranjit Jhala, and Amin Vahdat University of California San Diego {ckillian,jwanderson,jhala,vahdat}@cs.ucsd.edu Abstract finding bugs with model checking currently requires the programmer to have intimate knowledge of the low-level Modern software model checkers find safety violations: actions or conditions that could result in system failure. breaches where the system has entered some bad state. For We contend that for complex systems the desirable bemany environments however, particularly complex con- haviors of the system may be specified more easily than current and distributed systems, we argue that liveness identifying everything that could go wrong. Of course, properties are both more natural to specify and more im- specifying both desirable conditions and safety assertions portant to check. Liveness conditions specify desirable is valuable; however, current model checkers do not have system conditions in the limit, with the expectation that any mechanism for verifying whether desirable system they will be temporarily violated, perhaps as a result of properties can be achieved. Examples of such properties failure or during system initialization. include: i) a reliable transport eventually delivers all mesExisting software model checkers cannot verify live- sages even in the face of network losses and delays, ii) all ness because doing so...

Words: 19579 - Pages: 79