This sample chapter is for review purposes only. Copyright © The Goodheart-Willcox Co., Inc. All rights reserved.

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Chapter 7

7.1 Introduction
The majority of PLC manufacturers use the ladder logic diagram programming language to program their programmable logic controllers (PLCs). Some manufacturers prefer using logic gate circuits or Boolean expressions to program their PLCs. Therefore, it is beneficial to know how to convert one type of PLC programming language to the other. In this chapter, you will learn how to create logic gate circuits from ladder logic diagrams and vice versa. You will review the functions associated with the combinational logic gates. These gates are the NOT, AND, OR, NAND, NOR, XOR, and XNOR gates. You will learn how to create PLC ladder logic diagrams that emulate the functions of these gates.

Programming Logic Gate Functions in PLCs
Chapter Outline
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 Introduction Combinational and Sequential Logic Gate Circuits Boolean Expressions, Truth Tables, and Logic Gate Circuits NOT Gates or Inverters AND Gates OR Gates NAND Gates NOR Gates XOR (Exclusive OR) Gates XNOR (Exclusive NOR) Gates Simplifying Boolean Expressions Creating PLC Ladder Logic Diagrams from Logic Gate Circuits Creating PLC Ladder Logic Diagrams from Boolean Expressions Creating Logic Gate Circuits from PLC Ladder Logic Diagrams

Technical Terms combinational logic gates sequential logic devices Boolean expression Boolean algebra true state logic high false state logic low truth table gate symbols NOT gate AND gate OR gate NAND gate NOR gate XOR gate XNOR gate Karnaugh map Quine-McCluskey routine

Combinational logic gates: Logic devices in which the output of the device is dependent only on the present inputs to the device. There is no dependency on past inputs. Combinational logic gates do not require clock pulses to operate. Sequential logic devices: Logic devices in which the output of the device is dependent on the present and past inputs to the device. Sequential logic devices require clock pulses to operate.

7.2 Combinational and Sequential Logic Gate Circuits
Combinational logic gates do not require clock pulses to operate. Their outputs depend only on their inputs. This means that the outputs of combinational logic gates are generated instantaneously. Generally, the combinational logic gates are simply called logic gates. Seven logic gates exist. Seven logic gates exist: NOT, AND, OR, NAND, NOR, XOR (exclusive OR), and XNOR (exclusive NOR). The gates in a circuit represent a simple Boolean expression. For example, two-input AND gates with inputs A and B and output Y graphically represent the expression Y = A · B. Figure 7-1 displays a logic gate circuit which shows the connection of logic gates for a Boolean expression. Sequential logic devices have outputs that depend on their inputs as well as time. They require clock pulses. Therefore, an inherent delay time is always present for the sequential logic circuits. Flipflop devices such as reset-set (RS), JK, delay (D), and toggle (T) are sequential logic devices. Figure 7-2 displays a sequential logic circuit.

Learning Objectives
After completing this chapter, you will be able to: • Describe combinational and sequential logic gate circuits. • Create PLC ladder logic programs for NOT, AND, OR, NAND, NOR, XOR, and XNOR logic gates. • Create Boolean expressions and logic gate circuits from truth tables. • Use the Logic Converter instrument in NI Multisim to create logic tables and Boolean expressions from logic gate circuits. • Convert Boolean expressions to PLC ladder logic diagrams. • Convert PLC ladder logic diagrams to logic gate circuits and Boolean expressions.

A

AB′ AB′+A′B+C A′B

B

C Figure 7-1. A three-input logic gate circuit.
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1 kΩ/5 V +V 1 kΩ/5 V +V Clock pulses 0000 XXXX

J J 1 kΩ/5 V 1 kΩ/5 V +V J K Q +V Q JK flip-flop K Q′

Truth table: Table used to map Boolean expressions. Truth tables contain Boolean expression inputs and outputs. Gate symbols: Symbols used to display logic gate devices.

K Q′ JK flip-flop

Logic low is represented by the absence of a voltage potential. The logic high in a programmable logic controller is represented with five volts (+5 V), and the logic low is represented with zero volts (0 V). By applying conventional algebra, you can plot a function’s input and output points to create the characteristic of the function as a graph. This graph represents the function pictorially in an x–y coordinate system. The x-axis is for the input points and the y-axis is for the output points. In Boolean algebra, a table contains the digital input and output points. This table is called a truth table. Figure 7-3 displays a Boolean expression and its truth table. Note that a prime symbol (′) indicates the inverse value of the input. In Figure 7-3, the A with a prime represents the inverse of A. There are schematic symbols for every combinational and sequential logic device. The schematic symbols for logic gates are called gate symbols. Using logic gate symbols, one can create the logic gate circuits. Figure 7-4 displays the logic gate circuit for Boolean expression in Figure 7-3. In the following sections, you will learn what type of Boolean expressions, truth tables, and logic gate symbols are used for the seven logic gates introduced in Section 7.2.

Boolean expression: Y = AB + A′C Truth Table Figure 7-2. Sequential logic circuit. These circuits require clock pulses.
Boolean expression: Names for equations in Boolean algebra. Boolean algebra: Form of mathematics that uses two conditions or states: true and false. True state: State in digital electronics that is represented with a number 1. False state: State represented in digital electronics with a number zero. Logic high: State in digital electronics that is represented with 5 volts. Also called logic one. Logic low: State in digital electronics that is represented with zero volts. Also called logic zero.

In this textbook, you will study only combinational logic gate circuits. However, you first need to review the concepts of Boolean expressions, truth tables, and gate symbols.

7.3 Boolean Expressions, Truth Tables, and Logic Gate Circuits
In basic algebra, you learned that every function has its own equation. Similarly in the field of digital electronics, every gate logic function has its own equation called a Boolean expression. The nineteenth century British mathematician, George Boole, invented a type of algebra that uses only two conditions or states. The two states are true and false. This type of algebra using only two states is called Boolean algebra in honor of Boole. In Boolean algebra, the true state is represented by the number one, called logic high or logic one. The false state is represented by the number zero, called logic low or logic zero. In the field of digital electronics, logic high is represented by the presence of a voltage potential.

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 0 1 0 1 0 0 1 1

Figure 7-3. Boolean expression and its truth table.

A B AB Y A′C C Figure 7-4. Logic circuit for Boolean expression in Figure 7-3.

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7.4 NOT Gates or Inverters
The output of a NOT gate is the inverse of the input. The NOT gate is sometimes called an inverter. The function of a NOT gate is simulated by the electric circuit displayed in Figure 7-5. When the switch is closed, the electric bulb is short circuited, and it turns off. When the switch is open, electric current flows through the lightbulb, and the lightbulb turns on. Like the NOT gate, the output is on when the input is off and vice versa. The input is inverted to generate an output. Figure 7-6 displays the NOT logic gate symbol, its Boolean expression, and its truth table. Figure 7-7 displays that there are two different types of PLC ladder logic diagrams that perform the NOT function. • In rung 0000, the XIO (examine if open) device is connected to the output. Therefore, the XIO device is normally closed and output zero is ON. When you press pushbutton #1 (I:0/0), the output zero (pilot light #1) is turned off. (Notice that address I:0/0 references the port 0 on module 0.) • In rung 0001, pushbutton #2 (I:0/1) is connected to internal coil bit B3:0/0. (Notice that address I:0/1 references the port 1 on module 0.) In rung 0002, the internal contact bit B3:0/0 is inverted and connected to output one (pilot light #2). When normally open input I:0/1 is open, output one (O:0/1) is ON. Press input 0/1 to close it, then output one will turn OFF.
NOT gate: Gate that generates a logic high output when all inputs are logic low. Pushbutton #1 I:0 0000 0 Pushbutton #2 I:0 0001 1 Control relay B3:0 0002 0 0003

NOT or INVERTER Logic Gate Pilot light #1 O:0 0 Control relay B3:0 0 Pilot light #2 O:0 1 End

Figure 7-7. Two ways to program a NOT function in a PLC.

7.5 AND Gates
AND gate: Gate that only generates a logic high output when all inputs are logic high.

1 kΩ + − 5V 1 LT Switch is opened (SW = 0), Lamp is on (LT = 1)

0 Switch (SW)

Switch is closed (SW = 1), Lamp is off (LT = 0)

The function of an AND gate is simulated in the electric circuit displayed in Figure 7-8. Notice that the lamp will be on only when both switches are closed. Figure 7-9 displays a two-input AND logic gate symbol, its Boolean expression, and its truth table. In the truth table, you can see that there is only one set of inputs that produces a logic high output. Figure 7-10 displays a ladder logic diagram that performs the function of a two-input AND gate. When normally open inputs I:0/0 and I:0/1 are closed, output O:0/0 is energized.

7.6 OR Gates
Figure 7-5. Electric circuit emulating the function of a NOT gate.
OR gate: Gate that generates a logic high output in all states except when all inputs are logic low.

Boolean expression: Y = A′ A Y A 0 1 Y 1 0

NOT gate symbol

Truth table

The function of an OR gate is simulated in the electric circuit displayed in Figure 7-11. Notice that the lamp will be ON when one or both of the switches are closed. Figure 7-12 displays a two-input OR logic gate symbol, its Boolean expression, and its truth table. The truth table shows a logic high output for all combinations of inputs except where both A and B are low. When either input A, B, or both are on, the output is on. Figure 7-13 displays a ladder logic diagram that performs the function of a two-input OR gate. When either normally open (NO) inputs I:0/0, I:0/1, or both are closed, output O:0/0 is energized.

Figure 7-6. Boolean expression, gate symbol, and truth table for NOT logic gate.

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Switch A

0 1

0 1

Switch B

Switch A

0 1

Lamp on = 1 1 kΩ Lamp off = 0 1 kΩ Switch B

0 1 Lamp on = 1 Lamp off = 0

+

− 5V + 5V −

Figure 7-8. Electric circuit emulating an AND gate.

Figure 7-11. Electric circuit emulating an OR gate. Boolean expression: Y = A · B A B Y A 0 0 1 1 B 0 1 0 1 Truth table Two-input OR gate Y 0 0 0 1 Boolean expression: Y = A + B A B Y A 0 0 1 1 B 0 1 0 1 Truth table Y 0 1 1 1

Two-input AND gate

Figure 7-9. Boolean expression, gate symbol, and truth table for a two-input AND logic gate.

Figure 7-12. Boolean expression, gate symbol, and truth table for a two-input OR logic gate.

AND Logic Gate Pushbutton #1 Pushbutton #2 I:0 I:0 0000 0 1 0 0000 0 0001 End Pushbutton #2 I:0 1 0 Pilot light #1 O:0 Pushbutton #1 I:0 OR Logic Gate Pilot light #1 O:0

Figure 7-10. AND gate ladder logic diagram.
0001

End

Figure 7-13. Ladder logic diagram for an OR gate.

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7.7 NAND Gates
The function of a NAND gate is simulated in the electric circuit displayed in Figure 7-14. Notice that the lamp will be off when both switches are closed. The NAND gate takes its name from NOT and AND. Its outputs are the inverse of the AND gate. Figure 7-15 displays a two-input NAND logic gate symbol, its Boolean expression, and its truth table. Notice that the NAND gate can be built by connecting an AND gate in series with a NOT gate. Using the De-Morgan theorem, sometimes also called the Bubble method, you can convert a NAND gate to an OR gate with inverted inputs where (A · B) ′ = A′ + B′. Figure 7-16 displays that there are two different types of ladder logic diagrams that perform the NAND function. • Both normally closed inputs I:0/0 and I:0/1 must be energized (opened) to turn off the output O:0/0.
NAND gate: Gate that does not generate a logic high output when all inputs are logic low. An inverted AND.

•

When both normally open inputs I:0/2 and I:0/3 are energized (closed), the relay coil B3:0/0 is energized. Then the normally closed contact B3:0/0 is opened to turn off output O:0/1.

7.8 NOR Gates
NOR gate: Gate that generates a logic high output when all inputs are logic low. An inverted OR.

The function of a NOR logic gate is simulated in the electric circuit displayed in Figure 7-17. Notice that the lamp will be ON when both switches are open. The NOR gate takes its name from NOT and OR. Its outputs are the inverse of the OR gate.
NAND Logic Gate

Pushbutton #1 I:0 0000 0 Pushbutton #2 I:0

Pilot light #1 O:0 0

1 Switch A 1 kΩ 1 Switch B

0 Lamp on = 1 0 Lamp off = 0
0001 2

1 Creating NAND logic gate using AND and NOT logic gates. Control relay Pushbutton #3 Pushbutton #4 I:0 I:0 B3:0 3 0 Pilot light #2 O:0 1 End

+ 5V

−

Control relay B3:0 0002 0

Figure 7-14. Electric circuit emulating a NAND gate.

0003

Boolean expression: Y = A · B = A + B A B

Figure 7-16. Ladder logic diagram for a NAND gate.

Y =A·B

A B A·B

Y=A·B

A 0 0 1 1

B 0 1 0 1 Truth table

Y 1 1 1 0

Switch B 1 1 kΩ 0 1

Switch A 0

Lamp on = 1 Lamp off = 0

NAND gate Figure 7-15. Boolean expression, gate symbol, and truth table for a NAND logic gate.

+ 5V

−

Figure 7-17. Electric circuit emulating a NOR gate.

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Figure 7-18 displays a two-input NOR logic gate symbol, its Boolean expression, and its truth table. Notice the NOR gate can be built by connecting an OR gate in series with a NOT gate. Using the De-Morgan theorem, you can convert a NOR gate to an AND gate with inverted inputs where (A + B) ′ = A′ · B′. Figure 7-19 displays that there are two different types of ladder logic diagrams that perform the NOR gate function. • Both normally closed inputs I:0/0 and I:0/1 must be deenergized (remain closed) to turn on the output O:0/0.
Boolean expression: Y = A + B = A · B A B Y=A+B A 0 0 1 1 B 0 1 0 1 Truth table Y 1 0 0 0

•

When both normally open inputs I:0/2 and I:0/3 are de-energized, the relay coil B3:0/0 is de-energized. Then the normally closed contact B3:0/0 remains closed to turn on output O:0/1.

7.9 XOR (Exclusive OR) Gates
XOR gate: Gate that generates a logic high output when one input is logic high and the other input is logic low or vice versa.

A B A+B NOR gate

Y=A+B

The function of an XOR (exclusive OR) gate is simulated in the electric circuit displayed in Figure 7-20. Notice that the lamp will be on if one switch is open while the other switch is closed. Figure 7-21 displays an XOR logic gate symbol, its Boolean expression, and its truth table. Looking at the truth table, you can see that either inputs A or B (but not both) must be high to produce a high output. One input must be ON and the other one OFF in order to have the output ON. Figure 7-22 displays a ladder logic diagram that performs the function of an XOR gate. When I:0/0 is on, I:0/1 must be off and vice versa in order to turn on output O:0/0. When either Pushbutton #1 or Pushbutton #2 is pressed, the output is ON. When both pushbuttons are pressed, output is OFF.
Switch A Switch B

Figure 7-18. Boolean expression, gate symbol, and truth table for a NOR logic gate.
NOR Logic Gate Pushbutton #1 I:0 0000 0 1 0 Pushbutton #2 I:0 Pilot light #1 O:0

Lamp on = 1 1 kΩ Lamp off = 0
Creating NOR logic gate using OR and NOT logic gates. Control relay Pushbutton #3 I:0 B3:0

0001 2 Pushbutton #4 I:0 3 Control relay B3:0 0002 0 1 Pilot light #2 O:0 0

+ 5V

−

Figure 7-20. Electric circuit emulating an XOR gate. Boolean expression: Y = A + B = A · B + A · B A B Y A 0 0 1 1 B 0 1 0 1 Y 0 1 1 0

XOR gate
0003 End

Figure 7-19. Ladder logic diagram for a NOR gate.

Figure 7-21. Boolean expression, gate symbol, and truth table for an XOR logic gate.

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XOR Logic Gate Pushbutton #1 I:0 0000 0 Pushbutton #1 I:0 0 1 Pushbutton #2 I:0 1 0 Pushbutton #2 I:0 Pilot light #1 O:0

Boolean expression: Y = A + B = A · B + A · B A B Y A 0 0 1 1 B 0 1 0 1 Y 1 0 0 1

A B XNOR gate
End

0001

Figure 7-24. Boolean expression, gate symbol, and truth table for an XNOR logic gate.

Figure 7-22. Ladder logic diagram for an XOR gate.

7.10 XNOR (Exclusive NOR) Gates
The function of an XNOR (exclusive NOR) gate is simulated in the electric circuit displayed in Figure 7-23. Notice that the lamp will be on when either both switches are open or closed. The lamp will not be on if only switch A is activated, or if only switch B is activated. Figure 7-24 displays an XNOR logic gate symbol, its Boolean expression, and its truth table. Notice the XNOR gate can be built by connecting an XOR gate in series with the NOT gate. When either or both pushbuttons are pressed or not pressed, the output is ON.
XNOR gate: Gate that generates a logic high output when either both inputs are logic high or both inputs are logic low.

Figure 7-25 displays that there are two different types of ladder logic diagrams that perform the XNOR function. • Both inputs I:0/0 and I:0/1 must be on or off to turn on the output O:0/0. • When I:0/2 is on and input I:0/3 is off or vice versa (i.e., XOR gate), the relay coil B3:0/0 is energized. Then the normally closed contact B3:0/0 opens to turn off output O:0/1.

7.11 Simplifying Boolean Expressions
In previous sections, the use of Boolean expressions, truth tables, and logic gate circuits were studied. You saw how logic gates were converted to PLC ladder logic diagrams. In this and the next two sections, you will study how to create PLC ladder logic diagrams from truth tables. To convert a truth table to a PLC ladder logic diagram, you must first find its simplified Boolean expression. The next step is to use the gate logic to PLC ladder diagram conversion routine to create the PLC ladder logic diagram. Three methods are used to simplify Boolean expressions. • Karnaugh maps. • Quine-McCluskey routine. • Electronic simulation software.

Switch A

Switch B

Lamp on = 1 1 kΩ Lamp off = 0

Karnaugh Maps
+ 5V −
Karnaugh map: A tool that can be used to simplify Boolean expressions. This is an older, difficult method for Boolean expression simplification.

Figure 7-23. Electric circuit emulating an XNOR gate.

Karnaugh maps (K-Map) are graphical representations of truth tables. They use columns and rows to represent each term in a truth table. For an n-variable input truth table, there are 2n boxes in a Karnaugh map. For example, for a two-input truth table, four boxes (22) are needed. A K-Map has a box for every line in the truth table. Binary numbers are placed above each column and to the left of each row. Figure 7-26 shows how binary numbers related to the input values are placed in a two-input, three-input, and four-input K-Map.

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XNOR Logic Gate Pushbutton #1 I:0 0000 0 Pushbutton #1 I:0 0 1 Pushbutton #2 I:0 1 0 Pushbutton #2 I:0 Pilot light #1 O:0

Two-Input Karnaugh Map A 0 0 1 1 B 0 1 0 1 Y B 0 A 0 1

1

Creating XNOR logic gate using XOR and NOT logic gates. Control relay Pushbutton #1 Pushbutton #2 I:0 B3:0 I:0 0001 0 Pushbutton #1 I:0 0 Control relay B3:0 0002 0 1 1 Pushbutton #2 I:0 1 Pilot light #2 O:0 0

Three-Input Karnaugh Map A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y C 0 AB 00 01 11 10

1

Four-Input Karnaugh Map A 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 C 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 Y AB CD 00 00 01 11 10

0003

End

Figure 7-25. Ladder logic diagram for an XNOR gate.

01

Notice that the input values are placed so that the values for adjacent columns and rows change only a single bit. For example, for a threeinput K-Map, binary numbers related to inputs A and B are placed above the columns in the order 00, 01, 11, and 10. Binary numbers related to input C are placed to the left of the rows in the order 0 and 1. This ordering follows the Gray code system explained in Chapter 3. To use the K-Map, the expression must be in a sum of products (SOP) form, such as AB′ + BC. This means that the Boolean expression consists of groups that are created from ANDed inputs. Then, the groups are summed (ORed) to create the entire Boolean expression. Use the following steps and refer to Figure 7-27 to simplify the Boolean expressions using K-Maps. 1. Select an appropriate K-Map that has the correct number of input boxes, such as two-input and three-input. As stated, for an n-variable input truth table, there will be 2n boxes. Therefore, for a two-variable (A and B) input table, there will be 22 boxes, or 4 boxes.

11

10

Figure 7-26. Two-input, three-input, and four-input K-Maps.

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A B 0 1 0 0 1 1 Correct A B 0 1 0 1 0 1 1 0 Correct A B 0 1 0 1 1 1 1 1 Correct A 0 0 1 0 1 Group of 4 C 0 1 AB 00 1 0 C Group of 2 0 1 AB 00 0 0 1 B

A 0 0 1 0 1 Incorrect 01 1 0 11 1 0 10 1 0 Group of 3 1

A

Incorrect 01 1 0 11 1 0 10 1 1 Group of 5

B
Incorrect A 1 1 1 Correct AB C 0 1 00 1 0 01 1 0 Correct AB C Leftmost cell 0 1 00 1 1 Top cell 01 1 11 1 1 10 1 1 Rightmost cell 11 1 1 10 1 1 AB C 0 1 00 1 0 B 0 1 0 0 1 1 1 1 B

2. Plot only the terms in which Y = 1. 3. Follow the rules below for grouping the 1s in the K-Map that lead to simplifying the expression. • Adjacent groups with binary number 1 in them must be combined in groups of 1, 2, 4, 8, 16, and so on. See Figure 7-27A. • Each group must contain an even number of binary 1s. See Figure 7-27B. • Every 1 in adjacent cells must be included in a group. See Figure 7-27C. • The same 1 can be used in two or more overlapping groups. See Figure 7-27C. • Each group should be as large as possible. See Figure 7-27D. • The map can be considered closed, so that the end boxes are grouped adjacently (top and bottom, or left and right). Figure 7-27E shows how groups wrap around the K-Map. 4. Write the Boolean expressions for each group, and then simplify the expression by retaining only the common variables. See Figure 7-28. 5. Then, sum the common variables from each group to create the simplified sum of product (SOP) Boolean expression. See Figure 7-28.

C
Incorrect 01 1 0 11 1 1 10 1 1

D
Incorrect

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 0 0 1 0 1 0 1 1

AB C 0 1

Group 1 00 01 1 11 1 1 Group 3 10 1 Group 2

Boolean expression for each group: Group 1 = A′ B C′ + A B C′ Common variables = BC′ Group 2 = A B C′ + A B′ C′ Common variables = AC′ Group 3 = A B C′ + A B C Common variables = AB Simplified SOP Boolean expression: Y = BC′ + AC′ + AB

E
Bottom cell

Figure 7-27. Simplifying Boolean expressions using K-Maps. A—Grouping pairs of binary 1s in adjacent cells. B—Grouping even number of 1s in adjacent cells. C—Grouping 1s in the adjacent cells. D—Groups must be as large as possible. E—Groups can wrap around the K-Map.

Figure 7-28. Simplified sum of product (SOP) Boolean Expression.

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Example 7-1
The example displayed in Figure 7-29 illustrates how to use a Karnaugh map to find the simplified SOP Boolean expression. Examine the steps used to simplify. 1. There are three inputs: A, B, and C. Therefore, select a threeinput Karnaugh map. Note that the map will have 23 (8) boxes. 2. Plot only the terms in which Y = 1. 3. Group the adjacent logic highs (1s). Remember, each group should be as large as possible. For this Karnaugh map, there is only one group. 4. Then, write the expression for the group and then simplify the expression by retaining the common variable(s). The simplified SOP Boolean expression is Y = C.

Electronic Circuit Simulation
Using electronic circuit simulation software to find the simplified Boolean expression is the easiest method. This type of software allows you to enter the input and output data and solves and simplifies the expression for you. An example of this type of software is NI Multisim. In Example 7-2, you will learn how to use NI Multisim to find the simplified Boolean expression of a truth table. If you have access to this software, work through the following example.

Example 7-2
Open the NI Multisim program. From the Instruments toolbar, click the Logic Converter icon. Then, click a space in the work area to place the converter. Double-click the Logic Converter image to open the Logic Converter dialog box. Figure 7-30 displays the Logic Converter instrument and dialog box. Click the inputs A, B, C, and D since your example truth table has those four inputs. Next, click the output column and type the output bits for the truth table displayed in Figure 7-31 (column Y). Click the Simplify button to find the simplified Boolean expression: A′CD + B′CD + BC′D + ABCD′ The answer appears in the rectangle at the bottom of Figure 7-30. The simplified Boolean expression consists of the sum of four product

Quine-McCluskey Routine
For more than five inputs, the Karnaugh map method becomes very difficult. Therefore, for more than five input variables, the Quine-McCluskey routine is a better method for simplifying Boolean expressions. The Quine-McCluskey routine is a complicated method that uses the Boolean algebraic simplification rules to find the simplified Boolean expression. We will not study the theory of the QuineMcCluskey method in this textbook, but you should know that this method exists and might be used in an advanced course.
Quine-McCluskey routine: Tool used as an advanced Boolean expression simplification routine.

Truth Table: Example 7-1 A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 0 1 0 1 0 1 0 1 AB C 0 Group 1 1 1 1 1 1

00

01

11

10

Boolean expression for each group: Group 1 = A′ B′ C + A′ B C + A B C + A B′ C Common variable(s) = C Simplified SOP Boolean expression: Y=C

Figure 7-29. Using a Karnaugh map to find a simplified Boolean expression for Example 7-1.

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Y 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0

Figure 7-30. Truth table for Example 7-2.

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expressions. Therefore, four rungs must be connected in parallel. Each rung has series input devices on it. Figure 7-32 displays the PLC ladder logic diagram created from the simplified Boolean expression.

7.12 Creating PLC Ladder Logic Diagrams from Logic Gate Circuits
In previous sections, you learned how to create PLC ladder logic diagrams for the logic gates. To create the ladder logic diagram from a logic gate circuit, you must convert each gate to its equivalent ladder logic diagram. Note that these simple conversions were discussed in sections 7.4 through 7.10. In this section, three examples are used to illustrate how to create PLC ladder logic diagrams for logic gate circuits. Study the procedures used in the following examples.

Logic converter instrument Select A-D Output column

Example 7-3
Create the PLC ladder logic diagram for the logic gate circuit displayed in Figure 7-33. Examine Figure 7-33. The pilot light red (PLTR) output section has three inputs: PBR, PBG, and SW. Pushbutton red (PBR) and pushbutton green (PBG) are inputs to an XOR logic gate. The output of the XOR logic gate and the inverted switch (SW) are inputs to a twoinput AND logic gate. These inputs generate the pilot light red (PLTR) output. The two-input AND logic gate output is also fed into a two-input NAND logic gate. The temperature switch (TSW) is another input to the NAND logic gate. The output generated from the NAND logic gate is labeled pilot light white (PLTW). Using the transformations described in Section 7.7 (on NAND gates) and Section 7.9 (on XOR gates), you can generate a PLC ladder logic diagram. Figure 7-34 displays the PLC ladder logic diagram for Example 7-3.

Simplify button

Simplified Boolean expression Figure 7-31. Using the Logic Converter instrument to find the simplified Boolean expression for Example 7-2.

Example 7-2 A’CD + B’CD + BC’D + ABC D’ = Y
A I:0 0000 0 B I:0 1 B I:0 1 A I:0 0 0001 2 C I:0 2 C I:0 2 B I:0 1 3 D I:0 3 D I:0 3 C I:0 2 D I:0 C I:0 D I:0

A’CD

O:0 0

PBR PBG PLTR

B’CD

SW BC’D

PLTW TSW Figure 7-33. Logic gate circuit for Example 7-3.
3

ABCD’
End

Figure 7-32. PLC ladder logic diagram for Example 7-2.

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Example 7-3 PBR XOR PBG NOT AND PLTR (AND output)

Using the transformations from Section 7.5 (AND gates) and Section 7.6 (OR gates) you can create the PLC ladder logic diagram. Figure 7-36 displays the PLC ladder logic diagram for Example 7-4.

SW

PBR PBG

NAND TSW

PLTW (NAND output) SW

XOR output is ANDed with the inverted SW to generate PLTR output. PBR I:0 0000 0 PBR I:0 0 1 PBG I:0 2 0 PBG I:0 SW I:0 PLTR O:0

PLTR TSW Figure 7-35. Logic gate circuit for Example 7-4.

NOT

AND output Example 7-4 PBR
PLTW O:0 1

XOR AND

1

PLTR output is NANDed with TSW to generate PLTW output. PLTR O:0 0001 0 TSW I:0 3 0002

AND

PBG OR

NAND output

SW AND NOT TSW PLTR

NAND

End PBR I:0 0000 0 SW I:0 2 PBG I:0 1 TSW I:0 3 PLTR O:0 0

Figure 7-34. PLC ladder logic diagram for Example 7-3.

Example 7-4
Create the PLC ladder logic diagram for the logic gate circuit displayed in Figure 7-35. Pushbutton red (PBR) and pushbutton green (PBG) are inputs to a two-input AND gate. The output of the AND logic gate and the switch (SW) are inputs to a two-input OR logic gate. The output of the OR logic gate and an inverted temperature switch (TSW) are inputs to a second AND logic gate. This AND logic gate generates the output for pilot light red (PLTR).

AND

NOT

OR AND
End

0001

Figure 7-36. PLC ladder logic diagram for Example 7-4.

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Example 7-5
Create the PLC ladder logic diagram for the logic gate circuit displayed in Figure 7-37. Inputs A and B are fed into an XNOR logic gate. Inputs D and E are fed into a NOR logic gate. Outputs of the XNOR and NOR logic gates plus input C are fed into a three-input OR logic gate. The threeinput OR logic gate generates output Y. Figure 7-38 displays the PLC ladder logic diagram for Example 7-5.
A I:0 0000 0 A I:0 0 1 B I:0 1 B I:0

Example 7-5
Y O:0 0

7.13 Creating PLC Ladder Logic Diagrams from Boolean Expressions
Some manufacturers use Boolean expressions to program their PLCs. In this section, you will learn how to use Boolean expressions to create PLC ladder logic diagrams. Work through the following three examples that illustrate how to create ladder logic diagrams for Boolean expressions.
0001 D I:0 3

C I:0 2 E I:0 4 End

Example 7-6
Create the PLC ladder logic diagram for the following Boolean expression. Y = A′ + B + CD + EB To create the diagram, each rung or each portion of a rung is created by replacing the Boolean letter with the inputs that match. Figure 7-39 summarizes the Boolean expressions and ladder diagrams for the logic gates covered in Sections 7-4 through 7-10.
Figure 7-38. PLC ladder logic diagram for Example 7-5.

Figure 7-40 displays the PLC ladder logic diagram. Notice that inverted A, B, CD, and EB inputs are in parallel (OR). Inputs C and D are in series (AND). Inputs E and B are also in series (AND).

Example 7-7
A B C D E Figure 7-37. Logic gate circuit for Example 7-5. Y

Create the PLC ladder logic diagram for the following Boolean expression. Y = (AB)′ + AC + BC Figure 7-41 displays the PLC ladder logic diagram. Notice that inverted A and B inputs are in series to generate output at the control relay. Then, the inverted output of AB is in parallel with AC and BC.

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OR Gate: Y = A + B 000 I:1/0 A I:1/1 B NOR Gate: Y = A + B I:1/0 A I:1/1 B B3:0/0 002 A or B is Inverted AND Gate: Y = A · B I:1/1 I:1/0 A 004 B Y 4 O:2/2 Y 0001 1 O:2/1 O:2/0 Y 0000 0 B I:0 B3:0/0 1 A or B is Inverted C I:0 2 E I:0 D I:0 3 B I:0 A I:0

Example 7-6 A’ + B Y = A’ + B + C · D + E · B
Y O:0 0

001

C·D

E·B

003

End

Figure 7-40. PLC ladder logic diagram for Example 7-6.

NAND Gate: Y = A · B I:1/1 I:1/0 A B3:0/1 B

B3:0/1

Example 7-7
A and B are Inverted O:2/3 0000 A and B are Inverted XOR Gate: Y = A · B + A · B I:1/1 I:1/0 A I:1/0 A B I:1/1 B 0 O:2/5 Y 1 0002 A B 2 End B I:0 A I:1/0 B I:1/1 2 C I:0 Y 0 1 0 Y A I:0 B I:0 Control relay B3:0

005

006

O:2/4 0001 Y

Control relay B3:0 0 A I:0

(A · B)’

Y = (A · B)’ + (A · C) + (B · C)

O:0 0

C I:0

A·C

007

XNOR Gate: Y = A · B + A · B I:1/1 I:1/0

B·C

Figure 7-39. Boolean expression and ladder diagram summary.

Figure 7-41. PLC ladder logic diagram for Example 7-7.

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Example 7-8
Create the PLC ladder logic diagram for the following Boolean expression. Y = (A + B) · (C + D) Figure 7-42 displays the PLC ladder logic diagram. Notice that A is in parallel with B and C is in parallel with D. Then, (A + B) and (C + D) are in series.
A I:0 0000 0 1 C I:0 2 B I:0

Example 7-9
C I:0 2 D I:0 3 Y O:0 0 Control relay B3:0 0

B’ + C · D C·D

A · (B’ + C · D) · C’

7.14 Creating Logic Gate Circuits from PLC Ladder Logic Diagrams
In Sections 7.11, 7.12, and 7.13, you learned how to create PLC ladder logic diagrams from truth tables, logic gate circuits, and Boolean expressions. In this section, you will see the reverse process. You will use examples to study how to convert PLC ladder logic diagrams to logic gate circuits. The first step in this process is to find the Boolean expression that represents the ladder logic diagram. You can then draw the logic gate circuit using the Boolean expression similar. You can also use the logic converter instrument in the NI Multisim program to find truth tables and Boolean expressions from the logic gate circuits. Three examples are used to illustrate how to convert PLC ladder logic diagrams to logic gate circuits.
0001

A I:0 0 0002

Control relay B3:0 0

Y = A · [A · (B’ + C · D) · C’]’

End

Figure 7-43. PLC ladder logic diagram for Example 7-9.

Example 7-9
Create the logic gate circuit for the PLC ladder logic diagram displayed in Figure 7-43. First, turn the PLC ladder logic diagram shown in Figure 7-43 into a Boolean expression as shown in the ladder
Example 7-8
A I:0 0000 0 B I:0 1 2 D I:0 3 0

A+B

C I:0

C+D

Y O:0

Y = (A + B) · (C + D)

0001

End

Figure 7-42. PLC ladder logic diagram for Example 7-8.

diagram. Notice that in rung 0000, inverted input B is in parallel (ORed) with serial (ANDed) inputs C and D. This is represented by the following expression: B′ + C · D This combination (B′ + C · D) is in serial (ANDed) with input A and inverted input C′ in rung 0000. Therefore, the control relay output for this rung is the following: A · (B′ + C · D) · C′ In rung 0001, input A is in serial (ANDed) with the inverted output of the control relay from rung 0000 to generate the Boolean expression for output Y: Y = A · [A · (B′ + C · D) · C′] ′ Next, create the logic gate circuit using the Boolean expression from Figure 7-43. Figure 7-44 displays the logic gate circuit for this example. Notice that ANDed inputs C and D and inverted input B are ORed for the following Boolean expression: B′ + C·D Then, this is ANDed with input A and inverted input C for the following Boolean expression: A · (B′ + C · D) · C′ Finally, this output is inverted and ANDed with input A for the output of Y: Y = A · [A · (B′ + C·D) · C′] ′

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C

C C · D’ + C’ · D CD D B’ + CD B’ B A C’ A · (B’ + CD) · C’ A [A · (B’ + CD) · C’] A Y = A · [A · (B’ + CD) · C’)’ Figure 7-46. Logic gate circuit for Example 7-10. B Y = A · [B + (C · D’ + C’ · D)] D B + (C · D’ + C’ · D)

Figure 7-44. Logic gate circuit for Example 7-9.

Example 7-10
Create the logic gate circuit for the PLC ladder logic diagram displayed in Figure 7-45. First, turn the PLC ladder logic diagram shown in Figure 7-45 into a Boolean expression as shown in the ladder diagram. Notice that in rung 0000, inputs C and D in the bottom parallel branches create an XOR logic gate (CD′ + C′D). This is in parallel (ORed) with input B, forming the following Boolean expression: B + (C · D′ + C′ · D)
Example 7-10
A I:0 0000 0 1 C I:0 2 C I:0 2 0001 D I:0 3 D I:0 3 End 0 B I:0 Y O:0

Finally, this combination is in serial (ANDed) with input A to generate output Y: Y = A · [B + (C · D′ + C′ · D)] Next, create the logic gate circuit using the Boolean expression from Figure 7-45. Figure 7-46 displays the logic gate circuit for this example. Notice that inputs C and D are XORed and then ORed with input B. This combination is then ANDed with input A for the output of Y: Y = A · [B + (C · D′ + C′ · D)]

Example 7-11
Create the logic gate circuit for the PLC ladder logic diagram displayed in Figure 7-47. First, turn the PLC ladder logic diagram shown in Figure 7-47 into a Boolean expression as shown in the ladder diagram. Notice that in rung 0000, parallel (ORed) inputs A, B, and inverted C are in parallel (ORed) with the output from the control relay which is in series (ANDed) with inverted input D, forming the following Boolean expression: (A + B + C′) + [D′ · (A + B + C′ + D′)] Finally, inverted input E′ in rung 0001 is in serial (ANDed) with the output of the control relay. This is equal to the output of Y: Y = E′ {(A + B + C′) + [D′ · (A + B + C′ + D′)]} Next, create the logic gate circuit using the Boolean expression from Figure 7-47. Figure 7-48 displays the logic gate circuit for this example.

Y = A · [B + (C · D’ + C’ · D)] B + (C · D’ + C’ · D) C · D’ + C’ · D

Figure 7-45. PLC ladder logic diagram for Example 7-10.

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Example 7-11
A I:0 0000 0 B I:0 1 C I:0 2 D I:0 3 Control relay B3:0 0 0 Control relay B3:0

Summary
• • Combinational logic gates do not require clock pulses to operate. Combinational logic gates are called logic gates. There are seven logic gates: NOT, AND, OR, NAND, NOR, XOR (exclusive OR), and XNOR (exclusive NOR). Sequential logic devices require clock pulses and have outputs that depend on their inputs as well as time. Flip-flop devices such as reset-set (RS), JK, delay (D), and toggle (T) are sequential logic devices. Every gate logic function has its own equation called a Boolean expression. A type of algebra using only two states is called Boolean algebra in honor of Boole. In Boolean algebra, the true state is represented by the number one, called logic high or logic one. The false state is represented by the number zero, called logic low or logic zero. In Boolean algebra, a table, called a truth table, contains the digital input and output points. A prime symbol (′) indicates the inverse value of the input. The output of a NOT gate is the inverse of the input. The NOT gate is sometimes called an inverter. Karnaugh maps (K-Maps) are graphical representations of truth tables that use columns and rows to represent each term in a truth table.

• • • • •

A + B + C’

(A + B + C’) + [D’ · (A + B + C’ + D’)]

[D’ · (A + B + C’ + D’)]

•
Y = E’ {(A + B + C’) + [D’ · (A + B + C’ + D’)]}
Y O:0 0

E I:0 0001 4

Control relay B3:0 0

• • •

0002

End

Figure 7-47. PLC ladder logic diagram for Example 7-11.

Review Questions
Complete each of the following sentences with the correct word(s). 1. When the input to a NOT gate is a logic high, the output is a logic ______. 2. You can create a NOT gate ladder logic diagram using either one rung or ______ rungs. 3. In an one-rung NOT gate ladder logic diagram, the input instruction must be normally ______. 4. In a two-rung NOT gate ladder logic diagram, the input instruction must be normally ______. 5. In a two-rung NOT gate ladder logic diagram, you must use a(n) ______ contact. 6. In an AND gate ladder logic diagram, when both inputs are closed, the output is ______. 7. In an AND gate ladder logic diagram, when both inputs are open the output is ______.

A (A + B + C’) B C D D’ C’ (A + B + C’) + [D’ · (A + B + C’ + D’)] Y = E’ {(A + B + C’) + [D’ · (A + B + C’ + D’)]} E’

(A + B + C’ + D’) E

Figure 7-48. Logic gate circuit for Example 7-11.

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8. In an AND gate ladder logic diagram, when one input is closed and the other one is open, the output is ______. 9. An AND gate ladder logic diagram requires ______ rung(s). 10. In a NAND gate ladder logic diagram, when both inputs are open, the output is ______. 11. In a NAND gate ladder logic diagram, when both inputs are closed, the output is ______. 12. In a NAND gate ladder logic diagram, when one input is closed and the other one is open, the output is ______. 13. You can create a NAND gate logic diagram using either one rung or ______. 14. In an one-rung NAND gate ladder logic diagram, the inputs must be in ______. 15. In an OR gate ladder logic diagram, when both inputs are closed, the output is ______. 16. In an OR gate ladder logic diagram, when both inputs are open, the output is ______. 17. In an OR gate ladder logic diagram, when one input is closed and the other one is open, the output is ______. 18. An OR gate ladder logic diagram requires ______ rung(s). 19. The input for an OR gate ladder logic diagram must be normally ______. 20. In a NOR gate ladder logic diagram, when both inputs are open, the output is ______. 21. In a NOR gate ladder logic diagram, when both inputs are closed, the output is ______. 22. In a NOR gate ladder logic diagram, when one input is closed and the other one is open, the output is ______. 23. In a one-rung NOR gate ladder logic diagram, both inputs must be normally ______. 24. In a two-rung NOR gate ladder logic diagram, inputs are connected in ______. 25. In an XOR gate ladder logic diagram, when both inputs are open, the output is ______. 26. In an XOR gate ladder logic diagram, when both inputs are closed, the output is ______. 27. In an XOR gate ladder logic diagram, when one input is closed and the other one is open, the output is ______. 28. The inputs in an XOR gate ladder logic diagram are connected in ______ and ______. 29. The inputs in an XOR gate ladder logic diagram are normally ______ and ______.

30. In an XNOR gate ladder logic diagram, when both inputs are open, the output is ______. 31. In an XNOR gate ladder logic diagram, when both inputs are closed, the output is ______. 32. In an XNOR gate ladder logic diagram, when one input is closed and the other one is open, the output is ______. 33. In a one-rung XNOR gate ladder logic diagram, the normally closed inputs are connected in ______. Specify if the following statements are true or false. 34. Both inputs to an AND gate must be high to produce a high output. 35. Both inputs to a NAND gate must be high to produce a high output. 36. Inverting a NAND gate will result in creating an AND gate. 37. Only one input to an OR gate must be high to produce a high output. 38. Both inputs to a NOR gate must be high to produce a high output. 39. Inverting an OR gate will result in creating a NOR gate. 40. Both inputs to an XOR gate must be high to produce a high output. 41. Both inputs to an XNOR gate must be high to produce a high output. 42. All three inputs to a three-input AND gate must be high to produce a high output. Create a PLC ladder diagram for the truth tables in the following problems. 43. A
0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 I I I I I I I I I Y 0 0 0 1 0 1 0 1

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44. A
0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

I I I I I I I I I

Y 0 0 0 1 0 1 1 0

Create a relay logic diagram for the ladder diagrams in the following problems. 47. L1
A CR B C D E-1 CR E-2 L2

Create a PLC ladder diagram for the relay logic diagrams in the following problems. 45.
A B C D E F Y

M

48. L1
A B Y1

L2

A G H J C Y1-1 D

B E Y1-2 D Y2-1 Y2

46. A
B

C D E

Y

Create a PLC ladder diagram for the Boolean expressions in the following problems. 49. 50. 51. 52. Y = (A′ + B) + (A′ + B + C′)′ Y = A′B′C + AB′ + A′BC′ Y = B′(A + C) + C(A′ + B) + AC Y = (A′B + AB′) × (A′B′ + AB) + ABC