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The Impact of Operating Systems on Modern Cpu Designs (and Vice Versa)

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The Impact of Operating Systems on Modern CPU Designs (and Vice Versa)
Chris Schlaeger
Director Operating System Research Center February, 2008

Software Visible Features changed the Game

After the Megahertz Race

What has changed?

▪ 64 bit computing ▪ AMD-V™ technology ▪ Power consumption ▪ Multi-core

▪ Frequency and cache size changes are invisible to the OS ▪ Architectural features require changes to the OS!

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Impact of OSs on Modern CPU Designs

Degrees of Freedom for CPU designs
Address and instruction width Memory bus connection Instruction set Pipeline stages Number of execution units Number of cores Number of CPUs CPU Interconnects Caches ...

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Impact of OSs on Modern CPU Designs

AMD's HW/SW Co-Design Approach
Next-Gen CPU/GPU HW-Architecture
Architecture Improvements

CPU

Behavioural Description Binary Code

Cycle Accurate Simulator
Code Improvements

Operating System Prototype

Full In-House Design Cycle
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OS Reference Implementation

February, 2008

Impact of OSs on Modern CPU Designs

Uniform vs. Non-Uniform Memory

I/O I/O Hub Hub

Memory Controller PCI-E Hub

Bridge

PCI-E Bridge PCI-E PCI-E Bridge Bridge

PCI-E Bridge

PCI-E Bridge

I/O Hub

USB PCI

Traditional x86 architecture • Frontside bus limits memory bandwidth to a fixed maximum
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Direct Connect Architecture • Memory bandwidth scales with number of processors

February, 2008

Impact of OSs on Modern CPU Designs

Example: Advanced Synchronization Facility

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Advanced Synchronization Facility
Proposed facility for low-overhead atomic memory modification Change a set of cache lines, mass-commit atomically Primitive for higher-level synchronization primitives Roll your own DCAS / LL-SC Highly flexible Use almost any x86 instructions in critical sections

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Critical section structure
DCAS: retry: LOCK MOV R8, [mem1] LOCK MOV R9, [mem2] ACQUIRE RCX, 2 JNZ retry XOR RCX, RCX CMP R8, RAX JNZ out CMP R9, RBX JNZ out XCHG RDI, [mem1] XCHG RSI, [mem2] MOV RCX, 1 out: COMMIT

; Specification begins ; Atomic block begins ; Retry in case of abort ; DCAS semantics

; End of critical section

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Impact of OSs on Modern CPU Designs

Software Transactional Memory (STM)
Motivation: Parallel programming is here to stay Parallel programming is hard Transactional Memory (TM): New programming paradigm to ease parallel programming Provides transactions (as known from databases) Today's software implementations (STM) incur high overhead Can we accelerate STMs using hardware support?

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Advanced Synchronization Facility Evaluation
Can we accelerate STMs using Advanced Synchronization Facility? Methodology: Add facility to performance simulator Enhance an STM with facility Run facility-enabled STM on top of simulator In collaboration with TU Dresden Diploma thesis Foundation of VELOX project

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February 15, 2008

Impact of OSs on Modern CPU Designs

Simulating Advanced Synchronization Facility Performance
PTLsim “Cycle-accurate” K8 simulator (open source) Extended with models of SMP, cache coherency Added Advanced Synchronization Facility Worked around stability issues Why PTLsim? PTLsim has extremely fast turnaround (native execution mode based on Xen hypervisor) PTLsim is easy to share Experience with Xen

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Simulation Results — lock-free data structure

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STM Acceleration using the Facility
Using TinySTM State-of-the-art lock-based STM system Tried several optimization approaches Most were dead ends Most hot paths had been optimized already Final approach: Use facility to reduce bookkeeping Monitor up to 8 memory lines using the facility

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Simulation Results — STM (list)

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Impact of OSs on Modern CPU Designs

Simulation Results — Conclusion
Simulation has sufficiently high fidelity Advanced Synchronization Facility has very good potential for lock-free programming: Best single-thread performance Excellent scalability Advanced Synchronization Facility has potential for accelerating STM Competitive single-thread performance Excellent scalability Not all effects understood yet

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7 Challenges for the Future

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Impact of OSs on Modern CPU Designs

Challenges for the Future
OS and architecture support for parallelization OS support for noncoherent memory architectures Message Passing vs. Shared Memory vs. ? OS support for accelerators Power Management Architecture and operating-system support for secure computing Fault Tolerance

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Impact of OSs on Modern CPU Designs

Trademark Attribution
AMD, the AMD Arrow logo, AMD Opteron and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Linux® is a registered trademark of Linus Torvalds. Other names used in this presentation are for identification purposes only and may be trademarks of their respective owners. Linux 2.0 Penguin courtesy of lewing@isc.tamu.edu . ©2008 Advanced Micro Devices, Inc. All rights reserved.

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