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The Impact of Pipelining on Computer System Performance

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Computer Architecture has had a few great improvements since the birth of the computer. Reduced Instruction Set Computing (RISC), Pipelining, Cache Memory, and Virtual Memory are the four most important advances. If any of these techniques were to be implemented separately there would not be as great of an improvement in the computer systems we have today. They are each dependent upon the other to amplify the performance increases. While each of these performs separate tasks to improve system performance, Pipelining has helped to improve system performance the most.
Reduced Instruction Set Computing simplifies the instructions that are executed for a microprocessor. The RISC architecture was developed not to speed up the time with which processors can complete the instructions, but to simplify the instructions themselves. According to Masood in his article entitled RISC and CISC the Reduced Instruction Set Computer uses a “small, highly optimized set of instructions”, as opposed to the more complex instructions in other architecture systems. When a RISC architecture, which simplifies the instructions, is coupled with other methods, such as pipelining the system has a CPI of one cycle (Masood, 2011).
Cache Memory improves system performance by storing recently accessed data not in the main memory, but in a high-speed intermediate memory location. This reduces the time used to fetch these instructions. Modern microprocessors use various levels of cache memory to perform the cache memory functions. According to the Network Dictionary L1 Cache is a primary that is built into the CPU. This memory stores copies of the data that has been most frequently used in the main memory locations. L2 cache is a secondary cache location that is separate from the CPU and L1 cache. This secondary cache stores a subset of the contents of the main memory. Most recently L3

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