A Look into
Computer Memory Table of Contents
Abstract 3
A Look into Computer Memory 4
Memory Hierarchy 4
Allocation Policies 5
Relocation Policies 6
Hit and Hit Ratio 6
Modern Computer Applications 7
Conclusion 7
References 8

Abstract
The memory of a computer is a key component of the overall architecture of a computer. Several types of memory exist with the architecture of the computer which collectively is known as the memory hierarchy. The use of the memory hierarchy, placing and moving information, is effected by the allocation and relocation policies. How well these policies allow the processor to find the information it is looking for, known as a hit, is determined by the hit ratio. The modern processor available today relies on memory hierarchy to maintain their high performance. The paper will take a look at how these various pieces and policies work together within the architecture of a computer.

A Look into
Computer Memory
Memory plays a key role in the modern processor. The memory hierarchy is the foundation for which the allocation and relocation policies function upon. These policies work to provide the needed information in the proper memory location to attempt to maintain a high hit ratio to avoid processor delay. Regardless of the speed of a modern processor, a low hit ratio adds delay to the high performance processor.
Memory Hierarchy
Memory in a computer varies in size, speed with regards to access time and, just as importantly, cost. To allow for high speed processing, access to memory must be able to occur in 1 nanosecond or less (Parhami, 2005, p. 329). High speed memory with an access time of 1 nanosecond or less comes at a very high cost. Due to this high cost, millions of dollars per gigabyte, there is a very small amount of this type of memory, typically in the hundreds of bytes. To provide an affordable cost of a processor and in turn a computer, memories of various speeds and costs are used. The memory hierarchy is made up of these various levels of memory. A typical hierarchy, including size and cost, can be seen in Figure 1 with the smallest, fastest, and most expensive at the top of the pyramid. The register memory is available directly to the processor and is labeled Level 0. This memory is used explicitly for load/store instructions. In Figure 1, Level 1 memory is called the Cache 1 memory with Level 2 memory called the Cache 2 and so forth. Level 1 and Level 2 memories are typically part of the processor chip in order to allow direct access to the memory locations by the processor. Level 3 memory is the RAM installed on the motherboard of the computer and has an access time of hundreds of nanoseconds. The next level of memory, Level 4, which is considered the directly connected disks of the system, which have a significant amount of access time which is in the tens of milliseconds. Level 5 memory can be network storage or tape drives which may take minutes to access the appropriate data. It is worth noting the right hand column in Figure 1 showing the reduction in cost per GB as the size increases and the access speed decreases. To obtain high speed at an affordable cost, large amounts of information (programs and large data sets) is stored in the slower memory locations and moved into the faster memory locations, preferably before it is needed by the processor (Parhami, 2005, pp. 329-331).
Allocation Policies
Allocation policies determine where data will be placed within the memory hierarchy. The allocation policy is executed by the memory manager. The memory manager play an intricate part in maintaining the performance of the processor by keeping the immediately needed data in the optimal location for processor access to prevent delay in retrieving the information from slower access locations. There are three primary strategies that can be used for memory placement. They are Best Fit, First Fit and Worst Fir. When using the Best Fit policy, the memory manager looks for the closest fitting empty location where the data will fit without as little wasted space as possible. It is worth noting that the best fit location may not be the first available location where the data would fit. For placing the data in the first location where it will fit, the First Fit policy is used. This policy puts the data into the first location it fits with no regard for the amount of remain space after the data. Finally in Worst Fit, the memory manager looks for the largest location available to place the data with the end goal of having the maximum amount of space left available to place additional data into the remaining location (Virginia Polytechnic Institute and State University, 2013).
Relocation Policies
Relocation occurs when the OS loads a solid block of memory for a process. The first physical location of the process is known as the relocation address or base address. There are two types of relocation, static and dynamic. Static relocation is very basic in that a location is assigned to the process when it is first put into memory. From that point on, until the process is complete, the process remains in that particular location and cannot be moved. The downside to static relocation is once the process is started, the memory location and the amount of memory cannot be changed until the process is stopped. Dynamic relocation, however, can be an ever changing process. With dynamic relocation, the OS can move the process to a better location during execution to maintain efficiency. This enables the area for the process to increase as the needs of the process increases. One downside is that an add function on every memory reference causing a delay for the processor to process the add function. Other disadvantages of dynamic relocation is that the memory allocated cannot be shared among processes and the process itself is still limited to the physical size of the memory (The University of Utah, 2009).
Hit and Hit Ratio
When a processor accesses a memory location in the register, L1 or L2 Cache and finds the information it requires, this is known as a Hit. The Hit Ratio is the number of Hits the processor makes divided by the total number of times the processor accessed the memory for data. The higher the Hit Ratio, the better performance of the processor. When the information the processor needs is not in one of the higher levels of memory, it must go to the other memory locations for the information. As shown in the Memory Hierarchy, as the need to access the lower levels of memory occurs, the time it takes to obtain the information from these lower levels significantly increases the time it takes to complete a particular process. A branch predictor can be implemented to predict what information will be needed by the processer prior to the information being needed. This information can then be placed into a special buffer so it is available when the processor needs it avoiding the need for the processor to wait while information is retrieved from the slower memory locations (Hennessy & Patterson, 2007, p. 82).
Modern Computer Applications
The modern Intel i7 CPU uses four processing cores which utilize the Memory Hierarchy mentioned above with one additional level added to the pyramid. All four cores use a register, L1 and L2 Caches for executing instructions. Intel has added a third memory cache between the L2 Cache and the main memory of the computer. This L3 Cache as they call it is shared by the four processing cores as shown in Figure 2. This enables the cores to access information from one of the other cores without interrupting the other core due to the ability to access the common cache instead of the core specific register, L1 or L2 Cache. If the core specific register, L1 or L2 cache would need to provide information to another core, the specific core would have to pause it’s current process and hand off the information to the other core. The L3 Cache avoids this delay. The remaining memory beyond the cache level functions the same as previously indicated above (National Instruments, 2011).
Conclusion
The Memory Hierarchy along with the allocation policy, reallocation policy, memory manager and branch predictor all play key role in the functioning of the modern processor. Having the proper size and speed memory being utilized in the most efficient manner allows for maximum utilization of a processor’s computational ability.
References
Hennessy, J. L., & Patterson, D. A. (2007). Computer Architecture A Quantative Approach (4th ed.). San Francisco: Morgan Kaufmann.
National Instruments. (2011, March 10). Top Eight Features of the Intel Core i7 Processors for Test, Measurement, and Control. Retrieved from National Instruments: http://www.ni.com/white-paper/11266/en/
Parhami, B. (2005). Computer Architecture From Microprocessors to Supercomputers. Santa Barbara: Oxford University Press.
The University of Utah. (2009, December 2). Memory Managemetn. Retrieved from The University of Utah: http://www.cs.utah.edu/~mflatt/past-courses/cs5460/lecture8.pdf
Virginia Polytechnic Institute and State University. (2013, 11 10). Operating Systems - Memory Allocation. Retrieved from Virginia Polytechnic Institute and State University: http://courses.cs.vt.edu/~csonline/OS/Lessons/MemoryAllocation/index.html