Nonvolatile BIOS memory - CMOS
[pic]
CMOS Battery in a Pico ITX motherboard
Non-volatile BIOS memory refers to the memory on a personal computer motherboard containing BIOS settings and sometimes the code used to initialize the computer and load the operating system. The non-volatile memory was historically called CMOS RAM or just CMOS because it traditionally used a low-power CMOS memory chip (the Motorola MC146818, or one of its higher-capacity clones), which was powered by a small battery when the system power was off. The term remains in wide use in this context, but has also grown into a misnomer. The non-volatile BIOS storage in contemporary computers might be in an EEPROM or flash memory chip and not in a volatile CMOS RAM. In these cases, the battery back-up is meant to keep the RTC chip synchronized. The NVRAM normally has a storage capacity of 512 Bytes, which is enough for all BIOS-settings.

CMOS mismatch

CMOS mismatch errors typically occur if the computer's power-on self-test program: 1. Finds a device that is not recorded in the CMOS. 2. Does not find a device that is recorded in the CMOS. 3. Finds a device that has different settings than those recorded for it in CMOS. 4. Detects a CMOS checksum error. [1] [2]

CMOS battery

[pic]
Type CR2032 button cell, most common CMOS battery.
The memory and real-time clock are generally powered by a CR2032 lithium coin cell. These cells last two to ten years, depending on the type of motherboard, ambient temperature and the time that the system is powered off, while other common cell types can last significantly longer or shorter periods, such as the CR2016 which will generally last about 40% as long. Higher temperatures and longer power-off time will shorten cell life. When replacing the cell, the system time and CMOS BIOS settings may revert to default values. This may be avoided by replacing the cell with the power supply master switch on. On ATX motherboards, this will supply 5V standby power to the motherboard even if it is apparently "switched off", and keep the CMOS memory energized.

Resetting the CMOS settings

To access the BIOS setup when the machine fails to operate, occasionally a drastic move is required. In older computers with battery-backed RAM, removal of the battery and short circuiting the battery input terminals for a while did the job; in some more modern machines this move only resets the RTC. Some motherboards offer a CMOS-reset jumper or a reset button. In yet other cases, the EEPROM chip has to be desoldered and the data in it manually edited using a programmer. Sometimes it is enough to ground the CLK or DTA line of the I²C bus of the EEPROM at the right moment during boot, this requires some precise soldering on SMD parts. If the machine lets you boot but does not want to let you into the BIOS setup, one possible recovery is to deliberately "damage" the CMOS checksum by doing direct port writes using debug.exe, corrupting some bytes of the checksum-protected area of the CMOS RAM; at the next boot, the computer typically resets its setting to factory defaults.

AwardBIOS Error Messages

|When a personal computer is first turned on, the BIOS tests and configures various components to ensure that they are operating|
|correctly. This operation is called POST (power-on self test). If the BIOS detects any problems during this testing phase, it|
|will attempt to continue to start the computer. However, if the problems are severe, the BIOS may be forced to halt the |
|system. |
|When an error is detected, the BIOS program will: |
|Display the error to the screen, if possible. |
|Generate a POST beep code using the computer's internal speaker if it cannot access the display adaptor. |
|Provide a POST code output that can be read using a special hardware tool. |
|Beep Codes |
|The only AwardBIOS beep code indicates that a video error has occurred and the BIOS cannot initialize the video screen to |
|display any additional information. This beep code consists of a single long beep followed by two short beeps. Any other beeps |
|are probably a RAM (Random Access Memory) problems. |
| |
|Screen Error Messages |
|The following messages are examples of messages including errors detected by the BIOS during POST and a description of what |
|they mean and/or what you may do to correct the error. |
| |
| |
|BIOS ROM checksum error - System halted |
|The checksum of the BIOS code in the BIOS chip is incorrect, indicating the BIOS code may have become corrupt. Contact your |
|system dealer to replace the BIOS. |
| |
|CMOS battery failed |
|The CMOS battery is no longer functional. Contact your system dealer for a replacement battery. |
| |
|CMOS checksum error - Defaults loaded |
|Checksum of CMOS is incorrect, so the system loads the default equipment configuration. A checksum error may indicate that CMOS|
|has become corrupt. This error may have been caused by a weak battery. Check the battery and replace if necessary. |
| |
|CPU at nnnn |
|Displays the running speed of the CPU. |
| |
|Display switch is set incorrectly |
| |
|The display switch on the motherboard can be set to either monochrome or color. This message indicates the switch is set to a |
|different setting than indicated in Setup. Determine which setting is correct, and then either turn off the system and change |
|the jumper, or enter Setup and change the VIDEO selection. |
| |
|Press ESC to skip memory test |
|The user may press Esc to skip the full memory test. |
| |
|Floppy disk(s) fail |
| |
|Cannot find or initialize the floppy drive controller or the drive. Make sure the controller is installed correctly. If no |
|floppy drives are installed, be sure the Diskette Drive selection in Setup is set to NONE or AUTO. |
| |
|HARD DISK initializing |
|Please wait a moment |
|Some hard drives require extra time to initialize. |
| |
|HARD DISK INSTALL FAILURE |
| |
|Cannot find or initialize the hard drive controller or the drive. Make sure the controller is installed correctly. If no hard |
|drives are installed, be sure the Hard Drive selection in Setup is set to NONE. |
| |
|Hard disk(s) diagnosis fail |
|The system may run specific disk diagnostic routines. This message appears if one or more hard disks return an error when the |
|diagnostics run. |
| |
|Keyboard error or no keyboard present |
|Cannot initialize the keyboard. Make sure the keyboard is attached correctly and no keys are pressed during POST. To purposely |
|configure the system without a keyboard, set the error halt condition in Setup to HALT ON ALL, BUT KEYBOARD. The BIOS then |
|ignores the missing keyboard during POST. |
| |
|Keyboard is locked out - Unlock the key |
|This message usually indicates that one or more keys have been pressed during the keyboard tests. Be sure no objects are |
|resting on the keyboard. |
| |
|Memory Test: |
|This message displays during a full memory test, counting down the memory areas being tested. |
| |
|Memory test fail |
|If POST detects an error during memory testing, additional information appears giving specifics about the type and location of |
|the memory error. |
| |
|Override enabled - Defaults loaded |
|If the system cannot boot using the current CMOS configuration, the BIOS can override the current configuration with a set of |
|BIOS defaults designed for the most stable, minimal-performance system operations. |
| |
|Press TAB to show POST screen |
|System OEMs may replace the Phoenix Technologies' AwardBIOS POST display with their own proprietary display. Including this |
|message in the OEM display permits the operator to switch between the OEM display and the default POST display. |
| |
|Primary master hard disk fail |
|POST detects an error in the primary master IDE hard drive. |
| |
|Primary slave hard disk fail |
|POST detects an error in the secondary master IDE hard drive. |
| |
|Resuming from disk, Press TAB to show POST screen |
|Phoenix Technologies offers a save-to-disk feature for notebook computers. This message may appear when the operator re-starts |
|the system after a save-to-disk shut-down. See the Press Tab & message above for a description of this feature. |
| |
|Secondary master hard disk fail |
|POST detects an error in the primary slave IDE hard drive. |
| |
|Secondary slave hard disk fail |
|POST detects an error in the secondary slave IDE hard drive. |
| |

|Index of Setup Fields for AwardBIOS |
|This page lists Setup fields found in the following Setup screens: |
|Standard CMOS |
|BIOS Features |
|Chipset Features |
|Power Management |
|PNP/PCI Configuration |
|Integrated Peripherals |
|Numeric |
| |
|16 Bit I/O Recovery Time |
|See 8/16 Bit I/O Recovery Time, below. |
| |
|16 Bit ISA I/O Command WS |
|Your system quite possibly has much higher performance than some of your input/output (I/O) devices. This means that unless the system is instructed to allow more time, more |
|wait states, for devices to respond, it might think the device has malfunctioned and stop its request for I/O. If all your I/O devices are capable, then disabling this setting |
|could result in greater throughput. Otherwise, data could be lost. |
| |
|16 Bit ISA Mem Command WS |
|When memory is accessed on the ISA bus, the system must allow for the relatively slow speed of the ISA bus. This setting allows you to match the speed of device memory located |
|on the ISA bus with the system ability to read/write to that memory. |
| |
|1st/2nd Fast DMA Channel |
|Select up to two DMA channels for Type F DMA, if supported by the I/O peripheral using the DMA channel. |
| |
|1st/2nd/3rd/4th Available IRQ |
|If an installed PCI device requires interrupt service, you may manually select an unused interrupt line for PCI IRQs. NA indicates the interrupt is assigned to an ISA bus |
|device and is not available to any PCI slot. |
| |
|2 Bank PBSRAM |
|For PBSRAMs, 3-1-1-1 timing is available for both read and write transactions at 66 or 75 MHz. VP2 |
| |
|2nd Channel IDE |
|If you install an add-in IDE interface as the second IDE channel, select Disabled to avoid a conflict with the on-chip second IDE channel. |
| |
|8/16 Bit I/O Recovery Time |
|The I/O recovery mechanism adds bus clock cycles between PCI-originated I/O cycles to the ISA bus. This delay takes place because the PCI bus is much faster than the ISA bus. |
| |
|These two fields let you add recovery time (in bus clock cycles) for 16-bit and 8-bit I/O. |
| |
|A |
| |
|ACPI I/O Device Node |
|Selecting Enabled enables ACPI device node reporting from the BIOS to the operating system. VP2 |
| |
|AGP Aperture Size (MB) |
|Select the size of the Accelerated Graphics Port (AGP) aperture. The aperture is a portion of the PCI memory address range dedicated for graphics memory address space. Host |
|cycles that hit the aperture range are forwarded to the AGP without any translation. |
| |
|ALE During Bus Conversion |
|Depending on system speed, you can select a Single or a Multiple ALE signal during a bus conversion cycle. |
| |
|APM BIOS |
|Select Enabled to turn on the BIOS power-management features. |
| |
|Asysc. SRAM Read WS |
|Select the correct cycle timing combination for the system board design and SRAM specifications. |
| |
|Asysc. SRAM Write WS |
|Select the correct cycle timing combination for the system board design and SRAM specifications. |
| |
|AT Clock Option |
|The system board designer selects whether the AT bus clock is tightly synchronized with the CPU clock or is asynchronous. |
| |
|AT-BUS Clock |
|The chipset generates the ISA bus clock (ATCLK) from an internal division of PCICLK. You can set the speed of the AT bus in terms of a fraction of the CPU clock speed, or at |
|the fixed speed of 7.16 MHz. |
| |
|Audio DMA Select |
|Select a DMA channel for the audio port. |
| |
|Audio I/O Base Address |
|Select a base I/O address for the audio port. |
| |
|Audio IRQ Select |
|Select an interrupt for the audio port. |
| |
|Auto Clock Control |
|If APM is not enabled or not present in your system, the BIOS manages the CPU clock when this field is Enabled in the same way APM power management would manage the clock. |
| |
|Auto Configuration |
|Auto Configuration selects predetermined optimal values of chipset parameters. When Disabled, chipset parameters revert to setup information stored in CMOS. Many fields in this|
|screen are not available when Auto Configuration is Enabled. |
| |
|Auto Detect DIMM/PCI Clk |
|To reduce the occurrence of electromagnetic interference (EMI), the BIOS detects the presence or absence of components in DIMM and PCI slots and turns off system clock |
|generator pulses to empty slots. |
| |
|Auto Suspend Timeout |
|After the selected period of system inactivity, the system automatically enters Suspend mode. |
| |
|B |
| |
|Back to Back I/O Delay |
|Select Enabled to insert three ATCLK signals in back-to-back AT bus I/O cycles. |
| |
|Bank 0/1 DRAM Type |
|The value in this field is set by the system board manufacturer, depending on whether the board has paged DRAMs or EDO (extended data output) DRAMs. |
| |
|BIOS PM on AC |
|If you wish the BIOS power-management features to remain active when the system is connected to an external power source, set to On. |
| |
|BIOS PM Timers |
|After the selected period of inactivity for each subsystem (video, hard drive, peripherals), that subsystem enters Standby mode. |
| |
|Boot From LAN First |
|When Enabled, the BIOS attempts to boot from a LAN boot image before it attempts to boot from a local storage device. |
| |
|Boot Sequence |
|The original IBM PCs loaded the DOS operating system from drive A (floppy disk), so IBM PC-compatible systems are designed to search for an operating system first on drive A, |
|and then on drive C (hard disk). However, modern computers usually load the operating system from the hard drive, and may even load it from a CD-ROM drive. |
| |
|Boot Up Floppy Seek |
|When Enabled, the BIOS tests (seeks) floppy drives to determine whether they have 40 or 80 tracks. Only 360-KB floppy drives have 40 tracks; drives with 720 KB, 1.2 MB, and |
|1.44 MB capacity all have 80 tracks. Because very few modern PCs have 40-track floppy drives, we recommend that you set this field to Disabled to save time. |
| |
|Boot Up NumLock Status |
|Toggle between On or Off to control the state of the NumLock key when the system boots. When toggled On, the numeric keypad generates numbers instead of controlling cursor |
|operations. |
| |
|Boot Up System Speed |
|Select High to boot at the default CPU speed; select Low to boot at the speed of the AT bus. Some add-in peripherals or old software (such as old games) may require a slow CPU |
|speed. The default setting is High. |
| |
|Burst Write Combining |
|When this option is Enabled, the chipset assembles long PCI bursts from the data held in these buffers. |
| |
|Byte Merge |
|This field controls the byte-merge feature for frame buffer cycles. When Enabled, the controller checks the eight CPU Byte Enable signals to determine if data bytes read from |
|the PCI bus by the CPU can be merged. |
| |
|Byte Merge Support |
|Byte merging holds 8- or 16-bit data sent from the CPU to the PCI bus in a buffer where it is accumulated, or merged, into 32-bit data for faster performance. The chipset then |
|writes the data in the buffer to the PCI bus when appropriate. PCI Pipeline and Pipelining combine PCI or CPU pipelining with byte merging. Byte merging is used to enhance |
|video performance. |
| |
|C |
| |
|Cache Read Burst |
|These SRAM timing numbers are the pattern of cycles the CPU uses to read data from the cache. The system board designer must select the proper combination, depending on the |
|cache size and access speed of the cache SRAMs. Do not reset this option from its default. |
| |
|Cache Read Wait States |
|Select the number of wait states for the cache output enable signals. When 0 WS is selected, CROEA# and CROEB# are active for 2 CPU clocks; for 1 WS, CROEA# and CROEB# are |
|active for 3 CPU clocks. The actual number of clocks that CROE# remains active may be longer. The number is automatically adjusted during L2 cache write-back-to-DRAM cycles to |
|synchronize with the DRAM controller. |
| |
|Cache Timing |
|For a secondary cache of one bank, select Faster. For a secondary cache of two banks, select Fastest. VP2 |
| |
|Cache Write Burst |
|Sets the precise timing used during burst writes to the cache. |
| |
|Cache Write Wait State |
|The system board designer may elect to insert a wait state into the cache write cycle, if necessary. |
| |
|CAS Address Hold Time |
|Select the number of cycles it takes to change the CAS address after CAS has been initiated (asserted) aimed at a target address (location) in DRAM. |
| |
|CAS Low Time for Write/Read |
|The number of clocks cycles the CAS signal is pulled low for DRAM writes and reads depends on the DRAM timing. Do not reset this field from the default value specified by the |
|system designer. |
| |
|CAS# Precharge Time |
|Select the number of CPU clocks allocated for the CAS# signal to accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete |
|and data lost. |
| |
|CAS Pulse Width |
|The system designer must set the duration of a CAS signal pulse (in timer ticks). |
| |
|Chipset NA# Asserted |
|Selecting Enabled permits pipelining, in which the chipset signals the CPU for a new memory address before all data transfers for the current cycle are complete, resulting in |
|faster performance. |
| |
|Chipset Special Features |
|When disabled, the chipset behaves as if it were the earlier Intel 82430FX chipset. |
| |
|CPU Addr. Pipelining |
|Pipelining allows the system controller to signal the CPU for a new memory address even before all data transfers for the current cycle are complete, resulting in increased |
|throughput. |
| |
|CPU Burst Write Assembly |
|The chipset maintains four posted write buffers. When this option is enabled, the chipset is allowed to assemble long PCI bursts from the data held in these buffers. |
| |
|CPU Core Voltage |
|Set this field to match the voltage of the installed CPU, or set to Auto to permit the BIOS to autodetect the voltage. End users should not change the value in this field |
|unless they replace the CPU with one of a different voltage. VP2 |
| |
|CPU fan on temp high |
|When the CPU temperature reaches a preset limit, the CPU fan turns on. |
| |
|CPU Host/PCI Clock |
|Select Default or select a timing combination for the CPU and the PCI bus. When set to Default, the BIOS uses the actual CPU and PCI bus clock values. |
| |
|CPU Internal Cache /External Cache |
|Cache memory is additional memory that is much faster than conventional DRAM (system memory). CPUs from 486-type on up contain internal cache memory, and most, but not all, |
|modern PCs have additional (external) cache memory. When the CPU requests data, the system transfers the requested data from the main DRAM into cache memory, for even faster |
|access by the CPU. |
| |
|CPU Line Read |
|This field lets you Enable or Disable full CPU line reads. |
| |
|CPU L2 Cache ECC Checking |
|When you select Enabled, memory checking is enable when the external cache contains ECC SRAMs. |
| |
|CPU Line Read Multiple |
|A line read means that the CPU is reading a full cache line. When a cache line is full it holds 32 bytes (eight DWORDS) of data. Because the line is full, the system knows |
|exactly how much data it will be reading and it doesn't need to wait for an end-of-data signal, freeing it to do other things. |
| |
|When this item is Enabled, the system is allowed to read more than one full cache line at a time. |
| |
|CPU Line Read Prefetch |
|See the field below. When this item is Enabled, the system is allowed to prefetch the next read instruction and initiate the next process. |
| |
|CPU Read Multiple Prefetch |
|A prefetch occurs during a process (e.g., reading from the PCI or memory) when the chipset "peeks" at the next instruction and actually begins the next read instruction. This |
|chipset has four read lines. A multiple prefetch means that the chipset has the capacity to initiate more than one prefetch during a process. |
| |
|CPU to DRAM Page Mode |
|When Disabled, the memory controller closes the DRAM page after a DRAM access. When Enabled, the DRAM page remains open until the next access. |
| |
|CPU to PCI Buffer |
|When this field is Enabled, writes from the CPU to the PCI bus are buffered, to compensate for the speed differences between the CPU and the PCI bus. When Disabled, the writes |
|are not buffered and the CPU must wait until the write is complete before starting another write cycle. |
| |
|CPU-To-PCI Burst Mem. WR. |
|When this option is enabled, the chipset is allowed to assemble long PCI bursts from the data held in its buffers. SIS5597 |
| |
|CPU to PCI Byte Merge |
|Byte merging permits merging of the data in consecutive CPU-to-PCI byte/word writes with the same dword address, into the same posted write buffer location. The merged |
|collection of bytes is then sent over the PCI Bus as a single dword. Byte merging is performed in the compatible VGA range only (0A0000-0BFFFF). |
| |
|CPU-To-PCI IDE Posting |
|Select Enabled to post write cycles from the CPU to the PCI IDE interface. IDE accesses are posted in the CPU to PCI buffers, for cycle optimization. |
| |
|CPU to PCI POST/BURST |
|Data from the CPU to the PCI bus can be posted (buffered by the controller) and/or burst. These are the methods: |
|POST/CON.BURST |
|Posting and conservative bursting |
| |
|POST/Agg.BURST |
|Posting and aggressive bursting |
| |
|NONE/NONE |
|Neither posting nor bursting |
| |
|POST/NONE |
|Posting but not bursting |
| |
| |
| |
|CPU-To-PCI Write Buffer |
|When Enabled, the CPU can write up to four dwords of data to the PCI write buffer before the CPU must wait for the PCI bus cycles to finish. When Disabled, the CPU must wait |
|after each write cycle until the PCI bus signals that it is ready to receive more data. |
| |
|CPU-To-PCI Write Post |
|When this field is Enabled, writes from the CPU to the PCI bus are buffered, to compensate for the speed differences between the CPU and the PCI bus. When Disabled, the writes |
|are not buffered and the CPU must wait until the write is complete before starting another write cycle. |
| |
|CPU Warning Temperature |
|Select the combination of lower and upper limits for the CPU temperature. If the CPU temperature extends beyond either limit, any warning mechanism programmed into your system |
|will be activated. |
| |
|CPU/PCI Write Phase |
|Determines the number of clock signals between the address and data phases of the CPU-master-to-PCI-slave writes. |
| |
|CPUFAN Off in Suspend |
|When Enabled, the CPU fan turns off during Suspend mode. |
| |
|CRT Power Down |
|When Enabled, the CRT powers down when the system enters a Green mode. |
| |
|CRT Sleep |
|Determines the manner in which the monitor is blanked. |
| |
|Current CPU Temperature |
|This field displays the current CPU temperature, if your computer contains a monitoring system. |
| |
|Current CPUFAN 1/2/3 Speed |
|These fields display the current speed of up to three CPU fans, if your computer contains a monitoring system. |
| |
|Current System Temperature |
|This field displays the current system temperature, if your computer contains a monitoring system. |
| |
|D |
| |
|Date |
|The BIOS determines the day of the week from the other date information; this field is for information only. |
| |
|Press the right or left arrow key to move to the desired field (date, month, year). Press the PgUp or PgDn key to increment the setting, or type the desired value into the |
|field. |
| |
|Day of Month Alarm |
|Select a date in the month. Select 0 (zero) if you prefer to set a weekly alarm. SIS5597 |
| |
|Daylight Saving |
|When enabled, this parameter adds one hour to the clock when daylight-saving time begins. It also subtracts one hour when standard time returns. |
| |
|Delayed Transaction |
|The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2.1. |
| |
|Dirty pin selection |
|When Combine is selected in the Tag/Dirty Implement field, you can choose whether the dirty data pin is I/O, for bidirectional input/output, or IN, for input only. |
| |
|DMA Clock |
|This item allows you to set the speed of Direct Memory Access (DMA) at either equal to or one-half of the SYSCLK (system clock signal) speed. While speed is always desirable, |
|choosing the higher setting may prove to be too fast for some components. |
| |
|DMA n Assigned to |
|When resources are controlled manually, assign each system DMA channel as one of the following types: |
|Legacy ISA: |
|Devices compliant with the original PC AT bus specification, requiring a specific DMA channel |
| |
|PCI/ISA PnP: |
|Devices compliant with the Plug and Play standard, whether designed for PCI or ISA bus architecture. |
| |
| |
| |
|Doze Mode |
|After the selected period of system inactivity, the CPU clock runs at slower speed while all other devices still operate at full speed. |
| |
|Doze Speed (div by) |
|Select a divisor to reduce the CPU speed during Doze mode to a fraction of the full CPU speed. |
| |
|Doze Timer |
|After the selected period of system inactivity, the CPU clock runs at slower speed while all other devices still operate at full speed. |
| |
|Doze Timer Select |
|Select the timeout period (period of system inactivity) after which the system enters Doze mode. |
| |
|DRAM Auto Configuration |
|The system board designer must select the proper value for this field, according to the specifications of the installed DRAM chips. When Disabled, you can select the DRAM |
|timing type. |
| |
|DRAM Data Integrity Mode |
|Select Parity or ECC (error-correcting code), according to the type of installed DRAM. |
| |
|DRAM ECC/PARITY Select |
|Set this option according to the type of DRAM installed in your system: error-correcting code (ECC) or parity (default). |
| |
|DRAM Enhanced Paging |
|When Enabled, the chipset keeps the page open until a page/row miss. When Disabled, the chipset uses additional information to keep the DRAM page open when the host may be |
|"right back." |
| |
|DRAM Fast Leadoff |
|Select Enabled to shorten the leadoff cycles and optimize performance. |
| |
|DRAM Last Write to CAS# |
|Select the number of cycles elapse between the last data signal and CAS# asserted. This period is the setup time for the CAS signal. |
| |
|DRAM Leadoff Timing |
|Select the combination of CPU clocks the DRAM on your board requires before each read from or write to the memory. Changing the value from the setting determined by the board |
|designer for the installed DRAM may cause memory errors. |
| |
|DRAM Page Idle Timer |
|Select the amount of time in HCLKs that the DRAM controller waits to close a DRAM page after the CPU becomes idle. |
| |
|DRAM Page Open Policy |
|When Disabled, the page open register is cleared and the corresponding memory page is closed. When Enabled, the page remains open, even when there are no requests to service. |
| |
|DRAM Posted Write |
|See DRAM Posted Write Buffer, next. |
| |
|DRAM Posted Write Buffer |
|The chipset maintains its own internal buffer for DRAM writes. When this buffer is Enabled, CPU write cycles to DRAM are posted to the buffer, so the CPU can start another |
|write cycle before the DRAM finishes its cycle. |
| |
|DRAM R/W Leadoff Timing |
|Select the combination of CPU clocks the DRAM on your board requires before each read from or write to the memory. Changing the value from the setting determined by the board |
|designer for the installed DRAM may cause memory errors. |
| |
|DRAM RAS Only Refresh |
|An alternate to CAS-before-RAS refresh. Leave Disabled unless your DRAM requires this older method of refresh generation. |
| |
|DRAM RAS# Precharge Time |
|Select the number of CPU clocks allocated for the Row Address Strobe (RAS#) signal to accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, |
|refresh may be incomplete and data lost. |
| |
|DRAM RAS# Pulse Width |
|The system designer must select the number of CPU clock cycles allotted for the RAS pulse refresh, according to DRAM specifications. |
| |
|DRAM Read Burst (B/E/F) |
|Set the timing for burst-mode reads from DRAM. The lower the timing numbers, the faster the system addresses memory. |
| |
|DRAM Read Burst (EDO/FPM) |
|Sets the timing for reads from EDO (Extended Data Output) or FPM (Fast Page Mode) memory. The lower the timing numbers, the faster the system addresses memory. Selecting timing|
|numbers lower than the installed DRAM is able to support can result in memory errors. |
| |
|DRAM Read Prefetch Buffer |
|Each time there is a memory access request, a preprogrammed number of local bus clock signals is counted down. When the count reaches zero, if the number of filled posted write|
|buffer slots is at or above a predetermined threshold value, the memory request priority is raised. This mechanism is used to control memory access latency. |
| |
|DRAM Read Wait State |
|These DRAM timing numbers are the pattern of cycles the CPU uses to read data from the main memory. The system board designer must select the proper combination, depending on |
|the memory size and access speed of the DRAMs. Do not reset this option from its default. |
| |
|DRAM Read/Write Timing |
|Your system designer should select the timing that the system uses when reading from and writing to DRAM. Do not reset from the factory default value. |
| |
|DRAM Read-Around-Write |
|DRAM optimization feature: If a memory read is addressed to a location whose latest write is being held in a buffer before being written to memory, the read is satisfied |
|through the buffer contents, and the read is not sent to the DRAM. |
| |
|DRAM Refresh Period |
|Select the period required to refresh the DRAMs, according to DRAM specifications. |
| |
|DRAM Refresh Queue |
|Enabled permits queuing up to four DRAM refresh requests, so DRAM can refresh at optimal times. Disabled makes all refreshes priority requests. Installed DRAM must support this|
|feature; most do. |
| |
|DRAM Refresh Rate |
|Select the period required to refresh the DRAMs, according to DRAM specifications. |
| |
|DRAM Refresh Stagger By |
|Select the number of clock ticks (0-7) between refreshing rows in the memory array. Selecting 0 refreshes all rows at once. |
| |
|DRAM R/W Leadoff Timing |
|Select the combination of CPU clocks the DRAM on your board requires before each read from or write to the memory. Changing the value from the setting determined by the board |
|designer for the installed DRAM may cause memory errors. |
| |
|DRAM Slow Refresh |
|The default DRAM refresh request signal occurs every 15 µs. A 16-bit ISA bus master may activate a refresh request when it has bus ownership. Selecting a slow refresh period |
|here specifies the timing of the refresh request signal from an ISA master. |
| |
|DRAM Speculative Leadoff |
|A read request from the CPU to the DRAM controller includes the memory address of the desired data. When Enabled, Speculative Leadoff lets the DRAM controller pass the read |
|command to memory slightly before it has fully decoded the address, thus speeding up the read process. |
| |
|DRAM Speed Selection |
|The value in this field must correspond to the speed of the DRAM installed in your system. DO NOT change the default setting of this field, as determined by the system board |
|manufacturer for the installed DRAM. This value is access speed, so a lower value means a faster system. |
| |
|DRAM Timing |
|The value in this field depends on performance parameters of the installed memory chips (DRAM). Do not change the value from the factory setting unless you install new memory |
|that has a different performance rating than the original DRAMs. |
| |
|DRAM Timing Control |
|This allows you to determine the type of timing the system uses when reading or writing to DRAM. Selections are Fast, Fastest, Normal (default) and Slow. |
| |
|This field provides an alternative method of selecting DRAM timing. Again, the selected value must be set by the board designer, according to specifications of the installed |
|DRAM and other board components. Turbo mode reduces CAS access time by 1 clock tick. VP2 |
| |
|DRAM to PCI RSLP |
|When Enabled, the chipset permits prefetching of two lines of data from system memory to the PCI bus. |
| |
|DRAM Write Burst (B/E/F) |
|DRAM Write Burst Timing |
|Sets the timing for burst-mode writes from DRAM. The lower the timing numbers, the faster the system addresses memory. Selecting timing numbers lower than the installed DRAM is|
|able to support can result in memory errors. |
| |
|DRAM Write Wait State |
|The system board designer may elect to insert a wait state into the DRAM write cycle, if necessary. |
| |
|DREQ6 PIN as |
|This field lets the board designer invoke a software suspend routine by toggling the DREQ6 signal. Select Suspend SW only if your board has such a feature. |
| |
|Drive A |
|Drive B |
|Select the correct specifications for the diskette drive(s) installed in the computer. |
|None |
|No diskette drive installed |
| |
|360K, 5.25 in |
|5-1/4 inch PC-type standard drive; 360 kilobyte capacity |
| |
|1.2M, 5.25 in |
|5-1/4 inch AT-type high-density drive; 1.2 megabyte capacity |
| |
|720K, 3.5 in |
|3-1/2 inch double-sided drive; 720 kilobyte capacity |
| |
|1.44M, 3.5 in |
|3-1/2 inch double-sided drive; 1.44 megabyte capacity |
| |
|2.88M, 3.5 in |
|3-1/2 inch double-sided drive; 2.88 megabyte capacity |
| |
| |
| |
|Drive NA before BRDY |
|When Enabled, the NA signal is driven for one clock before the last BRDY# of every cycle for read/write hit cycles, thus generating ADS# in the next cycle after BRDY#, |
|eliminating one dead cycle. |
| |
|DRQ Detection |
|When Enabled, any activity on a DRQ signal line wakes up the system or resets the inactivity timer. |
| |
|Duplex Select |
|In an infrared port mode, this field appears. Full-duplex mode permits simultaneous two-direction transmission. Half-duplex mode permits transmission in one direction only at a|
|time. Select the value required by the IR device connected to the IR port. |
| |
|E |
| |
|ECP Mode Use DMA |
|Select a DMA channel for the port. |
| |
|EDO CASx# MA Wait State |
|The board designer may elect to insert one additional wait state before the assertion of the first CASx# for page hit cycles, thus allowing one additional clock of MA setup |
|time to the CASx# for the leadoff page hit cycle. Do not change from the manufacturer's default unless you are getting memory addressing errors. This field applies only if EDO |
|DRAM is installed in the system. |
| |
|EDO Back-to-Back Timing |
|Select the number of timer ticks required for back-to-back accesses, according to the specifications of installed EDO DRAM. SIS5571 |
| |
|EDO DRAM Read Burst |
|Set the timing for burst-mode reads from DRAM. The lower the timing numbers, the faster the system addresses memory. This field applies only if EDO DRAM is installed in the |
|system. |
| |
|EDO DRAM Speed Selection |
|The value in this field must correspond to the speed of the DRAM installed in your system. DO NOT change the default setting of this field, as determined by the system board |
|manufacturer for the installed DRAM. This value is access speed, so a lower value means a faster system. This field applies only if EDO DRAM is installed in the system. |
| |
|EDO DRAM Write Burst |
|Set the timing for burst-mode writes from DRAM. The lower the timing numbers, the faster the system addresses memory. This field applies only if EDO DRAM is installed in the |
|system. |
| |
|EDO RASx# Wait State |
|The board designer may elect to insert one additional wait state before RAS# is asserted for row misses, thus allowing one additional MAX[13:0] setup time to RASx# assertion. |
|This field applies only if EDO DRAM is installed in the system. |
| |
|EDO RAS# Precharge Time |
|The precharge time is the number of cycles it takes for the RAS to accumulate its charge before DRAM refresh. If insufficient time is allowed, refresh may be incomplete and the|
|DRAM may fail to retain data. This field applies only if EDO DRAM is installed in the system. |
| |
|EDO RAS# to CAS# Delay |
|This field applies only if EDO DRAM is installed in the system. It lets you insert a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read |
|from, or refreshed. Disabled gives faster performance; and Enabled gives more stable performance. |
| |
|EDO is short for Extended Data Output. EDO DRAM is faster than conventional DRAM if the cache controller in the system supports pipeline burst transfer mode. Unlike |
|conventional DRAM, which only allows one byte to be read at a time, EDO DRAM can copy an entire block of memory to its internal cache. While the processor is accessing this |
|cache, the memory can collect a new block to send. |
| |
|EDO Read WS |
|Select the correct cycle timing combination for the system board design and EDO DRAM specifications. |
| |
|Enhanced Memory Write |
|Select Enabled or Disabled for the Memory Write and Invalidate command on the PCI bus. This field must be Disabled if cache size is 512 KB and the tag address is 8 bits. |
| |
|Enhanced Page Mode |
|Select Enabled or Disabled, according to DRAM specifications. |
| |
|EPP Version |
|Select EPP port type 1.7 or 1.9. |
| |
|Extended CPU-PIIX4 PHLDA# |
|When Enabled, the system controller adds one clock signal to the length of time the PHLDA# signal is active under two conditions: |
|During the address phase at the beginning of a PCI read/write transaction |
|Following the address phase of a CPU LOCK cycle |
|When this field is Enabled, the Passive Release and Delayed Transaction fields should be Enabled. |
| |
|Extended Read-Around-Write |
|When Enabled, reads can bypass writes within the 82450GX memory interface component(s), provided their addresses do not match. |
| |
|External Cache |
|Cache memory is additional memory that is much faster than conventional DRAM (system memory). Most, but not all, modern PCs have additional (external) cache memory. When the |
|CPU requests data, the system transfers the requested data from the main DRAM into cache memory, for even faster access by the CPU. |
| |
|Extra AT Cycle WS |
|Select Enabled to insert one wait state in the standard AT bus cycle. Normally used when Legacy peripherals require additional response time. |
| |
|F |
| |
|Fast AT Cycle |
|Select Enabled to shorten AT bus cycles by one ATCLK signal. |
| |
|Fast Back-to-Back |
|When Enabled, consecutive write cycles targeted to the same slave become fast back-to-back on the PCI bus. |
| |
|Fast DRAM Refresh |
|The cache DRAM controller offers two refresh modes, Normal and Hidden. In both modes, CAS takes place before RAS but the Normal mode requires a CPU cycle for each. On the other|
|hand, a cycle is eliminated by "hiding" the CAS refresh in Hidden mode. Not only is the Hidden mode faster and more efficient, but it also allows the CPU to maintain the status|
|of the cache even if the system goes into Suspend power-management mode. |
| |
|Fast EDO Leadoff |
|Select Enabled only for EDO DRAMs in either a synchronous cache or a cacheless system. It causes a 1-HCLK pull-in for all read leadoff latencies for EDO DRAMs (i.e., page hits,|
|page misses, and row misses). Select Disabled if any of the DRAM rows are populated with FPM DRAMs. |
| |
|Fast EDO Path Select |
|When Enabled, a fast path is selected for CPU-to-DRAM read cycles for the leadoff, providing the system contains EDO DRAMs. It causes a 1-HCLK pull-in for all read leadoff |
|latencies (i.e., page hits, page misses, and row misses). |
| |
|Fast MA to RAS# Delay [CLK] |
|The values in this field are set by the system board designer, depending on the DRAM installed. Do not change the values in this field unless you change specifications of the |
|installed DRAM or the installed CPU. |
| |
|Fast RAS to CAS Delay |
|When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS to Column Address Strobe |
|(CAS). |
| |
|FDD Detection |
|When Enabled, any floppy drive activity wakes up the system or resets the inactivity timer. |
| |
|Floppy 3 Mode Support |
|When Enabled, the BIOS supports a type of 3.5-in diskette drive that can read 720-KB, 1.2-MB, and 1.44-MB diskettes. |
| |
|G |
| |
|Gate A20 Option |
|Gate A20 refers to the way the system addresses memory above 1 MB (extended memory). When set to Fast, the system chipset controls Gate A20. When set to Normal, a pin in the |
|keyboard controller controls Gate A20. Setting Gate A20 to Fast improves system speed, particularly with OS/2 and Windows. |
| |
|Global Standby Timer |
|After the selected period of inactivity for the entire system, the system enters Standby mode. |
| |
|Global Suspend Timer |
|After the selected period of global Standby mode, the system enters Suspend mode. |
| |
|GPI05 Power Up Control |
|When you select Enabled, a signal from General Purpose Input 05 returns the system to Full On state. SIS5597 |
| |
|Graphic Posted Write Buff |
|The chipset maintains its own internal buffer for graphics memory writes. When this buffer is Enabled, CPU write cycles to graphics memory are posted to the buffer, so the CPU |
|can start another write cycle before the graphics memory finishes its cycle. |
| |
|Guaranteed Access Time |
|When Enabled, Guaranteed Access Time mode is enabled, so a CHRDY time-out of 2.5 (s is guaranteed for the ISA bus. When Disabled, an ISA bus master is granted the ISA bus and |
|then the SIO chip arbitrates for the PCI bus. |
| |
|H |
| |
|Halt On |
|During the power-on self-test (POST), the computer stops if the BIOS detects a hardware error. You can tell the BIOS to ignore certain errors during POST and continue the |
|boot-up process. These are the selections: |
|No errors |
|POST does not stop for any errors. |
| |
|All errors |
|If the BIOS detects any non-fatal error, POST stops and prompts you to take corrective action. |
| |
|All, But Keyboard |
|POST does not stop for a keyboard error, but stops for all other errors. |
| |
|All, But Diskette |
|POST does not stop for diskette drive errors, but stops for all other errors. |
| |
|All, But Disk/Key |
|POST does not stop for a keyboard or disk error, but stops for all other errors. |
| |
| |
| |
|Hard Disks |
|The BIOS supports up to four IDE drives. This section does not show information about other IDE devices, such as a CD-ROM drive, or about other hard drive types, such as SCSI |
|drives. |
|NOTE: We recommend that you select type AUTO for all drives. |
|The BIOS can automatically detect the specifications and optimal operating mode of almost all IDE hard drives. When you select type AUTO for a hard drive, the BIOS detects its |
|specifications during POST, every time the system boots. |
|If you do not want to select drive type AUTO, other methods of selecting the drive type are available: |
|Match the specifications of your installed IDE hard drive(s) with the preprogrammed values for drive types 1 through 45. |
|Select USER and enter values into each drive parameter field. |
|Use the IDE HDD AUTO DECTECTION function in Setup. |
|Here is a brief explanation of drive specifications: |
|Type: The BIOS contains a table of pre-defined drive types. Each defined drive type has a specified number of cylinders, number of heads, write precompensation factor, landing |
|zone, and number of sectors. Drives whose specifications do not accommodate any pre-defined type are classified as type USER. |
|Size: Disk drive capacity (approximate). Note that this size is usually slightly greater than the size of a formatted disk given by a disk-checking program. |
|Cyls: Number of cylinders |
|Head: Number of heads |
|Precomp: Write precompensation cylinder |
|Landz: Landing zone |
|Sector: Number of sectors |
|Mode: Auto, Normal, large, or LBA |
|Auto: The BIOS automatically determines the optimal mode. |
|Normal: Maximum number of cylinders, heads, and sectors supported are 1024, 16, and 63. |
|Large: For drives that do not support LBA and have more than 1024 cylinders. Applicable to only a few drives. |
|LBA (Logical Block Addressing): During drive accesses, the IDE controller transforms the data address described by sector, head, and cylinder number into a physical block |
|address, significantly improving data transfer rates. For drives with greater than 1024 cylinders. |
| |
|HDD Detection |
|When Enabled, any hard drive activity wakes up the system or resets the inactivity timer. |
| |
|HDD Off After |
|After the selected period of drive inactivity, the hard disk drive powers down while all other devices remain active. Selecting Suspend tells the drive to power down |
|immediately. |
| |
|HDD Power Down |
|After the selected period of drive inactivity, the hard disk drive powers down while all other devices remain active. |
| |
|HDD Standby Timer |
|After the selected period of drive inactivity, the hard disk drive powers down. Its timing is separate from other PM modes listed above. |
| |
|Hidden Refresh |
|When Disabled, DRAM is refreshed by IBM AT methodology, using a CPU cycles for each refresh. When hidden refresh is Enabled, the DRAM controller seeks the most opportune moment|
|for a refresh, regardless of CPU cycles, with least disruption of system activity and least performance penalty. Hidden refresh is faster and more efficient, and it also allows|
|the CPU to maintain the status of the DRAM even if the system goes into a power management "suspend" mode. |
| |
|Host-to-PCI Bridge Retry |
|When Enabled, the peripherals controller (PIIX4) retries, without initiating a delayed transaction, CPU-initiated nonLOCK# PCI cycles. No delayed transactions to the controller|
|may be currently pending and passive release must be active. When this field is Enabled, the Passive Release and Delayed Transaction fields should be Enabled. |
| |
|Hot Key Power Off |
|Select Enabled if your system has a hot key for soft power off. SIS5597 |
| |
|I |
| |
|I/O Recovery Time |
|The peripheral controller insert a minimum of 2 bus clock (BCLK) delays between back-to-back 8- or 16-bit ISA I/O cycles issued from the PCI master. If a greater delay is |
|desired, select 4, 8, 12 clocks. |
| |
|IDE 32-bit Transfer Mode |
|The IDE interface in the integrated peripherals controller supports 32-bit data transfers. Select enabled only if your IDE hard drives can also support 32-bit transfer mode. |
| |
|IDE Buffer for DOS & Win |
|Select Enabled to increase throughput to and from IDE devices by using the on-chip read-ahead and posted-write IDE buffers. Note that use of the buffers may cause some slow IDE|
|devices to be even slower. When in doubt, experiment with this setting for optimal performance and data integrity. |
| |
|IDE Burst Mode |
|Selecting Enabled reduces latency between each drive read/write cycle, but may cause instability in IDE subsystems that cannot support such fast performance. If you are getting|
|disk drive errors, try setting this value to Disabled. This field does not appear when the Internal PCI/IDE field is Disabled. |
| |
|IDE Data Port Post Write |
|Selecting Enabled speeds up processing of drive reads and writes, but may cause instability in IDE subsystems that cannot support such fast performance. If you are getting disk|
|drive errors, try setting this value to Disabled. |
| |
|IDE HDD Block Mode |
|Block mode is also called block transfer, multiple commands, or multiple sector read/write. If your IDE hard drive supports block mode (most new drives do), select Enabled for |
|automatic detection of the optimal number of block read/writes per sector the drive can support. |
| |
|IDE Prefetch Mode |
|The onboard IDE drive interfaces supports IDE prefetching, for faster drive accesses. If you install a primary and/or secondary add-in IDE interface, set this field to Disabled|
|if the interface does not support prefetching. |
| |
|IDE Primary/ Secondary Master/Slave PIO |
|The four IDE PIO (Programmed Input/Output) fields let you set a PIO mode (0-4) for each of the four IDE devices that the onboard IDE interface supports. Modes 0 through 4 |
|provide successively increased performance. In Auto mode, the system automatically determines the best mode for each device. |
| |
|IDE Primary/ Secondary Master/Slave UDMA |
|UDMA (Ultra DMA) is a DMA data transfer protocol that utilizes ATA commands and the ATA bus to allow DMA commands to transfer data at a maximum burst rate of 33 MB/s. When you |
|select Auto in the four IDE UDMA fields (for each of up to four IDE devices that the internal PCI IDE interface supports), the system automatically determines the optimal data |
|transfer rate for each IDE device. |
| |
|IDE Second Channel Control |
|The chipset contains a PCI IDE interface with support for two IDE channels. Select Enabled to activate the secondary on-chip IDE interface. Select Disabled to deactivate this |
|interface, if you install a secondary add-in IDE interface. |
| |
|In Order Queue Depth |
|Select 8 to track up to eight pipelined bus transactions. |
| |
|IN0-IN6 (V) |
|These fields display the current voltage of up to seven voltage input lines, if your computer contains a monitoring system. |
| |
|Inactive Timer Select |
|Select the timeout period (period of system inactivity) after which the system enters Inactive mode. This period should be longer than the period selected for Standby mode. |
| |
|Init AGP Display First |
|Init Display First |
|Initialize the AGP video display before initializing any other display device on the system. Thus the AGP display becomes the primary display. |
| |
|Internal PCI/IDE |
|The chipset contains a PCI IDE interface that supports two IDE channels: Primary (IRQ 14) and Secondary (IRQ 15). Each channel supports two IDE devices, so the system is |
|capable of supporting a total of four IDE devices. Select Primary, Secondary, or Both to activate chipset IDE interface(s) installed on your system board. |
| |
|InfraRed Duplex Type |
|IR Function Duplex |
|Select the value required by the IR device connected to the IR port. Full-duplex mode permits simultaneous two-direction transmission. Half-duplex mode permits transmission in |
|one direction only at a time. If no infrared port is present in the system, select Disabled. |
| |
|IR Duplex Mode |
|Select the value required by the IR device connected to the IR port. Full-duplex mode permits simultaneous two-direction transmission. Half-duplex mode permits transmission in |
|one direction only at a time. If no infrared port is present in the system, select Disabled. |
| |
|IRQ n Assigned to |
|When resources are controlled manually, assign each system interrupt as one of the following types, depending on the type of device using the interrupt: |
|Legacy ISA: |
|Devices compliant with the original PC AT bus specification, requiring a specific interrupt (such as IRQ4 for serial port 1) |
| |
|PCI/ISA PnP: |
|Devices compliant with the Plug and Play standard, whether designed for PCI or ISA bus architecture. |
| |
| |
| |
|IRQ8 Break Suspend |
|IRQ8 Break [Event From] Suspend |
|You can Enable or Disable monitoring of IRQ8 (the Real Time Clock) so it does not awaken the system from Suspend mode. |
| |
|IRQ8 Clock Event.. |
|You can turn On or Off monitoring of IRQ8 (the Real Time Clock) so it does not awaken the system from Suspend mode. |
| |
|IRQn Detection |
|When Enabled, any activity from the selected IRQ (IRQ3-IRQ12; IRQ14-IRQ15) wakes up the system or resets the inactivity timer. |
| |
|IRRX Mode Select |
|This field appears only when IrDA mode 1.1 is selected for UART2 Mode. The value in this field depends on the type of transceiver module used for IrDA mode 1.1 (called fast |
|IR). One type has a mode pin (IRMODE) and the other type has a second receive data channel (IRRX3). Do not change the factory default value of this field unless your IR |
|peripheral documentation explicitly states a mode requirement for fast IR, or if you are having a problem configuring your IR peripheral in fast IR mode. |
| |
|ISA Bus Clock |
|You can set the speed of the AT bus at one-third or one-fourth of the CPU clock speed. |
| |
|ISA Bus Clock Option |
|ISA Bus Clock Frequency |
|The ISA bus clock speed is the speed at which the CPU communicates with the AT bus (expansion bus). The speed is measured as a fraction of PCICLKI, the timing signal of the PCI|
|bus. Experiment with setting the bus timing to a lower speed (for example, from PCICLKI/3 to PCICLKI/4) if an installed expansion peripheral has performance problems. |
| |
|ISA Clock |
|You can set the speed of the AT bus at one-third or one-fourth of the CPU clock speed. |
| |
|ISA I/O Recovery |
|The CPU and local bus are much faster than industry standard architecture (ISA) input/output (I/O) bus. Select Enabled to allow additional time for I/O devices to respond to |
|the system. Otherwise, data could be lost. If all your I/O devices are capable of fast I/O, selecting Disabled can speed up processing. |
| |
|ISA Line Buffer |
|The PCI to ISA Bridge has an 8-byte bidirectional line buffer for ISA or DMA bus master memory reads from or writes to the PCI bus. When Enabled, an ISA or DMA bus master can |
|prefetch two doublewords to the line buffer for a read cycle. |
| |
|J |
| |
|Joystick Function |
|If your system has a joystick peripheral, select Enable. |
| |
|K |
| |
|KBC input clock |
|The system designer must select the correct frequency for the keyboard controller input clock. Do not change this value from the default value. |
| |
|Keyboard Controller Clock |
|The keyboard controller clock speed is the speed at which the CPU communicates with the keyboard controller. Depending on the specifications of the installed keyboard |
|controller, the speed may be fixed at 7.16 MHz or may be a fraction of PCICLKI, the timing signal of the PCI bus. |
| |
|Keyboard Emulation |
|When Enabled, Gate A20 and software reset emulation for an external keyboard controller are enabled. Be sure to make the setting of this field agree with the setting of the |
|Gate A20 Option field in the BIOS Features Setup screen (Fast = Enabled; Normal = Disabled). |
| |
|Keyboard Resume |
|When Disabled, keyboard activity does NOT awaken the system from Suspend mode. VP2 |
| |
|L |
| |
|L1 Cache Policy |
|Write-Through means that memory is updated with data held in the cache whenever the CPU issues a write cycle. On the other hand, Write-Back causes memory to be updated only |
|under certain conditions, such as read requests to the memory whose contents are currently in the cache. Write-Back allows the CPU to operate with fewer interruptions, |
|increasing its efficiency. |
| |
|L2 Cache Cacheable Size |
|Select 512 MB only if your system RAM is greater than 64 MB. |
| |
|L2 Cache Write Policy |
|In addition to the Write-Back and Write-Through options, the L2 cache also offers Adaptive WB1 and Adaptive WB2. Both adaptive write-back modes try to reduce the disadvantages |
|of both the write-through and write-back policies. The system designer must select the optimal cache write policy, according to the SRAM specifications. |
| |
|L2 to PCI Read Buffer |
|The chipset maintains its own internal buffer for external-cache-to-PCI writes. When this buffer is Enabled, external cache write cycles to the PCI bus are posted to the |
|buffer, so the each device can complete its cycles without waiting for the other. |
| |
|L2 (WB) Tag Bit Length |
|The system uses tag bits to determine the status of data in the cache. Set this field to match the specifications (7 or 8 bits) of the system external cache. |
| |
|LCD&CRT |
|Select your video display device: |
|LCD |
|Notebook liquid crystal display |
| |
|CRT |
|Auxiliary monitor |
| |
|AUTO |
|The BIOS autosenses the device in use (this value lets you switch between devices without being left "in the dark"). |
| |
|LCD&CRT |
|Display on both devices |
| |
| |
| |
|LDEV Detection |
|When Enabled, any activity on the LDEV signal line wakes up the system or resets the inactivity timer. |
| |
|Linear Merge |
|When Enabled, only consecutive linear addresses can be merged. |
| |
|Linear Mode SRAM Support |
|Select Enabled if your system contains a CPU that requires linear mode (e.g., Cyrix M1/M2 CPU). |
| |
|Local Memory 15-16M |
|To increase performance, your system can map slower device memory (usually a device is connected to the slower ISA bus) into much faster local bus memory. It does this by |
|setting aside local memory and transferring the start point from the device memory to the local memory. Use this setting to enable/disable this capability. It is Enabled by |
|default. |
| |
|LREQ Detection |
|When Enabled, any activity on the LREQ signal line wakes up the system or resets the inactivity timer. |
| |
|M |
| |
|M1 Linear Burst Mode |
|Select Enabled if your system contains a Cyrix M1 CPU. |
| |
|MA Additional Wait State |
|Selecting Enabled inserts an additional wait state before the beginning of a memory read. The setting of this parameter depends on the board design. Do not change from the |
|manufacturer's default unless you are getting memory addressing errors. |
| |
|Master Mode Byte Swap |
|Master Byte Swap Control |
|Select Enabled or Disabled. |
| |
|Master Retry Timer |
|This sets how many PCI clock signals the CPU master attempts a PCI cycle before the cycle is unmasked (terminated). |
| |
|Mem. Drive Str. (MA/RAS) |
|(Memory Address Drive Strength) This field controls the strength of the output buffers driving the MA and BA1 pins (first value) and SRASx#, SCASx#, MWEx#, and CKEx pins |
|(second value). |
| |
|Memory |
|You cannot change any values in the Memory fields; they are only for your information. The fields show the total installed random access memory (RAM) and amounts allocated to |
|base memory, extended memory, and other (high) memory. RAM is counted in kilobytes (KB: approximately one thousand bytes) and megabytes (MB: approximately one million bytes). |
|RAM is the computer's working memory, where the computer stores programs and data currently being used, so they are accessible to the CPU. Modern personal computers may contain|
|up to 64 MB, 128 MB, or more. |
|Base Memory |
|Typically 640 KB. Also called conventional memory. The DOS operating system and conventional applications use this area. |
| |
|Extended Memory |
|Above the 1-MB boundary. Early IBM personal computers could not use memory above 1 MB, but current PCs and their software can use extended memory. |
| |
|Other Memory |
|Between 640 KB and 1 MB; often called High memory. DOS may load terminate-and-stay-resident (TSR) programs, such as device drivers, in this area, to free as much conventional |
|memory as possible for applications. Lines in your CONFIG.SYS file that start with LOADHIGH load programs into high memory. |
| |
| |
| |
|Memory Hole at 15M Addr. |
|You can reserve this area of system memory for ISA adapter ROM. When this area is reserved, it cannot be cached. The user information of peripherals that need to use this area |
|of system memory usually discusses their memory requirements. |
| |
|Memory Hole at 15M-16M |
|You can reserve this area of system memory for ISA adapter ROM. When this area is reserved, it cannot be cached. The user information of peripherals that need to use this area |
|of system memory usually discusses their memory requirements. |
| |
|Memory Parity Check |
|Select Enabled if the DRAM chips in your system support parity. |
| |
|Memory Parity/ECC Check |
|Select Enabled, Disabled, or Auto. In Auto mode, the BIOS enables memory checking automatically when it detects the presence of ECC or parity DRAM. |
| |
|MODEM Use IRQ |
|Name the interrupt request (IRQ) line assigned to the modem (if any) on your system. Activity of the selected IRQ always awakens the system. |
| |
|Monitor Event in Full On Mode |
|In On mode, the Standby timer (Standby Timer Select, 2-256 min) starts counting if no activity is taking place and the programmable time-out period has expired. |
|When you Enabled monitoring (checking) of a device listed under this category, it is included in the list of devices that the system monitors during the PM timers count-down. |
|When you Disable monitoring (checking) of a device listed under this category, activity does not interrupt the PM timers count-down. |
| |
|Month Alarm |
|Select a month (1-12) or NA if you want the alarm active during all months. SIS5597 |
| |
|MPS Version Control for OS |
|The BIOS supports versions 1.1 and 1.4 of the Intel multiprocessor specification. Select the version supported by the operating system running on this computer. |
| |
|MPU-401 Configuration |
|Select Enabled to configure the MPU-401 interface. |
| |
|MPU-401 I/O Base Address |
|Select a base I/O address for the MPU-401 interface |
| |
|N |
| |
|NA# Enable |
|Selecting Enabled permits pipelining, in which the chipset signals the CPU for a new memory address before all data transfers for the current cycle are complete, resulting in |
|faster performance. |
| |
|O |
| |
|Onboard Audio Chip |
|Select Enabled to use the audio capabilities of your system. Most of the following fields do not appear when this field is Disabled. |
| |
|Onboard FDC/FDD Controller |
|Select Enabled if your system has a floppy disk controller (FDC) installed on the system board and you wish to use it. If you install an add-in FDC or the system has no floppy |
|drive, select Disabled in this field. |
| |
|Onboard IDE Controller |
|The chipset contains a PCI IDE interface with support for two IDE channels. Select Primary to activate the only primary IDE interface, if you install an add-in secondary |
|interface. Select Both to activate both interfaces, or Disabled to deactivate both interfaces, if you install both a primary and a secondary add-in IDE interface. |
| |
|Onboard Parallel Port |
|Select a logical LPT port address and corresponding interrupt for the physical parallel port. |
| |
|Onboard PCI SCSI Chip |
|Select Enabled if your system contains a built-in PCI SCSI controller. |
| |
|Onboard Serial Ports (1/2, A/B) |
|Select a logical COM port name and matching address for the first and second serial ports. Select an address and corresponding interrupt for the first and second serial ports. |
| |
|Onboard UART 1/2 |
|See Onboard Serial Ports, above. |
| |
|Onboard UART 1/2 Mode |
|See UART 2 Mode. Available modes apply to selected serial port. |
| |
|On-Chip IDE Controller |
|The integrated peripheral controller contains a IDE interface with support for two IDE channels. Select Enabled to activate the IDE interface. |
| |
|On-Chip IDE First/Second Channel |
|The chipset contains a PCI IDE interface with support for two IDE channels. Select Enabled to activate the first and/or second IDE interface. Select Disabled to deactivate an |
|interface, if you install a primary and/or secondary add-in IDE interface. |
| |
|On-Chip Local Bus IDE |
|The chipset contains an enhanced IDE interface with two IDE channels. Because each channel supports two IDE devices, the system supports a total of four IDE devices. If your |
|system board has one or two IDE connectors, this option should be Enabled. If you install an add-in IDE interface, disable one or both on-chip IDE channels. |
| |
|On-Chip PCI IDE |
|The chipset contains a PCI IDE interface with support for two IDE channels. Select Enabled to activate the IDE interface. Select Disabled to deactivate this interface, if you |
|install a primary and/or secondary add-in IDE interface. You can disable the second IDE interface separately in the IDE Second Channel Control field in the BIOS Features Setup |
|screen. |
| |
|On-Chip Primary/ Secondary PCI IDE |
|The integrated peripheral controller contains an IDE interface with support for two IDE channels. Select Enabled to activate each channel separately. |
| |
|OS Select for DRAM > 64MB |
|Select OS2 only if you are running OS/2 operating system with greater than 64 MB of RAM on your system. |
| |
|P |
| |
|Page Hit Control |
|This function is used for testing the controller. |
| |
|Page Mode Read WS |
|Select the correct cycle timing combination for the system board design and Page Mode DRAM specifications. |
| |
|Parallel Port EPP Type |
|Select EPP port type 1.7 or 1.9, as required by your parallel peripheral. |
| |
|Parallel Port Mode |
|Select an operating mode for the onboard parallel (printer) port. Select Normal, Compatible, or SPP unless you are certain your hardware and software both support one of the |
|other available modes. |
|For information about parallel port modes, see http://www.fapo.com/1284int.htm |
| |
|Passive Release |
|When Enabled, CPU to PCI bus accesses are allowed during passive release. Otherwise, the arbiter only accepts another PCI master access to local DRAM. |
| |
|PCI 2.1 Compliance |
|Select Enabled to support compliance with PCI specification version 2.1. |
| |
|PCI Arbitration Mode |
|The method by which the PCI bus determines which bus master device gains access to the bus. Typically, the system manages or arbitrates access to the PCI bus on a |
|first-come-first-served basis. When priority is rotated, once a device gains control of the bus it is assigned the lowest priority and every other device is moved up one in the|
|priority queue. |
| |
|PCI Burst |
|When Enabled, data transfers on the PCI bus, where possible, make use of the high-performance PCI burst protocol, in which greater amounts of data are transferred at a single |
|command. |
| |
|If the write transaction is a burst transaction, the information goes into the write buffer and burst transfers are later performed on the PCI bus. If the transaction is not a |
|burst, PCI write occurs immediately (after a write buffer flush). VP2 |
| |
|PCI Burst Write Combine |
|When this option is Enabled, the chipset assembles long PCI bursts from the data held in these buffers. |
| |
|PCI CLK |
|The system board designer selects whether the PCI clock is tightly synchronized with the CPU clock or is asynchronous. |
| |
|PCI Delayed Transaction |
|The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2.1. |
| |
|PCI Dynamic Bursting |
|When Enabled, every write transaction goes to the write buffer. Burstable transactions then burst on the PCI bus and nonburstable transactions do not. VP2 |
| |
|PCI Fast Back to Back Wr |
|When Enabled, the PCI bus interprets CPU read cycles as the PCI burst protocol, so back-to-back sequential CPU memory read cycles addressed to the PCI bus will be translated |
|into fast PCI burst memory cycles. |
| |
|PCI IDE 2nd Channel |
|Since your chipset supports a second IDE channel, you can use this selection to enable or disable the second channel. The second channel may connect to a CD-ROM. |
| |
|PCI IDE Controller |
|The chipset contains a PCI IDE interface that is permanently configured as the secondary IDE channel. Select Secondary to activate this IDE interface. Select Disabled to |
|deactivate this interface, if you install an add-in secondary IDE interface. |
| |
|PCI IDE IRQ Map to |
|This field lets you select PCI IDE IRQ mapping or PC AT (ISA) interrupts. If your system does not have one or two PCI IDE connectors on the system board, select values |
|according to the type of IDE interface(s) installed in your system (PCI or ISA). Standard ISA interrupts for IDE channels are IRQ14 for primary and IRQ15 for secondary. |
| |
|PCI IRQ Activated by |
|Leave the IRQ trigger set at Level unless the PCI device assigned to the interrupt specifies Edge-triggered interrupts. |
| |
|PCI Master 0 WS Write |
|When Enabled, writes to the PCI bus are executed with zero wait states. |
| |
|PCI Mem Line Read |
|When Enabled, PCI Memory Read Line commands fetch full cache lines. When Disabled, a PCI Memory Read Line command results in read partials on the CPU bus. |
| |
|PCI Mem Line Read Prefetch |
|When Enabled, PCI Memory Commands fetch a full cache line plus a prefetch of up to three additional full cache lines. Prefetching does not cross 4-KB address boundaries. When |
|Disabled, no line prefetching is performed for PCI Memory Read Line commands. This field is irrelevant if PCI Mem Line Read, above, is Disabled. |
| |
|PCI Passive Release |
|When Enabled, CPU to PCI bus accesses are allowed during passive release. Otherwise, the arbiter only accepts another PCI master access to local DRAM. |
| |
|PCI Posted Write Buffer |
|You can Enable or Disable the chipset's ability to use a buffer for posted writes initiated on the PCI bus. |
| |
|PCI Preempt Timer |
|Set the length of time (in LCLK ticks) before one PCI master preempts another when a service request is pending. |
| |
|PCI Pre-Snoop |
|Pre-snooping is a technique by which a PCI master can continue to burst to local memory until a 4K page boundary is reached rather than just a line boundary. |
| |
|PCI Read burst WS |
|Select the number of cycles allotted for a PCI master burst read. |
| |
|PCI Slot IDE 2nd Channel |
|You may separately disable the second channel on an IDE interface installed in a PCI expansion slot. |
| |
|PCI Timeout |
|When Disabled, the PCI cycles is disconnected if the first data access is not completed with 16 PCI clocks. When Enabled, the PCI cycles remains connected, even if the first |
|data access is not completed with 16 PCI clocks. |
| |
|PCI to DRAM Buffer |
|Your system supports buffered writes from the PCI bus to DRAM for greater efficiency. |
| |
|PCI to L2 Write Buffer |
|The chipset maintains its own internal buffer for PCI-to-external-cache writes. When this buffer is Enabled, PCI write cycles to the external cache are posted to the buffer, so|
|the each device can complete its cycles without waiting for the other. |
| |
|PCI Write Burst |
|When Enabled, consecutive PCI write cycles become burst cycles on the PCI bus. |
| |
|PCI Write burst WS |
|Select the number of cycles allotted for a PCI master burst write. |
| |
|PCI/VGA Palette Snoop |
|Leave this field at Disabled. |
| |
|PCI-To-CPU Write Posting |
|When this field is Enabled, writes from the PCI bus to the CPU are buffered, so the PCI bus can continue writing while the CPU is occupied with other processing. When Disabled,|
|the writes are not buffered and the PCI bus must wait until the CPU is free before starting another write cycle. |
| |
|PCI-To-DRAM Pipeline |
|DRAM optimization feature: If Enabled, full PCI-to-DRAM write pipelining is enabled. Buffers in the chipset store data written from the PCI bus to memory. When Disabled, PCI |
|writes to DRAM are limited to a single transfer per write cycle. |
| |
|Peer Concurrency |
|Peer concurrency means that more than one PCI device can be active at a time. |
| |
|Pipeline |
|Select Enabled to enable the cache pipeline function when pipelined synchronous cache SRAM is installed in the system. |
| |
|Pipeline Cache Timing |
|For a secondary cache of one bank, select Faster. For a secondary cache of two banks, select Fastest. |
| |
|Pipelined Function |
|When Enabled, the controller signals the CPU for a new memory address before all data transfers for the current cycles are complete, resulting in faster performance. |
| |
|PM Control by APM |
|If Advanced Power Management (APM) is installed on your system, selecting Yes gives better power savings. |
| |
|PM Events |
|You may disable activity monitoring of some common I/O events and interrupt requests so they do not wake up the system. The default wake-up event is keyboard activity. When On |
|(or named, in the case of LPT & COM), any activity from one of the listed system peripheral devices or IRQs wakes up the system. |
| |
|A power-management (PM) event awakens the system from, or resets activity timers for, Suspend mode. You can disable monitoring of common interrupt requests so they do not |
|generate PM events. VP2 |
| |
|PM Mode |
|Power management is configured for SMI Green mode, which is the mode required by the system CPU. |
| |
|PM wait for APM |
|If Advanced Power Management (APM) is installed on your system, selecting Yes gives better power savings. |
| |
|PnP BIOS Auto-Config |
|The Award Plug and Play BIOS can automatically configure Plug and Play-compatible devices. If you select Enabled, the Available IRQ fields disappear, because the BIOS |
|automatically handles their configuration. |
| |
|PNP OS Installed |
|Select Yes if the system operating environment is Plug-and-Play aware (e.g., Windows 95). |
| |
|Posted PCI Memory Writes |
|When this field is Enabled, writes from the PCI bus to memory are posted. This is an intermediate posting. If the CPU and PCI-to-DRAM posted write buffer in enabled, the data |
|is interleaved with CPU write data and posted a second time before being written to DRAM. |
| |
|Power Button Over Ride |
|When you select Enabled, pressing the power button for more than 4 seconds forces the system to enter the Soft-Off state when the system has "hung."