Abstract:

This term paper presents two instructions set architectures, particularly the CISC and the RISC, which have been developed as computer architects aimed for a fast, cost-effective design. Included in this paper are the arguments made for each architecture, and of some performance comparisons on RISC and CISC processors. These data are collected from various papers published concerning the RISC versus CISC discussion.

INTRODUCTION:

The advent of microprocessor and strides in integrated circuit technology improved the performance of computer system at roughly 35% per year. Mass production of lower cost microprocessors has increased the share of microprocessor based computer in the market. This new architecture of microprocessor based computers has become a true success after two major changes in computer marketplace. One is elimination of programming at the assembly language level which eliminated the need for object-code compatibility. So any architecture could reuse the source code written in higher level languages. The second is the creation of standardized vendor-independent operating systems like UNIX and its clones like Linux which lowered the cost and risk of bringing out a new architecture. The open standard of systems eased the new computer architecture introduction. The above improvements helped evolve computer architecture from general microprocessor based architecture to a new set of architectures called RISC architectures. RISC stands for Reduced Instruction Set Computer (employ simpler instruction set). CISC stands for Complex Instruction Set Computer (employs rich and complex set of instructions).

During the 1980’s, RISC was presented as a solution to derive more instruction set power out of a computer. It is not just a means to reduce the instruction set, but it is a way of significantly enhancing the performance of a system while having minimal costs compared to that of a CISC implementation.

Nowadays RISC and CISC are quite popular topics on the net. Every time Intel (CISC) or Apple (RISC) introduces a new CPU, the topic pops up again.

What is CISC?

CISC is an acronym for Complex Instruction Set Computer and are chips that are easy to program and which make efficient use of memory. Since the earliest machines were programmed in assembly language and memory was slow and expensive, the CISC philosophy made sense, and was commonly implemented in such large computers as the PDP-11 and the DEC system 10 and 20 machines. Most common microprocessor designs such as the Intel 80x86 and Motorola 68K series followed the CISC philosophy. CISC was developed to make compiler development simpler. It shifts most of the burden of generating machine instructions to the processor. For example, instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this. But recent changes in software and hardware technology have forced a re-examination of CISC and many modern CISC processors are hybrids, implementing many RISC principles.

CISC Attributes:

The design constraints that led to the development of CISC (small amounts of slow memory and fact that most early machines were programmed in assembly language) give CISC instructions sets some common characteristics: a) A 2-operand format, where instructions have a source and a destination. Register to register, register to memory, and memory to register commands. Multiple addressing modes for memory, including specialized modes for indexing through arrays b) Variable length instructions where the length often varies according to the addressing mode c) Because of complex instructions, difficult targets are required for optimizing compilers. d) Instructions require multiple clock cycles to execute.

E.g. Pentium is considered a modern CISC processor

What’s the RISC?

RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. Though it may seem less effective for a computational task to be executed with many simple instructions rather than a few complex instructions, the simple instructions take fairly the same amount of time to be performed, making them ideal for pipelining

RISC Attributes:
a) Single-cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called PIPELINING
b) PIPELINING: a technique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions.
c) Large number of registers: the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory .
d) Relatively few instructions and addressing modes makes it easy for the control unit to interpret instructions.
e) Fixed instruction format makes decoding of instructions fast and easy
f) More compile-time effort offers opportunity to explicitly move static run-time complexity into compiler

Arguments for RISC and CISC:

Factor | RISC | CISC | Implementation Feasibility | Simple architecture makes RISC being realizable at earlier date | Complex architecture make it difficult to implement on a single chip with the design rules at that time | Design Time | Design that can be easier to design and debug can use much superior technology than design that takes a long time to implement | Lengthened design time may lead to problems such as having a machine with an old technology, or trying to predict future technology and have a go at attempting to build that technology | Speed | Gains in speed from better use of chip area and from simple design – with less instructions and addressing modes, these would lead to a less complicated control structure | More instructions and addressing modes result to complicated control structure | Use of Chip Area | Area left on chip due to simple design may be used to make RISC improve performance even more | Complex design leaves no room on chip for enhancements |

The Counter-arguments for RISC :

These are counter-arguments made against the RISC architecture.

a) False Dichotomy: Complexity of a machine cannot be measured by instruction count alone, and cannot be the only decisive factor for categorizing a machine as RISC or CISC.
b) Lengthy Design Time: Designing products for a high-volume manufacturing company has time-consuming processes that do not exist in a small company .There are differences in the design environments for academic research and from companies that produce commercial products.
c) Language Multiplicity: An instruction set that supports only a particular language can make the implementation of a different language difficult. Designing a machine for a particular language is different from designing one that accepts a wide range of languages.
d) Instruction Execution Time: Frequency of execution of instruction must not be the focus of attention, but also to the length of time an instruction is executed .
e) Micro benchmarks: Small programs (e.g. Towers of Hanoi, Fibonacci) that have been used to measure performance on RISC machines have a narrow scope on functions, although they execute millions of instructions. These benchmarks do not represent actual applications used in the industry.
f) Specialized Hardware: Higher-level hardware-software interface has the advantage of possible use of specialized hardware for better performance.
g) Chip Usage: Chip area left by RISC’s simple design can indeed be used by adding enhancements for better performance. But these enhancements are not inherent in RISC architectures.
h) Ignored Operating System: The system is not only made of software, hardware and application code. The operating system overhead and needs have been given too little attention in RISC research.
i) More Instructions: Breaking up complex instructions of CISC results to more instructions per program.

RISC vs. CISC :

There is still considerable controversy among experts about which architecture is better. Some say that RISC is cheaper and faster and therefor the architecture of the future. Others note that by making the hardware simpler, RISC puts a greater burden on the software. Software needs to become more complex. Software developers need to write more lines for the same tasks. Therefore they argue that RISC is not the architecture of the future, since conventional CISC chips are becoming faster and cheaper anyway. RISC has now existed more than 10 years and hasn't been able to kick CISC out of the market. If we forget about the embedded market and mainly look at the market for PC's, workstations and servers I guess a least 75% of the processors are based on the CISC architecture. Most of them the x86 standard (Intel, AMD, etc.), but even in the mainframe territory CISC is dominant via the IBM/390 chip. Looks like CISC is here to stay …

Is RISC than really not better?

The answer isn't quite that simple. RISC and CISC architectures are becoming more and more alike. Many of today's RISC chips support just as many instructions as yesterday's CISC chips. The PowerPC 601, for example, supports more instructions than the Pentium. Yet the 601 is considered a RISC chip, while the Pentium is definitely CISC. Furthermore today's CISC chips use many techniques formerly associated with RISC chips. So simply said: RISC and CISC are growing to each other.

X 86:

An important factor is also that the x 86 standards, as used by for instance Intel and AMD, is based on CISC architecture. X86 is the standard for home based PC's. Windows 95 and 98 won't run at any other platform. Therefore companies like AMD an Intel will not abandoning the x 86 markets just overnight even if RISC was more powerful, changing their chips in such a way that on the outside they stay compatible with the CISC x86standard, but use RISC architecture inside is difficult and gives all kinds of overhead which could undo all the possible gains. Nevertheless Intel and AMD are doing this more or less with their current CPU's. Most acceleration mechanisms available to RISC CPUs are now available to the x86 CPU's as well. Since in the x86 the competition is killing, prices are low, even lower than for most RISC CPU's. Although RISC prices are dropping also.
For instance, SUN Ultra SPARC is still more expensive than an equal performing PII workstation which is equal in terms of integer performance. In the floating point-area RISC still holds the crown. However CISC's 7th generation x86 chips like the K7 will catch up with that. The one exception to this might be the Alpha EV-6. Those machines are overall about twice as fast as the fastest x86 CPU available. However this Alpha chip costs about €20000, not something we're willing to pay for a home PC. Maybe interesting to mention is that it's no coincidence that AMD's K7 is developed in co-operation with Alpha and is for al large part based on the same Alpha EV-6 technology.

EPIC:

The biggest threat for CISC and RISC might not be each other, but a new technology called EPIC.EPIC stands for Explicitly Parallel Instruction Computing. Like the word parallel already says EPIC can do many instruction executions in parallel to one another. EPIC is a created by Intel and is in a way a combination of both CISC and RISC. This will in theory allow the processing of Windows-based as well as UNIX-based applications by the same CPU It will not be until 2000 before we can see an EPIC chip. Intel is working on it under code-name Merced . Microsoft is already developing their Win64 standard for it. Like the name says, Merced will be a 64-bit chip. If Intel's EPIC architecture is successful, it might be the biggest thread for RISC. All of the big CPU manufactures but Sun and Motorola are now selling x86-based products, and some are just waiting for Merced to come out (HP, SGI). Because of the x86 market it is not likely that CISC will die soon, but RISC may. So the future might bring EPIC processors and more CISC processors, while the RISC processors are becoming extinct.

Modern Day Advancement:

CISC and RISC Convergence:

State of the art processor technology has changed significantly since RISC chips were first introduced in the early '80s. Because a number of advancements are used by both RISC and CISC processors, the lines between the two architectures have begun to blur. In fact, the two architectures almost seem to have adopted the strategies of the other. Because processor speeds have increased, CISC chips are now able to execute more than one instruction within a single clock. This also allows CISC chips to make use of pipelining. With other technological improvements, it is now possible to fit many more transistors on a single chip. This gives RISC processors enough space to incorporate more complicated, CISC-like commands. RISC chips also make use of more complicated hardware, making use of extra function units for superscalar execution. All of these factors have led some groups to argue that we are now in a "post-RISC" era, in which the two styles have become so similar that distinguishing between them is no longer relevant. However, it should be noted that RISC chips still retain some important traits. RISC chips strictly utilize uniform, single-cycle instructions. They also retain the register-to-register, load/store architecture. And despite their extended instruction sets, RISC chips still have a large number of general purpose registers.

Conclusion:

The difference between RISC and CISC chips is getting smaller and smaller. What count is how fast a chip can execute the instructions it is given and how well it runs existing software. Today, both RISC and CISC manufacturers are doing everything to get an edge on the competition. The future might not bring victory to one of them, but makes both extinct. EPIC might make first RISC obsolete and later CISC too.

References:

a) www.sunderland.ac.uk/~ts0jti/comparch/ciscrisc.html. b) www.visionengineer.com/comp/why_cisc.shtml. c) D. Bhandarkar, “RISC versus CISC: a tale of two chips,” Computer Architecture News, 1994. d) www.heyrick.co.uk/assembler/riscvcisc.html.