...The CPU is a very important part of any computer. This part of the computer fetches the data, performs operations to the data and stores the data (the fetch execute cycle). The Workshop PC has an “AMD Athlon 64x2 4400+” processor these processors were first implemented into machines in 2005 meaning it has a possibility of being up to 6 years old. This processor has 2 cores meaning that the processor can receive 2 data strings at once rather than individually receiving them. Having a dual core processor is better than just a single core due to the fact that it can handle more data at once. But there are also newer quad core processors which would be much better than this processor. This processor has a core speed of 2294.4 MHZ this seems to be a reasonable speed for a processor to run at. It also has a multiplier of 11.5 having a multiplier of 11.5 means that there will be 11.5 cycles for every external clock cycle. The processor has a bus speed of 199.5MHz, the bus speed refers to how much data can travel across the bus at any one specific time. The speed of the bus can drastically affect the computers performance as the bus is essential for the transfer of data. The processor requires 1.350v of power to run it, this is relatively high compared to a lot of modern CPU’s that are available. The AMD Athlon has cache L1 data and L1 Inst of 2 x 64Kbytes and has L2 of 2 x 512Kbytes. The amount of cache memory is important as the cache memory stores data from the most used memory locations...
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...On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-Core Interconnects George Nychis†, Chris Fallin†, Thomas Moscibroda§, Onur Mutlu†, Srinivasan Seshan† † Carnegie Mellon University {gnychis,cfallin,onur,srini}@cmu.edu moscitho@microsoft.com § Microsoft Research Asia ABSTRACT In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting similarities and differences between the two. As an initial case study, we examine network congestion in bufferless NoCs. We show that congestion manifests itself differently in a NoC than in traditional networks. Network congestion reduces system throughput in congested workloads for smaller NoCs (16 and 64 nodes), and limits the scalability of larger bufferless NoCs (256 to 4096 nodes) even when traffic has locality (e.g., when an application’s required data is mapped nearby to its core in the network). We propose a new source throttlingbased congestion control mechanism with application-level awareness that reduces network congestion to improve system performance. Our mechanism improves system performance by up to 28% (15% on average in congested workloads) in smaller NoCs, achieves linear throughput scaling in NoCs up to 4096 cores (attaining similar performance scalability to a NoC with large buffers), and reduces power consumption by up to 20%. Thus, we show an effective application of a network-level concept, congestion control, to a class...
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...An Analysis of Linux Scalability to Many Cores Silas Boyd-Wickizer, Austin T. Clements, Yandong Mao, Aleksey Pesterev, M. Frans Kaashoek, Robert Morris, and Nickolai Zeldovich MIT CSAIL A BSTRACT This paper analyzes the scalability of seven system applications (Exim, memcached, Apache, PostgreSQL, gmake, Psearchy, and MapReduce) running on Linux on a 48core computer. Except for gmake, all applications trigger scalability bottlenecks inside a recent Linux kernel. Using mostly standard parallel programming techniques— this paper introduces one new technique, sloppy counters—these bottlenecks can be removed from the kernel or avoided by changing the applications slightly. Modifying the kernel required in total 3002 lines of code changes. A speculative conclusion from this analysis is that there is no scalability reason to give up on traditional operating system organizations just yet. but the other applications scale poorly, performing much less work per core with 48 cores than with one core. We attempt to understand and fix the scalability problems, by modifying either the applications or the Linux kernel. We then iterate, since fixing one scalability problem usually exposes further ones. The end result for each application is either good scalability on 48 cores, or attribution of non-scalability to a hard-to-fix problem with the application, the Linux kernel, or the underlying hardware. The analysis of whether the kernel design is compatible with scaling rests on the extent to which...
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...A Tale of Two Processors: Revisiting the RISC-CISC Debate Ciji Isen1, Lizy John1, and Eugene John2 1 ECE Department, The University of Texas at Austin ECE Department, The University of Texas at San Antonio {isen,ljohn}@ece.utexas.edu, ejohn@utsa.edu 2 Abstract. The contentious debates between RISC and CISC have died down, and a CISC ISA, the x86 continues to be popular. Nowadays, processors with CISC-ISAs translate the CISC instructions into RISC style micro-operations (eg: uops of Intel and ROPS of AMD). The use of the uops (or ROPS) allows the use of RISC-style execution cores, and use of various micro-architectural techniques that can be easily implemented in RISC cores. This can easily allow CISC processors to approach RISC performance. However, CISC ISAs do have the additional burden of translating instructions to micro-operations. In a 1991 study between VAX and MIPS, Bhandarkar and Clark showed that after canceling out the code size advantage of CISC and the CPI advantage of RISC, the MIPS processor had an average 2.7x advantage over the studied CISC processor (VAX). A 1997 study on Alpha 21064 and the Intel Pentium Pro still showed 5% to 200% advantage for RISC for various SPEC CPU95 programs. A decade later and after introduction of interesting techniques such as fusion of micro-operations in the x86, we set off to compare a recent RISC and a recent CISC processor, the IBM POWER5+ and the Intel Woodcrest. We find that the SPEC CPU2006 programs are divided between...
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...INTRODUCTION: Shared memory is a memory that can be used by multiple programs to avoid redundant copies or to provide communication among them. In other words we can say that, it is a technique, in this exchanging of data in process of program is done more quickly than by reading and writing using the services of OS. It is the fastest form of IPC available. A number of basic issues in the design of shared memory system have to be taken into consideration. Once the memory is mapped into the address space of the processes that are sharing the memory region, no kernel involvement occurs in passing the data between the processes. It refers to a multiprocessing design where several processors access globally shared memory. These include access control, synchronization, protection and security. Access control determines which process accesses are possible to which recourses. Synchronization constraints limit the time of access from sharing processes to shared resources. Protection is a system feature that prevents processes from making arbitrary access to resources belong to other processes. At the memory module the requests arrive through its two ports. The simplest shared memory system consists of one memory module that can be accessed from two processors. Classification of shared memory: Depending on the interconnection of network, a shared memory leads to system can be classified as :- • UMA: - Shared memory...
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...(SEC) cartridge -Dual inline package (DIP) -Flip chip-PGA (FC-PGA) package -Pin grid array (PGA) Central Processing Unit (CPU)? -Interprets and carries out basic instructions that operate a computer. -Also called the processor. Components of the CPU? -Control Unit -Arithmetic/Logic Unit (ALU) -Register Control Unit? -Directs and coordinates operations in computer. Control unit repeats four basic operations: -Fetch-obtain program instruction or data item from memory. (Taking Out From Memory) -Decode-Translate instruction into commands. (Understand It) -Execute-Carry out command. (Writing out It) -Store-Write result to memory. (Write the Result) Machine Cycle? -Four operations of the CPU comprise a machine cycle. -Also called instruction cycle. -Instruction time (I-time)-time taken to fetch and decode -Execution time (e-time)-time taken to execute and store. (I-time) (E-time) Fetch Decode Execute Store (Completed 1 Instruction) CPU’s Speed measured? -According to how many millions of instructions per second (MIPS) it can process. Two designs used for the CPU? CISC (complex instruction set computing) -Support large number of instructions -CPU executes complex instructions more quickly. RISC (reduced instruction set computing) -Supports smaller number of instructions -CPU executes simple instructions more quickly....
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...Oscar Martinez NT 1110 Lab 4 Task 1: LGA 1156, also known as Socket H[2][3] or H1, is an Intel desktop CPU socket. LGA stands for land grid array. Its incompatible successor is LGA 1155. LGA 1156, along with LGA 1366, were designed to replace LGA 775. Whereas LGA 775 processors connect to a northbridge using the Front Side Bus, LGA 1156 processors integrate the features traditionally located on a northbridge on the processor itself. The LGA 1156 socket allows the following connections to be made from the processor to the rest of the system: PCI-Express 2.0 ×16 for communication with a graphics card. Some processors allow this connection to be divided into two ×8 lanes to connect two graphics cards. Some motherboard manufacturers use Nvidia's NF200 chip to allow even more graphics cards to be used. DMI for communication with the Platform Controller Hub (PCH). This consists of a PCI-Express 2.0 ×4 connection. FDI for communication with the PCH. This consists of two DisplayPort connections. Two memory channels for communication with DDR3 SDRAM. The clock speed of the memory that is supported will depend on the processor. LGA 1156 socket and processors were discontinued sometime in 2012, along with LGA 1366.[4] Supported processors Code name | Brand name | Model (list) | Frequency | Cores/Threads | Max...
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...Task 1: 1. Which is used to rewrite the M-BIOS chip if corrupted a. The B-BIOS Chip - the backup BIOS 2. LGA 1156 connector b. Processors used with it i. Intel Core i3, Core i5, Core i7, and Xeon 300 c. What is purpose ii. Connects motherboard to the CPU 3. Intel H55 chipset d. Processors iii. Intel Core i7-800, Core i5, Core i3 e. Purpose iv. Provides the interface for the PCIe lanes on the motherboard 4. Interesting information on Gigabyte GA-H55M-UD2H motherboard f. •Unique On/Off Charge delivers the best recharging capability to iPad, iPhone and iPod Touch g. •3x USB power delivery for greater compatibility and extra power for USB devices h. •Leading quality standard of Ultra Durable™ 3 classic technology with 2oz copper PCB design i. •Innovative Smart 6 technology for smarter PC management j. •Supports Intel Core™ i7/ Core™ i5/ Core™ i3 LGA1156 processors k. •Dynamic Energy Saver™ 2 technology enables best energy efficiency l. •2 PCI-E 2.0 x16 graphics interface(x16+x4) with ATI CrossFireX support for ultimate graphics performance (all information for task #1 procedure #4 is from Gigabyte.com website) Task 2: 1. Examine motherboard 2. AMD 770 Northbridge Chipset a. What processors used i. Phenom b. What is purpose ii. Gaming 3. AMD SB710 Southbridge Chipset c. Processors used ...
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...NT1110 Motherboard Components and Form Factors LGA 1156: LGA 1156 works with Intel Celeron, core i3, i5, i7, Pentium, and the Intel Xeon. Nehalem The LGA 1156 connector is designed to connect the 1156 pin processor. LGA means land grid array. The H55: utilizes the 1st gen. core i CPUs. The H55 is used with a 1st generation Intel Core processor like the Intel Core i5-660. Purpose to integrate the PCI Express on the motherboard. The Gigabyte GA-H55M-UD2H motherboard: has unique On/Off Charge, PC can be on or off to charge cell phones, IPads, IPods, 3x USB power delivery for greater compatibility and extra power for USB devices, Patented DualBIOS, Easy BIOS setting for GPU overclocking, supports 6 devices without the need for drivers to be installed before being fully operational. AMD 770 Northbridge Chipset.: AMD AM3 Processor Support Based on the AMD 770 chipset, the MSI 770-G45 AMD motherboard supports AMD's latest generation Phenom II processors, as well as Athlon II and Sempron 100 series processors in AM3 socket. The purpose of the 770 Northbridge chipset on the motherboard is to link the computer system's hardware to the processor. Processors used in a AMD SB710 Southbridge Chipset: Socket AM3/AM2 Processors: AMD Turion II Neo, AMD Athlon, II Neo Processors (ASB2), AMD Turion Neo, AMD Athlon Neo, and AMD Sempron Processors (ASB1) The purpose of the motherboard for the AMD SB710 Southbrdge chipset is to control the processes that are going...
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...[Type the company name] | REPORT | SWEL: Hardware Cache Coherence Protocols to Map Shared Data onto Shared Caches | | Asadullah | 12/15/2013 | … | Contents Abstract 3 Introduction 3 Proposed Solution (SWEL) 5 Optimizations of SWEL 6 Dynamically Tuned RSWEL 7 Implementation 7 Experiment and Results 7 Conclusion 10 References 10 Abstract Shared Memory Multi processors require cache coherence in order to keep cached values updated while performing operations. Snooping and directory based protocols are two well known standards of cache coherence. However both of them possess some problems. Snooping protocol is not scalable and is only suitable for systems of 2 to 8 SMP’s. Whereas directory based protocol gives rise to memory overhead when there are too many sharers of a particular block. We propose a novel protocol for cache coherence that exploits the private block of memory. Coherence protocol invoked only for shared data blocks. This reduces network and storage overhead and it does not compromise with scalability as well. Introduction Shared Memory Multi Processor has multiple processors with their caches and a global memory. Memory is connected with processors and a global address space is maintained. When a block of data is cached by one processor, it said to private. The block of data is called shared if more than one processor cache the same block of data. In later case it necessary that read operation of any processor should return...
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...(LATEST COMPUTER HARDWARE and LATEST MICROPROCESSOR) LATEST COMPUTER HARDWARE 1. Microsoft Desktop 3000 Reliable 2.4-GHz Wireless Enjoy the 2.4-gigahertz (GHz) wireless technology, which delivers a reliable connection with up to a 30-foot range, with virtually no interference. BlueTrack Technology Take advantage of BlueTrack Technology, which combines the power of optical with the precision of laser for remarkable tracking on virtually any surface. Snap-in Mini-Transceiver Plug the wireless receiver into your computer’s USB port when you’re ready to work. Then snap it into the bottom of your mouse when you travel. Media Center Control media playback from your keyboard. Hot Keys Gain one-touch access to Windows Media Player, email, home, calculator, My Documents, zoom, instant messaging and photos. Tilt Wheel and More Navigate fluidly with four-way scroll, five programmable buttons, rubber side grips and magnifier. Device Stage Quickly and easily access common tasks, including product information, registration, settings, and more for popular devices such as cell phones, cameras, printers, and mouse, keyboard, and webcam products. Battery Status Indicators Avoid being caught with a dead battery. The battery status indicator glows red when the battery is running low. PRICE: $36.99 2. Alienware TactX Headset Functionality: Obviously ideal for gaming, the Alienware TactX VoIP headset connects...
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...Chapter 4 Objectives Differentiate among various styles Differentiate among various styles of system units of system units Identify chips, adapter cards, and other Identify chips, adapter cards, and other components of aamotherboard components of motherboard Describe the components of aaprocessor and how Describe the components of processor and how they complete aamachine cycle they complete machine cycle Identify characteristics of various personal Identify characteristics of various personal computer processors on the market today computer processors on the market today Define aabit and describe how aaseries of bits Define bit and describe how series of bits represents data represents data Explain how programs transfer in Explain how programs transfer in and out of memory and out of memory Differentiate among the various Differentiate among the various types of memory types of memory Describe the types of expansion slots and Describe the types of expansion slots and adapter cards adapter cards Explain the difference among aaserial port, aa Explain the difference among serial port, parallel port, aaUSB port, and other ports parallel port, USB port, and other ports Describe how buses contribute to aa Describe how buses contribute to computer’s processing speed computer’s processing speed Identify components in mobile computers Identify components in mobile computers and mobile devices and mobile devices Chapter 4 The Components of the System Unit Next The System Unit ...
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...features preprocessing techniques, exploits sparsity, and offers primal and dual solving routines. It can be used as a standalone solver reading MPS or LP format files as well as embedded into other programs via a C++ class library. Sphinx is an open source full text search server, designed from the ground up with performance, relevance (aka search quality), and integration simplicity in mind. It's written in C++ and works on Linux (RedHat, Ubuntu, etc), Windows, MacOS, Solaris, FreeBSD, and a few other systems (Sphinx Technologies, 2013). NAMD is a parallel molecular dynamics code designed for high-performance simulation of large bimolecular systems. NAMD uses the popular molecular graphics program VMD for simulation setup and trajectory analysis, but is also file-compatible with AMBER, CHARMM, and X-PLOR. NAMD is distributed free of charge with source code (NIGMS, 2013). Examine the authors’ findings Soplex and Sphinx ran in a memory domain, while Gamess and Namd shared another...
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...Assignment 2: Multiprocessing MSMP and SMP Master-slave multiprocessing, or MSMP, is when one CPU (the master) controls the system, all resources and scheduling. Only this master can execute the operating system. The other CPU’s are slaves that perform all of the work assigned by the master (Englander, 2009). This configuration is not widely used anymore. Conversely, Symmetrical multiprocessing, or SMP, is where each CPU has the same access to the operating system, all resources, and memory. In this set-up, each CPU is identical (Englander, 2009). In a master-slave configuration, the master holds the memory and is the one who allocates the needed memory to the other CPU’s. The problem with this is that the master CPU becomes bottlenecked. A solution of this could be to enable direct access memory (DMA). DMA is an operation in which data is copied from one resource to another resource in a computer system without the involvement of the CPU (TechTerms, 2013). An example would be data being sent directly from an attached device, like a flash drive, directly to the memory. The microprocessor does not have to do anything, and therefore speeds up the overall computer operation. In SMP configuration, memory access could present a problem. All the memory access is posted to the same memory bus. If there are only a handful of CPU’s, this is fine. However, when there are larger numbers of CPU’s competing for access (anything over about 12), this could bottleneck and present...
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...an interrupt or a trap, which caused either by an error or by a specific request from a user program that an OS service be performed . * Dual-mode Operation allows OS to protect itself and other system components whereas Multimode Operation increasingly CPUs support multi-mode operations. * System call provides the means for a user program to ask OS to perform OS tasks on the user program’s behalf. When a system callis executed, it is treated by H/W as a S/W interrupt. * Timer protects CPU resource from getting stuck by a user program. To ensure OS maintains control over the CPU, a timer can be set to interrupt the computer after a specified period. Use it to prevent a user program from running too long. 1.6 * A process is a program in execution. It is a unit of work in the system. A program by itself is not a process. It is a passive entity, like the contents of a file stored on disk, whereas a process is an active entity. 1.7 * To improve CPU utilization and responsive time, general-purpose computers must keep several programs in memory, creating a need for memory management. 1.8 * OS provides a uniform, logical view of information storage. * Caching is an important principle, performed at many levels in a computer and an information in use copied from slower to faster storage temporarily. There are Hardware cache and Software-controlled cache. * Cache Coherency in Multiprocessor Environment. Must make sure that an update to...
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