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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2014

Active Mode Subclock Power Gating
Jatin N. Mistry, Member, IEEE, James Myers, Bashir M. Al-Hashimi, Fellow, IEEE,
David Flynn, Senior Member, IEEE, John Biggs, Member, IEEE, and Geoff V. Merrett, Member, IEEE

Abstract— This paper presents a technique, called subclock power gating, for reducing leakage power during the active mode in low performance, energy-constrained applications. The proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock period (subclock) and 2) reducing the virtual supply to less than Vth rather than shutting down completely as is the case in conventional power gating. To achieve this reduced voltage, a pair of nMOS and pMOS transistors are used at the head and foot of the power gated logic for symmetric virtual rail clamping of the power and ground supplies. The subclock power gating technique has been validated by incorporating it with an ARM Cortex-M0 microprocessor, which was fabricated in a 65-nm process. Two sets of experiments are done: the first experimentally validates the functionality of the proposed technique in the fabricated test chip and the second investigates the utility of the proposed technique in example applications. Measured results from the fabricated chip show 27% power saving during the active mode for an example wireless sensor node application when compared with the same microprocessor without subclock power gating.
Index Terms— Active mode, embedded microprocessors, energy harvesting, leakage control, low power, power gating, subthreshold. I. I NTRODUCTION

L

EAKAGE power can be as dominant as dynamic power below 65 nm and poses a large source of power consumption in digital circuits during the active mode [1], i.e., when the digital circuit is doing useful work. A number of techniques have been proposed for reducing active leakage power dissipation. These include dual threshold logic [2] which uses high threshold voltage logic gates on noncritical timing paths and adaptive body biasing [3], which raises or lowers the threshold voltage of transistors for active power management. The effectiveness of power gating to reduce leakage power has also been demonstrated during active mode.
A finer granularity power gating has been proposed in [4], which involves disabling executional units during active mode.
Similarly, a method of power gating part of a multiplier depending on the data width during run-time was proposed in [5]. Recent work has demonstrated the use of power gating on a granularity akin to clock gating. The use of the clock

Manuscript received December 14, 2012; revised June 26, 2013; accepted
August 20, 2013. Date of publication September 20, 2013; date of current version August 21, 2014.
J. Mistry, J. Myers, D. Flynn, and J. Biggs are with ARM Ltd., Cambridge
CB1 9NJ, U.K. (e-mail: jatin.mistry@arm.com; james.myers@arm.com; david.flynn@arm.com; john.biggs@arm.com).
B. M. Al-Hashimi and G. V. Merrett are with the School of Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ,
U.K. (e-mail: bmah@ecs.soton.ac.uk; gvm@ecs.soton.ac.uk).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2013.2280886

enables signal to power gate an integer execution core was shown in [6]. On the other hand, the use of the clock enable signals to power gate the fan-in logic of the clock-gated registers was shown in [7]. All these methods attempt to reduce power with minimal impact on maximum clock frequency.
In some current and emerging applications such as wireless sensor nodes and biomedical sensor applications, performance is not critical (10–100s kHz) whereas power and energy is the primary design goal (10–100s µW). Recent work has demonstrated the use of aggressive voltage scaling, known as subthreshold operation, to improve energy efficiency with impact on performance [8]. This technique, however, has two critical barriers to its adoption: process-related variability, which affects circuit reliability, and the complex design flow required for implementation [8]. Instead, to avoid this complexity, active power reduction is primarily targeted through choice of a low super threshold voltage and low clock frequency in some applications. Examples of this principal are reported in [9], which utilizes a Texas Instruments MSP430 [10] at
1.8 V and uses its 32 kHz mode of operation for device control consuming 300 µW. Similarly, an ASIC for wireless sensor nodes, which operates at 1 V and 10–100 kHz, is reported in [11] and an ASIC for wireless monitoring of an Electrocardiography (ECG) signal that operates at 1.1 V and 32 kHz is reported in [12]. Although the active leakage power reduction techniques described above in [4]–[7] are successful over multiple clock cycles, in applications where low performance is appropriate, leakage power dissipation becomes an increasing problem within the clock period due to idle combinational logic. As the clock frequency is reduced at a fixed Vdd , the clock period becomes longer than the evaluation time of the next state thereby increasing idle time of the combinational logic.
In this paper, we propose a technique, called subclock power gating (SCPG), targeted at applications that demand low power where performance is not a primary concern. The techniques capitalizes on the increased idle time of combinational logic, which results from low performance operation at a fixed Vdd .
Power reduction is achieved by power gating within the clock period (subclock) to reduce leakage power during the active mode. This is unlike previous active mode power gating techniques where the power is shut down over multiple clock cycles [5], [6]. Rather than power gating completely, which we refer to as shutdown power gating, the proposed technique provides a less than Vth voltage across the combinational logic
(referred to in literature as subthreshold) to minimize power mode transition energy overheads. To generate this voltage, symmetric virtual rail clamping of both the power (Vdd ) and ground (Vss) supplies is proposed and can be achieved

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through the use of both an nMOS and pMOS transistor at the head and foot of the power gated logic. The rest of this paper is organized as follows. Section II introduces the symmetric virtual rail clamping technique and compares the wake-up energy cost with two other power gating techniques.
Section III shows how the proposed SCPG technique can minimize active leakage. Sections IV and V describe the implementation and experimental validation of the technique.
Conclusions are presented in Section VI.
II. WAKE -U P E NERGY C OST OF D IFFERENT P OWER
G ATING A PPROACHES
Before discussing SCPG, the energy cost of wake-up power mode transitions (moving from the sleep to active mode) is considered for three different power gating techniques: traditional shutdown power gating [13], virtual rail clamping [14], and symmetric virtual rail clamping, which is introduced in this paper. In shutdown power gating, the energy overhead of moving between power modes is dominated by the recharging of the virtual supply rail and glitching of internal signals resulting from the reevaluation of logic cones [15]. Recharging of the virtual supply rail in power gating is a discernable energy overhead, but it has recently been reported that logic reevaluation and glitching account for 75.7% of the wake-up energy [15]. These energy overheads stem from the supply rail being fully discharged and subsequent loss of valid logic gate outputs. In traditional applications of shutdown power gating during standby mode [13], the wake-up energy associated with moving between power modes (E oh ) is generally negligible; however, as the length of the idle period becomes shorter, this overhead becomes comparable with the energy saved (E sav ).
In applications of active-mode power gating with short idle periods, such as SCPG, which is proposed in Section III, a technique that minimizes E oh is preferable to improve energy efficiency. Virtual rail clamping has been proposed as a way to maintain a voltage across the power gated logic to retain register state [14], but maintaining a voltage across the power gated logic has been proven to reduce the recharge, glitching, and wake-up cost associated with power gating as valid logic outputs are maintained [16]–[18]. An inverter employing virtual rail clamping is demonstrated in Fig. 1(a) where a pair of nMOS and pMOS transistors are used at the head of the power gated logic to enable reduction in the supply voltage.
In this circuit, the pMOS transistor, marked as Sleep, is a conventional power gating transistor and the nMOS transistor, marked as Ret, is used to clamp the virtual rail. When Sleep and Ret are logic 1 the V Vdd rail is reduced to Vdd − Vthn where Vthn is the threshold voltage of the nMOS transistor.
Using an implementation where the wells are kept always on, the inverter’s pMOS transistor can additionally benefit from reverse body biasing (RBB) by connecting its body to Vdd , as shown. Although the effectiveness of RBB in newer technologies is known to be limited [19], the Vthn potential across Vbs induces an increase in the threshold voltage of the pMOS transistor due to the body effect providing a further reduction in subthreshold leakage currents [6]. Using MOS

Fig. 1. Inverter with (a) single virtual rail clamping [14] and (b) proposed symmetrical virtual rail clamping.

transistors to implement the virtual rail clamping also has the added advantage of being able to achieve shutdown power gating by forcing Sleep to logic 1 and Ret to logic 0.
Virtual rail clamping enables a single threshold voltage drop reduction across the power gated logic, but to maximize leakage power savings of the power gated logic, it is desirable to reduce the clamped voltage by more than a single threshold voltage, since power is the product of voltage and current [20].
Multiple nMOS transistors placed in series at the head of the power gated logic can enable this, however, we choose to mirror the Vdd virtual rail clamping on the Vss supply rail.
This proposed symmetric virtual rail clamping technique is shown in Fig. 1(b), where there is now a pair of nMOS and pMOS transistors at the head and foot of the example inverter circuit. When Sleep and Ret are logic 1 (and thus nSleep and nRet are logic 0) the V Vdd is clamped to Vdd − Vthn and the
V Vss is clamped to Vss + Vthp . The result is a much more aggressive reduction in voltage across the power gated logic but also has three advantages over single rail clamping [14].
Firstly the charge that is stored in the V Vdd supply rail is recycled to charge up the V Vss supply rail in the sleep mode [21] achieving greater reduction in supply voltage in

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TABLE I
R ING O SCILLATOR WAKE -U P E NERGY, S TANDBY L EAKAGE ,
AND

Fig. 2. Symmetric virtual rail clamping effect on (a) Vds reduction speed in
101 stage ring oscillator and (b) minimum clamped voltage four-input NOR gate. the same time frame at lower energy cost to single virtual rail clamping. This is shown in Fig. 2(a) from simulation on a 101 stage ring oscillator, where 30% greater reduction in
Vds (the effective voltage between the virtual supply rails) is observed for symmetric virtual rail clamping over the same period of time. Secondly, using an implementation where the wells are always powered, both the body of the pMOS and nMOS transistors in the power gated circuit can be connected to the true supplies achieving a Vth reverse body bias on all the transistors in the circuit, reducing leakage further. Thirdly, the symmetric RBB ensures better equality of nMOS and pMOS drive strength degradation, as strong RBB on the pMOS transistor from single rail clamping [Fig. 1(a)], can result in poor logic 1 drive. This is because when a gate’s supply voltage is lowered and threshold voltage is increased, the Ion current of the transistors degrades and can become comparable with the Ioff current, resulting in a battle between the ON/ OFF transistors to maintain the correct output voltage [8]. It is known that NOR and NAND gates suffer the greatest effects of this because of large numbers of parallel transistors in the logic gates [8]. Consequently, to observe the benefit of symmetric clamping over single rail clamping, a four-input
NOR gate ( NOR4) from a 90-nm gate library was simulated with both techniques. Fig. 2(b) shows the percentage deviation of a logic 1 output with respect to clamped Vds in both

WAKE -U P T IME

cases. As can be seen, the reverse body biasing used on only the pMOS transistors in virtual rail clamping causes the
NOR4 gate output to sharply deviate at supply voltages below approximately 300 mV. Conversely, the symmetric virtual rail clamping enables the NOR4 gate to hold its output for supply voltages down to approximately 200 mV. In addition to the clamped voltage, independent control of Sleep, Ret, nSleep, and nRet in Fig. 1(b) can be used to achieve full shutdown power gating.
To quantify the wake-up energy cost of shutdown power gating, single rail clamping, and our symmetric virtual rail clamping, the three approaches have been implemented on a 101 stage ring oscillator using a 90-nm library. In line with the results presented in Fig. 2(b), a 300 mV clamped voltage was chosen for virtual rail clamping achieved with a high threshold voltage nMOS clamping transistor and a
200 mV clamped voltage was chosen for symmetric virtual rail clamping achieved with low threshold voltage pMOS and nMOS clamping transistors. All three circuits were simulated with 0.6 V Vdd using HSpice. Table I shows the wakeup energy, sleep mode leakage current saving, and wake-up time for the three power gating approaches. As can be seen, the proposed symmetric virtual rail clamping has the lowest wake-up energy and is 3× lower than shutdown power gating.
This is because the voltage maintained across the power gated logic from equal reduction in both V Vdd and V Vss supply rails eliminates signal glitching from the logic reevaluation present in shutdown power gating. Furthermore, despite using a lower clamped voltage than single virtual rail clamping, the charge recycling in symmetric virtual rail clamping results in lower wake-up energy cost. As expected, Table I shows that standby leakage saving is highest in shutdown power gating because the power supply is fully disconnected achieving greater reduction in Vds . However, the proposed symmetric virtual rail clamping has a greater standby leakage saving compared with single rail clamping and can be attributed to exploitation of RBB of both nMOS and pMOS transistors and the lower achievable Vds . Finally, Table I shows that the proposed symmetric virtual rail clamping has a shorter wakeup time compared with shutdown power gating, which permits a longer power gated period and is particularly useful over short power gated periods.
III. P ROPOSED SCPG T ECHNIQUE
In some recent and emerging applications such as wireless sensor networks and biomedical sensors, performance is not of

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Fig. 3. Idle time within the clock period resulting from aggressive frequency scaling. Fig. 4.

Proposed SCPG technique with symmetric virtual rail clamping.

concern whereas energy is a primary concern. In these applications, a low clock frequency (10–100s kHz) is utilized with fixed Vdd due to low performance demands [9], [11], [12]. As the clock frequency of the digital circuit is reduced, the clock period becomes longer than the combined hold time (Thold ), evaluation time of the next state (Teval ), and the setup time
(Tsetup), resulting in idle time (Tidle ) within the clock period
(Fig. 3). This idle time presents an opportunity to power gate within the clock period to reduce active mode leakage.
The proposed SCPG technique is shown in Fig. 4 and has three distinct parts. Firstly, the design is split into two domains: power-gatable combinational logic, marked as Comb. Logic and separate always-on sequential logic, marked as Seq. Logic.
This split is made to avoid the need for state retention registers to store state in sleep mode, which would increase area by
20%–50% and time taken to change between the sleep and active modes [13]. Secondly, symmetric virtual rail clamping, described in Section II, is used to power gate the combinational logic because of its low wake-up energy cost. The separation of the sequential logic from the combinational logic has a further benefit as the aggressive voltage reduction attainable with symmetric virtual rail clamping can be used for the combinational logic while ensuring that saved state remains intact during active operation, as will be shown in Section V.
The third distinguishing feature is the isolation logic between combinational and sequential domains, shown as ISOL in
Fig. 4. This is required to ensure that the output signals of the combinational domain do not cause short-circuit currents in the sequential logic when the combinational domain is powered down. In traditional power gating schemes, the control to the power gates is usually driven by a power gating controller state

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Fig. 5.

Example of isolation control circuit.

machine [13]. However, this is impractical in the proposed
SCPG technique because the control needs to be issued within the clock period. The proposed technique instead uses the clock signal, as shown in Fig. 4. The nMOS and pMOS transistors at the head of the combinational logic (Sleep and Ret) use the normal clock signal while the nMOS and pMOS transistors at the foot (nSleep and nRet) use the inverse of the clock signal. Therefore, when the clock is high, the combinational logic is clamped to less than Vth by the symmetric virtual rail clamping and when the clock is low it is restored to Vdd . The energy saved from using the proposed technique is therefore proportional to the length of time the clock is held high, and so, to maximize the power saving achievable with SCPG, it is possible to change the clock duty cycle to extend the high phase of the clock, as will be demonstrated in Section V. The nOverride control signal shown in Fig. 4 provides a method to disable the SCPG technique to achieve normal timing.
Also in traditional power gating, a power gating controller would be used to control the output isolation [13]. In the proposed SCPG technique though, the circuit of Fig. 5 is used to drive the ISOLATE signal to the ISOL block in
Fig. 4. The circuit has three inputs: the clock signal, the value of the combinational logic V Vdd that is derived from a TIEHI logic gate, and the nOverride signal. When the clock is logic 1, ISOLATE is driven to a logic 1, thereby isolating the combinational outputs. When the clock is logic 0,
ISOLATE is held at logic 1 while the V Vdd input remains at logic 0 (clamped). This ensures the combinational outputs remain isolated until the supply rail is charged to an equivalent logic 1, eliminating short-circuit currents during wake-up. The use of a V Vss is unnecessary as the pairs of nMOS and pMOS transistors are assumed to be balanced to ensure equal voltage drop and charge/discharge times. The nOverride signal ensures that if the SCPG technique is disabled, additional dynamic power is not consumed by the isolation being activated in every clock cycle.
The timing diagram of the combinational logic in the SCPG mode of operation with symmetric virtual rail clamping is shown in Fig. 6. After the state is captured into the positive edge triggered registers, the voltage to the combinational logic is clamped to less than Vth but the amount of time taken for the virtual rails to discharge ensures register hold times (Thold ) will be met. Throughout this paper, we assume the capacitance of the virtual rail and logic’s resistance aren’t low enough for this to not occur. At this point, the output isolation is also enforced.
The virtual supply rails are held at the clamped voltages for the remainder of the high phase of the clock (Tpglow) minimizing leakage power dissipation, and the outputs of the

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Fig. 6.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2014

Timing diagram of SCPG.

combinational domain remain isolated (Tisolate). Note that by changing the duty cycle of the clock it is possible to extend this off period (high phase of clock), maximizing the leakage power savings. The virtual supply rails are restored following the negative edge of the clock but the output isolation is held until the virtual supply rails are fully restored (Tpgstart ). The remainder of the clock period is used for the evaluation of the next state (Teval ) and ensuring setup time (Tsetup) is met before the process repeats in the next clock period.
IV. I MPLEMENTATION
The proposed SCPG technique has been proven by incorporating it with an ARM Cortex-M0 microprocessor made available to us as a soft IP core from our industrial project partner and fabricated in a 65-nm process. The Cortex-M0 is a 32-b RISC microprocessor with a three-stage pipeline and is chosen because of its relevance to low performance, energyconstrained applications. The design flow for augmenting a digital circuit with the SCPG technique is shown in Fig. 7; three additional steps are added to a traditional power gating design flow. We assume the use of the IEEE 1801 Unified
Power Format (UPF), a leading power intent standard for defining the strategy of a multivoltage or power gated design and the Synopsys EDA tool suite is used. To achieve the power domain split shown in Fig. 4, the RTL must be written with separate combinational and sequential logic Verilog modules for compatibility with UPF. The first two additional steps in Fig. 7 are used to achieve this split. Firstly, the RTL is synthesized to a generic gate library, such as the GTECH library in the Synopsys tools, to give a gate level representation of the circuit, and secondly a Perl script is used to identify and split combinational and sequential logic into two separate
Verilog modules. The final additional step, wraps the new
Verilog modules together with the isolation control circuit
(Fig. 5) and the power gate control statements before being synthesized with a traditional power gating design flow and target gate library. It should be noted that to ensure the hold time of the sequential elements is honored (Fig. 6), hold timing constraints are applied on the sequential elements to enable the EDA tool to balance the isolation control signal path and prevent the ISOLATE signal from triggering too early.
The Cortex-M0 together with the proposed SCPG technique was part of a 2 mm × 2 mm system on chip (SoC)

Fig. 7.

Design flow of SCPG.

which is shown on the right in Fig. 8. The entire CortexM0 microprocessor, marked as CM0 in Fig. 8, has its own power supply in the SoC to allow power measurement, and analog pads are included for observation of the virtual supply rails. The rest of the SoC was made up of static RAM for instruction and data, an ASCII Debug Protocol to facilitate communication and control of the chip via USB and a clock modulator circuit. As mentioned in Section III, the high phase of the clock can be changed to capitalize on all the idle time of the combinational logic to maximize power savings with the proposed SCPG technique. The circuit in Fig. 9 is used to achieve this modulation of clock duty cycle. An external clock is fed into the modulator and is divided down to a period of
(1 + n).Tclk , where n can be programmed to values up to 232 .
The resulting output clock from the modulator is low for Tclk and high for n.Tclk as shown in Fig. 9.
Shown on the left in Fig. 8 is the layout of the ARM CortexM0 with the proposed SCPG technique. The final layout was
200 µm × 310 µm, approximately 7% of the total area can be attributed to the inclusion of the proposed SCPG technique.
A breakdown of this area overhead is given in Table II showing the area of the power gating cells, isolation cells, and the control circuitry for the power gating and isolation.
As mentioned in Section III, the proposed technique requires separation of combinational and sequential logic to implement the power gating technique and Fig. 8 shows this separation with the combinational logic located in the middle of the layout and the sequential logic on its periphery. Note that these two areas of the layout directly correspond to the Comb.

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Fig. 8.

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Complete floor plan of (left) SCPG Cortex-M0 microprocessor and (right) test chip die photograph.

Fig. 9. Clock modulation circuit to convert system clock to Cortex-M0 clock with optimized duty cycle.

TABLE II
B REAKDOWN OF T OTAL A REA OVERHEAD I NTRODUCED
BY I NCLUSION OF SCPG

Logic and Seq. Logic blocks in Fig. 4. The implementation method used to achieve the power gating of the combinational logic is the popular voltage area approach described in [13] and [22]. In this implementation, the logic to be power gated is grouped together such that traditional double back placement can be used both within the voltage area and outside of it to reduce the power routing complexity while also minimizing routing overhead. The split in logic does, however, introduce an increase in routing requirement and a 20% increase in total signal net length was seen. The reader is directed to [23] for a more detailed discussion of the implementation of the ARM
Cortex-M0 with SCPG. When area and routing are critical, a number of works have proposed different physical layout techniques for lower power designs such as power gated rows [22] or dRail [23]. Highlighted on the boundary between the combinational and sequential areas of the layout are the isolation

cells, which corresponds to the ISOL block from Fig. 4. The pairs of nMOS and pMOS transistors in Fig. 4, used for symmetric virtual rail clamping of the combinational logic, were placed in a grid pattern throughout the combinational logic and are labeled in Fig. 8. The power gating transistors were sized using the EDA tools for 5% IR drop. The minimum clamped voltage on the other hand was estimated through
HSpice simulation. A logic path of 40 NOR3 and NAND4 gates was used to represent a pathological worst case critical path in the Cortex-M0. The circuit was simulated by decreasing the effective supply voltage in 20 mv decrements through clamping of the V Vdd and V Vss supplies. It was found that a correct output value of the entire path was held at supply voltages down to 160 mV with an output deviation ranging up to 6%. At 140 mV and below, however, valid logic gate outputs were lost, which would result in increased wakeup glitching energy. To enable this supply voltage, HSpice simulation showed that, with the 65-nm library used, eight regular threshold voltage transistors of width 3.6 µm enabled a clamped voltage of 180 mV. At the top of the layout is an always-on region, which accommodates the power gating and isolation control circuitry. For experimental comparisons, three modes of operation were implemented in the Cortex-M0: the proposed SCPG with symmetric virtual rail clamping, no power gating enforced using the nOverride signal in Fig. 4, and SCPG with complete shut down [24] achieved by disabling the Ret and nRet transistors shown in Fig. 4.
V. E XPERIMENTAL VALIDATION
Two sets of experiments were carried out to demonstrate the proposed SCPG and symmetric virtual rail clamping techniques. The first experimentally validates the functionality of the SCPG and symmetric virtual rail clamping techniques. The second shows the utility of the SCPG technique in example applications and compares traditional shutdown power gating

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Fig. 10. Measured V Vdd and V Vss behavior with SCPG operation and symmetric virtual rail clamping.

Fig. 11. Normalized measured power of ARM Cortex-M0 microprocessor with 10 kHz clock at varying duty cycle in SCPG with symmetric virtual rail clamping, Vdd = 0.7 V.

with symmetric virtual rail clamping. In addition to these two experiments, a brief analysis of the ground bounce induced by the power gating in the test chip is also given. In line with the scaled voltage typically found in processors designed for the target applications [11], a 0.7 V external power supply is used for the Cortex-M0’s independent Vdd . To emphasize the negative impact of leakage on the microprocessor a temperature of 90 ◦ C is used. An ammeter with 10 nA resolution is connected in series with the power supply to allow current measurement of the microprocessor.
A. Test Chip Validation
Fig. 10 shows an oscilloscope trace of the V Vdd /V Vss supply rails when using the proposed SCPG technique with symmetric virtual rail clamping. The clock used in this trace is 8 kHz with 2:1 (high:low) duty cycle. Over the first part of the clock period (Tclk ), the V Vdd and V Vss rails are clamped to 450 and 270 mV respectively, aggressively reducing the combinational voltage to 180 mV (Tpglow). Over the second part of the clock period, the rails are restored returning the combinational logic to the full 0.7 V supply voltage. Note that while the combinational logic supply voltage is clamped down to below the threshold voltage, it is not operated at this voltage and so if some logic gate outputs were to flip while clamped, then this would not be an issue as they would be rectified when the supply is returned to its nominal value. As discussed in Section IV, the duty cycle of the clock can be modulated to maximize the leakage power saving of the SCPG technique. The effect of duty cycle on power saving when using SCPG with symmetric virtual rail clamping is shown in
Fig. 11. The clock frequency used in these measurements is
10 kHz and the power values are normalized to the Cortex-M0 operating at 0.7 V with no power gating. The high phase of the clock period increases from left to right in Fig. 11 and as can be seen, the power goes down (savings increase) as it does so. It is interesting to note that the normalized power reduces but a lower bound is slowly reached. This is because the combinational logic has some finite leakage in the clamped state and the registers and other always-on logic

Fig. 12. Measured V Vdd and V Vss behavior in SCPG with shutdown power gating [24].

also remain active. The charge-up time of the virtual rails in symmetric virtual rail clamping is measured to be 45 ns from the oscilloscope trace. Considering the critical path length found through static timing analysis (75 ns), the minimum allowable low period of the clock is determined to be 200 ns to allow enough timing margin for the rails to recharge and the combinational logic to evaluate the next state while avoiding timing errors. Using the clock modulator circuit (Fig. 9), a
200 ns low period corresponds to an external clock frequency of 5 MHz while n can be programmed as necessary to vary the clock frequency.
Fig. 12 shows the behavior of the virtual supply rails when using SCPG with shutdown power gating. In this trace an
8-kHz clock with 2:1 duty cycle is used. Unlike symmetric virtual rail clamping (Fig. 10), the V Vss rail is unclamped and the V Vdd is fully discharged in the first part of the clock period
(Tpgoff ). In the second part of the clock period, the V Vdd rail is restored to the full 0.7 V supply. Notice that the chargeup (Tpgstart ) and evaluation time (Teval ) of the combinational logic is clearly visible in Fig. 12 and has been expanded in
Fig. 13. The droop seen in the V Vdd rail can be attributed to the current demanded by the high volume of signal glitching that

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Fig. 13.
Measured V Vdd charge-up and evaluation time in SCPG with shutdown power gating [24].

occurs as the combinational logic is brought out of shut down and reevaluates, which opposes the recharging of V Vdd [13].
This droop subsequently slows the combinational reevaluation, exacerbating the length of Teval to 4 µs as shown. This is unlike the symmetric virtual rail clamping shown in Fig. 10 where the voltage maintained across the combinational logic helps to eliminate signal glitching during charge-up and avoid a virtual rail droop, allowing the combinational logic to be charged in
45 ns. The consequence of this increased wake-up time when using shutdown power gating is the need for a clock with a low phase of at least 4000 ns to ensure correct operation, as opposed to a 200-ns low phase achievable with symmetric virtual rail clamping.
Experimental measurement from the chip shows that when the Cortex-M0 is fully powered but the clocks are stopped, the leakage power dissipation is 7.51 µW. On the other hand, when the combinational logic is fully shut down, power dissipation is 1.46 µW, representing an 80.6% reduction in power.
Alternatively, when the combinational logic supply is clamped using symmetric virtual rail clamping the power dissipation is
2.44 µW, a 67.5% reduction in leakage power. This is to be expected, since shutdown power gating completely disconnects the supply whereas symmetric virtual rail clamping maintains a voltage across the combinational logic and matches with the trends shown in Table I.
B. Applications
Next we compare the power consumption of the Cortex-M0 with and without the proposed SCPG with symmetric virtual rail clamping technique over a range of clock frequencies. To investigate the utility of SCPG in one of the target applications, we use a program used in an actual wireless sensor node for the
Next Generation Energy Harvesting Electronics project, which tracks the vibration frequency to tune a vibrational energy harvester to maintain resonance (between 42 and 55 Hz) [25].
The program takes a set of 1000 samples from an accelerometer to calculate the current frequency of vibration, which is then used to set a stepper position on an energy harvester.
A clock duty cycle with 200 ns low phase is used in the SCPG

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Fig. 14. Measured average power of ARM Cortex-M0 microprocessor at varying clock frequency in tuning program, Vdd = 0.7 V.

with symmetric virtual rail clamping and the measured results across five test chips are shown in Fig. 14. As can be seen, the proposed SCPG technique achieves lower power consumption at all frequency points up to a clock frequency of just over
400 kHz. At all of these frequency points, the energy saved
(E sav ) from using the proposed SCPG technique exceeds the energy overhead (E oh ) of power gating, resulting in the savings seen. However, as clock frequency increases, E sav reduces because of the shorter combinational idle time and eventually becomes comparable with E oh , resulting in the convergence point around 400 kHz in Fig. 14. At clock frequencies above
400 kHz, E oh > E sav and the power consumed by the
Cortex-M0 when using SCPG exceeds that of the Cortex-M0 without power gating. In the intended applications of SCPG, if clock frequencies above and below 400 kHz are required, the processor could be switched to no power gating mode by using the nOverride signal (Fig. 4) for clock frequencies above
400 kHz.
Five test chips were used for the data shown in Fig. 14 to compare results across multiple dies, and as can be seen, the measurements all follow the same trend. The spread between plotted points can be explained by die to die process variation. The average power and energy per operation of the five test chips is shown in Table III. In the final column, the percentage saving achieved when using the proposed technique is stated. As can be seen, the proposed technique saves up to 67% of the energy compared with no power gating and demonstrates SCPG’s ability to improve energy efficiency for a circuit operating at low clock frequencies. At
455 kHz, the processor would need to switch to no power gating with the nOverride signal to remain in the lowest energy mode of operation. In the real wireless sensor node application, the accelerometer is sampled at a frequency of
2 kHz to improve accuracy in the frequency calculation. As the program loops around a maximum of 85 instructions, at a sampling rate of 2 kHz, the Cortex-M0 can be operated at 200 kHz without missing a new sample. At 200 kHz, without SCPG the processor would dissipate 9 µW consuming 45 pJ/operation and with SCPG the processor dissipates
6.6 µW consuming 33.20 pJ/operation. This represents a

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TABLE III
AVERAGE M EASURED P OWER AND E NERGY OVER F IVE T EST C HIPS
W ITH P OWER G ATING D ISABLED (N O -PG) AND SCPG E NERGY
H ARVESTER T UNING

Fig. 16. Measured average power of ARM Cortex-M0 microprocessor at varying clock frequency in Dhrystone, Vdd = 0.7 V.

Fig. 15. Measured power of Cortex-M0 with power gating disabled, proposed
SCPG with symmetric virtual rail clamping and SCPG with shutdown power gating [24].

27% reduction in power and 1.4× improvement in energy efficiency. Table I shows that the wake-up energy associated with shutdown power gating was higher than the proposed symmetric virtual rail clamping circuit through ring oscillator simulations.
To compare SCPG with shutdown power gating [24] and the proposed symmetric virtual rail clamping, both techniques have been compared across a range of clock frequencies.
Fig. 15 compares graphically, the measured average power of SCPG using shutdown power gating, SCPG using the proposed symmetric virtual rail clamping technique, and power gating disabled. To permit direct comparison of the two power gating techniques, both SCPG modes used a clock with a 4 µs low phase achieved with a 250 kHz external clock (Fig. 9).
As can be seen, at 500 Hz and 1 kHz in Fig. 15, SCPG with shutdown power gating has lower power consumption than without power gating but is higher than the proposed symmetric virtual rail clamping. This can be attributed to the high wake-up energy cost associated with the signal glitching that occurs when restoring the virtual rail in shutdown power

gating. Note also, this high wake-up energy cost causes the energy overhead of shutdown power gating to exceed the energy saving at all frequency points above 1 kHz, resulting in higher power consumption in comparison with no power gating. The increasing power trend of the shutdown power gating mode is reversed after 20 kHz because the virtual rail does not discharge fully during shut down due to the shorter idle time within the clock period. However, despite the V Vdd rail remaining partially charged at these frequency points it still dissipates more power than the proposed symmetric virtual rail clamping technique and is a result of the combination of asymmetric RBB of the logic gates and lack of charge recycling discussed in Section II. The observations seen here provide further validation for the symmetric virtual rail clamping proposed in Section II to reduce wake-up energy cost and improve the energy efficiency of the SCPG technique.
We envisage the proposed SCPG with symmetric virtual rail clamping technique being applicable in a range of general purpose, low performance, energy-constrained applications.
Therefore we have used the Dhrystone benchmark [26], to validate the power saving trends of SCPG with symmetric virtual rail clamping in a second test program. The Dhrystone benchmark program occupies between 1–1.5 kB of memory and is chosen since it uses a combination of integer arithmetic and string functions, logic decisions and memory accesses, which are representative of the data acquisition and manipulation of many general purpose applications [26]. Overall the benchmark consists of approximately 50% arithmetic and 50% comparison and logical operations and uses an assortment of operand types and operand locality. The benchmark finishes by printing out the hard coded expected results in addition to the computed result that provided a method to ensure logical errors were not introduced during the SCPG mode of operation.
The measured power across the five test chips used with the wireless sensor node example when executing the Dhrystone benchmark is shown in Fig. 16. As can be seen a similar trend to the energy harvester tuning program can be observed with SCPG with symmetric virtual rail clamping showing power saving over no power gating up to a clock frequency of 400 kHz. It should be noted that the similarity between

MISTRY et al.: ACTIVE MODE SUBCLOCK POWER GATING

Fig. 17.

Measured ground bounce on the always-on VSS supply rail.

the results (Figs. 14 and 16) when executing the Energy
Harvesting Tuning Program and the Dhrystone benchmark is to be expected as at the these low operating frequencies the dominant source of power dissipation is leakage power and overall power consumption is largely insensitive to change in dynamic operation.
C. Ground Bounce
A potential concern when applying power gating is the ground bounce that is induced on the always-on supply rail [13]. This ground bounce occurs as a result of the large rush of current that is required to recharge the virtual rails, and it can potentially cause signal integrity issues and corruption to registers in the always-on areas of the digital design. In our fabricated Cortex-M0, 24 header and footer power gates were used to power gate the combinational logic to achieve an IR drop of less than 5%. Fig. 17 shows the measured ground bounce on the VSS supply rail when using symmetric virtual rail clamping (Fig. 4). The maximum amplitude of the measured ground bounce is approximately 10 mV, which for a supply of 0.7 V is just over 1%. Therefore, the register states will not be affected by the ground bounce induced by the proposed technique. The application of the symmetric virtual rail clamping as part of the proposed technique has helped in reducing the effect of in-rush on ground bounce, as the virtual rails need to be charged less, and because there is less potential glitching. VI. C ONCLUSION
This paper has proposed a power gating technique that reduces leakage power during the active mode for low performance energy-constrained applications by power gating combinational logic within the clock period. Rather than shutting down completely, symmetric virtual rail clamping was proposed to reduce wake-up power mode transition energy cost. The proposed SCPG with symmetric virtual rail clamping technique has been demonstrated with an ARM Cortex-M0 microprocessor, fabricated in 65-nm technology. Measured results up to a clock frequency of 400 kHz from the fabricated

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chip showed that it is possible to reduce average power by up to 67% during the active mode, with only 7% of the layout area accountable to extra circuitry. Using an actual wireless sensor node program example, it was shown that the microprocessor with SCPG can achieve 27% reduction in power and 1.4× improvement in energy efficiency. Comparison between SCPG with shutdown power gating and symmetric virtual rail clamping provided experimental validation for the need to use symmetric virtual rail clamping to improve energy efficiency. The work proposed in this paper can be considered as an orthogonal approach to the recently proposed subthreshold technique for maximizing energy efficiency when operating at low performance. The subthreshold technique enables realization of minimum energy computation by scaling the supply voltage below Vth until a minimum energy point is found where dynamic energy equals leakage energy per operation [8]. Due to the aggressively scaled supply voltage, the technique comes at a cost of performance making it suitable for low performance, energy-constrained applications. Subclock power gating, on the other hand, provides a power/performance tradeoff allowing the digital circuit to toggle between low power, low performance and high power, high performance states unlike subthreshold, which is optimized for low performance only. Additionally, since SCPG is used with limited voltage scaling, it avoids increased design complexity making it fully compatible with standard EDA tools and gate libraries, and avoids sensitivity to supply voltage and threshold voltage variation associated with operating below Vth [8].
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James Myers received the M.Eng. degree from
Imperial College London, London, U.K.
He is a Staff Engineer with the Silicon Research and Development Group, ARM Ltd., Cambridge,
U.K. He joined ARM in 2007, where he was initially responsible for developing reference implementation flows for the various ARM soft processor cores. Joining Research and Development full time in 2009, he has focused on deployable techniques for reduction of CPU and SoC power. His current research interests include low power circuits, advanced power gating, low voltage, and better than worst-case design.

Bashir M. Al-Hashimi (M’99–SM’01–F’09) is a
Professor of computer engineering and the Director of the Pervasive Systems Center, University of
Southampton, Southampton, U.K. He is an ARM
Professor of computer engineering and the CoDirector of the ARMECS Research Center. His current research interests include methods, algorithms, and design automation tools for low-power design and test of embedded computing systems.

David Flynn (SM’13) received the B.Sc. degree in computer science from Hatfield Polytechnic, Hertfordshire, U.K., and the Doctoral degree in electronic engineering from Loughborough University, Loughborough, U.K.
He has been a Fellow in Research and Development with ARM Ltd., Cambridge, U.K., since 1991, specializing in system-on-chip IP deployment and methodology. He is the original architect behind
ARM’s synthesizable CPU family and the AMBA on-chip interconnect standard. He has served as a part-time Visiting Professor with the Electronics and Computer Science
Faculty, University of Southampton, Southampton, U.K., since 2008, and is a
Co-Director of the ARM-ECS Research Center. He holds a number of patents in on-chip bus, low power, and embedded processing subsystem design. His current research interests include low-power system-level design.

John Biggs (M’13) received the B.Sc. degree in electrical and electronic engineering from the
University of Manchester, Manchester, U.K.
He has been involved with ARM developments since 1986 and co-founded ARM Ltd., Cambridge,
U.K., in 1990. After a number of years working as a VLSI Design Engineer, he went on to form
ARM’s Design Methodology Group in 1995. He is currently a Senior Principal Engineer with ARM’s
Research Group, on the development of advanced methodologies for the low-power deployment of synthesizable ARM IP.
Mr. Biggs is a Chair of the IEEE P1801 UPF Work Group.

Jatin N. Mistry (M’04) received the B.Eng. (Hons.) and Ph.D. degrees in electronic engineering from the
University of Southampton, Southampton, U.K., in
2009 and 2013, respectively.
He was the first graduate of the University of Southampton ARM-ECS Research Center, CoDirected by Prof. B. M. Al-Hashimi and Prof. D.
Flynn. He is currently an Engineer with the Processor Division, Cores Implementation Group, ARM
Ltd., Cambridge, U.K., where he is responsible for the physical design and implementation of ARM
IP, and the development and deployment of methodologies to improve the efficiency of implementation. His current research interests include low power design, power gating, and implementation of low power techniques.

Geoff V. Merrett (M’06) received the B.Eng.
(Hons.) and Ph.D. degrees in electronic engineering from the University of Southampton, Southampton,
U.K., in 2004 and 2009, respectively.
He is currently a Lecturer with the University of
Southampton. He has published over 50 journal and refereed conference papers, and is a reviewer for a number of prestigious journals. His current research interests include low-power embedded systems and sensor networks.
Dr. Merrett served as a Co-Chair of the First
International Workshop on Energy Neutral Sensing Systems in 2013 and serves on the TPCs of many international conferences and workshops.