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IS2202 Computer Systems Architecture

Lecture review pipeline and memory hierarchy

EECS 252 Graduate Computer Architecture

Computer Systems Architecture
Review of Pipeline and cache memory concepts t
Mats Brorsson, professor matsbror@kth.se, tel. 790 4121

Lec 3 – Performance + Pipeline Review
Electrical Engineering and Computer Sciences El t i l E i i dC t S i University of California, Berkeley http://www.eecs.berkeley.edu/~pattrsn http://www‐inst.eecs.berkeley.edu/~cs252

David Patterson

Review from last lecture
• Tracking and extrapolating technology part of architect’s responsibility • Expect Bandwidth in disks DRAM network and Expect Bandwidth in disks, DRAM, network, and processors to improve by at least as much as the square of the improvement in Latency • Quantify Cost (vs. Price)
– IC ≈ f(Area2) + Learning curve, volume, commodity, margins

Outline
• • • • • • • • Review MIPS – An ISA for Pipelining 5 stage pipelining 5 t i li i Structural and Data Hazards Forwarding Branch Schemes Exceptions and Interrupts Conclusion

• Quantify dynamic and static power Quantify dynamic and static power
– Capacitance x Voltage2 x frequency, Energy vs. power

• Quantify dependability
– Reliability (MTTF vs. FIT), Availability (MTTF/(MTTF+MTTR)
3/28/2008 CS252-s06, Lec 02-intro 3 3/28/2008 CS252-s06, Lec 02-intro 4

1

IS2202 Computer Systems Architecture

Lecture review pipeline and memory hierarchy

MIPS ‐‐ A "Typical" RISC ISA
• • • • 32‐bit fixed format instruction (3 formats) ( p ) 32 32‐bit GPR (R0 contains zero, DP take pair) 3‐address, reg‐reg arithmetic instruction Single address mode for load/store: base + displacement
– no indirection
31

Example: MIPS (‐ MIPS)
Register-Register
26 25 21 20 16 15 11 10 6 5 0

Op
31

Rs1
26 25 21 20

Rs2

Rd

Opx
0

Register-Immediate
16 15

Op Branch
31

Rs1
26 25 21 20

Rd
16 15

immediate

• Simple branch conditions • D l db Delayed branch h see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowerPC, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3

Op Jump / Call
31

Rs1

Rs2/Opx

immediate

0

26 25

Op

target

0

3/28/2008

CS252-s06, Lec 02-intro

5

3/28/2008

CS252-s06, Lec 02-intro

6

Datapath vs Control
Datapath signals Controller

Approaching an ISA
• Instruction Set Architecture
– Defines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencing

• Meaning of each instruction is described by RTL on architected Meaning of each instruction is described by RTL on architected registers and memory • Given technology constraints assemble adequate datapath
– – – – Architected storage mapped to actual storage Function units to do all the required operations Possible additional storage (eg. MAR, MBR, …) Interconnect to move information among regs and FUs

Control Points
• Datapath: Storage, FU, interconnect sufficient to perform the desired functions
– – Inputs are Control Points Outputs are signals Based on desired function and signals
CS252-s06, Lec 02-intro 7



Controller: State machine to orchestrate operation on the data path


• Map each instruction to sequence of RTLs Map each instruction to sequence of RTLs • Collate sequences into symbolic controller state transition diagram (STD) • Lower symbolic STD to control points • Implement controller
3/28/2008 CS252-s06, Lec 02-intro 8

3/28/2008

2

IS2202 Computer Systems Architecture

Lecture review pipeline and memory hierarchy

5 Steps of MIPS Datapath
Figure A.2, Page A‐8

5 Steps of MIPS Datapath
Figure A.3, Page A‐9

Instruction Fetch
Next PC

Instr. Decode Reg. Fetch
Next SEQ PC
RS1

Execute Addr. Calc

Memory Access MUX

Write Back

Instruction Fetch
Next PC

Instr. Decode Reg. Fetch
Next SEQ PC

Execute Addr. Calc
Next SEQ PC

Memory Access MUX

Write Back

Adder

Adder

4
Address
3/28/2008

Zero?

4
Address Data Memory y L M D

RS1

Zero?

MUX MUX

MEM/WB

Memory

RS2

RS2

EX/MEM

Reg File

MUX MUX

ID/EX

IF/ID

IR

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