CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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Chapter 1 Homework Solutions
1.1-1 Using Eq. (1) of Sec 1.1, give the base-10 value for the 5-bit binary number 11010 (b4 b3 b2 b1 b0 ordering). From Eq. (1) of Sec 1.1 we have bN-1 2 + b N-2 2 + bN-3 2 + ...+ b0 2-N =
-1 -2 -3

∑bN-i2-i i=1 N

1 1 0 1 0 1 × 2-1 + 1× 2-2 + 0 × 2-3 + 1 × 2-4 + 0 × 2-5 = 2 + 4 + 8 + 16 + 32 = 16 + 8 + 0 + 2 + 0 26 13 = 32 = 16 32

1.1-2 Process the sinusoid in Fig. P1.2 through an analog sample and hold. The sample points are given at each integer value of t/T.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11

Sample times t __ T Figure P1.1-2

1.1-3 Digitize the sinusoid given in Fig. P1.2 according to Eq. (1) in Sec. 1.1 using a four-bit digitizer.

Amplitude

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1

1111 1110 1101 1100 1010 1000 0110 0101 0011 0010 0010 1000

Amplitude

2

3

4

5

6

7

8

9

10

11

Sample times t __ T Figure P1.1-3

The figure illustrates the digitized result. At several places in the waveform, the digitized value must resolve a sampled value that lies equally between two digital values. The resulting digitized value could be either of the two values as illustrated in the list below. Sample Time 0 1 2 3 4 5 6 7 8 9 10 11 4-bit Output 1000 1100 1110 1111 or 1110 1101 1010 0110 0011 0010 or 0001 0010 0101 1000

1.1-4 Use the nodal equation method to find vout/vin of Fig. P1.4.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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A

B

R1 vin R3 v1

R2 gmv1 R4 vout

Figure P1.1-4

Node A: 0 = G1(v1-vin) + G3(v1) + G2(v1 - vout) v1(G1 + G2 + G3) - G2(vout) = G1(vin) Node B: 0 = G2(vout-v1) + gm1(v1) + G4( vout) v1(gm1 - G2) + vout (G2 + G4) = 0  G1+G2 +G3 G1vin   g -G  0  m1 2  vout = G +G +G - G2   1 2 3  g -G G2 + G4  m1 2   G1 (G2 - gm1) vout = G G +G G +G G +G G +G G +G g vin 1 2 1 4 2 4 3 2 3 4 2 m1

1.1-5 Use the mesh equation method to find vout/vin of Fig. P1.4.
R1 vin ia R2 R3 v1 ib gmv1

ic

R4

vout

Figure P1.1-5

0 = -vin + R1(ia + ib + ic) + R3(ia)

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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0 = -vin + R1(ia + ib + ic) + R2(ib + ic) + vout vout ic = R 4 ib = gm v1 = gm ia R3 vout   0 = -vin + R1ia + gm ia R3 + R  + R3ia 4  vout  vout    0 = -vin + R1ia + gm ia R3 + R  + R2 gm ia R3 + R  + vout 4 4   R1 vin = ia (R1 + R3 + gm R1 R2) + vout R 4 R1 + R2+ R4  vin = ia (R1 + gm R1 R3 + gm R2 R3) + vout   R4  

R1+R3 + gm R1 R3 vin    R +g R R +g R R v   1 m 1 3 m 2 3 in  vout = R1+ R3 + gm R1 R3 R1/ R4    R + g R R + g R R (R + R +R ) / R   1 m 1 3 m 2 3 1 2 4 4  vin R3 R4 (1 - gm R2) (R1 + R3 + gm R1 R3) (R1 + R2 + R4) - (R1 + gmR1 R3 + gmR1 R2 R3)
2 2

vout =

vin R3 R4 (1 - gm R2) vout = R R + R R + R R + R R + R R + g R R R 1 2 1 4 1 3 2 3 3 4 m 1 3 4 R3 R4 (1 - gm R2) vout = R R +R R +R R +R R +R R +g R R R vin 1 2 1 4 1 3 2 3 3 4 m 1 3 4 1.1-6 Use the source rearrangement and substitution concepts to simplify the circuit shown in Fig. P1.6 and solve for iout/iin by making chain-type calculations only.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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i

R2 iin R1 v1 rmi R3 iout

i

R2 iin R1 v1 rmi rmi R3 iout

i

R2 iin R1 v1 R-rm rmi R3 iout

Figure P1.1-6

-rm iout = R i 3 R1 i = R + R - r iin 1 m iout -rm R1/R3 = R+R -r iin 1 m

1.1-7 Find v2/v1 and v1/i1 of Fig. P1.7.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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i1

gm(v1-v2)

v1

RL

v2

Figure P1.1-7

v2 v1 = gm (v1 - v2) RL v2 (1 + gm RL ) = gm RL v1 v2 gm RL = 1+g R v1 m L v2 = i1 RL substituting for v2 yields: i1 RL gm RL = 1+g R v1 m L v1 RL( 1 + gm RL ) i1 = gm RL v1 1 = RL + g i1 m 1.1-8 Use the circuit-reduction technique to solve for vout/vin of Fig. P1.8.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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Av(vin - v1)

vin

R1

v1

R2

vout

N1 Avv1 Avvin

N2

vin

R1

v1

R2

vout

Figure P1.1-8a

Multiply R1 by (Av + 1)
Avvin

vin R1(Av+1)

v1

R2

vout

Figure P1.1-8b

-Avvin R2 vout = R + R (A +1) 2 1 v vout -Av R2 = R + R (A +1) vin 2 1 v

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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vout vin =

-Av -Av + 1 R2 R2 Av + 1 + R1

As Av approaches infinity, vout -R2 vin = R1

1.1-9 Use the Miller simplification concept to solve for vout/vin of Fig. A-3 (see Appendix A).
R1 R3

rm i a vin ia R2 v1 ib vout

Figure P1.1-9a (Figure A-3 Mesh analysis.)

vout -rm ia -rm K= v = i R = R 1 a 2 2 Z1 = R3 rm 1+ R 2 -rm R3 R 2 rm - R -1 2

Z2 =

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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R3 2 Z2 = r = R m 2 R2 + 1 rm + 1
R1

R3 rm R

rmia vin ia R2 Z1 Z2 vout

Figure P1.1-9b

vin (R2 || Z1)  1  ia = (R || Z ) + R R  2 1 1  2 vout = -rm ia

-vin rm (R2 || Z1)  1  vout = (R || Z ) + R R  2 1 1  2 vout -rm (R2 || Z1)  1  vin = (R2 || Z1) + R1 R2   vout -rm R3 = (R R + R R + R r + R R ) vin 1 2 1 3 1 m 2 3

1.1-10 Find vout/iin of Fig. A-12 and compare with the results of Example A-1.

iin

R1

v1

R'2 gmv1

R3

vout

Figure P1.1-10

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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' v1 = iin (R1 || R2) ' vout = -gmv1 R3 = -gm R3 iin (R1 || R2) vout ' iin = -gm R3(R1 || R2) R2 ' R2 = 1 + g R m 3 R1R2 1 + gm R3

' R1 || R2 = (1 + g R ) R + R m 3 1 2 1 + gm R3 R1R2 ' R1 || R2 = (1 + g R ) R + R m 3 1 2 vout -gm R1 R2R3 = R +R +R +g R R iin 1 2 3 m 1 3 The A.1-1 result is: vout R1 R3 - gm R1 R2R3 = R +R +R +g R R iin 1 2 3 m 1 3 if gmR2 >> 1 then the results are the same. 1.1-11 Use the Miller simplification technique described in Appendix A to solve for the output resistance, vo/io, of Fig. P1.4. Calculate the output resistance not using the Miller simplification and compare your results.
R1 vin R3 v1 R2 gmv1 R4 vout

Figure P1.1-11a

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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Zo with Miller K = -gm R4

-R2 gm R4 R2 gm R4 Z2 = -g R - 1 = 1 + g R m 4 m 4 gm R2 R4 1 + gm R4 (1 + gm R4) R4 + gm R2 R4 1 + gm R4
2 2

Z0 = R4 || Z2 =

gm R2 R4 Z0 = R4 || Z2 = R + g R ( R + R ) 4 m 4 4 2 Zo without Miller iT R2 R1||R3 v1 gmv1 R4 vT

2

Figure P1.1-11b

vT   v1 = (R1 || R3) i + gmv1 - R  4  vT   v1 [1 + gm (R1 || R3)] = ( R1 || R3 ) iT + - R  4  (R1 || R3) (iT R4 + - vT) (1) v1 = R [1 + g (R || R )] 4 m 1 3

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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vT (R1 || R3) (2) v1 = R || R + R 1 3 2 Equate (1) and (2)

(R1 || R3) (iT R4 - vT) vT (R1 || R3) = R [1 + g (R || R )] R1 || R3 + R2 4 m 1 3 vT iT R4 - vT = R [1 + g (R || R )] R1 || R3 + R2 4 m 1 3
 

vT  R4 [1 + gm (R1 || R3)] + R2+ R1||R3  = iT R4 (R2+ R1||R3)   R4 (R2+ R1||R3 ) Z0 = R + R + g R (R ||R ) + R ||R 2 4 m 4 1 3 1 3 R1R3R4 R4 R2 + R + R 1 3 R2 + R4 + gm R4R1 R3 + R1 R3 R1+R3

Z0 =

R4 R2 (R1 + R3) + R1R3R4 Z0 = (R + R ) (R + R ) + R R + g R R R 2 4 1 3 1 3 m 1 3 4 R1 R2 R4 + R2R3 R4 + R1R3R4 Z0 = R R + R R + R R + R R + R R + g R R R 1 2 2 3 3 4 1 4 1 3 m 1 3 4 1.1-12 Consider an ideal voltage amplifier with a voltage gain of Av = 0.99. A resistance R = 50 kΩ is connected from the output back to the input. Find the input resistance of this circuit by applying the Miller simplification concept.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions : 9/20/2002

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i R=50K v1
0.99v1

vout

Figure P1.1-12

R Rin = 1 - K K = 0.99 50 KΩ 50 K Ω Rin = 1 - 0.99 = 0.01 = 5 Meg Ω

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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Chapter 2 Homework Solutions Problem 2.1-1 List the five basic MOS fabrication processing steps and give the purpose or function of each step. Oxidation: Combining oxygen and silicon to form silicondioxide (SiO2). Resulting SiO2 formed by oxidation is used as an isolation barrier (e.g., between gate polysilicon and the underlying channel) and as a dielectric (e.g., between two plates of a capacitor). Diffusion: Movement of impurity atoms from one location to another (e.g., from the silicon surface to the bulk to form a diffused well region). Ion Implantation: Firing ions into an undoped region for the purpose of doping it to a desired concentration level. Specific doping profiles are achievable with ion implantation which cannot be achieved by diffusion alone. Deposition: Depositing various films on to the wafer. Used to deposit dielectrics which cannot be grown because of the type of underlying material. Deposition methods are used to lay down polysilicon, metal, and the dielectric between them. Etching: Removal of material sensitive to the etch process. For example, etching is used to eliminate unwanted polysilicon after it has been laid out by deposition. Problem 2.1-2 What is the difference between positive and negative photoresist and how is photoresist used? Positive: Exposed resist changes chemically so that it can dissolve upon exposure to light. Unexposed regions remain intact. Negative: Unexposed resist changes chemically so that it can dissolve upon exposure to light. Exposed regions remain intact. Photoresist is used as a masking layer which is paterned appropriately so that certain underlying regions are exposed to the etching process while those regions covered by photoresist are resistant to etching. Problem 2.1-3 Illustrate the impact on source and drain diffusions of a 7° angle off perpendicular ion implant. Assume that the thickness of polysilicon is 8000 Å and that out diffusion from point of ion impact is 0.07 µm.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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7

o

Ion implantation Polysilicon Gate

(a)

Implanted ions

Polysilicon Gate

After ion implantation

(b)

Polysilicon Gate

After diffusion

No overlap of gate to diffusion

Polysilicon Gate

Significant overlap of polysilicon to gate

Implanted ions diffused (c)
Figure P2.1-3

Problem 2.1-4 What is the function of silicon nitride in the CMOS fabrication process described in Section 2.1

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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The primary purpose of silicon nitride is to provide a barrier to oxygen so that when deposited and patterned on top of silicon, silicon dioxide does not form below where the silicon nitride exists. Problem 2.1-5 Give typical thickness for the field oxide (FOX), thin oxide (TOX), n+ or p+, p-well, and metal 1 in units of µm. FOX: ~ 1 µm TOX: ~ 0.014 µm for an 0.8 µm process N+/p+: ~ 0.2 µm Well: ~ 1.2 µm Metal 1: ~ 0.5 µm Problem 2.2-1 Repeat Example 2.2-1 if the applied voltage is -2 V. NA = 5 × 1015/cm3, ND = 1020/cm3

φo = q ln  2  =  n   i 
 2εsi(φo−vD)NA  xn=   qND(NA + ND) 

kT

NAND

1.381×10-23×300  5×1015×1020  ln   = 0.9168 1.6×10-19  (1.45×1010)2

1/2

2×11.7×8.854×10-14 (0.9168 +2.0) 5×1015  =  1.6×10-19×1020 ( 5×1015 + 1020)  

1/2

= 43.5×10-12 m

2εsi(φo − vD)ND xp = −   qNA(NA + ND) 

1/2

2×11.7×8.854×10-14 (0.9168 +2.0) 1020 =   1.6×10-19×5×1015 ( 5×1015 + 1020) 

1/2

= −0.869 µm

xd = xn − xp = 0 + 0.869 µm = 0.869 µm

1/2 dQj  εsiqNAND  Cj0 = dv = A   D 2(NA + ND) (φo)

11.7×8.854×10-14×1.6×10-19×5×1015×1×1020 Cj0 = 1×10-3×1×10-3   2(5×1015+1×1020) (0.917)  

1/2

= 21.3 fF

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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Cj0 =

Cj0

φ0  1 −  vD 

1/2

=

21.3 fF -2   1 −  0.917 
1/2

= 11.94 fF

Problem 2.2-2 Develop Eq. (2.2-9) using Eqs. (2.2-1), (2.2-7), and (2.2-8). Eq. 2.2-1 xd = xn − xp Eq. 2.2-7 2εsi(φo − vD)NA xn =    qND(NA + ND)  Eq. 2.2-8 2εsi(φo − vD)ND xp = −    qNA(NA + ND) 
1/2 1/2

2ε (φ − v )N 2 + 2ε (φ − v )N 21/2 si o D D  si o D A xd =   qNA ND (NA + ND)    2ε N 2 + N 2 1/2 si A  D  xd = (φo − vD)1/2   qNA ND (NA + ND) Assuming that 2NA ND 0

vGD-VTD> 5 × 108 thus slow regime 2 × 30 × 10-15 |2φf| + |vbs| −  |2φf|  = 0.7 + 0.4   0.7 + 2.0 −  0.7  = 1.023

=

W · CGD0 + Cchannel 2  Verror =  CL  

π U CL W · CGD0 + (VS + VT − VL ) CL 2β

5 × 10-6 × 220 × 10-12 + 12.35 × 10-15 2 × Verror =  -15 30 × 10  

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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×

π × 5 × 108 × 30 × 10-15 5 × 10-6 · 220 × 10-12
2×110 × 10-6 + 30 × 10-15

(2 + 1.023 − 0 ) = 0.223

Vout(t1) = 2.0 − Verror = 2.0 − 0.223 = 1.777

Problem 4.1-8 In Problem 4.1-7, how long must φ1 remain high for C1 to charge up to 99% of the desired final value (2.0 volts)? rON = 1 L = ∂ID/∂VDS K'W(|VGS| − |VT|)

rON =

1 -6 × (3 − 1.135) = 972.3 Ω 5 × 110 × 10 = 972.3 × 30 × 10-15 = 29.2 ps = 2 × ( 1 − e-t/RC ) = 0.99 × 2.0

rON C1 vO(t) C1

e-t/RC ) = 0.01 t = −RC ln(0.01) = 134.3 ps

Problem 4.1-9 In Problem 4.1-7, the charge feedthrough could be reduced by reducing the size of M1. What impact does reducing the size (W/L) of M1 have on the requirements on the width of the φ1 pulse width? The width of φ1 must increase since a decrease in size (and thus feedthrough) increases resistance and thus the time required to charge the capacitor to the desired final value. Problem 4.1-10 Considering charge feedthrough due to slow regime only, will reducing the magnitude of the φ1 pulse impact the resulting charge feedthrough? What impact does reducing the magnitude of the φ1 pulse have on the accuracy of the voltage transfer to the output?

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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Reducing the magnitude does not effect the result of feedthrough in the slow regime because all of the charge except residual channel charge (at the point where the device turns off) returns to the voltage source. Decreasing the magnitude does effect the accuracy because the time required to charge the capacitor is increased due to higher resistance when the device is on. Problem 4.1-11 Repeat Example 4.1-1 with the following conditions. Calculate the effect of charge feedthrough on the circuit shown in Fig. 4.1-9 where Vs = 1.5 volts, CL = 150 fF, W/L = 1.6µm/0.8µm, and VG is given for two cases illustrated below. The fall time is 0.1ns instead of 8ns. Case 1: 0.1ns fall time VT = VT0 + γ   |2φf| + |vbs| −  |2φf|  = 0.7 + 0.4   0.7 + 1.5 −  0.7  = 0.959

VHT = VH − VS − VT = 5 − 1.5 − 0.959 = 2.541 VH 5 U= t = = 50 × 109 -9 0.1 × 10 2 βVHT 2CL 2×110 × 10-6 × 2.541 = 4.735 × 109 > 625 × 106 thus slow regime 2 × 150 × 10-15

W · CGD0 + Cchannel 2  Verror =  CL   and VS = 1.5 volts VL = 0.0 volts

π U CL W · CGD0 + (VS + VT − VL ) CL 2β

Cchannel = W × L × Cox = 1.6 × 10-6 × 0.8 × 10-6 × 24.7 × 10-4 = 3.162 × 10-15 F

W · CGD0 + Cchannel 2  Verror =  CL  

π U CL W · CGD0 + (VS + VT − VL ) CL 2β

1.6 × 10-6 × 220 × 10-12 + 3.162 × 10-15 2 × Verror =  150 × 10-15  
Error! Vout(t1) = 2.0 − Verror = 2.0 − 0.0163 = 1.984

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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Problem 4.1-12 Figure P4.1-12 illustrates a circuit that contains a charge-cancellation scheme. Design the size of M2 to minimize the effects of charge feedthrough. Assume slow regime.
5V φ1 0V t1

φ1

φ1

M1 2.0

M2 C1 vout

Figure P4.1-12

When U is small, the expression for the charge feedthrough due to M1 in the slow regime can be approximated as

W · CGD0 + Cchannel 2  Verror =  CL  
Verror ≅ W · CGD0 (VS + VT − VL ) CL

π U CL W · CGD0 + (VS + VT − VL ) CL 2β

Because M2 is driven by the inversion of φ1 , charge is injected in the opposite direction from that of M1. The charge injected is due to the overlap capacitance and due to the channel capacitance. The overlap capacitance from the drain or source is simply Coverlap = W · CGD0 Because both the drain and the source are involved, the charge injected from both must be added. Capacitance due to the channel once M2 channel inverts is simply

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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Cchannel = W · L · Cox Consider the voltage on C1 due to charge injected from the overlap and the channel separately. The error voltage due to overlap is approximated to be Verror_overlap ≅ 2 · W · CGD0 (VS + VT − VL ) CL

Notice the factor of “2” to account for the overlap from the drain and the source. The error voltage due to the channel is approximated to be Verror_channel ≅ Cchannel CL (5 − VS − VT )

where the “5” comes from the maximum value of φ1 . If VL is zero, then the total error voltage due to M2 alone is approximately Verror_M2 ≅ 2 · W2 · CGD0 Cchannel (VS + VT ) + C (5 − VS − VT ) CL L

Since the error voltage due to M2 is in the opposite direction to that due to M1 then to minimize the overall effect due to charge injection, the error due to M1 and M2 should be made equal. Therefore 2 · W2 · CGD0 Cchannel W1 · CGD0 (VS + VT ) = (VS + VT ) + C (5 − VS − VT ) CL CL L (W1 · CGD0) (VS + VT ) = (2 · W2 · CGD0) (VS + VT ) + Cchannel_M2 (5 − VS − VT ) (W1 · CGD0) (VS + VT ) = (2 · W2 · CGD0) (VS + VT ) + W2 L2COX (5 − VS − VT ) W1 = 2 · W2 + W2 L2COX (5 − VS − VT ) CGD0 (VS + VT )

L2COX (5 − VS − VT )    W1 = W2  2 + CGD0 (VS + VT )  

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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-1 L2COX (5 − VS − VT )    W2 = W1  2 + CGD0 (VS + VT )   Design L2 to be the minimum allowed device length and calculate W2.

Problem 4.3-1 Figure P4.3-1 illustrates a source-degenerated current source. Using Table 3.1-2 model parameters calculate the output resistance at the given current bias.

10 µA 2/1 +

VGG

vOUT 100K -

Figure P4.3-1

The small-signal model of this circuit is shown below

iout gmvgs rds gmbsvbs + vs vout +

r

-

First calculate dc terminal conditions.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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ID = 10 µA VS = ID × R = 10 × 10-6 × 100 × 103 = 1 volt VS = VSB vout rout = i = r + rds + [(gm + gmbs)rds]r ≅ (gmrds)r out gm ≅ (2K'W/L)|ID| = 2× 110×10-6 ×2/1 × 10×10-6 = 66.3 ×10-6 = 66.3×10-6 0.4 = 10.17×10-6 2(0.7 + 1)1/2

gmbs = gm

2(2|φF| + VSB)1/2

γ

gds ≅ ID λ = 10×10-6 × 0.04 = 400×10-9 1 rds = g = 2.5×106 ds thus rout = 100 × 103 + 2.5×106 + [(66.3 ×10-6 + 10.17×10-6) 2.5×106] 100 × 103 = 21.7×106 rout = 21.7×106 Problem 4.3-2 Calculate the minimum output voltage required to keep device in saturation in Problem 4.3-1. The minimum voltage across drain and source while remaining in saturation is VON VON = 2iD

β

=

2 × 10 ×10-6 = 2 × 110 ×10-6

10 110 = 0.302

The minimum drain voltage is VD(min) = VS(min) + VON = 1 + 0.302 = 1.302

Problem 4.3-3

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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Using the cascode circuit shown in Fig. P4.3-3, design the W/L of M1 to achieve the same output resistance as the circuit in Fig. P4.3-1. Ignore body effect.
10 µA + 2/1 VGC M2 vOUT

M1

-

Figure P4.3-3

rDS1 = g

1 m1 1 gm = 100 kΩ gm1 = 1 ≅ 100 kΩ 2K'(W/L)1ID =
2

2× 110×10-6 × 10×10-6

(W/L)1

 10-5 1 W   L =   = 22  1  2× 110×10-6 × 10×10-6 From the previous problem, gm2 = 66.3 ×10-6 rds2 = 2.5×106 Note that the terminal conditions of M2 must change in order to support the larger gate voltage required on M1. This will be addressed in the next problem. Problem 4.3-4 Calculate the minimum output voltage required to keep device in saturation in Problem 4.3-3. Compare this result with that of Problem 4.3-2. Which circuit is a better choice in most cases?

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

21

First calculate the gate voltage of M1 VGS1 = 2ID K'(W/L) + VT = 20 µ + 0.7 = 2.7 110 µ (1/22)

From Problem 4.3-2, VON2 = 0.302 Therefore, the minimum output voltage to keep devices in saturation is Vout(min) = VGS1+ VON2 = 2.7 + .302 = 3.02 In for the circuit in problem 4.3-2, the minimum output voltage is lower than the circuit in 4.3-3 and is thus generally a better choice. Problem 4.3-5 Calculate the output resistance and the minimum output voltage, while maintaining all devices in saturation, for the circuit shown in Fig. P4.3-5. Assume that IOUT is actually 10µA. Simulate this circuit using SPICE LEVEL 3 model (Table 3.4-1) and determine the actual output current, IOUT . Use Table 3.1-2 for device model information.
10 µA iOUT + 5/1 M4 5/1 M1 M3 5/1 5/1 vOUT M2

Figure P4.3-5

First calculate node voltages and currents. Assume a near perfect current mirror so that the current in all devices is 10 µA. Calculate node voltages. VGS3 = VG3 = 2iD + VT = 2 × 10 ×10-6 + 0.7 = 5 × 110 ×10-6 20 550 + 0.7 = 0.891

β

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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VSB2 = VG3 = 0.891 VDS1 = VG3 + VGS4 − VGS2 because all devices are matched. gm2 = gm4 ≅ (2K'W/L)|ID| = 2× 110×10-6 ×5/1 × 10×10-6 = 104.9 ×10-6 = 104.9 ×10-6 0.4 = 16.63×10-6 2(0.7 + 0.891)1/2

gmbs2 =gmbs4 = gm2

2(2|φF| + VSB

γ

)1/2

vout rout = i = rds1 + rds2 + [(gm2 + gmbs2)rds2] rds1 out gds1 = gds2 ≅ ID λ = 10×10-6 × 0.04 = 400×10-9 1 rds1 =rds2 = g = 2.5×106 ds rout = rds1 + rds2 + [(gm2 + gmbs2)rds2] rds1 = 2.5×106+ 2.5×106 rout = 2.5×106+ 2.5×106 + [(104.9 ×10-6 + 16.63×10-6) 2.5×106] 2.5×106 rout = 764×106 Spice Simulation
IBIAS 5 10 µA iOUT 2 5/1 M4 5/1 3 M3 5/1 5/1 M1 1 VOUT M2

VPLUS

4

Spice simulation circuit

Problem 4.3-5 M4 4 4 3 0 nch w=5u l=1u M3 3 3 0 0 nch w=5u l=1u M2 2 4 1 0 nch w=5u l=1u

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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m1 1 3 0 0 nch w=5u ibias 5 4 10u vplus 5 0 5 vout 2 0 3 .op .model nch NMOS + LEVEL = + VTO = + UO = + TOX = + NSUB = + XJ = + LD = + NFS = + VMAX = + DELTA = + ETA = + KAPPA = + THETA = + CGDO = + CGSO = + CGBO = + MJ = + CJSW = + MJSW = .model pch + LEVEL + VTO + UO + TOX + NSUB + XJ + LD + NFS + VMAX + DELTA + ETA + KAPPA + THETA + CGDO + CGSO + CGBO + MJ .end PMOS = = = = = = = = = = = = = = = = =

l=1u

3 0.70 660 1.40E-08 3E+16 2.0e-7 1.6E-08 7e+11 1.8e5 2.40 0.1 0.15 0.1 2.20E-10 2.20E-10 7.00E-10 0.50 3.50E-10 0.38

3 -0.70 210 1.40E-08 6.00e16 2.0e-7 1.5E-08 6E+11 2.00e5 1.25 0.1 2.5 0.1 2.20E-10 2.20E-10 7.00E-10 0.50

DC Operating Point Analysis, 27 deg C Fri Aug 30 23:00:34 2002 ----------------------------------------------------------------------->>> i(vout) = -1.0157e-005 i(vplus) = -1.0000e-005 v(0) = 0.0000e+000 v(1) = 8.5259e-001 v(2) = 3.0000e+000 v(3) = 8.1511e-001 v(4) = 1.7609e+000 v(5) = 5.0000e+000

Problem 4.3-6

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Calculate the output resistance, and the minimum output voltage, while maintaining all devices in saturation, for the circuit shown in Fig. P4.3-6. Assume that IOUT is actually 10µA. Simulate this circuit using SPICE Level 3 model (Table 3.4-1) and determine the actual output current, IOUT . Use Table 3.1-2 for device model information.
10 µA 10 µA iOUT + M2 M4 1/1 M1 M3 4/1 4/1 4/1 vOUT

Figure P4.3-6

First calculate node voltages and currents. Assume a near perfect current mirror so that the current in all devices is 10 microamps. Calculate node voltages. VGS4 = VG4 = VGS3 = VG3 = -VGS of M2 must be solved taking into account the back-bias voltage and its effect on threshold voltage. The following equations relate to M2 terminals (subscripts dropped for simplicity) VGS = VG − VS = 2iD + VT0 + γ   |2φf| + vSB − |2φf|   2iD + VT = 2 × 10 ×10-6 + 0.7 = 1 × 110 ×10-6 2 × 10 ×10-6 + 0.7 = 4 × 110 ×10-6 20 110 + 0.7 = 1.126 20 + 0.7 = 0.913 440

β β

2iD

+ VT =

β

Noting that the bulk terminal is ground we get VG − VS = 2iD + VT0 + γ   |2φf| + vS − |2φf|  

β

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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VG − VS − VG − 2iD

2iD

β

− VT0 + γ

|2φf| = γ  

|2φf| + vS   |2φf| + vS  

β

− VT0 + γ |2φf| + vS  

|2φf| − VS = γ  

A − VS = γ   where A = VG −

2iD

β

− VT0 + γ

|2φf|

2 (A − VS) = γ2 |2φf| + vS    2 A2 − 2AVS + VS = γ2 |2φf| + vS    2 VS − VS( 2A + γ2) + A2 − γ2|2φf|  = 0  

Now solving numerically: A = VG −
2

2iD

β

− VT0 + γ

|2φf| = 1.126 −

20 − 0.7 + 0.4 0.7 = 0.5475 440

VS − VS [2(0.5475) + 0.42] + 0.54752 − 0.42( 0.7 ) = 0 VS − VS (1.255) + 0.1877 = 0 VS = 0.1736 VON = 2iD = 20 = 0.2132 440
2

β

VOUT (min) = VON + VS = 0.2132 + 0.1736 = 0.3868 Small signal calculation of output resistance: gm1 = gm2 ≅ (2K'W/L)|ID| = 2× 110×10-6 ×4/1 × 10×10-6 = 93.81 ×10-6

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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gmbs2 = gm2

2(2|φF| + VSB

γ

)1/2

= 93.81 ×10-6

0.4 = 20.07×10-6 2(0.7 + 0.1736)1/2

vout rout = i = rds1 + rds2 + [(gm2 + gmbs2)rds2] rds1 out gds1 = gds2 ≅ ID λ = 10×10-6 × 0.04 = 400×10-9 1 rds1 =rds2 = g = 2.5×106 ds rout = rds1 + rds2 + [(gm2 + gmbs2)rds2] rds1 = 2.5×106+ 2.5×106 rout = 2.5×106+ 2.5×106 + [(93.81 ×10-6 + 20.07×10-6) 2.5×106] 2.5×106 rout = 717×106 Spice Simulation
5 IBIAS1 10 µA 3 M2 M4 1/1 4 M1 M3 4/1 4/1 4/1 1 VOUT 10 µA iOUT 2 IBIAS2

VPLUS

Spice simulation circuit

Problem 4.3-6 M4 3 3 0 0 nch M3 4 4 0 0 nch M2 2 3 1 0 nch m1 1 4 0 0 nch ibias1 5 3 10u ibias2 5 4 10u vplus 5 0 5 vout 2 0 3 .op

w=1u w=4u w=4u w=4u

l=1u l=1u l=1u l=1u

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.model nch + LEVEL + VTO + UO + TOX + NSUB + XJ + LD + NFS + VMAX + DELTA + ETA + KAPPA + THETA + CGDO + CGSO + CGBO + MJ + CJSW + MJSW .model pch + LEVEL + VTO + UO + TOX + NSUB + XJ + LD + NFS + VMAX + DELTA + ETA + KAPPA + THETA + CGDO + CGSO + CGBO + MJ .end

NMOS = = = = = = = = = = = = = = = = = = = PMOS = = = = = = = = = = = = = = = = =

3 0.70 660 1.40E-08 3E+16 2.0e-7 1.6E-08 7e+11 1.8e5 2.40 0.1 0.15 0.1 2.20E-10 2.20E-10 7.00E-10 0.50 3.50E-10 0.38

3 -0.70 210 1.40E-08 6.00e16 2.0e-7 1.5E-08 6E+11 2.00e5 1.25 0.1 2.5 0.1 2.20E-10 2.20E-10 7.00E-10 0.50

Problem 4.3-6 DC Operating Point Analysis, 27 deg C Mon Sep 02 16:24:37 2002 ----------------------------------------------------------------------->>> i(vout) = -8.1815e-006 i(vplus) = -2.0000e-005 v(0) = 0.0000e+000 v(1) = 3.2664e-001 v(2) = 3.0000e+000 v(3) = 1.1450e+000 v(4) = 8.4156e-001 v(5) = 5.0000e+000

Problem 4.3-7 Design M3 and M4 of Fig. P4.3-7 so that the output characteristics are identical to the circuit shown in Fig. P4.3-6. It is desired that IOUT is ideally 10µA.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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5µA

5µA

iOUT + M2

M4

4/1 vOUT M1 M3 4/1 -

Figure P4.3-7

By comparison with the circuit in P4.3-6, the output transistors are identical but the bias currents are halved. In order to achieve the same gate voltages on M1 and M2, the W/L of M3 and M4 must be half of those in Fig P4.3-6. This is illustrated in the following equations. 2iD K'(W/L) + VT 2(5µA) + VT = VGS (10µA) = K'(W/L)5µA = 2(10µA) K'(W/L)10µA 2(10µA) + VT K'(W/L)10µA

VGS =

VGS (5µA) = 2(5µA) K'(W/L)5µA

5µA 10µA = (W/L) (W/L)5µA 10µA (W/L)10µA 10µA = =2 (W/L)5µA 5µA (W/L)10µA = 2(W/L)5µA Thus for Fig. 4.3-7 (W/L)4 = 1/2 (W/L)3 = 2/1 Problem 4.3-8

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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For the circuit shown in Fig. P4.3-8, determine IOUT by simulating it using SPICE Level 3 model (Table 3.4-1). Use Table 3.1-2 for device model information. Compare the results with the SPICE results from Problem 4.3-6.
10 µA 10 µA iOUT + M2 M4 1/1 4/1 M3 M1 4/1 vOUT

4/1

4/1 -

Figure P4.3-8

5 IBIAS1 10 µA 3 M5 M4 1/1 6 M3 10 µA 4

IBIAS2

iOUT 2 M2 4/1 1 VOUT

VPLUS

M1

4/1

4/1

Spice simulation circuit

Problem 4.3-8 M5 4 3 6 0 nch M4 3 3 0 0 nch M3 6 4 0 0 nch M2 2 3 1 0 nch m1 1 4 0 0 nch ibias1 5 3 10u ibias2 5 4 10u vplus 5 0 5 vout 2 0 3

w=4u w=1u w=4u w=4u w=4u

l=1u l=1u l=1u l=1u l=1u

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

30

.op .model nch + LEVEL + VTO + UO + TOX + NSUB + XJ + LD + NFS + VMAX + DELTA + ETA + KAPPA + THETA + CGDO + CGSO + CGBO + MJ + CJSW + MJSW .model pch + LEVEL + VTO + UO + TOX + NSUB + XJ + LD + NFS + VMAX + DELTA + ETA + KAPPA + THETA + CGDO + CGSO + CGBO + MJ .end

NMOS = = = = = = = = = = = = = = = = = = = PMOS = = = = = = = = = = = = = = = = =

3 0.70 660 1.40E-08 3E+16 2.0e-7 1.6E-08 7e+11 1.8e5 2.40 0.1 0.15 0.1 2.20E-10 2.20E-10 7.00E-10 0.50 3.50E-10 0.38

3 -0.70 210 1.40E-08 6.00e16 2.0e-7 1.5E-08 6E+11 2.00e5 1.25 0.1 2.5 0.1 2.20E-10 2.20E-10 7.00E-10 0.50

Problem 4.3-8 DC Operating Point Analysis, 27 deg C Mon Sep 02 18:01:39 2002 -----------------------------------------------------------------------i(vout) = -1.0233e-005 i(vplus) = -2.0000e-005 v(0) = 0.0000e+000 v(1) = 3.0942e-001 v(2) = 3.0000e+000 v(3) = 1.1450e+000 v(4) = 8.6342e-001 v(5) = 5.0000e+000 v(6) = 2.4681e-001

Notice that the output current is more accurate than that simulated in problem 4.3-6. This is because M3 and M1 have more closely matched terminal conditions. Problem 4.4-1

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

31

Consider the simple current mirror illustrated in Fig. P4.20. Over process, the absolute variations of physical parameters are as follows: Width variation +/- 5% Length variation +/- 5% K’ variation +/- 5% VT variation +/- 5mV Assuming that the drain voltages are identical, what is the minimum and maximum output current measured over the process variations given above.
20 µA iO

3/1 + VDS1 -

M1 + VGS -

M2

3/1 + VDS2 -

Figure P4.4-1

W iD = K' L (vGS − VT )2 and vGS = 2iD K'(W/L) + VT

Thus, combining these expressions for the circuit in Fig. P4.4-1, W 2 iO = K'2  L  (vGS2 − VT2 )  2 W  iO = K'2  L    2   2×20×10-6 + VT1 − VT2  K'1(W/L)1 
2

Minimum and Maximum occurs under the following conditions K'1 iO(min) Max K'2 Min (W/L)1 Max (W/L)2 Min VT1 Min VT2 Max

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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iO(max)

Min

Max

Min

Max

Max

Min

Substituting in the expression for drain current yields: K'1 27.82 µ 56.93 µ 115.5 µ 104.5 µ K'2 104.5 µ 115.5 µ (W/L)1 3.316 2.714 (W/L)2 2.714 3.316 VT1 0.695 0.705 VT2 0.705 0.695

Problem 4.4-2 Consider the circuit in Fig. P4.21 where a single MOS diode (M2) drives two current mirrors (M1 and M3). A signal (vsig) is present at the drain of M3 (due to other circuitry not shown). What is the effect of vsig on the signal at the drain of M1, vOUT ? Derive the transfer function vsig(s)/ vOUT(s). You must take into account the gate-drain capacitance of M3 but you can ignore the gate-drain capacitance of M1. Given that IBIAS=10µA, W/L of all transistors is 2µm/1µm, and using the data from Table 3.1-2 and Table 3.2-1, calculate vOUT for vsig =100mV at 1MHz.

IBIAS

IBIAS

IBIAS

+ vOUT vsig M1 M2 M3

Figure P4.4-2

The small-signal model for Fig. 4.4-2 is

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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Cgd3

vg1 gm1vg1 vOUT r1

vsig

gm3vgs3

r3

Cgs1+Cgs2

1/gm2

Cgd3

vg1 vOUT gm1vg1

vsig

Z

r1

Z   vg1 = vsig Z + 1/sCgd3    Z vsig  vOUT = -gm1 r1 vg1 = -gm1 r1    Z + 1/sCgd3 vOUT s Cgd3   = -gm1 r1 s (C +C +C ) + g  vsig gd3 gs1 gs2 m1  vOUT(ω)    = -gm1 r1    vsig (ω)     2 [ω (Cgd3+Cgs1+Cgs2)]2 + gm1  ω Cgd3

The transfer function has the following poles and zeros.

ωp =  C + C + C  gs1 gs2  gd3 ωz = r1 = gm1 = gm1 Cgd3 1 1 = = 2.5 × 106 λid 0.04 × 10 × 10-6 2K'(W/L)iD = 2 × 110 × 10-6 × 2× 10 × 10-6 = 66.33 × 10-6



gm1



CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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Cgs1 =

2 C × W × L + CGSO × W = 3.29 fF + 0.44 fF = 3.73 fF 3 ox

Cgs1 = Cgs2 Cgd3 = CGSO × W = 0.44 fF Substituting numerical values yields: vOUT(ω)   = 66.33 × 10-6 × 2.5 × 106 ×  vsig (ω)   ×     [6.28 × 106 (0.44 × 10-15+ 3.73 × 10-15+ 3.73 × 10-15)]2 + (66.33 × 10-6)2 6.28 × 106 × 0.44 × 10-15

vOUT(ω)   = 6.91 × 10-3 at ω = 6.28 Mrps vsig (ω)   For vsig = 100 mV vOUT = vsig × 6.91 × 10-3 = 100 × 10-3 × 6.91 × 10-3 = 691 µV Problem 4.5-1 Show that the sensitivity of the reference circuit shown in Fig. 4.5-2(b) is unity.

βP

  2  VDD − VREF − | VTP | 

2

N = 2  VREF − VTN   

β

2

 βP 1/2    VDD − VREF − | VTP |  =  VREF − VTN      βN   βP  β   N
1/2

 V − |V | + V TP  TN  DD  βP  1+   βN
1/2

VREF =

When:

βP = βN , | VTP | = VTN then CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

35

VREF =

VDD 2

∂VREF ∂ VDD

= ??

Use a small-signal model to simplify analysis.
VDD

gmp

+ gmn VREF

-

Figure P4.5-1

∂VREF

vREF = v ∂VDD DD 1/gmN gmP = 1/g + 1/g = g + g ∂VDD mN mP mN mP = 2βP ID 2βP ID + 2βN ID ID ID + ID

∂VREF

∂VREF ∂VDD
VREF

=

= 1/2

S
VDD

∂VREF  VDD  1/2 =  = =1  ∂VDD  VREF 1/2

Problem 4.5-2

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Fig P4.5-2 illustrates a reference circuit that provides an interesting reference voltage output. Derive a symbolic expression fo VREF .
5 volts

I

M4 M3 4/1 1/1

4/1 M1 4/1

M2

VREF

Fig. P4.5-2

VGS1 + VGS3 − VGS4 = VREF VREF = VON1 + VT1 + VON3 + VT3 − VON4 − VT4 VT4 = VT3 VON1 = VON3 VON4 = 2VON3 VREF = 2VON1 + VT1 + VT3 − 2VON1 − VT3 = VT1 VREF = VT1 Problem 4.5-3 Figure P4.5-3 illustrates a current reference. The W/L of M1 and M2 is 100/1. The resistor is made from n-well and its nominal value is 400kΩ at 25 °C. Using Table 3.1-2 and an n-well resistor with a sheet resistivity of 1kΩ/sq. ± 40% and temperature coefficient of 8000 ppm/°C, calculate the total variation of output current seen over process, temperature of 0 to 70 °C, and supply voltage variation of ± 10%. Assume that the temperature coefficient of the threshold voltage is –2.3 mV/°C.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

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5 volts

R

Iout

M1

M2

Fig. P4.5-3

IREF = 1 R

VDD −

2IREF

β

+ VT

R = VDD − VT − IREF R

2IREF

β

Define V = VDD − VT 2IREF

β

= (V − IREF R)2

1 2  IREF R2 − 2IREF VR +  + V2 = 0 β  1  V2 2 V IREF − 2IREF  R + 2  + 2 = 0 βR  R  V 1 1 IREF = R + 2 ± R βR IREF = 2V 1 + βR β2R2 2(VDD − VT) + 1

VDD − VT 1 1 + 2 ± R R βR

βR

β2R2

Rmin (25°C) = 500kΩ × (1 − 0.4) = 300kΩ Rmax (25°C) = 500kΩ × (1 + 0.4) = 700kΩ R(T) = R(T0) × ( 1 + TC×∆T)

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

38

Rmin(0 °C) = Rmin(25 C) × ( 1 + 8000×10-6 × -25) = 300 × 0.8 = 240kΩ Rmax(70 °C) = Rmax(25 C) × ( 1 + 8000×10-6 × 45) = 700 × 1.36 = 952kΩ VT(min) (25°C) = 0.7 − 0.15 = 0.55 VT(max) (25°C) = 0.7 + 0.15 = 0.85 VT(min) (70°C) = 0.55 − 45 × 0.0023 = 0.4465 VT(max) (0°C) = 0.85 + 25 × 0.0023 = 0.9075
-6 -6 K'(max) (25°C) = 110 × 10 × 1.1 = 121 × 10

K'(min) (25°C) = 110 × 10-6 × 0.9 = 99 × 10-6 T K' (T) = K' (T0) × T   0
-1.5

-1.5 343 K'(min) (70°C) = 99 × 10 × 298 = 80.17 × 10-6   -6 -1.5 273 K'(max) (0°C) = 121 × 10 × 298 = 138 × 10-6   -6

Minimum and Maximum occurs under the following conditions K' IREF(min) IREF(max) Max Min VT Max Min VDD Min Max R Max Min

K' IREF(min) IREF(max) 80.17 × 10-6 138 × 10-6

VT 0.9075 0.4465

VDD 4.5 5.5

R 952 K 240 K

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39

Plugging in these minimums and maximums yields the following over process and temperature: IREF(min) = 3.81 × 10-6 IREF(max) = 21.3 × 10-6

Problem 4.5-4 Figure 4.5-4 illustrates a current reference circuit. Assume that M3 and M4 are identical in size. The sizes of M1 and M2 are different. Derive a symbolic expression for the output current Iout .
VDD

M4

M3

R

Iout

M2 M1 M5

Fig. P4.5-4

Assume that M3 and M4 make a perfect current mirror, as does M2 and M5. VGS2 − VGS1 + IR = 0 VT1 + VON1 − VT2 − VON2 = IR IR = VON1 − VON2 = IR = 2iD K'    2iD K'(W/L)1 − 1 (W/L)1 − 2iD K'(W/L)2

 1 (W/L)2  

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

40

1 I= R

2iD K'

  

1 (W/L)1 −

 1 (W/L)2  

Problem 4.5-5 Find the small-signal output resistance of Fig. 4.5-3(b) and Fig. 4.5-4(b).
VDD VDD

I

R

I

R

+

R1

+

R1

VREF

R2

VREF

R2

-

-

Figure 4.5-3(b)

Figure 4.5-4(b)

IT

+ Vπ rπ R1 R gmVπ R2 rο VT

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41

IT

R1 R + Vg R2 gmVg rο VT

Part a:  rπ || R1  vπ = vt  r || R + R  1 2  π vt    vt  it =  r || R + R  +  R  + gm vπ + 2    π 1 vt rο

 1   1   gm (rπ || R1)  1  it = vt  r || R + R  +  R  +  r || R + R  + r  2    π 1 2 ο  π 1 vt  R rο (rπ || R1 + R2 )  =  R r + r (r || R + R ) + R r g (r || R ) + R (r || R + R ) it  ο ο π 1 2 ο m π 1 π 1 2  if rπ || R1 >> R2 then vt it = 1 gm

Part b: vG = vt 

 R2    R 1 + R2 

vt vt vt + + it = gm vG + R R1 + R2 rο it g m R2 1 1 1 = + + + vt R 1 + R2 rο R R1 + R2

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

42

if R2 >> R1 then it 1 1 1 = gm + + + vt rο R R2 if gm >> it = gm vt 1 1 1 , g >> , gm >> then R2 m rο R

Problem 4.5-6 Using the reference circuit illustrated in Fig. 4.5-3(b), design a voltage reference having VREF=2.5 when VDD=5.0. Assume that IS = 1 fA and βF=100. Evaluate the sensitivity of VREF with respect to VDD.
VDD

I

R I1

+

R1 IB

VREF

R2

-

Figure 4.5-3

(b)

IR = 2.5 Choose R = 250 kΩ, I = 10µA I = I1 + IE choose IE = 1 µA, and I1 = 9 µA With β=100, base current is insignificant and will be ignored.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

43

2.5 2.5 I1 = R + R = 9 µA = R + R 1 2 1 2 R1 + R2 = 277.8 kΩ VREF = I1 R2 + VEB 1 µA 2.5 = 9 µA R2 + 0.0259 × ln 1 fA    R2 = 218.1 kΩ R1 = 59.64 kΩ VEB = VREF R1 R1+ R2 R1+ R2 R1+ R2 VDD − VREF  =  R Vt ln R1 R IS 1     R IS   1  R1+ R2  VDD      Vt V − V V   REF  DD REF  R IS  R1 

VREF = VEB
VREF

S
VDD VREF

∂VREF  VDD  = =   ∂VDD  VREF

S
VDD VREF

 VDD   1  R1+ R2 = V   Vt V − V   REF  DD REF  R1 

S
VDD

5  1   277.8  = 2.5 0.0259 2.5  59.64 = 0.0965     

Problem 4.6-1 An improved bandgap reference generator is illustrated in Fig. P4.6-1. Assume that the devices M1 through M5 are identical in W/L. Further assume that the area ratio for the bipolar transistors is 10:1. Design the components to achieve an output reference voltage of 1.262 V. Assume that the amplifier is ideal. What advantage, if any, is there in stacking the bipolar transistors?

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

44

VDD

M1

M2

M3

M4 opamp polarity corrected +

M5

I2

I1 + VR1 R1 + R2 VREF

Q2b

Q1b

Q2a

Q1a

Q3

-

Figure P4.6-1

VREF  

T=T0

= VG0 + Vt0 (γ − α) = 1.262 @ 300 K

KVt0 = VG0 − VBE0 + Vt0 (γ − α) VG0 − VBE0 + Vt0 (γ − α) R2 K = R  ln (10) = Vt0  1 kT  I  VBE0 = q lnI   S ∆VBE I = R =1 µA 1 R1 = 0.0259 ln(10) = 59.64 kΩ 1 µA

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

45

K=

R2 1.205 - 0.53 + 0.0259(2.2) = 28.26 kΩ = R  ln (10) 0.0259  1

R2 = 732 kΩ Stacking bipolar transistors reduces sensitivity to amplifier offset. Problem 4.6-2 In an attempt to reduce the noise output of the reference circuit shown in Fig. P4.6-1, a capacitor is placed on the gate of M5. Where should the other side of the capacitor be connected and why? The other end of the capacitor should be connected to VDD. At high frequencies, the capacitor is a small-signal short circuit. Therefore, high-frequency noise on VDD also appears at the gate of M5 and thus is not amplified by M5. If on the other hand, the capacitor was connected to ground, noise on VDD would appear as vGS of M5 and thus be amplified to the output. Problem 4.6-3 In qualitative terms, explain the effect of low Beta for the bipolar transistors in Fig. P4.6-1? In our analysis, we assume that IE = IS e(VBE/ Vt) but in reality, this is the expression for IC . If β is large, then the approximation is warranted, but if not, the performance will deviate from the ideal. Problem 4.6-4 Consider the circuit shown in Fig. P4.6-4. It is a variation of the circuit shown in Fig. P4.6-1. What is the purpose of the circuit made up of M6-M9 and Q4? This circuit performs base-current compensation so that none of the base currents in Q1b and Q2b flow into Q1a and Q2a respectively. Problem 4.6-5 Extend Example 4.6-1 to the design of a temperature-independent current based upon the circuit shown in Fig. 4.6-4. The temperature coefficient of the resistor, R4, is +1500 ppm/°C.

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

46

R3

R2

opamp polarity corrected + M1 M2

I1 I2 VR1 Q2 Q1 + R1

IREF

R4

Figure P4.6-5

 Ae1   A  = 10  e2 Veb = 0.7 , R2 = R3 , Vt = 26 mV , TC4 = 1500 ppm/°C VG0 = 1.205 , γ = 3.2 , α = 1 , T0 = 27 °C Since the amp forces V + = V − , then I1 = I2 VREF IREF = I4 + 2 I1 = R + 2 I1 4 ∆Vbe 1 kT I1 = R = R q ln(10) 1 1 We want ∂IREF ∂T ∂IREF ∂T 2 ∂I1

=0

T = T0

=

∂ VREF  ∂ (2 I1)  + ∂T R4  ∂T

2K  ln(10) = q  R ∂T   1

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

47

∂ VREF   = ∂T R4  ∂R4 ∂T

∂VREF ∂T

R4 − VREF R4
2

∂R4 ∂T

=

∂ (R + R4TC4∆T) = R4TC4 ∂T 4

∂VREF

Vt0 VBE0 − VG0 (α − γ)Vt0 = K T  + + T0 T0 ∂T  0

∂IREF

1  Vt0 VBE0 − VG0 (α − γ)Vt0 VREF 2K  ln(10) = R K  T  + + TC4 +  q  R T0 T0 R4 ∂T   4   0 1 

R2  Ae1  R2 K = R ln A  = R ln(10) 1  e2 1 R2 choose R = 10 then K = 23.03 1 I1 = thus R1 = 29.93 kΩ , and R2 = 299.3 kΩ assume that VREF = 1.262 and solve for R4 T0 R1 VG0−VBE0 (γ −α)Vt0 Vt0 VREF TC4 T0  R4 = 2 V ln(10)  + − K T  + T0 T0 T0 t  0   R1   R4 = 2 V ln(10)  (VG0−VBE0) + (γ −α)Vt0 − K Vt0 + VREF TC4 T0 t ∆ VBE kT ln(10) R1 = q  R1  = 2 µA  

R4 = 250 × 103 × 0.153 = 3825 Ω

CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002

48

VREF 1.262 IREF = R + 2 I1 = 4 × 10-6 + 3825 = 333.9 × 10-6 4

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-1

CHAPTER 5 – HOMEWORK SOLUTIONS
Problem 5.1-01 Assume that M2 in Fig. 5.1-2 is replaced by a 10kΩ resistor. Use the graphical technique illustrated in this figure to obtain a voltage transfer function of M1 with a 10kΩ load resistor. What is the maximum and minimum output voltages if the input is taken from 0V to 5V? Solution A computer generated plot of this problem is shown below.

5 +5V 4 10kΩ Vin Μ1 Vout 2µm 1µm

Vout (V)

3

2

1

0 0 1 2 Vin(V) 3 4 5
Fig. S5.1-01

The maximum output is obviously equal to 5V. The minimum output requires the following calculation assuming that M1 is in the active region. 110x10-6·2[(5-0.7)vout – 0.5vout2] = 5-vout 4.3 vout - vout2 = 2.22 → This gives, vout (min) = 4.25±4.2945 = 0.5V 5- vout 10kΩ vout2 – 9.5 vout + 4.504 = 0

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.1-02 Using the large-signal model parameters of Table 3.1-2, use Eqs. (1) and (5) to calculate the values of vOUT(max) and vOUT(min). Compare with the results shown on Fig. 5.1-2 on the voltage transfer function curve. Solution From Eq. (5.1-1), Vout (max) can be calculated as 5V

Page 5-2

M2 M1 + vIN

W2 = 1µm L2 1µm ID + vOUT W1 = 2µm L1 1µm -

Vout (max) = VDD − VTp = 4.3 V
From Eq. (5.1-5), Vout (min) can be calculated as (V − VT ) Vout (min) = VDD − VT − DD β 1+ 2 β1

-

Fig. S5.1-02

Vout (min) = 5 − 0.7 −

(5 − 0.7) = 0.183 V (50)(1) 1+ (110)(5)
5V W2 = β 2 L2 ID + vOUT W1 = β 1 L1 -

Problem 5.1-03 What value of β1/β2 will give a voltage swing of 70% of VDD if VT is 20% of VDD? What is the small-signal voltage gain corresponding to this value of β1/β2? Solution V Given VT = 0.2VDD and ( out (max) − Vout (min)) = 0.7VDD From Eq. (5.1-1) and (5.1-5)
Vout (max) − Vout (min) =

M2 M1 + vIN

-

(VDD − VT ) β 1+ 2 β1
→

Fig. S5.1-03

or,

0.7VDD =

(V DD − 0.2VDD ) β 1+ 2 β1

1 + β 2  =  8  β1   7  

2

→

β2

β1 = 0.306

The small-signal voltage gain can be given by

Av ≅ −

gm1 β = − 1 = -1.8 V/V gm 2 β2

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.1-04 What value of Vin will give a current in the active load inverter of 100µA if W1/L1 = 5µm/1µm and W2/L2 = 2µm/1µm? For this value of V in, what is the small-signal voltage gain and output resistance? Solution Assuming M 1 is operated in saturation 2   '  W  (Vin − VT ) I D1 = K N    L 1 2   (V − 0.7) 2  or, 100 µ = (110 µ )(5) in  2   The small-signal gain can be given by 5V

Page 5-3

M2 M1 + vIN

W2 = 2µm L2 1µm ID + vOUT W1 = 5µm L1 1µm -

-

Fig. S5.1-04

→ Vin = 1.303V g Av ≅ − m1 = − gm 2
Rout ≅

(K )  W   L  (K )  L   W 
' N ' P 1

= -2.345 V/V
2

The output resistance can be given by Problem 5.1-05

1 = 7.07 kΩ gm 2

Repeat Ex. 5.1-1 if the drain current in M1 and M2 is 50µA. Solution From Eqs. (5.1-1) and (5.1-5) we get vOUT(max) = 4.3V 5-0.7 vOUT(min) = 5 – 0.7 = 0.418 V 1 + (50·1/110·2) From Eq. (5.1-7) we get, gm1 vout 148.3 = - g +g +g = 2.0 + 2.5+ 70.71 = -1.972 V/V vin ds1 ds2 m2 From Eq. (5.1-8) we get, 1 106 Rout = g +g +g = 2.0 + 2.5 + 70.71 = 13.296 kΩ ds1 ds2 m2 The zero is at, gm1 148.3µS z1 = C = 0.5ff = 2.966x1011 rads/sec → 47.2 GHz gd1 The pole is at, p1 = -ω-3dB = R 1 1 (Cbd1+Cbd2+Cgs2+CL) = (13.296kΩ)(1.0225pF) out

= 73.555x106 rads/sec. → 11.71 MHz

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.1-06 Assume that W/L ratios of Fig. P5.1-6 are W1/L1 = 2µm/1µm and W 2/L2 = W3/L3 = W4/L4 = 1µm/1µm. Find the dc value of V in that will give a dc current in M1 of 110µA. Calculate the small signal voltage gain and output resistance of Fig. P5.1-6 using the parameters of Table 3.1-2. Solution Assuming all transistors are in saturation and ideal current mirroring
' I D1 = K N

Page 5-4

VDD

M2

+ vIN

M3 + M1 vOUT -

M4 100µA

Figure P5.1-6

 W   (Vin − VT )    L 1 2  
2

or,

 (V − 0.7) 2  110 µ = (110 µ )(2) in  2  

→

Vin = 1.7V

The small-signal voltage gain can be given by
' gm1 K N  W   L   I D1    = -6.95 V/V AV ≅ − =− ' gm 2 K P  L 1 W  2  I D 2 

where, I D 3 = I D 4 = 100 µA , and I D 2 = 10 µA . The output resistance can be given by
Rout ≅ 1 = 31.6 kΩ gm 2

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-5

Problem 5.1-07 Find the small-signal voltage gain and the -3dB frequency in Hertz for the active-load inverter, the current source inverter and the push-pull inverter if W1 = 2µm, L1 = 1µm, W2 = 1µm, L2 = 1µm and the dc current is 50µA. Assume that Cgd1 = 4fF, Cbd1 = 10fF, Cgd2 = 4fF, Cbd2 = 10fF and CL = 1pF.

VDD M2 ID vIN vOUT M1

VGG2 vIN M2 ID vOUT M1 vIN ID

M2 vOUT M1

Active Current PushPMOS Load Source Load pull Inverter Inverter Inverter Figure 5.1-1 Various types of inverting CMOS amplifiers.
Solution 1. Active load inverter The output resistance can be given by 1 1 = 14.14 kΩ Rout ≅ = gm 2 2(50 µ )(1)(50 µ ) The total output capacitance can be given by Cout = CL + Cgs2 + Cbd 2 + Cgd 1 + Cbd 1 = 1.029 pF The –3 dB frequency can be given by 1 f −3 dB = = 10.9 MHz 2πRout Cout 2. Current-source inverter The output resistance can be given by 1 1 Rout ≅ = = 222.22 kΩ gds1 + gds2 I D ( λN + λP ) The total output capacitance can be given by Cout = CL + Cgd 2 + Cbd 2 + Cgd 1 + Cbd 1= 1.028 pF The –3 dB frequency can be given by 1 f −3 dB = = 0.697 MHz 2πRout Cout

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.1-07 - Continued 3. Push-pull inverter The output resistance can be given by
Rout ≅ 1 1 = = 222.22 kΩ gds1 + gds2 I D ( λN + λP )

Page 5-6

The total output capacitance can be given by

Cout = CL + Cgd 2 + Cbd 2 + Cgd 1 + Cbd 1= 1.028 pF
The –3 dB frequency can be given by f −3 dB = 1 2πRout Cout

= 0.697 MHz

Problem 5.1-08 What is the small-signal voltage gain of a current-sink inverter with W1 = 2µm, L1 = 1µm, W2 = L2 = 1 µm at ID = 0.1, 5 and 100 µA? Assume that the parameters of the devices are given by Table 3.1-2. 1. I D = 0.1 µA gm1 =

5V W2 = 2µm L2 1µm ID + vOUT W1 = 2µm L1 1µm -

2.5V

M2 M1 + vIN

(0.1µ ) = 1.538 µS I D1 = n pVt (2.5)(26 m) gm1 gm1 =− = - 170.9 V/V (gds1 + gds2 ) ID (λN + λP )

-

Av = −

2. I D = 5 µA
' gm1 = 2K P

W  I = 31.62 = 31.62 µS  L 1 D1

Av = −

gm1 gm1 =− = - 70.27 V/V (gds1 + gds2 ) ID (λN + λP )

3. I D = 100 µA
' gm1 = 2K P

W  I = 141.42 µS  L 1 D1

Av = −

gm1 gm1 =− = -15.71 V/V (gds1 + gds2 ) ID (λN + λP )

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-7

Problem 5.1-09 A CMOS amplifier is shown. Assume M1 and M2 operate in the saturation region. a.) What value of VGG gives 100µA through M1 and M2? b.) What is the DC value of vIN? c.) What is the small signal voltage gain, vout/vin, for this amplifier? d.) What is the -3dB frequency in Hz of this amplifier if Cgd = Cgd = 5fF, Cbs = Cbd = 30fF, and CL = 500fF? Solution a) VGG = VT 2 + Vdsat 2
VGG = VT 2 + 2ID 2 = 2.05 V K (W L) 2
' N

VDD M1 vin M2 VGG Figure P5.1-9 5µm/1µm vout 1µm/1µm

b) Vin = VDD − VT 1 − c) Av = d)

2 I D1 = 3.406 V K (W L)1
' P

v out gm1 =− = -24.85 V/V v in (gds1 + gds2 )

f −3 dB =

2π Cgd 1 + Cgd 2 + Cbd 1 + Cbd 2 + CL

(

(gds1 + gds2 )

)

= 2.51 MHz.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-8

Problem 5.1-10 A current-source load amplifier is shown. (a.) If C BDN =CBDP = 100fF, CGDN =C GDP = 50fF, C GSN = C GSP = 100fF, and C L = 1pF, find the -3dB frequency in Hertz. M3 (b.) If Boltzmann’s constant is Joules/°K, find the equivalent input thermal noise voltage of this amplifier at room temperature (ignore bulk effects, η = 0). Solutions (a.) The -3dB frequency is equivalent to the magnitude of the output pole which is given as
Fig. P5.1-10 VDD M2 100µA vin vout

1.38x10-23

CL
M1

All W/L's equal 10

1 1 1 1 Cout where Rout = gds1+gds2 = 100µA(0.04+0.05) = 9x10-6 = 111kΩ out Cout = Cgd1+Cbd1+Cgd2+Cbd2+CL = 0.05 + 0.05 + 0.1 + 0.1 +1 pF = 1.3pF

ω-3dB = R

1 ∴ ω-3dB = 0.111MΩ·1.3pF = 6.923x106 rads/sec. → (b.) The noise voltage at the output can be written as  gm1 2  gm2 2 eno 2 = en1 2 g +g  + en2 2 g +g   ds1 ds2  ds1 ds2

f-3dB = 1.102 MHz

Reflecting this noise voltage back to the input gives the equivalent input noise as, 8kT  g 3g  gm2  gm22en22  m22 m2   eni 2 = en1 2 1 +g  e   = en1 2 1 + g  8kT = en1 21 + g    m1  n1  m1    m1 3g    m1 where gm1 = and
2

2IDKNW1 = 469µS, gm2 = L1

2IDKPW2 = 316µS, L2

8kT 8·1.38x10-23·300 en1 = 3g = = 2.354x10-17 V2/Hz 3·469x10-6 m1

eni 2 = 2.354x10-17·1.6738 = 3.94x10-17V2/Hz → eni = 6.277nV/ Hz

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-9

Problem 5.1-11 Six inverters are shown. Assume that KN' = 2KP' and that λN = λP, and that the dc bias current through each inverter is equal. Qualitatively select, without using extensive calculations, which inverter(s) has/have (a.) the largest ac small signal voltage gain, (b.) the lowest ac small signal voltage gain, (c.) the highest ac output resistance, and (d.) the lowest ac output resistance. Assume all devices are in saturation.

VDD M2 vIN vOUT vIN M1 Circuit 1 M1 Circuit 2 M2 vOUT vIN M1 Circuit 3 Circuit 4 vIN M2 vOUT M1 vIN M1 Circuit 5 VBN Circuit 6 M2 vOUT M2 vOUT vIN M2 vOUT M1

VBP

Figure P5.1-11
Solution Circuit 1 gmN= 2 gmP Circuit 2 gmP Circuit 3 gmN= 2 gmP ≈g 1 mP gm

Circuit 4 gmP ≈g 1 mN Circuit 5 gmN= 2 gmP

Circuit 6 gmP

1 1 Rout ≈gmN+gmbN ≈gmP+gmbP 0.707 =g +g mP mbP |Gain| gmP gmP+gmbP gmP gmP+gmbP

0.707 ≈ g mP 2 1 2

1 1 gdsN+gdsP gdsN+gdsP = = 1 1 gdsP(1+ 2) gdsP(1+ 2) gmP 2 gmP gdsP(1+ 2) gdsP(1+ 2)

(a.) (b.) (c.) (d.)

Circuit 5 has the highest gain. Circuit 4 has the lowest gain (assuming normal values of gm/gmb). Circuits 5 and 6 have the highest output resistance. Circuit 1 has the lowest output resistance.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.1-12 Derive the expression given in Eq. (5.1-29) for the CMOS push-pull inverter of Fig. 5.1-8. If Cgd1 = Cgd2 = 5fF, Cbd1 = Cbd2 = 50fF, CL = 10 pF, and ID = 200 µA, find the small-signal voltage gain and the −3 dB frequency if W1/L1 = W2/L2 = 5 of the CMOS push-pull inverter of Fig. 5.1-8. Solution The effective transconductance can be given by  ' W   ' W  gm ,eff = gm1 + gm 2 = 2 I D  K N + KP  L 1  L 2    The output conductance can be given by g out = (g ds1 + g ds 2 ) = I D (λ1 + λ 2 ) Thus, the small-signal gain becomes g m, eff Av = − g out  ' W   ' W  + KP KN  L 1  L 2  2  Av = −   ID (λ1 + λ2 )     For I D = 200 µA Av = −43.63 = -43.63 V/V The total capacitance at the output node is Ctotal = Cgd 1 + Cgd 2 + Cbd 1 + Cbd 2 + CL = 10.11 pF. Thus, the –3 dB frequency is gout f −3 dB = = 283.36 kHz. 2πCtotal

Page 5-10

5V W2 = 2µm L2 1µm ID + vOUT W1 1µm = L1 1µm Fig.P 5.1-12

M2 + vIN M1

Eq. (5.1-29)

(

)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.1-13

Page 5-11

For the active-resistor load inverter, the current-source load inverter, and the push-pull inverter compare the active channel area assuming the length is 1µm if the gain is to be −1000 at a current of ID = 0.1 µA and the PMOS transistor has a W/L of 1.

VDD M2 ID vIN vOUT M1

VGG2 vIN M2 ID vOUT M1 vIN ID

M2 vOUT M1

Active Current PushPMOS Load Source Load pull Inverter Inverter Inverter Figure 5.1-1 Various types of inverting CMOS amplifiers.
Soluton Given, I D = 10 µA , and Av = −100 V/V a) Active-resistor load inverter g Av ≅ − m1 g m2

→

100 =

’ K N ( L )1 W ’ K P (1)

→

W1 L1 = 4546

Active area = 4546·1 + 5·1 = 4551 µm2 b) Current-source load inverter g m1 Av = − (g ds1 + g ds 2 )
’ 2 K N ( L )1 W I D (λ1 + λ 2 )2

→

100 =

→

W1 L1 = 3.64

Active area = 3.64·1 + 5·1 = 8.64 µm 2 c) Push-pull inverter
Av = −
’ ’ W1 2 K N ( L )1 + 2 K P ( / 1) 1 W → L = 1.55 1 I D (λ1 + λ 2 )2

(g m1 + g m2 ) → (g ds1 + g ds 2 )

100 =

Active area = 1.55·1 + 5·1 = 4.55 µm 2

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.1-14 For the CMOS push-pull inverter shown, find the small signal voltage gain, Av, the output resistance, Rout, and the -3dB frequency, f-3dB if ID = 200µA, W1 /L1 = W2/L2 = 5, Cgd1 = Cgd2 = 5fF, Cbd1 = Cbd2 = 30fF, and CL = 10pF. Solution The small-signal model for this problem is shown below.

Page 5-12

VDD

M2 vIN M1
VSS

vOUT

CM
+ vin gm1vin rds1 gm2vin rds2

iout + vout -

Fig. P5.1-14

Cout

Fig. S5.1-14

Summing the currents at the output (ignoring the capacitors) gives, gm1vin + gds1vout + gm2vin + gds2vout = 0 Solving for the voltage gain gives, W1 2 L I D KN +
1

gm1+ gm2 vout =- g +g =vin ds1 ds2 vout vin = Av = ∴ 2 200x10-6

W2 2 L I D KP
2

I D ( λ N+ λ P )

=-

2 ID

W1 W2 KN + L1 L 2 KP λ N+ λ P

5·110x10-6 + 5·50x10-6 = - (100)(0.436) = - 43.63V/V 0.05 + 0.04

Av = - 43.63V/V

The output resistance is found by setting vin = 0 and solving for vout/iout. Rout is simply expressed as, 1 1 1 = = = 55.55kΩ Rout = g + g ID(λN+ λP) 200x10-6 (0.05+0.04) ds1 ds2 ∴ Rout = 55.55kΩ gds1 + gds2 1 = Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL Rout(Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL)

From Eq. (5.1-26) we can solve for the –3dB frequency as

ω-3dB = ω1 =
= ∴

1 1 ≈ = 1.8x106 rad/s 55.55x10-3( 5fF + 5fF + 30fF + 30fF + 10pF ) 55.55x103·10x10-12

ω-3dB = 1.8x106 rad/s → f-3dB = 286.5 kHz

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-13

Problem 5.2-01 Use the parameters of Table 3.1-2 to calculate the small-signal, differential-in, differential-out transconductance g md and voltage gain Av for the n-channel input, differential amplifier when ISS = 100 µ A and W1/L1 = W2/L2 = W3/L3 = W4/L4 = 1 assuming that all channel lengths are equal and have a value of 1µm. Repeat if W1/L1 = W2/L2 = 10W3/L3 = 10W4/L4 = 10. Solution Referring to Fig. 5.2-5 and given that a)
W  W  W  W  = = = =1  L 1  L  2  L  3  L  4

Differential-in differential-out transconductance is given by
' gmd = gm1 = gm 2 = K N

W  I = 104.8 µS  L 1 SS

Small-signal voltage gain is given by
Av = gm 2 2 gm 2 = = 23.31 V/V (gds2 + gds4 ) ISS (λ2 + λ4 )

b)

W  W  W  W  = 10 = = 10 = 10  L 1  L  2  L 3  L 4 gmd = gm1 = gm 2 = 331.4 µS

Av =

gm 2 = 36.82 V/V (gds2 + gds4 )

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-14

Problem 5.2-02 Repeat the previous problem for the p-channel input, differential amplifier. Solution Referring to Fig. 5.2-7 and given that (a.)
W  W  W  W  = = = =1  L 1  L  2  L  3  L  4

Differential-in differential-out transconductance is given by
' gmd = gm1 = gm 2 = K P

W  I = 70.71 µS  L 1 SS

Small-signal voltage gain is given by
Av = gm 2 2 gm 2 = = 15.7 V/V (gds2 + gds4 ) ISS (λ2 + λ4 )

(b.)

W  W  W  W  = 10 = = 10 = 10  L 1  L  2  L 3  L 4 gmd = gm1 = gm 2 = 223.6 µS

Av =

gm 2 = 24.84 V/V (gds2 + gds4 )

Problem 5.2-03 Develop the expressions for VIC(max) and VIC(min) for the p-channel input differential amplifier of Fig. 5.2-7. Solution The maximum input common-mode input is given by
V IC (max) = VDD − (VT 1 + Vdsat1 + Vdsat 5 )

or,

 I DD 2 I DD  VIC (max) = VDD −  VT 1 + +  ' ' K P (W L)1 K P (W L) 5  

The minimum input common-mode input is given by
V IC (min) = VSS − VT 1 + VT 3 + Vdsat 3

or,

VIC (min) = VSS − VT 1 + VT 3 +

I DD K (W L) 3
' N

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-15

Problem 5.2-04 Find the maximum input common mode voltage, v IC (max) and the minimum input common mode voltage, vIC(min) of the n-channel input, differential amplifier of Fig. 5.25. Assume all transistors have a W/L of 10µm/1µm, are in saturation and ISS = 10µA. What is the input common mode voltage range for this amplifier? Solution The maximum input common-mode input is given by
V IC (max) = VDD + VT 1 − VT 3 − Vdsat 3

or,

VIC (max) = VDD + VT 1 − VT 3 −

I SS = 4.86 V K (W L) 3
' P

The minimum input common-mode input is given by
V IC (min) = VSS + VT 1 + Vdsat1 + Vdsat 5

or,

VIC (min) = VSS + VT 1 +

I SS 2 I SS = 0.93 V + ' K (W L)1 K N (W L) 5
' N

So, the input common-mode range becomes
ICMR = VIC (max) − VIC (min) = 3.93 V

Problem 5.2-05 Find the small signal voltage gain, vo/vi, of the circuit in the previous problem if vin = v1 - v2. If a 10pF capacitor is connected to the output to ground, what is the -3dB frequency for Vio(jω)/VIN(jω) in Hertz? (Neglect any device capacitance.) Solution Small-signal voltage gain is given by
Av = gm 2 2 gm 2 = = 233.1 V/V (gds2 + gds4 ) ISS (λ2 + λ4 )

The –3 dB frequency is given by

f −3 dB ≅

(gds2 + gds4 ) = ISS (λ2 + λ4 )
2πCL 4 πCL

= 7.16 kHz.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-16

Problem 5.2-06 For the CMOS differential amplifier of Fig. 5.2-5, find the small signal voltage gain, vout/vin, and the output resistance, Rout, if ISS = 10µA, V DD = 2.5V and vin = vgs1-vgs2. If the gates of M1 and M2 are connected together, find the minimum and maximum common mode input voltage if all transistors must remain in saturation (ignore bulk effects). Solution Small-signal model for calculations:

+ vin + + vgs2 vgs1 gm1vgs1 Rout = g

iout i3 1 rds1 rds3 gm3 + vout -

gm2vgs2

i3

rds2

rds4

Fig. S5.2-06

1 1 + gds4 = (0.04 + 0.05)5µA = 2.22 MΩ ds2 gm1gm3rp1  vout =  vgs1 − gm2vgs2Rout ≈ (gm1vgs1 – gm2vgs2)Rout = gm1Routvin  1 + gm3rp1  vout ∴ v = gm1Rout = gm2Rout , gm1= gm2 = 2·110·5·2) µS = 46.9 µS in vout vin = 46.9µS·2.22MΩ = 104.1 V/V Common mode input range:  Vicm(max) = VDD – VSG3 + VTN = 2.5 -   Vicm(min) = 0+VDS5(sat)+VGS1= = 1.2147 V 2·10   110·2   2·5  50·2+0.7 + 0.7 = 2.5 - 0.3162 = 2.184 V  2·5  110·2+0.7 = 0.3015+0.9132

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-17

Problem 5.2-07 Find the value of the unloaded differential-transconductance gain, gmd, and the unloaded differential-voltage gain, Av, for the p-channel input differential amplifier of Fig. 5.2-7 when ISS = 10 microamperes and ISS = 1 microampere. Use the transistor parameters of Table 3.1-2. Solution Assuming all transistors have W/L = 1 a) Given, I SS = 10 µA
' gmd = K P

W  I = 22.36 µS  L 1 SS

Av =

gmd 2 gmd = = 49.69 V/V (gds2 + gds4 ) ISS (λ2 + λ4 )

b) Given, I SS = 1 µA
' gmd = K P

W  I = 7.07 µS  L 1 SS

Av =

gmd 2 gmd = = 157.11 V/V (gds2 + gds4 ) ISS (λ2 + λ4 )

Problem 5.2-08 What is the slew rate of the differential amplifier in the previous problem if a 100 pF capacitor is attached to the output? Solution Slew rate can be given as I SR = SS CL For I SS = 10 µA and C L = 100 pF I SR = SS = 0.1 V/µs CL For I SS = 1 µA and C L = 100 pF
SR = I SS = 0.01 V/µs CL

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-18

Problem 5.2-09 Assume that the current mirror of Fig. 5.2-5 has an output current that is 5% larger than the input current. Find the small signal common-mode voltage gain assuming that ISS is 100µA and the W/L ratios are 2µm/1µm for M1, M2 and M5 and 1µm/1µm for M3 and M4. Solution Given that I D 4 = (1.05) I D3 or, I D 2 = (1.05) I D1 This mismatch in currents in the differential input pair will result in an input offset voltage. Now, I D1 + I D 2 = I SS So, I D1 ≅ (0.49) I SS and I D 2 ≅ (0.51) I SS To calculate the common-mode voltage gain, let us assume a small signal voltage v s applied to both the gates of the differential input pair. The small-signal output current iout is given by iout = (i D 4 − i D 2 ) where,  0.5 gds5  gm 4 v s iD 4 ≅   gm 3  i D 2 ≅ (0.5 g ds5 )v s So, g  iout = (iD 4 − iD 2 ) = (0.5 gds5 ) m 4 − 1v s  gm 3  The output conductance can be given as g out ≅ g ds 4

as M 2 and M 5 form a cascode structure.

Thus,

v out = or, or, or,

 iout g g ≅ ds5  m 4 − 1v s gout 2 gds4  gm 3   v out g g = ds5  m 4 − 1 vs 2 gds4  gm 3   v out I SS ( λ5 )  I D 4 = − 1  vs I SS ( λ4 )  I D 3  v out = 0.02 V/V vs

Thus, the small-signal common-mode gain is approximately 0.02 V/V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-19

Problem 5.2-10 Use the parameters of Table 3.1-2 to calculate the differential-in-to-single-ended-output voltage gain of Fig. 5.2-9. Assume that ISS is 50 microamperes. Solution Let, the aspect ratio of all the transistors be 1. The small-signal differential-in single-ended out voltage gain is given by g Av = m1 = 2 gm 3 W ' KN L ' 4KP W L

( ) ( )

1 3

= 0.74 V/V

Problem 5.2-11 Perform a small-signal analysis of Fig. 5.2-10 that does not ignore rds1. Compare your results with Eq. (5.2-27). Solution Referring to Fig. 5.2-10 Applying KVL
 v o − v ic − v gs1 v ic − v gs1 = gm1v gs1 2 rds5 +  rds1 

(

)

(

) 2r
 

ds 5

or,

v gs1 { ds1 + 2rds5 ( + g m1rds1 ) + vo (2rds 5 ) = vic (rds1 + 2rds5 ) r 1 }

(1)

Also, applying KCL
−v o

 v o − v ic − v gs1  = gm1v gs1 +   rds1 1   + rds3   gm 3 

(

)

or,

v gs1 =

v { ic − vo (1 + g m3 rds1 )} (1 + g m1rds1 )

(2)

Putting Eq. (2) in Eq. (1), and assuming g m1rds1 >> 1 v { ic − vo (1 + g m3 rds1 )} (2rds5 (1 + g m1rds1 ))+ vo (2rds5 ) = vic (rds1 + 2rds5 ) (1 + g m1rds1 )

or, or,

− vo (g m3 rds1 )2rds5 = vic rds1 vo 1 =− vic (g m3 2rds5 )

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-20

Problem 5.2-12 Find the expressions for the maximum and minimum input voltages, vG1(max) and vG1(min) for the n-channel differential amplifier with enhancement loads shown in Fig. 5.2-9. Solution
VG1 (min) = VT 1 + Vdsat1 + Vdsat 5

or,

VG1 (min) = VT 1 +

I SS ’ KN ( W

L )1

+

2 I SS ’ K N ( L )5 W

VG1 (max) = VDD + VT 1 − VT 3 + Vdsat 3

or,

VG1 (max) = VDD + VT 1 − VT 3 +

’ K P ( L )3 W

I SS

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-21

Problem 5.2-13 If all the devices in the differential amplifier of Fig. 5.2-9 are saturated, find the worstcase input offset voltage, V O S , if |VTi| = 1 ± 0.01 volts and β i = 10-5 ± 5 × 10-7 amperes/volt2. Assume that

β1 = β2 = 10β3 = 10β4 and ∆ β1 = ∆ β2 = ∆ β3 = ∆ β4

β1
Solution Referring to the figure

β2

β3

β4

Carefully state any assumptions that you make in working this problem.

or,

VGS1 = VT 1 + Vdsat1 2 I D1 VGS1 = VT 1 + β1

VGS 2 = VT 2 + Vdsat 2 2I D 2 or, VGS 2 = VT 2 + β2 The input-offset voltage can de defined as
VOS = VGS1 − VGS 2

2 I D1 2 I D1 − β1 β2 Considering the transistors M 3 and M 4 , mismatches in these two transistors would cause an offset voltage between the output nodes. But, if it is assumed that this offset voltage between the output nodes is small as compared to the drain-to-source voltages of the transistors M 1 and M 2 , then V DS1 ≅ V DS 2 Thus, it is assumed here that I D1 = I D 2 = I So, the input-offset voltage becomes 2I 2I VOS = VT 1 − VT 2 + − β1 β2

or,

VOS = VT 1 − VT 2 +

Assuming I = 50 µA , the worst-case input offset voltage can be given by  2(50 µ ) 2(50 µ )  VOS = (1.01 − 0.99) +  − 1.05(10 µ )   0.95(10 µ )  or, VOS(max) = 0.18 V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-22

Problem 5.2-14 Repeat Example 5.2-1 for a p-channel input, differential amplifier. Solution The best way to do this problem is to use the equations for the n-channel, source-coupled pair with opposite type transistor parameters and then subtract the result from 5V. Eq. (5.2-15) gives  VIC(max) = 4 −    2·50µA + 0.85 + 0.55 = 4 – 1.855 + 0.55 = 2.695 volts 99µA/V 2·1 

Subtracting from 5V gives VIC(min) =5 − 2.695 = 2.305 V and Eq. (5.2-17) gives  VIC(min) = 0 + 0.2 +   Subtracting from 5 V gives, VIC(max) = 5 − 1.717 = 3.282 V Therefore, the worst-case input common-mode range is 0.978V with a nominal 5V power supply.  2·50µA +0.85 = 0.2 + 1.517 = 1.717 volts 45µA/V 2·5 

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-23

Problem 5.2-15 Five different CMOS differential amplifier circuits are shown in Fig. P5.12-15. Use the intuitive approach of finding the small signal current caused by the application of a small signal input, vin, and write by inspection the approximate small signal output resistance, Rout, seen looking back into each amplifier and the approximate small signal, differential voltage gain, vout/vin. Your answers should be in terms of gmi and gdsi, i = 1 through 8. (If you have to work out the details by small signal model analysis, this problem will take too much time.)
VDD

M7 M8

M7 M8 VBP vOUT vOUT

M7 M8

M7 M8

M7 M8

vOUT

M5 M6 vOUT M3

M5 M6 vOUT M4

M1 vIN M2 vIN

M1 M2 vIN

M1 M2

M1 M2

M1

VBN M2

ISS Circuit 1

ISS Circuit 2

ISS Circuit 3 Figure P5.2-15

ISS Circuit 4

ISS Circuit 5

Solution Assume gm1 = gm2 otherwise multiply the gain of circuits 1 and 2 by g Circuit 1 2 3 4 Rout 1 gds2+gm8+gds8 1 gds2+gds8 1 gds2+gds8 gm6 1 = g g +g g gds6gds8 ds6 ds8 m6 ds2 gds2˚+ g m6 gm4gm6 gds2gm6gds4˚+gm6gds4gds8 gm2 . m1+gm2

vout/vin gm1gm2 0.5gm2 = g +g +g (gm1+gm2)(gds8+gm8+gds8) ds2 m8 ds8 gm1gm2 0.5gm2 = g +g (gm1+gm2)(gds2+gds8) ds2 ds8 gm1+gm2 2(gds2+gds8) (gm1+gm2)˚gm6 2(gm6gds2+gds6gds8) (gm1+gm2)gm4gm6 2(gds2gm6gds4˚+gm6gds4gds8)

5

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-24

Problem 5.2-16 If the equivalent input-noise voltage of each transistor of the differential amplifier of Fig. 5.2-5 is 1nV/ Hz find the equivalent input noise voltage for this amplifier if W 1/L1 = W2/L2 = 2 µm/1 µ m, W3/L3 = W 4/L4 = 1 µ m/1 µm and I SS = 50 µ A. What is the equivalent output noise current under these conditions? Solution From Equation. (5.2-39) 2  gm 3  2 2 2 2 2  (en 3 + en 4 ) eeq = en1 + en 2 +   gm1    g 2  2 2 2 or, eeq = 2en 1 +  m 3   = 2.455en   gm1   Given en = 1 nV / Hz Thus, eeq. = 1.567 nV/ Hz The equivalent output noise current is given by
2 2 2 ito = g m1eeq

or,

ito = 164 fA/ Hz

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-25

Problem 5.2-17 Use the small-signal model of the differential amplifier using a current mirror load given in Fig. 5.2-8(a) and solve for the ac voltage at the sources of M1 and M2 when a differential input signal, vid, is applied. What is the reason that this voltage is not zero? Solution Neglecting the current source i3 in the figure, let us assume that v v g1 = −v g 2 = id 2 Applying nodal analysis, we will get the following three equations

(g m1 + g ds1 )v s1 = g m1v g1 + (g m3 + g ds1 )v D3 (g m2 + g ds 2 )vs1 = g m2 v g 2 + (g ds 2 + g ds 4 )vout (g m1 + g m2 + g ds1 + g ds2 − g ds5 )v s1 = g m1v g1 + g m2 v g 2 + g ds1v D3 + g ds2 vout v Now, assuming g m >> g ds , g m1 = g m 2 , g ds1 = g ds 2 , and v g1 = −v g 2 = id 2 g ds1v D3 + g ds 2 vout v s1 = (g m1 + g m2 + g ds1 + g ds 2 − g ds5 ) g v + g ds 2 v out v s1 = ds1 D 3 or, (2 g m1 + 2 g ds1 − g ds5 )

(1) (2) (3)

Substituting from Equations (1) and (2), we get
 g  gm10.25 − ds1  gm 3   v v s1 =   id  gm1  −g  0.75 gm1 + gds12 − gm 3  ds5   

The value of v s1 is non-zero because the loads (M3 and M4) seen by the input transistors (M1 and M2) at their drains are different.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-26

Problem 5.2-18 The circuit shown Fig. P5.2-18 +1.5V called a folded-current mirror differential amplifier and is useful for low values of power M9 M8 M6 M7 supply. Assume that all W/L vout values of each transistor is 100. v1 v2 a.) Find the maximum input M1 M2 common mode voltage, v IC (max) and the minimum M4 M3 M5 M10 input common mode voltage, 100µA v IC(min). Keep all transistors in saturation for this problem. b.) What is the input common Fig. P5.2-18 mode voltage range, ICMR? c.) Find the small signal voltage gain, vo/vin, if vin = v1 - v2. d.) If a 10 pF capacitor is connected to the output to ground, what is the -3dB frequency for Vo(jω)/Vin(jω) in Hertz? (Neglect any device capacitance.) Solution a.) v1(max) = VDD - VDS6(sat) + VTN = 1.5 ∴ v1(max) = 2V  2·100  110·100 +   2·50  110·100 + 0.7 200 50·100 + 0.7 = 1.5 – 0.2 + 0.7

v1(min) = 0 + VDS5(sat) + VGS1(50µA) = = 0.1348 + 0953 + 0.7 = 0.9302V ⇒ b.) ICMR = v1(max) - v1(min) = 1.0698V

v1(min) = 0.9302V

c.) Using intuitive analysis approach gives: vin vin vin id1 = gm1 2  ⇒ id3 = -gm1 2  ⇒ id4 =-gm1 2        Also, vin id2 = -gm2 2  . ∴ vout = -Rout(id2 + id4)   vout gm1 1 However, Rout = rds2||rds4||rds7 = gds2+gds4+gds7 ⇒ vin = gds2+gds4+gds7 gm1 = 2·50·110·100 = 1049µS, g ds2 = gds4 = 0.04·50 = 2µS and gds7 = 0.05·100 = 5µS ∴ vout 1049 vin = 7 = 149.8V/V

1 7x10-6 d.) ω-3dB = Rout10pF = 10x10-12 = 0.7x106 → ∴ f-3dB = 111.4kHz

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.2-19 Find an expression for the equivalent input noise voltage of Fig. P5.2-18, veq2 , in terms of the small signal model parameters and the individual equivalent input noise voltages, vni2 , of each of the transistors (i = 1 through 7). Assume M1 and M2, M3 and M4, and M6 and M7 are matched. Solution Equivalent noise circuit: en62

Page 5-27

+1.5V

M9

M8 v1

M6 M1

M7 M2 M5 v2 M3 M4

vout

100µA

M10

Fig. P5.2-18

VDD

*
M6
v1 en12

* en72 M7 v1 vout

*

M1

M2

* en22 M3 en32 en42

*

*

M4
S99FES6

VSS
2 2 2 2 2 2

e out = (gm12 e n1+ gm22 e n2+ gm32 e n3+ gm42 e n4+ gm52 e n6+ gm62 e n7)Rout2 e
2 eq

2

=

2 2 gm12 2 2 gm12 2 2 = e n1+ e n2+ g  ( e n3+ e n4)+g  ( e n6+ e n7) 2 (gm1Rout)  m3  m6

e out

2

If M1 through M2 are matched then gm1 = gm3 and we get gm12 2 2 2 e eq = 4 e n1 + 2g  e n6  m6

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.2-20 Find the small signal transfer function V3(s)/Vin(s) of Fig. P5.220, where Vin = V1-V2, for the capacitors shown in algebraic form (in terms of the small signal model parameters and capacitance). Evaluate the lowfrequency gain and all zeros and poles if I = 200µA and C1 = C2 = C3 = C4 = 1pF. Let all W/L = 10. Solution Small-signal model:L ΣiA = 0: (Gout = gds1 + gds5) 0.5gm1vin + sC1v3 + Goutv3 + gm5v6 = 0 ΣiB = 0: sC2v6 + gm6v6 = 0.5gm3vin = 0  0.5gm3  → v6 =  sC + g  v6 m6  2 Fig. P5.2-20

Page 5-28

VDD M5 v3 C1 v1 M1 M2 M3 I VBias M9 M4 C2 M6 M7 C3 C4 v2 M8 v4

A gm1vin 2 rds1 rds5 C1 v3 C2 gm5v6
1 gm6

B v6 rds3 rds6 gm3vin 2

From the first equation we get,  0.5gm3  v3(sC1 + Gout) + gm5 sC + g  vin + 0.5gm1vin = 0 m6  2 Solving for v3 gives, v3  -0.5gm1 sC2 + gm5 + gm6 vin = sC1 + Gout sC2 + gm6     gmN = rdsN = 2·50µA·110x10 -6·10 = 331.6µS, gmP= When s → 0, v3 -gm1 =g +g vin ds1 ds5

2·50µA·50x10 -6·10 = 223.6µS,

1 1 -6 = 0.5MΩ, and rdsP = 0.05·50x10-6 = 0.4MΩ 0.04·50x10 v3 ∴ vin = - gmN·Rout = -(331.6)(0.5||0.4) = -73.69 V/V Poles are at, -gm6 -223.6µS -1 -1 p1 = R C = = -4.5x106rad/s & p2 = C = 1pF = -223.6 x106 rad/s out 1 22.22kΩ·1pF 2 A zero is at, z1 = -(gm5+ gm6) -(223.6µS + 223.6µS) = = -447.2 x106 rad/s C2 1pF

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.2-21

Page 5-29

For the differential-in, differential-out amplifier of Fig. 5.2-13, assume that all W/L values are equal and that each transistor has approximately the same current flowing through it. If all transistors are in the saturation region, find an algebraic expression for the voltage gain, vout/vin, and the differential output resistance, Rout, where vout = v3-v4 and vin = v1-v2. Rout is the resistance seen between the output terminals. Solution v out (v3 − v 4 ) g m1 = =− (v1 − v2 ) (g ds1 + g ds3 ) vin or,
’ 2K N W vout L1 =− vin I BIAS (λ1 + λ3 )2

( )

Considering differential output voltage swing, the output resistance can be given by 1 1 Rout = + (g ds1 + g ds3 ) (g ds2 + g ds 4 ) or,
Rout = 2 2 = (g ds1 + g ds3 ) I BIAS (λ1 + λ3 )

Problem 5.2-22 Derive the maximum and minimum input common mode voltage for Fig. 5.2-15 assuming all transistors remain in saturation. What is the minimum power supply voltage, VDD, that will give zero common input voltage range? Solution The minimum input common-mode voltage is given by
V IC (min) = VT 1 + Vdsat1 + Vdsat 5

The maximum input common-mode voltage is given by
V IC (max) = VDD + VT 1 − Vdsat 3

Assuming all the Vdsat voltages to be the same, the minimum supply voltage for zero input common mode can be given by
V IC (max) − VIC (min) = 0

or, or,

(VDD + VT1 − Vdsat 3 )− (VT1 + Vdsat1 + Vdsat 5 ) = 0
VDD ≈ 3Vds(sat)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-30

Problem 5.2-23 Find the slew rate, SR, of the differential amplifier shown where the output is differential (ignore common-mode stability problems). Repeat this analysis if the two current sources, 0.5ISS, are replaced by resistors of RL. Solution a.) Slew rate of the differential output amplifier with constant current source loads. Under large signal swing conditions, the maximum current that can be carried by each of the two transistors M 1 and M 2 is I SS . Due to the presence of constant current sources as loads, the maximum charging or discharging current through C L would be 0.5I SS . Thus, the slew rate can be given by ISS SR = 2C
L

VDD 0.5ISS CL + vOUT M2 M1 0.5ISS

ISS VSS Fig. P5.2-23

b.) Slew rate of the differential output amplifier with resistive loads. In presence of resistive loads, the maximum charging or discharging current through C L would be I SS . Thus, the slew rate can be given by ISS SR = C
L

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-31

Problem 5.2-24 If all the devices in the differential amplifier shown in Fig. 5.2-5 are saturated, find the worst-case input-offset voltage VOS using the parameters of Table 3.1-2. Assume that 10(W4/L4 = 10(W 3/L3) = W2/L2 = W1/L1 = 10 µ m/10 µ m. State and justify any assumptions used in working this problem. Solution The offset voltage between the input terminals is given by
Vos = VGS1 − VGS 2

The drain current equations are β I D1 = 1 ( GS1 − VT 1 )2 V 2 β I D 2 = 2 ( GS 2 − VT 2 )2 V 2 or,
Vos = VGS1 − VGS 2 = ( T 2 − VT 1 )+ V 2 I D1 2I D 2 − β1 β2

Mismatches would cause ID1 ≠ ID2. But, to simplify the problem, it can be assumed that I D1 = I D 2 = 0.5I SS . Under this assumption and considering the mismatches in VT and β only, the worst-case input-offset voltage (from Table 3.1-2) can be given by
Vos = 0.3 + I SS I SS − 0.9 β 1.1β

Assuming I SS = 100 µA
Vos = 0.3 + 100 µ 100µ = 0.48 V − 0.9( µ )( / 10 ) 110 10 1.1( µ )( / 10 ) 110 10

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-32

Problem 5.3-01 Calculate the small-signal voltage gain for the cascode amplifier of Fig. 5.3-2 assuming that the dc value of vIN is selected to keep all transistors in saturation. Compare this value with the slope of the voltage transfer function given 2.3V in this figure. Solution The small-signal voltage gain can be approximated as g Av ≅ − m1 g ds 3 or,
Av ≅ −
’ 2K N ( L ) W 1 2 I D 3 λ3

5V M3 W3 2µm = L3 1µm ID M2 + W2 = 2µm L2 1µm vOUT W1 = 2µm L1 1µm Fig. P5.3-2

3.4V
M1 + vIN -

ID is calculated from M3 as, KP'W2 ID = 2L (VSG3-|VTP|)2 = 50·(2.7-0.7)2 µA = 200µA 2 ∴ Av = 2KN'(W1/L1) = IDλN2 2·50·2 200·0.05·0.05 = -20 V/V

From the transfer characteristics, the small-signal gain is approximately -10 V/V.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-33

Problem 5.3-02 Show how to derive Eq. (5.3-6) from Eqs. (5.3-3) through (5.3-5). Hint: Assume that VGG2-VT2 is greater than vDS1 and express Eq. (5.3-4) as iD2 ≈ β2(VGG2-VT2)vDS2. Solve for vOUT as vDS1 + vDS2 and simplify accordingly. Solution From Eqs. (5.3-3) through (5.3-5)
I D1 ≅ β1 ( DD − VT 1 ) ds1 V V I D 2 ≅ β 2 ( GG 2 − Vds1 − VT 2 )( out − Vds1 ) V V I D3 = 0.5β 3 ( DD − VGG 3 − VT 3 ) V Assuming, when Vin is taken to V DD , the magnitudes of Vds1 and Vout are small. Equating I D1 = I D 3
2

β1 ( DD − VT 1 ) ds1 = 0.5β 3 ( DD − VGG 3 − VT 3 ) V V V or, Vds1 = V 0.5β 3 ( DD − VGG 3 − VT 3 )
2

2

β1 ( DD − VT 1 ) V

(1)

Equating I D1 = I D 2

β1 ( DD − VT 1 ) ds1 = β 2 ( GG 2 − Vds1 − VT 2 )( out − Vds1 ) V V V V or, or,

(VDD − VT1 )Vds1 = (VGG 2 − VT 2 )(Vout − Vds1 ) Vout ( GG 2 − VT 2 ) V Vds1 = (VDD + VGG 2 − VT1 − VT 2 )
 2 β3 1 1 VDD − VGG 3 − VT 3  +  2 β1 VDD − VT 1 VGG 2 − VT 2  

(2)

From Eqs. (1) and (2), the minimum output voltage is given by

Vout (min) =

(

) (

) (

)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-34

Problem 5.2-03 Redrive Eq. (5.3-6) accounting for the channel modulation where pertinent. Solution From Eqs. (5.3-3) through (5.3-5)
I D1 ≅ β1 ( DD − VT 1 ) ds1 V V I D 2 ≅ β 2 ( GG 2 − Vds1 − VT 2 )( out − Vds1 ) V V I D3 = 0.5β 3 ( DD − VGG 3 − VT 3 ) ( + λ3 ( DD − Vout )) V 1 V
2

Assuming, when Vin is taken to V DD , the magnitudes of Vds1 and Vout are small. Equating I D1 = I D 3

β1 ( DD − VT 1 ) ds1 = 0.5β 3 ( DD − VGG 3 − VT 3 ) ( + λ3 ( DD − Vout )) V V V 1 V
2

or,

V V 0.5β 3 ( DD − VGG 3 − VT 3 ) ( + λ3 ( DD − Vout )) 1 Vds1 = β1 ( DD − VT 1 ) V
2

(1)

Equating I D1 = I D 2

β1 ( DD − VT 1 ) ds1 = β 2 ( GG 2 − Vds1 − VT 2 )( out − Vds1 ) V V V V or, or,

(VDD − VT1 )Vds1 = (VGG 2 − VT 2 )(Vout − Vds1 ) Vout ( GG 2 − VT 2 ) V Vds1 = (VDD + VGG 2 − VT1 − VT 2 )

(2)

From Eqs. (1) and (2), assuming V DD − Vout ≅ V DD , the minimum output voltage is given by

Vout (min) =

 2 β3 1 1 VDD − VGG 3 − VT 3  +  1 + λ3VDD 2 β1 VDD − VT 1 VGG 2 − VT 2  

(

) (

) (

)(

)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-35

Problem 5.3-04 VDD Show that the small signal input resistance looking in the source of M2 of the cascode amplifier of Fig. 5.3-1 is equal to rds if the simple current source, M3 is replaced by a cascode current source. VGG4 M4 Solution The effective resistance of the cascoded PMOS transistors is VGG3 represented by RD3 and it is given by
RD3 ≅ g m3 rds 3 rds 4

M3 RD3 Vout

Referring to the small-signal model in the figure

 v x − v1 v1 = gm 2v x + rds 2  or, v1 =

(

) R

 D3 

VGG2

M2 RS2

(1 + g m2 rds2 )RD3 v (R D3 + rds 2 ) x
(1)

Vin

M1

Now ix = g m2 v x +

(v x − v1 ) rds 2

+

vx rds1

VSS

i x = ( g m2 + g ds 2 + g ds1 )v x − g ds 2 v1 i x ≅ g m 2 v x − g ds 2 v1

Replacing v1 from Eq. (1) and assuming RD3 >> rds 2 ix ≅ v x

[g m2 (RD3 + rds 2 )− g m2 R D3 ]
RD 3

or, or,

v R D3 RS 2 = x ≅ ix g m 2 rds 2 g r r RS 2 = m3 ds 3 ds 4 = rds g m 2 rds 2

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-36

Problem 5.3-05 Show how by adding a dc current source from VDD VDD to the drain of M1 in Fig. 5.3-1 that the smallsignal voltage gain can be increased. Derive an VGG3 expression similar to that of Eq. (11) in terms of M3 ID1 and ID4 where ID4 is the current of the added dc current source. If ID2 = 10 µA, what value for this current source would increase the voltage gain by a factor of 10. How is the output resistance affected? Solution Assuming all the transistors are in saturation
I D1 = I D 2 + I D 4 g Av ≅ − m1 g ds 3
’ W 2K N 

Vout VGG2

ID4

M2

Vin

M1 Fig. S5.3-05 VSS

or,

Av ≅ −

  (I D 2 + I D 4 )  L 1 2 I D 2λ2 3

or,

I Av ≅ Avo 1 + D 4 I D2
’ W 2K N  L

where, Avo = −

  1

I D 2 λ2 3 I D4 I D2

is the gain in absence of the current source I D 4

Thus,

Av = 1+ Avo

The small-signal voltage gain can be increased by making I D 4 >> I D 2 . In order to achieve Av I = 10 → 10 = 1 + D 4 Avo I D2 or,
I D 4 = 99 I D 2 = 990 µA Rout ≅ [g m2 rds 2 rds1 || rds3 ]

The output resistance can be given by

The value of rds1 decreases due to increased current through M 1 , thus decreasing the overall output resistance.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.3-06 Assume that the dc current in each transistor in Fig. P5.3-6 is 100µA. If all transistor have a W/L of 10µm/1µm, find the small signal voltage gain, VP1 vout/vin and the small signal output resistance, Rout, if all transistors are in the saturated region. Solution This circuit is a folded cascode amplifier. The small signal analysis is best done by the schematic analysis approach. In words, v i n vin creates a current flowing into the drain of M1 of gm1vin. This current flows through M4 from drain to source back around to M1. The output voltage is simply this current times Rout . The details are: vout = -gm1Routvin Rout ≈ [rds6(gm5rds5)]||[(rds1||rds2||rds3)(gm4rds4)] The various small signal parameters are: gmN = 2·110·100·10 = 469µS, gmP = 2·50·100·10 = 316.2µS 25V 20V rdsN = 100µA = 0.25MΩ and rdsP = 100µA = 0.2MΩ ∴ Rout ≈ 29.31MΩ||(0.0667MΩ)(63.2) = 29.31MΩ||4.216MΩ = 3.686MΩ Rout = 3.686MΩ vout vin = -(469µS)(3.686MΩ) = -1,729 V/V
+5V

Page 5-37

M3 M2
VP2 VN2

M4 Rout vout M5 M6

M1 VN1

Fig. P5.3-6

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.3-07

Page 5-38

Six versions of a cascode amplifier are shown below. Assume that K'N = 2K'P, λP = 2λN, all W/L ratios of all devices are equal, and that all bias currents in each device are equal. Identify which circuit or circuits have the following characteristics: (a.) highest small signal voltage gain, (b.) lowest small signal voltage gain, (c.) the highest output resistance, (d.) the lowest output resistance, (e.) the lowest power dissipation, (f.) the highest Vout(max), (g.) the lowest Vout (max), (h.) the highest Vout (min), (i.) the lowest Vout (min), and (j.) the highest -3dB frequency.
VDD VBP1

vIN

vIN

vIN

VBP2 vOUT VBN2 vIN VBN1 Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6 vIN vIN vOUT vOUT vOUT vOUT vOUT

Figure P5.3-7

Solution gm Rout Circuit 1 gmN ≈ rdsP Circuit 2 gmP ≈ rdsN Circuit 3 gmN R* Circuit 4 gmP R* Circuit 5 2 gmN ≈ rdsP Circuit 6 2 gmP ≈ rdsN

R* = (gmP·rdsP2)||(gmN·rdsN2) e.) f.) g.) h.) i.) j.)

Note that gmN = 2 gmP and rdsN = 2rdsP

Circuit 3 has the highest gain. Circuit 1 has the lowest gain. Circuits 3 and 4 have the highest output resistance. Circuits 1 and 5 have the lowest output resistance. Circuits 1-4 have the lowest power dissipation. Circuits 1 and 5 have the highest Vout(max).

k.) Circuit 4 has the worst (lowest) Vout(max). l.) Circuits 2 and 6 have the best (lowest) Vout(min). m.) Circuit 3 has the worst (highest) Vout(min). n.) Circuits 1 and 5 have the highest –3dB frequency because of lowest Rout.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-39

Problem 5.3-08 All W/L ratios of each transistor in the amplifier shown in Fig. P5.3-8 are 10µm/1µm. Find the numerical value of the small signal voltage gain, vout/vin, and the output resistance, Rout. Solution The output resistance can be given as
Rout ≅ [g m 2 rds 2 rds1 || g m3 rds3 rds 4 ]

VDD M8 M4

M7 100µA M6

M3 Rout vout M2 vin

Neglecting body effects g m1 = g m 2 = 469 µS g m3 = g m 4 = 316 µS g ds1 = g ds 2 = 4 µS g ds3 = g ds 4 = 5 µS

M5

M1

Figure P5.3-8

Thus, Rout ≅ [29.31M || 12.64 M ] or, Rout ≈ 8.838 MΩ

The small-signal voltage gain is given as v out = −gm1Rout = -41.42 V/V v in

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-40

Problem 5.3-09 Use the Miller simplification described in Appendix A on the capacitor C2 of Fig. 5.35(b) and derive an expression for the pole, p1, assuming that the reactance of C2 at the frequency of interest is greater than R3. Compare your result with Eq. (5.3-32).
Vout

R1 Vin/Rs

C1 (1-Av)C2

V1

gm1V1

C3

C2

Av (Av-1)

R3

sC2 or, R3 Referring to the figure Vin ( s) V1 ( s) = 1  RS + s C1 + (1 + Av )C2  R1    where, Av = gm1R3

(

)

(1)

−gm1V1 ( s) −gm1V1 ( s) ≅ 1  sC3  + sC3   R3  −gm1 Vin ( s) Vo ( s) = or, 1  1   + sC3  RS + s C1 + (1 + Av )C2  R1   R3    The dominant pole in Eq. (2) can be expressed as −1 −1 p1 = ≅ R1 ( Av C2 + C1 ) R1 ( Av C2 )

Also, Vo ( s) =

(

)

(2)

or,

p1 = g

-1 R 1 R 3 C2 m1

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-41

Problem 5.3-10 Consider the current-source load inverter of Fig. 5.1-5 and the simple cascode amplifier of Fig. 5.3-1. If the W/L ratio for M2 is 1 µm/1 µm and for M1 is 3 µm/1 µm of Fig. 5.15, and W3/L3 = 1 µm/1 µm, W2/L2 = W1/L1 = 3 µm/1 µm for Fig. 5.3-1, compare the minimum output-voltage swing, vOUT(min) of both amplifiers if VGG2 = 0 V and VGG3 = 2.5 V when VDD = −VSS = 5 V. Solution a) Current source load inverter When Vin = V DD , it can be assumed that M 1 operates in the triode region and M 2 is in saturation. Thus,

β1 ( DD − VSS − VT 1 )( out (min) − VSS ) = 0.5β 2 ( SG 2 − VT 2 ) V V V or, V 0.5 β 2 ( SG 2 − VT 2 ) Vout (min) = + VSS V β1 ( DD − VSS − VT 1 )
2

2

Assuming, VSG 2 = 5 V Vout(min) = -4.85 V b) Simple cascode amplifier
Vout (min) = VSS + Vdsat1 + Vdsat 2 2 I D1 ’ K N ( L )1 W 2 I D2 ’ K N ( L )2 W

or, Now,

Vout (min) = VSS +

+

I D3 =

β3 ( DD − VGG3 − VT 3 )2 = 81 µA V 2

Thus, Vout(min) = -3.6 V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-42

Problem 5.3-11 Use nodal analysis techniques on the cascode amplifier of Fig. 5.3-6(b) to find vout/vin. Verify the result with Eq. (5.3-37) of Sec. 5.3. Solution Nodal analysis of cascode amplifier Applying KCL g m1vin + g ds1v1 + g m 2 v1 + g mbs 2 v1 = g ds 2 (vout − v1 ) or, or, g m1vin + ( g ds1 + g m 2 + g mbs 2 + g ds 2 )v1 = g ds 2 vout v1 =

(g ds 2 vout − g m1vin )
( g ds1 + g m 2 + g mbs 2 + g ds 2 )

(1)

Again, applying KCL g ds 4 v 4 + g ds3 (v 4 − vout )+ g m3v 4 + g mbs 3v 4 = 0

or, Also,

v4 =

g ds3 v (g m3 + g ds3 + g ds4 + g mbs3 ) out

(2)

(g m3 + g mbs3 )v4 + g ds3 (v4 − vout )+ (g m2 + g mbs2 )v1 + g ds 2 (v1 − vout ) = 0 (g m3 + g mbs3 + g ds3 )v4 + (g m2 + g mbs2 + g ds 2 )v1 = (g ds3 + g ds4 )vout
(3)

or,

Using Eqs. (1) through (3) and neglecting body effect, it can be shown that
Av = − g m1 g m 2 g m3 (g m3 g ds1 g ds 2 + g m2 g ds3 g ds 4 ) − g m1  g ds1 g ds 2 g ds 3 g ds 4  +  g g m3 m2     

or,

Av =

or,

Av =

’ W − 2 K1 ( L )1

 λ3 λ 4 λ1λ 2  ID + ’ ’  2K 2 ( L) W 2 2 K 3 ( L )3 W 

    

Eq. (5.3-37)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-43

Problem 5.3-12 Find the numerical value of the small signal VDD voltage gain, vout/vin, for the circuit of Fig. M3 M6 M5 M4 P5.3-12. Assume that all devices are saturated 4/1 and use the parameters of Table 3.1-2. Assume 4/1 4/1 40/1 vout that the dc voltage drop across M7 keeps M1 in M2 saturation. 4/1 Solution M7 I D 3 = I D 2 = 20 µA 1/1 vin M1 I D 3 = 220 µA 20µA 4/1 Now, gm1 = 440 µS and rds1 = 113.64 kΩ gm 2 = 132.67 µS and rds2 = 1.25 kΩ rds3 = 1 MΩ

Fig. P5.3-12

Thus,

Rout = [rds3 || gm 2 rds2 rds1 ] or, So,
Av = −gm1Rout = -418 V/V

Rout = [1M || 18.8 M ] = 950 kΩ

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-44

Problem 5.3-13 A cascoded differential amplifier is shown in VDD Fig. P5.3-13. M7 (a) Assume all transistors are in saturation M8 M12 and find an algebraic expression for the small I7 I8 signal voltage gain, vout/vin. M5 M6 (b) Sketch how would you implement VBias? M11 vout (Use a minimum number of transistors.) M4 (c.) Suppose that I7+I8≠ I9. What would be M3 + the effect on this circuit and how would you I + M1 VBias vin solve it? Show a schematic of your solution. M2 You should have roughly the same gain and M9 the same output resistance. I9 Solution M10 a ) The effective transconductance is VSS given by g Fig. P5.3-13 gm ,eff = m1 2 The output resistance of the cascoded output is given by     1 Rout =  gds2 gds4 gds6 gds8  +  gm 4 gm 6    Thus, the small-signal voltage gain is given by

    0.5 gm1 Av =  gds2 gds4 gds6 gds8  +  gm 4 gm 6   
b) The magnitude of VBIAS should be at least VGS + Vdsat . One way to implement VBIAS is shown in Fig. 6.5-1(b) of the text. c) If the currents were not equal, the voltages at the drains of M3-M5 and M4-M6 will near VDD or near the sources of M1 and M2. Either, M5-M8 or M1-M4 will not be saturated. The best way to solve this problem is through the use of common mode feedback. This is illustrated in Fig. 5.2-15 of the text.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.3-14

Page 5-45

Design a cascode CMOS amplifier using Fig. 5.3-7 for the following specifications. VDD = 5V, Pdiss ≤ 0.5mW, |Av| ≥ 100V/V, vOUT(max) = 3.5V, vOUT(min) = 1.5V, and slew rate of greater than 5V/µs for a 5pF capacitor load. Verify your design by simulation. Solution 1.) The slew rate should be at least 5 V/µs driving a 5 pF load. So, the load current should be at least 25 µA. Let, I D 3 = I D 2 = I D1 = 25 µA 2.) The maximum output voltage swing should be at least 3.5 V Let, Vdsat 3 = 1.5 V
2I W  = ' D23 = 0.44  L  3 K PVdsat 3 So, let us choose W  W  = =1  L 3  L 4

3.) The small-signal voltage gain should be at least 100  W  ( Av λ3 ) I D1 = = 2.84 or, '  L 1 2K N So, let us choose W  =3  L 1 Vdsat1 = 0.39 V 4.) The minimum output voltage swing should be greater than 1.5 V
2

Av ≅ −gm1rds3

Vout (min) = Vdsat1 + Vdsat 2

or, or,

Vdsat 2 = Vout (min) − Vdsat1 = 1.11 V

2I W  = ' D22 = 0.37  L  2 K NVdsat 2 So, let us choose W  =1  L 2 5.) The bias voltage VGG 2 can be calculated as
VGG 2 = VT 1 + Vdsat1 + Vdsat 2 = 1.76 V

6.) The power dissipation is given by
Pdiss = I D 3VDD = 0.125 mW

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.4-01 Assume that io = Ai(ip-in) of the current amplifier shown in Fig. P5.4-1. Find vout/vin and compare with Eq. (5.4-3). Solution Referring to the figure, i p = 0 . So,

Page 5-46

i2 i1 R 1 vs in ip

R2 io Ai vo

io = Ai i p − in = − Aiin v o = −i2 R2

(

)

Now, v in = i1R1

Current Amplifier Figure P5.4-1

or,

v o = (i1 − in ) R2

→

v i  v o =  in + o R2  R1 Ai 
→
R2 vo R1 = v in 1 + 1  Ai  

or,

  −v o   R2   v in  R vo =  + Ai  2  R1  

Eq. (5.4-3)

Problem 5.4-02 The simple current mirror of Fig. 5.4-3 is to be used as a current amplifier. If the W/L of M1 is 1µm/1µm, design the W/L ratio of M2 to give a gain of 10. If the value of I 1 is 100µA, find the input and output resistance assuming the current sources I1 and I2 are ideal. What is the actual value of the current gain when the input current is 50µA? Solution The current gain can be expressed as (W L)2 Ai = (W L)1 For Ai = 10 , W 2 = 10 µm and L2 = 1 µm. If I1 = 100 µA, then I 2 = 1000 µA. The input resistance is 1 Rin = = 6.74 kΩ gm1 The output resistance is 1 Rout = = 25 kΩ λN I D 2 When I1 = 50 µA, then I 2 = 500 µA and the current gain ( Ai ) is still 10.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.4-03 The capacitances of M1 and M2 in Fig. P.4-3 are Cgs1=Cgs2=20fF, Cgd1=Cgd2 =5fF, and Cbd1=Cbd2=10fF. Find the low frequency current gain, iout/iin, the input resistance seen by iin, the output resistance looking into the drain of M2, and the -3dB frequency in Hz. Solution

Page 5-47

VDD 100µA 100µA

VDD

iout
5µm 1µm RL=0

M1 iin
5µm/1µm

M2

Fig. P5.4-3

+ iin gm1

gds1

V1 C1 -

iout

gm1V1
S99E2S3

(a.) Small-signal model is shown. Note that C1=Cbd1 + Cgs2 + Cgd2 + Cgs1 = 55fF, gm1=gm2 = and gds1 = λNI1 = 0.04·100µA = 4µS The current gain is, iin˚   iout = gm2g +g +sC  1  m1 ds1 W1 2KN· L I1 = 2·110·5·100 = 332µS
1

The low frequency current gain is gm2 332 Ai(0) = g +g = 336 = 0.988⇒ m1 ds1 Rin = g 1 1 +gds1 = 336µS = 2.796kΩ m1 ⇒

Ai(0) = 0.988 ⇒ Rin = 2796Ω

Rout = 1/gds2 = 1/gds1 = 250kΩ

Rout = 250kΩ ⇒ f-3dB = 973MHz

ω-3dB =

gm1+gds1 332µS+4µS = = 6.11x109 C1 55fF

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-48

Problem 5.4-04 Derive an expression for the small-signal input resistance of the current amplifier of Fig. 5.4-5(a). Assume that the current sink, I3, has a small signal resistance of rds4 in your derivation. Solution Referring to the figure v s3 = v x v g1 = v d 3 ≅ g m3 v (g ds3 + g ds 4 ) x

VDD I1

I2

ix M3 Vx M1 rds4 VGG3 M2

i x = id1 + id 3

or, or,

i x = g m1v g1 + g m3v x g m3 i x = g m1 v +g v (g ds3 + g ds4 ) x m3 x

or,

v (g + g ds 4 ) Rin = x ≅ ds3 ix g m1 g m3

Problem 5.4-05 Show how to make the current accuracy of Fig. 5.4-5(a) better by modifying the circuit so that VDS1 = VDS2. Solution Referring to the figure, M3-M6 form a differential amplifier. If it is assumed that the smallsignal gain of this differential amplifier is large enough, then the bias voltages at the gates of M3 and M4 would almost be equal (because in presence of I1 large gain, the differential input ports would act as null ports). Thus, the drain bias voltages of M1 and M2 would almost be identical causing very good mirroring. M1 It is also important to note that the bias voltage at the drain of M4 could be very large as gate bias voltages for M1 and M2. One can use a PMOS differential amplifier in place of the shown NMOS differential amplifier to overcome this problem.

VDD M5 M3 M6 M4

I2

M2 I3

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-49

Problem 5.4-06 Show how to use the improved high-swing current mirror of Sec. 4.4 to implement Fig. 5.4-7(a). Design the current amplifier so that the input resistance is 1kΩ and the dc bias current flowing into the input is 100µA (when no input current signal is applied) and the dc voltage at the input is 1.0V. Solution The high-swing cascode current mirror, constitut-ing the transistors M1 through M4, is shown in the figure. The overall figure shows a differential current amplifier. To design the highswing cascode current mirror, it is desired that
Rin = 1 kΩ

VDD I i1-i2 2I i2 M3 M4 M7 M8 VBias = M5 M6 VT + 2VON
Fig. S5.4-06

i1 i2

I

iout i1-i2

or, or,

g m1 = 1 µS
W  W  = = 45.5  L 1  L  2 W  W  = = 45.5  L 3  L 4

M1 M2

Let us assume

Then, ignoring bulk effects
VBIAS = VT 3 + Vdsat 3 + Vdsat1 = 1.1 V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-50

Problem 5.4-07 Show how to use the regulated cascode mirror of Sec. 4.4 to implement a single-ended input current amplifier. Calculate an algebraic expression for the small signal input and output resistance of your current amplifier. Solution iout vg3 iin M1 M4 M3 vs3 M2 rds2 + vgs3=(-gm1rds1)vs3 vs3 vx ix

gm3vgs3

rds3

Referring to the figure, the current gain of the regulated cascode mirror can be expressed as (W L)2 i Ai = out ≅ iin (W L) 4 The input resistance is given by 1 Rin = gm 4 The output resistance can be calculated as follows: v g 3 = −( gm1rds1 )v s3 Now, ix = gm 3v gs3 + or, (1)

(v x − v s3 ) rds3 ix = −gm 3 ( gm1rds1 )v s3 +

(v x − v s3 ) rds3 (2) (3)

Also, v s3 = ix rds2

Using Eqs. (2) and (3), it can be shown that

v x = ix ( gm1rds1gm 3 rds3 rds2 ) or, Rout = vx = ( gm1rds1gm 3 rds3 rds2 ) ix

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.4-08 Find the exact expression for the small signal input resistance of the circuit shown when the output is short-circuited. Assume all transistors have identical W/L ratios, are in saturation and ignore the bulk effects. Simplify your expression by assuming that gm=100gds and that all transistors are identical. Sketch a plot of iout as a function of iin. Solution Rin A small signal model for this problem is: gm4 vgs4 M1

Page 5-51

VDD I I I iout

iin M3

M4

M2 Figure P5.4-8

Rin

D2=G3=S4 + + vgs4 rds2 + rds3 rds4 D3=G4

D4

it

vt v gs3 -

gm3 vgs3

S2=S3 it = (gds2+gds4)vt - gm4vgs4
But, vgs4 = -gm3rds3vgs3 - vt and vgs3 = vt ∴ it = (gds2+gds4)vt + gm4(1+gm3rds3)vt Thus, Rin is vt 1 1 Rin = it = gds2+gds4+gm4 + gm3gm4rds3 ≈ gm3gm4rds3 Sketching iout as a function of iin: Note that iD4 = I + iout and iD4 + iin = iD2 = iD1 = I Therefore, I + iout = I - iin ⇒ iout = - iin

i out 1 1 i in

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.4-09 Find the exact small signal expression for Rin for the circuit in Fig. P5.4-9. Assume VDC causes the current flow through M1 and M2 to be identical. Assume M1 and M2 are identical transistors and that the small signal rds of M5 can be ignored (do not neglect rds1 and rds2). Solution The small-signal model is shown below. We may write that, vin = vd1 = (iin – gm1vgs1)rds1 + (iin+ gm2vgs2) rds2 but vgs1 = - vs1 and vgs2 = vg2 – vs2

Page 5-52

VDD Vb2 M1 Vb1 Rin vin M5 M2

VDD

+ + Fig. 5.4-9 M3 M4

VDC

gm1vgs1 iin vin + vd1 ∴

gm2vgs2 rds2 S1=S2 G1=D2 gm2vd1 G2 = D3 = D4 + vg2 -

D1 rds1

rds3 gm4vd1

rds4

Fig. S5.4-9

vin = iin rds1 + gm1vs1rds1 + iin rds2 + gm2vg2rds2 - gm2vs2rds2  gm3+ gm4  = iin rds1 + iin rds2 + gm2vg2rds2 = iin (rds1 + rds2) - gm2rds2 g + g  vin ds4  ds3

∴

vin =

(rds1 + rds2)iin vin (rds1 + rds2) → Rin = i = gm2rds2(gm3+ gm4) gm2rds2(gm3+ gm4) in 1+ 1+ gds3 + gds4 gds3 + gds4 rds1 + rds2 rds2(gm3+ gm4)rds3||rds4 m2

or

Rin = 1 + g

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.4-10 A CMOS current amplifier is shown. Find the small signal values of the current gain, Ai = iout/iin, input resistance, Rin, and output resistance, Rout. For Rout, assume that gds2/gm6 is equal to gds1/gm5. Use the parameters of Table 3.1-3. Solution Since this is a new circuit, use the small signal model approach. The model for this problem is given below. iout = -(gm7v1 + gm8v2) gm7 gm7 gm7i1 gm8i2 - g = - g (i1+i2) = g iin → =- g m5 m6 m5 m5 gm2vin

Page 5-53

+2V 10/1 M5 Rin iin 10/1 10/1 M3 M1 M4 M2 10/1 10/1 M6 10/1 50µA M7 100/1 iout Rout 100/1 M8 50µA -2V iout Ai = i = -10 in
S98FEP6

i2 iin + vin i1 rds1 1 gm5 rds2 gm1vin v1

v2

iout 1 gm6 gm7v1

gm8v2

rds7 rds8
S98FES6

Rout = g

1 1 1 +gds8 = (500µA)(0.04+0.05) = 45µS = 22.2kΩ ds7

Rin: iin = gm1vin + gm2vin + gds1(vin-v1) + gds2(vin-v2) gds1i1 gds2i2 gds1 = (gm1+gm2+gds1+gds2)vin - g - g = (gm1+gm2+gds1+gds2)vin - g iin m5 m6 m5 gds1 1+g vin m5 ∴ Rin = i = g +g +g +g , gm1 = in m1 m2 ds1 ds2 gm2 = Thus,

2KN·10·50 = 331.7µS, gds1= 2µS

2KP·10·50 = 223.6µS, gds1= 2.5µS, and gm5 = gm2 1 + 0.0112 Rin = 331.7+223.6+2+2.5 = 1.8kΩ

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.4-11 Find the exact algebraic expression (ignoring bulk effects) for the following characteristics of the amplifier shown. Express your answers in terms of gm’s and rds’s in the form M6 of the ratio of two polynomials. (a.) The small signal voltage gain, Av = vout/vin., and current gain, Ai = iout/iin. (b.) The small signal input resistance, Rin. ∴ The small signal output resistance, Rout. Solution

Page 5-54

VDD M3 Rout iout 100µA M2 Rin vout

M5

iin vin

(a.) Small-signal model is shown below. Summing currents M4 at the output node gives: gm2vin + gds2(vin-vout) = gds3vout or vout gm2+gds2 rds3+gm2rds2rds3 vin = gds2+gds3 = rds2+rds3

M1

Figure P5.4-11

gm2vgs2 iin + vin rds1 rds2 rds3 iout iin i + + vgs2 = -vin vin vout -

R

gm2vin iout rds2 rds3 + vout S98E2S3

rds1

(b.) The input resistance is best done by finding R and putting it in parallel with rds1. vin = (i-gm2vin)rds2 + irds3 → vin rds2+rds3 R = i = 1+g r m2 ds2 rds1(rds2+rds3) Rin = r +r +r +g r r ds1 ds2 ds3 m2 ds2 ds1

 rds2+rds3  ∴ Rin = rds1||R = rds1||1+g r  → m2 ds2  (c.) rds2rds3 Rout = rds2||rds3 = r +r ds2 ds3

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.4-12 Find the exact expression for the small signal input resistance of the circuit shown. Assume all transistors have identical W/L ratios, are in I saturation and ignore the bulk effects. Simplify your expression by assuming that gm=100gds and that all transistors are identical. Sketch a plot of iin iout as a function of iin. Solutions A small signal model for this problem is: Rin gm4 vgs4 M1 Rin D2=G3=S4 D4 rds4 + + vgs4 D3=G4 rds2 vt v it + gs3

Page 5-55

VDD
I I

iout

M4 M3 M2

Figure P5.4-12

-

rds3 S2=S3

gm3 vgs3

it = (gds2+gds4)vt - gm4vgs4 But, vgs4 = -gm3rds3vgs3 - vt and vgs3 = vt ∴ it = (gds2+gds4)vt + gm4(1+gm3rds3)vt Thus, Rin is vt 1 1 Rin = it = gds2+gds4+gm4 + gm3gm4rds3 ≈ gm3gm4rds3 Sketching iout as a function of iin: Note that iD4 = I + iout and iD4 + iin = iD2 = iD1 = I Therefore, I + iout = I - iin ⇒ iout = - iin

i out 1 1 i in

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-56

Problem 5.5-01 Use the values of Table 3.1-2 and design the W/L ratios of M1 and M2 of Fig. 5.5-1 so that a voltage swing of ±3 volts and a slew rate of 5 volts/µs is achieved if RL = 10 kΩ and CL = 1 nF. Assume that VDD = −VSS = 5 volts and VGG2 = 2 volts. Solution
' KP  W  V − VGG 2 − VT 2 2  L  2 DD

ID 2 =

(

)

2

For positive swing of the output voltage, the slew rate should be at least +5 V/µs.
SR = ID 2 CL
W  ≅ 38/1  L 2

Thus, I out = I D 2 = SR(CL ) = 5 mA Now,
2ID 2 W  = '  L 2 K V − V − V P DD GG 2 T2

(

)

2

→

Also, for the output voltage to swing to +3 V, the load current into RL will be 0.3 mA. Since I D 2 is greater than 0.3 mA, the output voltage would be greater than +3 V. For negative output voltage swing

I out = SR(CL ) = 5 mA
I D1 = −I out + I D 2 = 10 mA

or,

2 I D1 W  = '  L 1 K (V − V − V ) 2 N DD SS T1

→

W  = 2.1 ≅ 3/1  L 1

For Vout (min) = −3 V, I out = −0.3 mA. Since I D1 > −I out + I D 2 , the output will be able to swing down to –3 V.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-57

Problem 5.5-02 Find the W/L of M1 for the source follower of Fig. 5.5-3a when VDD = −VSS = 5 V, VOUT = 1 V, and W2/L2 = 1 that will source 1 mA of output current. Use the parameters of Table 3.1-2. Solution Given, Vout = 1 V and VSS = −5 V So,
VGS 2 = 6 V
' KN  W  = (V − V )2  L  2 GS 2 T 2 2

ID 2

→

I D 2 = 1.55 mA

Thus, I D1 = I D 2 + I out = 2.55 mA Due to body effects, the threshold voltage of M1 can be given by VT 1 = VT 0 + γ 1 Vout − VSS = 1.68 V Now,

2 I D1 W  = 8.6/1 = '  L 1 K (V − V − V ) 2 N DD out T1

Problem 5.5-03 Find the small-signal voltage gain and output resistance of the source follower of Fig. 5.5-3b. Assume that VDD = −VSS = 5 V, VOUT = 1 V, ID = 50 µA, and the W/L ratios of both M1 and M2 are 20 µm/10 µm. Use the parameters of Table 3.1-2 where pertinent. Solution The small-signal voltage gain is given by gm1 Av = (gm1 + gds1 + gds2 ) VT 1 = VT 0 + γ 1 Vout − VSS
' gm1 = 2K N

→ →

VT1 = 1.68 V gm1 = 148 µS

W  I  L 1 D1

gds1 + gds2 = 4.5 µS

∴

Av = 0.943 V/V

The output resistance is given by 1 Rout = = 6.37 kΩ (gm1 + gds1 + gds2 )

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.5-04 An output amplifier is shown. Assume that vIN can vary from -2.5V to +2.5V. Let KP’ = 50µA/V 2, VTP = -0.7V, and λP = 0.05V-1. Ignore bulk effects. a.) Find the maximum value of vOUT, vOUT(max). b.) Find the minimum value of vOUT, vOUT(min). c.) Find the positive slew rate, when vOUT = 0V in volts/microseconds. d.) Find the negative slew rate, SR- when vOUT = 0V in volts/microseconds. SR+ vIN +2.5V

Page 5-58

200µA vOUT 300/1 -2.5V 50pF 10kΩ

e.) Find the small signal output resistance (excluding the 10kΩ resistor) when vOUT = 0V. Solution ∴ When vIN = +2.5V, the transistor is shut off and vOUT(max) = 200µA·10k Ω = +2V ∴ When vIN = -2.5V, the transistor is in saturation (drain = gate) and the minimum output voltage under steady-state is, 50·300  vOUT = -10kΩ(ID-200µA) = -10kΩ  2 (vOUT+2.5-0.7)2 - 200µA    2 +2 2+3.6133v vOUT = -75(vOUT+1.8) → vOUT OUT + 3.21333 = 0 3.61333 (3.61333)2 - 4·3.21333 ± = -1.80667 ± 0.22519 ∴ vOUT = 2 2 It can be shown that the correct choice is vOUT(min) = -1.80667 + 0.22519 = -1.5815V 200µA c.) The positive slew rate is SR+ = 50pF = +4V/µs → SR+ = +4V/µs d.) The negative slew rate is found as follows. With vOUT = 0V, the drain current is ID = 7.5mA/V2(2.5-0.7)2 = 24.3mA Therefore, the sourcing current is 24.3mA-0.2mA = 24.1mA which gives a negative slew 24.1mA SR- = - 482V/µs rate of SR- = 50pF = - 482V/µs → e.) The output resistance, Rout, is approximately equal to 1/gm. Therefore, 1 Rout ≈ g = m L 1 2KPIDW = 2·50·200·300 = 408.2Ω → Rout ≈ 408Ω

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-59

Problem 5.5-05 An output amplifier is shown. Assume that +2.5V vIN can vary from -2.5V to +2.5V. Ignore bulk effects. Use the parameters shown 300µm below. vIN 1µm a.) Find the maximum value of vOUT, vOUT(max). b.) Find the minimum value of vOUT, 50pF 200µA vOUT(min). c.) Find the positive slew rate, SR+ when vOUT = 0V in volts/microseconds. -2.5V d.) Find the negative slew rate, SR- when Figure P5.5-5 vOUT = 0V in volts/microseconds. e.) Find the small signal output resistance when vOUT = 0V. Solution (a.) When vIN = 2.5V, the transistor shuts off and vOUT(max) = 200µA·10kΩ = +2V (b.) Assume vIN = -2.5V. Therefore, the transistor is in saturation and the minimum output voltage under steady-state is, 110x10-6·300   vOUT = -10kΩ(ID-200µA) = -10kΩ  (vOUT+2.5-0.7)2-200µA  2  or vOUT = -165(vOUT+1.8)2 + 2V → ∴ vOUT = vOUT2 + 3.6061 vOUT + 3.228 = 0 3.6061 (3.6061)2 - 4·3.228 ± = -1.8030 ± 0.1516 2 2 It can be shown that the correct choice is vOUT = -1.8030 + 0.1516 = -1.6514V Thus vOUT(min) = -1.6514V 200µA (c.) The positive slew rate is SR+ = 50pF = +4V/µs (d.) The negative slew rate is found as follows. With vOUT = 0V, the drain current is 110x10-6·300 ID = (2.5-0.7)2 = 53.46mA 2 Therefore, the sourcing current is 53.46mA - 0.2mA = 53.44mA which gives a negative slew rate of SR- = 53.44mA 50pF = 1069V/µs

vOUT 10kΩ

(e.) The output resistance, Rout, is approximately equal to 1/gm. Therefore, 1 Rout = g = m L 106 = = 275.24Ω 2KIDW 2·110·300·200

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.5-06 For the circuit shown in Fig. P5.5-6, find the small signal voltage gain, vout/vin and the small signal output resistance, Rout. Assume vin that the dc value of vOUT is 0V and that the dc current through M1 and M2 is 200µA. Solution -3V (Unfortunately the gate-source voltage is given on the schematic which causes a conflict with the problem statement of 200µA of current. We will use the 200µA in the solution.) The small-signal model for this problem is shown below.

Page 5-60

+5V M1 10/1 -5V M2 Rout 10/1 vout

-5V Fig. P5.5-6

+ vgs1 rds1 gm1vgs1 gmb1vbs1 rds2

iout + vout Fig. S5.5-6

gm1 = 2·110·200·10 µS = 663.3µS, gmb1 = gds1 = gds2 = 0.04·200µA = 8µS Summing currents at the output,

663.3µS(0.4) = 55.57µS, 2 0.7 + 5

vout(gds1 + gds2) = gm1vgs1 + gmb1vbs1 = gm1vin - gm1vout - gmb1vout vout gm1 663.3 (e.) v = g + g + gds1 + gds2 = 663.3 + 55.57 + 8 + 8 = 0.9026 V/V in m1 mb1 vout 1 1 Rout = i =g +g + gds1 + gds2 = 663.3 + 55.57 + 8 + 8 = 1361Ω out m1 mb1

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-61

Problem 5.5-07 Develop an expression for the efficiency of the source follower of Fig. 5.5-3b in terms of the maximum symmetrical peak-output voltage swing. Ignore the effects of the bulksource voltage. What is the maximum possible efficiency? Solution Efficiency (η) is expressed as PRL Psup ply  Vout ( peak ) 2    2 RL   = (VDD − VSS )IQ

η max =

The maximum output voltage swing is
Vout (max) ≅ VDD − VT 1

The minimum output voltage swing is
Vout (min) ≅ VSS

Assuming symmetrical maximum positive and negative output swings
Vout ( peak ) ≅ VDD − VT 1

The quiescent current can be expressed as (V (max) − Vout (min)) IQ = out 2 RL (V − VSS − VT 1) IQ = DD or, 2 RL Thus,  Vout ( peak ) 2    2 RL (VDD − VT 1)2   η max = = (VDD − VSS )IQ (VDD − VSS )(VDD − VSS − VT 1) Assuming
VDD = −VSS = 5 V gives ηmax ≈ 20%

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-62

Problem 5.5-08 Find the pole and zero location of the source followers of Fig. 5.5-3a and Fig. 5.5-3b if Cgs1 = Cgd2 = 5fF and Cbs1 = Cbd2 = 30fF and CL = 1 pF. Assume the device parameters of Table 3.1-2, ID = 100 µA, W1/L1 = W2/L2 = 10 µm/10 µm, and VSB = 5 volts. Solution
Cgd1 Cgs1 vout CL RL2=(gm2+gds2+gL)-1 gm1vgs rds1

+ vgs vin -

a.) Referring to the figure The location of the zero of the follower is given by −g z = m1 = -14.9 GHz Cgs1 The location of the pole of the follower is given by p= (C

−( gm1 + gm 2 + gds1 + gds2 + gL ) gs1 + Cgs2 + Cbd 1 + Cbd 2 + CL

)

= -140.8 MHz

b.) Referring to the figure The location of the zero of the follower is given by −g z = m1 = -14.9 GHz Cgs1 The location of the pole of the follower is given by p= −( gm1 + gds1 + gds2 + gL )

(C

gs1 + Cgs 2 + Cbd 1 + Cbd 2 + CL

)

= -71.1 MHz

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.5-09

Page 5-63

Six versions of a source follower are shown below. Assume that K'N = 2K'P, λP = 2λN, all W/L ratios of all devices are equal, and that all bias currents in each device are equal. Neglect bulk effects in this problem and assume no external load resistor. Identify which circuit or circuits have the following characteristics: (a.) highest small-signal voltage gain, (b.) lowest small-signal voltage gain, (c.) the highest output resistance, (d.) the lowest output resistance, (e.) the highest vout(max) and (f.) the lowest vout(max). vin M1 vout
M2 M2

vin M1 vout vout vin
M2

M2

vin M1 VBP vout
M2

M2

VDD vout vout vin M1

vin M1

M1

VBN
Circuit 5

Circuit 1 Solution

Circuit 2

Circuit 3

Circuit 4

VSS Circuit 6
FS02E1P1

Small signal model: vout gm The voltage gain is found as: vin = gm+GL where GL is the load conductance. Therefore we get:

(a.) and (b.) - Voltage gain.

+ vin g v g v - m in m out GL

+ vout -

Circuit 1 2 3 4 5 6 vout gmN gmP gmN gmP gmN gmP vin gmN+gmN gmP+gmP gmN+gmP gmP+gmN gmN+gdsN+gdsP gmP+gdsN+gdsP But gmN = 2 gmP and gdsN = 0.5gdsP, therefore Circuit vout vin 1 1 2 2 1 2 3 0.5858 4 0.4142 5 gmP gmP+(gdsP+gdsN)/ 2 6 gmP gmP+gdsP+gdsN

Thus, circuit 5 has the highest gain and circuit 4 the lowest gain (c.) and (d.) - Output resistance. The denominators of the first table show the following: Ckt.6 has the highest output resistance and Ckt. 1 the lowest output resistance. (e.) Assuming no current has to be provided by the output, circuits 2, 4, and 6 can pull the output to VDD. ∴ Circuits 2, 4 and 6 have the highest output swing. (f.) Assuming no current has to be provided by the output, circuits 1, 3, and 5 can pull the output to ground. ∴ Circuits 1, 3 and 5 have lowest output swing. Summary (a.) Ckt. 5 has the highest voltage gain (b.) Ckt. 4 has the lowest voltage gain (c.) Ckt. 6 has the highest output resistance (d.) Ckt. 1 has the lowest output resistance (e.) Ckts. 2,4 and 6 have the highest output (f.) Ckts. 1,3 and 5 have the lowest output

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.5-10 Show that a class B, push-pull amplifier has a maximum efficiency of 78.5% for a sinusoidal signal. Solution
VDD M1

Page 5-64

VBias Referring to the figure, assuming there is no v cross-over distortion, the efficiency can be given IN V Bias by

VSS iOUT vOUT M2 VSS VDD RL

η=

(VDD

Vout ( peak ) 2 RL  V ( peak )   − VSS ) out  πRL  vin 2

Fig. S5.5-10A

For maximum efficiency, it can be assumed that the output swing is symmetrical and the peak output voltage can be given by
Vout ( peak ) = VDD = −VSS
2 VDD 2 RL

t

Thus, η =

vout vout(peak) t

(VDD

V 2  − VSS ) DD   πRL 

or,

η=

π = 78.5% 4

id1 vout(peak)/RL t

id2

t -vout(peak)/RL

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.5-11 Assume the parameters of Table 3.1-2 are valid for the transistors of Fig. 5.5-5a. Design VBias so that M1 and M2 are working in class-B operation, i.e., M1 starts to turn on when M2 starts to turn off. Solution VGS1 = (Vin + VBIAS − Vout )
VDD M1 VBias vIN VBias M2 VSS

Page 5-65

VSS iOUT vOUT VDD RL

VGS 2 = (Vin − VBIAS − Vout )
In Class B operation, when M1 starts to turn on and M 2 starts to turn off, the drain currents can be written as
I D1 = I D 2 + I out

Fig. S5.5-10A

or,

' ' KN  W  (VGS1 − VT 1)2 = KP  W  VSG 2 − VT 2 2  L 1 2  L 2

(

)

2

+

Vout RL

Assuming, when Vin = 0 , Vout = 0 , we get
' ' KN  W  (VBIAS − VT 1)2 = KP  W  VBIAS − VT 2 2  L 1 2  L 2

(

)

2

or,

'  VBIAS − VT 1  KP  W   L   = ' K N  L  2  W 1  VBIAS − VT 2 

or,

VBIAS

 VT 1 − =  1 − 

'  KP  W   L  VT 2  ' K N  L  2  W 1  ' KP  W   L   ' K N  L  2  W 1  

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.5-12

Page 5-66

Find an expression for the maximum and minimum output voltage swing for Fig. 5.5-5a. Solution To calculate the maximum output voltage swing, it can be assumed that the input is taken to VDD . Thus,

VGS1 − VT 1 = (VDD + VBIAS − Vout (max) − VT 1 ) and, So,

VDS1 = (VDD − Vout (max)) VDS1 − (VGS1 − VT 1 ) = (VBIAS − VT 1 )

Thus, if VBIAS ≥ VT 1, VDS1 ≥ (VGS1 − VT 1 ) and M1 will be in saturation. Now, I D1 = I L or, or,
' (max) KN  W  (V + VBIAS − Vout (max) − VT 1)2 = Vout R  L 1 DD 2 L

Vout (max) = (VDD + VBIAS − VT 1 ) + Y

where, Y =

1 − RL K (W L)1
' N

(R K (W L) )
L ' N 1

1

2

+

2(VDD + VBIAS − VT 1 )

(R K (W L) )
L ' N 1

To calculate the minimum output voltage swing
I D 2 = −I L

or, or,

' KP  W  V − VBIAS − Vout (min) + VT 2 2  L  2 SS

(

)

2

=−

Vout (min) RL

Vout (min) = VSS − VBIAS + VT 2 − Z

(

)

where, Z =

1 − ' RL K P (W L) 2

(R K (W L) )
L ' P 2

1

2

−

2 VSS − VBIAS + VT 2

(

(R K (W L) )
L ' P 2

)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 5.5-13 Repeat the previous problem for Fig. 5.5-8. Solution Assuming M 2 operate in triode region when Vin = VSS , the maximum output voltage swing can be calculated as follows:
I D 2 = I out

Page 5-67

VDD M2 VTR2 vIN VTR1 M1CL RL iOUT vOUT

or,

Figure 5.5-8 Push-pull inverting CMOS amplifier.
' KP

V (max) W  VSS − VDD + VTR 2 + VT 2 (Vout (max) − VDD ) = out  L 2 RL

(

)

or,

Vout (max) =

VDD     1 1 +  '  W    K P  L  RL VSS − VDD + VTR 2 + VT 2 2       

(

)

Assuming M1 operate in triode region when Vin = VDD , the minimum output voltage swing can be calculated as follows:
I D1 = −I out

or,

' KN

W  (−VSS + VDD − VTR1 − VT 1)(Vout (min) − VSS ) = −VoutR(min)  L 1 L

or,

Vout (min) =

VSS       1 1+    ' W    K N  L  RL ( −VSS + VDD − VTR1 − VT 1 )   1  

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-68

Problem 5.5-14 Given the push-pull inverting CMOS amplifier shown in Fig. 5.5-14, show how shortcircuit protection can be added to this amplifier. Note that R1 could be replaced with an active load if desired. Solution

VDD M9 ISC

VSS VDD M3 VBIAS Vout M7

M8 VSS VDD

M2 Vin M1 VSS M4 M5

M6

ISC VSS

The current source I SC in the figure represents the short circuit current whose value can be set as desired. The current through the transistors M2 and M3 need to be regulated for short circuit protection. The currents carried by M2 and M3 are mirrored into M4 and M9 respectively. When the current tends to increase in M2, the current in M4 would also increase. This would tend to increase the voltage at the drain of M5, but it will decrease the current in M5. Since the current carried by M4 and M5 are same, the gate bias of M4 as well as M2 cannot increase beyond a point where they both carry the maximum limit of the current as set by the short circuit current source. Similarly, the diode-connected transistor M9 would limit the gate bias of M3, thus limiting the output sinking current.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-69

Problem 5.5-15 If R1 = R2 of Fig. 5.5-12, find an expression for the small-signal output resistance Rout. Repeat including the influence of RL on the output resistance. Solution v g1 = v g 2 = R1 v (R1 + R2 ) x

VDD

or,

v g1 = v g 2 = 0.5v x id 1 = 0.5 gm1v x

id2 R1 R2 ix

and,

id 2 = 0.5 gm 2v x

Now, ix = id 1 + id 2 or,

ix = 0.5( gm1 + gm 2 )v x

R1 Vx (R1+R2)

id1

Vx

So, the output resistance becomes
Rout v 2 = x = ix ( gm1 + gm 2 )

VSS

In presence of load ( RL ) , the output resistance will become
  2 Rout =   || [RL ]  ( gm1 + gm 2 ) 

The presence of the load resistance ( RL ) will tend to decrease the output resistance.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-70

Problem 5.5-16 Develop a table that expresses the dependence of the small-signal voltage gain, output resistance, and the dominant pole as a function of dc drain current for the differential amplifier of Fig. 5.2-1, the cascode amplifier of Fig. 5.3-1, the high-output-resistance cascode of Fig. 5.3-6, the inverter of Fig. 5.5-1, and the source follower of Fig. 5.5-3b. Solution Differential Amplifier
VDD M3 M4 vout M1 M2

Cascode Amplifier
VDD

High-Gain Cascode Amp.
M4 VDD VGG4
+

Inverting Amplifer
VDD

Source Follower
VDD M1 vIN

M3 VGG3 M2 VGG2 vout M3 VGG3 M2 VGG2 vin M1 vo Rout

VGG2 vIN M2 ID vOUT M1
VGG2

VSS M2 VSS
Fig. 5.5-3(b)

iOUT vOUT

Circuit
+ vi VBias

M5
FigS5.2-05

+ vin
-

M1
Figure 5.3-1

-

Figure 5.1-1
Fig. 5.3-6(a)

Av

2 λΝ+λP

KN'W 2IDL1 -

2KN'W1 L1IDλP2 1 ∝I

See Eq. (5.337) Gain ∝ ID-1

-2 λΝ+λP

KN'W 2IDL1

Error!

Rout |p1|

1 ∝I

D

D

∝

1 ID
-1.5

1 ∝I

D

∝

1 ID

∝ ID

∝ ID

∝ ID1.5

∝ ID

∝ ID0.5

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-71

Problem 5.6-01 Propose an implementation of the VCCS of Fig. 5.6-2(b). Solution

VDD M3 M4 io

+ vi VBias

M1

M2

M5

FigS5.6-01

Problem 5.6-02 Propose an implementation of the VCVS of Fig. 5.6-3(b). Solution

VDD M3 M4 M6 + vi VBias
FigS5.6-02

M1

vo M2

M5

M7

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 5-72

Problem 5.6-03 Propose an implementation of the CCCS of Fig. 5.6-4(b). Solution
VDD I i1 i2 M1 M2 i2 M3 M4 VDD 2I VDD I io

i1-i2

Fig. S5.6-03

Problem 5.6-04 Propose an implementation of the CCVS of Fig. 5.6-5(b). Solution
VDD I i1 i2 M1 M2 i2 M3 M4 VDD 2I VDD I VDD

M6 i1-i2 vo M7

VBias
Fig. S5.6-04

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-1

CHAPTER 6 – HOMEWORK SOLUTIONS
Problem 6.1-01 Use the null port concept to find the voltage transfer function of the noninverting voltage amplifier shown in Fig. P6.1-1. Solution Let, v1 and v 2 be the voltages at the non-inverting and inverting terminals respectively. Using the Null-port concept and assuming that the lower negative rail is at ground v1 = v 2 = vin

+ vin -

+ -

+ R2 vout -

R1

Figure P6.1-1

Applying KCL

(vout
 vout   v  in

− v2 )

R2

=

(v 2 )
R1 R2 R1    

→

(vout

− v in )

R2

=

(vin )
R1

or,

     = 1 +  

Problem 6.1-02 Show that if the voltage gain of an op amp approaches infinity that the differential input becomes a null port. Assume that the output is returned to the input by means of negative feedback. Solution Rs Ro Referring to the figure, in Vout the presence of negative series feedback, the Vi Rin AvVi differential input can be Vin written as v in = v S − fvout and, So, or, v out = Av v in v in = v S − fAv vin vS v in = 1 ( + fAv ) fVout For a finite value of the negative feedback factor ( f ) , if the value of open-loop differential gain (Av ) tends to become infinite, then the value of the differential input voltage (vin ) would tend to become zero and become a null port.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-2

Problem 6.1-03 Show that the controlled source of Fig. 6.1-5 designated as v1/CMRR is in fact a suitable model for the common-mode behavior of the op amp.

CMRR

v1

Ricm

IB2

VOS v1
Ricm IB1

Ideal Op Amp

Figure 6.1-5 A model for a nonideal op amp showing some of the nonideal linear characteristics.
Solution Referring to the figure, considering only the source representing the common-mode behavior, v1 / CMRR , the following analysis is carried out The common-mode input, v cm , is given by v cm = v1 = v2 Thus, the differential input is v1 v id = v1 − v 2 + CMRR v1 v id = or, CMRR The output voltage is given by v out = Avd v id and, the common-mode rejection ratio is given by A CMRR = vd Acm where, Avd and Acm are the differential and common-mode gains respectively. Thus,
 v  v out = Avd v id = (CMRR )(Acm ) 1   CMRR  v out = (Acm )v1 v out = (Acm )v cm →

or,

This expression proves that the source v1 / CMRR represents the common-mode behavior of the op amp.

+

in2

Cid

Rid

-

v2

vn2

*

Rout

vout

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-3

Problem 6.1-04 Show how to incorporate the PSRR effects of the op amp into the model of the nonideal effects of the op amp given in Fig. 6.1-5. Solution + − Referring to the figure, the sources (v dd / PSRR ) and (v ss / PSRR ) would model the positive PSRR and negative PSRR respectively.
CMRR

v1

vdd PSRR+

Ricm

IB2

VOS v1

Ideal Op Amp Ricm IB1

Problem 6.1-05 Replace the current mirror load of Fig. 6.1-8 with two separate current mirror and show how to recombine these currents in an output stage to get a push-pull output. How can you increase the gain of the configuration equivalent to a two-stage op amp? Solution Referring to the figure, if the aspect ratios of M3 through M6 are same and that of M7 and M8 are equal, then the small-signal gain of this configuration becomes equivalent to a twostage op amp. The small-signal gain of this configuration is given by   g m 2 (g m 6 + g m5 ) Av =    (g   ds2 + g ds4 )(g ds6 + g ds8 ) 
VDD

M5

M3

M4

M6

Vout M1 M2

M7 VBIAS M5

M8

VSS

+

vss PSRR-

in2

Cid

Rid

-

v2

vn2

*

Rout

vout

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-4

Problem 6.1-06 Replace the I→I stage of Fig. 6.1-9 with a current mirror load. How would you increase the gain of this configuration to make it equivalent to a two-stage op amp? Solution In the figure, the transistor M4 is a diode-connected transistor.

VDD VBias M3 M12 M13 + vin M1 M2 M10 M11 VBias M5 VBias M4 M6 M7 VSS I→V Fig. S6.1-6 The gain in the above circuit is already at the level of a two-stage op amp. The gain could easily be increased by making the W/L ratio of M7 to M4 and M6 to M5 greater than one. V→ I I→I
M8 M9

vout

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-5

Problem 6.2-01 Develop the expression for the dominant pole in Eq. (6.2-10) and the output pole in Eq. (6.2-11) from the transfer function of Eq. (6.2-9). Solution The transfer function is given by Equation (6.2-9). Assuming the dominant pole and the output pole are wide apart, the dominant pole, p1 , can be calculated as the root of the polynomial

[ + s{R I (C I + CC )+ RII (C II 1

+ C C )+ g mII R I R II CC } = 0 ]

2 where, the effect due to the s term is neglected assuming the dominant pole is a low frequency pole. −1 p1 = {R I (C I + CC )+ RII (C II + C C )+ g mII R I RII CC }

Considering the most dominant term −1 p1 ≅ {g mII R I R II CC } To compute the output pole (which is assumed to be at high frequency), the polynomial 2 with the s and s terms are considered.

[{R (C s
I

C I + CC )+ RII ( II + CC )+ g mII R I R II CC }+ s p2 = p2 ≅ p2 ≅

2

{R I RII (C I C II + C I CC

+ C CC II )} = 0

]

or, or,

− { I (C I + CC ) + R II (C II + CC )+ g mII R I RII CC } R {RI R II (C I CII + C I CC + CC C II ) } − { mII R I R II CC } g

{ I R II (C C CII )} R { II } C

or,

− { mII } g

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-6

Problem 6.2-02 Fig. 6.2-7 uses asymptotic plots to illustrate the difference between an uncompensated and compensated op amp. What is the approximate value of the real phase margin using the actual curves and not the asymptotic approximations? Solution Assume that the open-loop gain can be expressed as -A v0 where p1 is the dominant pole L(jω) = s  + 1  s + 1   p1   GB The magnitude and phase shift of the open-loop gain can be expressed as, A v0 | L(jω)| =  ω 2  ω 2 p  + 1  GB + 1  1 Arg[L(jω)] = ±180° - tan-1(ω/p1) - tan-1(ω/GB) At frequencies near GB, we can simplify these expression as, GB ω | L(jω)| ≈  ω 2  GB + 1 Arg[L(jω)] = ±180° - 90° - tan-1(ω/GB) = 90° - tan-1(ω/GB) The unity gain frequency is found as, GB ωο =1 → (ωο/GB)4 + (ωο/GB)2-1 = 0  ωο  2   +1  GB (ωο/GB)2 = 0.5 ± 0.5 1+4 = 0.6180 The phase margin becomes, Arg[L(jωο)] = 90° - tan-1(ωο/GB) = 90° - tan-1(0.7862) = 90° - 38.173° = 51.83° ∴ The actual phase margin is 51.83° compared to 45° estimated from the Bode plot. →

ωο = 0.7862GB

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-7

Problem 6.2-03 Derive the relationship for GB given in Eq. (6.2-17) of Sec. 6.2. Solution The small signal voltage gains of the two stages can be given by
Av1 = g m1R I Av 2 = g m 2 R II

And, the overall small-signal voltage gain is given by
Av = g m1 RI g m 2 R II

Assuming the dominant pole is much smaller than the output pole, and the Gain-bandwidth frequency is smaller than the output pole, the overall transfer function of the op amp can be approximated by a single dominant pole, p1 . Av Av ( s) =  s  1 +   p1    where, p1 ≅ Av ( jω ) = −1 {g mII R I R II CC } Av  jω  1 +   p1   

or,

It can be seen that at ω ≅ Av p1 , Av ( jω ) = 1 So, the Gain-bandwidth frequency, ω GB , is given by

ω GB ≅ Av p1 =

gmI CC

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-8

Problem 6.2-04 For an op amp model with two poles and one RHP zero, prove that if the zero is 10 times larger than GB, then in order to achieve a 45° phase margin, the second pole must be placed at least 1.22 times higher than GB. Solution Given, z = 10(GB ) The transfer function is given by s  Av  1 −  z  Av ( s) =  s  s  1 +  1 +    p1   p2   

The phase margin, PM, can be written as   GB  −1  GB  −1  GB    PM = 180 o −  tan −1     p  + tan  p  + tan  z        1  2   or, or,
  GB  o  45 o = 180o −  90 o + tan −1   p  + 5 .7     2   p2 = 1.22(GB )

→

 GB  o tan− 1   p  = 39.3   2

Problem 6.2-05 For an op amp model with three poles and no zero, prove that if the highest pole is 10 times GB, then in order to achieve 60° phase margin, the second pole must be placed at least 2.2 times GB. Solution The transfer function is given by Av Av ( s) =  s  s  s  1 +  1 +  1 +     p1   p 2  p3    The phase margin, PM, can be written as   GB  −1  GB  −1  GB    PM = 180 o −  tan −1   p  + tan  p  + tan  p          1  2   3   or, or,
   GB  60 o = 180o −  90 o + tan −1   + 5 .7 o  p     2   p2 = 2.2(GB )

→

 GB  o tan− 1   p  = 24.3   2

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-9

Problem 6.2-06 Derive the relationships given in Eqs. (6.2-34) through (6.2-37) in Sec. 6.2. Solution The transfer function is given by Equations (6.2-32) through (6.2-36). Now, the denominator of Equation (6.2-32) cannot be factorized readily. So, the roots of this polynomial can be determined intuitively. The zero can be calculated as   CC    − R z CC   = 0 1 − s g    mII    or,
  CC  RZ − 1 g mII    The dominant pole, p1 , is given by z= −1

[ + s{R I (C I + CC )+ RII (C II 1

+ C C )+ g mII R I R II CC + RZ CC } = 0 ]

2 where, the effect due to the s and higher order terms are neglected assuming the dominant pole is a low frequency pole. −1 p1 = {R I (C I + CC )+ RII (C II + C C )+ g mII R I RII CC + RZ CC } Considering the most dominant term −1 p1 ≅ {g mII R I R II CC }

To compute the output pole (which is assumed to be at high frequency), the polynomial 2 with the s and s terms from Equations (6.2-34) and (6.2-35) are considered. − { I (CI + CC ) + R II (CII + CC ) + g mII R I R II C C + R Z CC } R p2 = or, {RI R II (C I CII + C I CC + CC C II )+ RZ C C (RI C I + R II C II ) } or, or, p2 ≅ p2

{ I R II (C C CII )} R − { mII } g ≅ { II } C

− { mII R I R II CC } g

2 3 To compute the third pole, p4 , the polynomial with the s and s terms from Equations (6.2-35) and (6.2-36) are considered. R } − { I R II (C I CII + C I CC + CC C II )+ RZ C C (RI C I + R II C II ) p4 = or, RI R II R Z C I CII CC R − { I R II C II CC } p4 ≅ or, R I RII R Z C I C II CC

or,

p4 ≅

−1 RZ C I

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-10

Problem 6.2-07 Physically explain why the RHP zero occurs in the Miller compensation scheme illustrated in the op amp of Fig. 6.2-8. Why does the RHP zero have a stronger influence on a CMOS op amp than on a similar type BJT op amp? Solution Referring to the figure and considering the VDD M 6 , there are two paths from the transistor input (gate) to the output (drain): inverting and non-inverting. The signal current in the inverting path is M6 given by iinv = g m6 v g 6

The signal current in the non-inverting path is given by V1 i non − inv = v g6 − v out sCC

iinv Cc inon-inv Vout

( (

) )

The zero is created when iinv = inon − inv and iout = 0 g m6 v g 6 = v g 6 − v out sCC v out vg 6 =

or, or,

(− g m6 + sCC ) sCC Thus, the RHP zero is given by the numerator (− g m 6 + sCC ) . The RHP zero has a stronger (degrading) influence in MOS than in BJT as g m, MOS < g m, BJT and, the RHP zero is closer to the Gain-bandwidth frequency thus decreasing the phase margin.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-11

Problem 6.2-08 A two-stage, Miller-compensated CMOS op amp has a RHP zero at 20GB, a dominant pole due to the Miller compensation, a second pole at p2 and a mirror pole at -3GB. (a) If GB is 1MHz, find the location of p2 corresponding to a 45° phase margin. (b) Assume that in part (a) that |p2| = 2GB and a nulling resistor is used to cancel p2. What is the new phase margin assuming that GB = 1MHz? (c) Using the conditions of (b), what is the phase margin if CL is increased by a factor of 4? Solution a.) Since the magnitude of the op amp is unity at GB, then let ω = GB to evaluate the phase.  GB  GB  GB  GB Phase margin= PM = 180° - tan-1 |p1|  - tan-1 |p2|  - tan-1 |p3|  - tan-1 |z1|  But, p1 = GB/Ao, p3 = -3GB and z1 = -20GB which gives GB PM = 45° = 180° - tan-1(Ao) - tan-1 |p2|  - tan-1(0.33)- tan-1(0.05)   GB GB 45° ≈ 90° - tan-1 |p2|  - tan-1(0.33)- tan-1(0.05) = 90° - tan-1 |p2|  - 18.26° - 2.86°    GB GB ∴ tan-1 |p2|  = 45° - 18.26° - 2.86° = 23.48° → |p2| = tan(23.84°) = 0.442   p 2 = - 2.26·GB = -14.2x10 6 rads/sec b.) The only roots now are p1 and p3. Thus, PM = 180° - 90° - tan -1 (0.33) = 90° - 18.3° = 71.7° c.) In this case, z1 is at -2GB and p2 moves to -0.5GB. Thus the phase margin is now, PM = 90° - tan -1 (2) + tan -1 (0.5) - tan -1 (0.33) = 90°-63.43°+26.57°-18.3° = 34.4°

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.2-09 Derive Eq. (6.2-53). Solution
Cc -A

Page 6-12

gmIIvi Vi

CII

RII

Vout

Referring to the figure, applying KCL 1 (− Av i (s) − v out (s))sCC = gmII v i (s) +  sCII + R v out (s) or, 1 (sACC + gmII )v i (s) = − sCII + R    + sCC v out ( s)     II 

II

or,

(sACC + gmII ) v out ( s) =−   v i ( s) 1  sCII + + sCC  RII   v out ( s) ACC =− v i ( s)  (CC + CII )  1 s +   RII (CC + CII )   g   s + mII   ACC 

or,

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-13

Problem 6.2-10 For the two-stage op amp of Fig. 6.2-8, find W1/L1, W6/L6, and Cc if GB = 1 MHz, |p2| = 5 GB, z = 3 GB and CL = C2 = 20 pF. Use the parameter values of Table 3.1-2 and consider only the two-pole model of the op amp. The bias current in M5 is 40 µA and in M7 is 320 µA. Solution Given GB = 1 MHz. p2 = 5GB z = 3GB CL = C2 = 20 pF g Now, p2 = m 6 C2 or, gm 6 = 628.3 µS or, gm 6 2 W  = ≅ 12.33 '  L  6 2K P I D 6 RHP zero is given by z= or, gm 6 CC gm 6 = 33.3pF z gm1 CC vin +

VDD M6 M3 M4

Cc vout C3
M1 M2

C1

C2
M7

+ VBias -

M5

VSS Figure 6.2-8 A two-stage op amp with various parasitic and circuit capacitances shown.

CC =

Finally, Gain-bandwidth is given by GB = or, or,

gm1 = 209.4 µS gm12 W  = ≅ 10 '  L 1 2K N I D1

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-14

Problem 6.2-11 In Fig. 6.2-13, assume that RI = 150 kΩ, RII = 100 kΩ, gmII = 500 µS, CI = 1 pF, CII = 5 pF, and Cc = 30 pF. Find the value of Rz and the locations of all roots for (a) the case where the zero is moved to infinity and (b) the case where the zero cancels the next highest pole. Solution (a.) Zero at infinity. 1 1 Rz = g = 500µS mII R z = 2kΩ Check pole due to Rz. −1 -1 p4 = R C = = -500x106 rps or 79.58 MHz z I 2kΩ·1pF The pole at p2 is p2 ≅ −gmII -500µS ≅ C = 5pF = 100x106 rps or 15.9 MHz II C IC II + C c C I + C c C II −gmIICc

Therefore, p2 is the next highest pole. (b.) Zero at p2.  C c + C II 30+5 1  (1/gmII) =  30  500µS = 2.33kΩ Rz =  C     c R z = 2.33kΩ

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-15

Problem 6.3-01 Express all of the relationships given in Eqs. (6.3-1) through (6.3-9) of Sec. 6.3 in terms of the large-signal model parameters and the dc values of drain current. Solution I SR = 5 (6.3-1) CC
’ 2 K N ( L)1 W Av1 = − 2 I1 (λ P + λ N )

(6.3-2)

Av 2 = −

I 6 (λ P + λ N )

’ 2K P ( L)6 W

2

(6.3-3)

GB =

’ W 2 K N ( L)1 I1 CC

(6.3-4)

’ W 2 K p ( L)6 I 6 p2 = − CL

(6.3-5)

z1 =

W 2K ’p ( L)6 I 6 CC I5 − VT 03 (max) + VT 1 (min)

(6.3-6)

Positive CMR
Vin (max) = V DD −
’ K P (W L )3

(6.3-7)

Negative CMR
Vin (min) = V SS + K ’ (W L ) N 1 I5 + K ’ (W L )5 N 2I 5 + VT 1 (max)

(6.3-8)

VDS(sat) =

2IDS

β

(6.3-9)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-16

Problem 6.3-02 Develop the relationship given in step 5 of Table 6.3-2. Solution Referring to the figure, p3 is generated at the drain of M 3 . Resistance looking into the drain of M 3 is given by 1 1 RIII = ≅ (g m3 + g ds3 + g ds1 ) g m3 The total capacitance at the drain of M 3 is given by
C III = C gs3 + C gs 4 + Cbd 3 + C bd1 + C gd1 ≅ 2C gs3 Thus, the pole at the drain of M 3 is given by −1 p3 = R III C III − g m3 p3 = or, 2C gs3

(

)

Now, if

gm3 2C gs3 o > 10GB , then the contribution due to this pole on the phase margin is less

than 5.7 , i.e., this pole can be neglected. Problem 6.3-03 Show that the relationship between the W/L ratios of Fig. 6.3-1 which guarantees that VSG4 = VSG6 is given by S6/S4 = 2(S7/S5) where Si = Wi/Li. Solution Let us assume that V SG 4 = V SG6 or, So,
VT 4 + V dsat4 = VT 6 + V dsat6 V dsat4 = V dsat6

(1) →
VT 4 = VT 6 2I 4 = K ’ ( L)6 PW 2I6

→

’ K P (W L )4

or,

(W L )6 (W L )4 (W L )6 (W L )4

I I = 6 = 7 I4 I4

→

(W L )6 (W L )4

=

2I 7 I5

Since, VGS 5 = V GS 7 , we have
=2

(W L )7 (W L)5

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-17

Problem 6.3-04 Draw a schematic of the op amp similar to Fig. 6.3-1 but using p-channel input devices. Assuming that same bias currents flow in each circuit, list all characteristics of these two circuits that might be different and tell which is better or worse than the other and by what amount (if possible). Solution In working this problem we shall assume that KN’>KP’. +5V M3 M4 Cc + vin M1 M2 vout vin + M7 M3 -5V Circuit 1 Characteristic Noise Phase margin Gainbandwidth Vicm(max.) Vicm(min.) Sourcing output current Sinking output current Circuit 1 Worse but not by much because the first stage gain is higher. Poorer (gmI larger but gmII is smaller) Larger (GB = gmI/Cc) Larger Smaller Large Constrained M4 M6 M6 VBias +5V

M5

M7 vout

M1

M2 Cc

M5 VBias

-5V Circuit 2 Fig. S6.3-04 Circuit 2 Better but degraded by the lower first stage gain Better Smaller Smaller Larger Constrained Large

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-18

Problem 6.3-05 Use the op amp designed in Ex. 6.3-1 and assume that the input transistors, M1 and M2 have their bulks connected to -2.5V. How will this influence the performance of the op amp designed in Ex. 6.3-1? Use the W/L values of Ex. 6.3-1 for this problem. Wherever the performance is changed, calculate the new value of performance and compare with the old. Solution Referring to the design in Example. 6.3-1, it can be shown that the threshold voltages of the input transistors M1 and M 2 are increased due to body effect (VBS ≠ 0) V BS1 = VBS 2 = −V DS 5 Let us assume that V DS 5 = 1 V. Then,
VT 1 = VT 2 = VT 0 + γ N

( 2φ + V SB1 −

2φ

)

or,

VT 1 = VT 2 = 0.89 V

Assuming that the bias currents in the various branches remain the same, the small-signal g m and g ds values will remain the same. Considering all the performance specifications of the op amp, only the ICMR will be effected. The maximum input common-mode voltage can be given by
Vin (max) = V DD + VT 1 (min) − VT 3 (max) − 2I 3 ’ K P (W L)3

or,

Vin (max) = 2.5 + 0.55 − (0.89 + 0.15) − 0.2 = 1.81 V

The original value of Vin (max) was 2 V. The minimum input common-mode voltage can be given by
Vin (min) = V SS + VT 1 (max) + 2 I1 + ’ K N ( L)1 W 2I5 ’ K N ( L)5 W

Vin (min) = − 2.5 + 0.89 + 0.15 + 0.3 + 0.35 = −0.81 V or, The original value of Vin (min) was -1 V.

The new value of ICMR is 2.62 V as compared to 3 V.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-19

Problem 6.3-06 Repeat Ex. 6.3-1 for a pchannel input, two-stage op amp. Choose the same currents for the first-stage and second-stage as in Ex. 6.3-1. Solution Following the steps of Ex. 6.3-1 we have the following: Cc = 3pF, I5 = 30µA, (W/L)3 =

+ VBias + vin -

VDD M5 M6

M1

M2

Cc

vout

M3

M4 M7 VSS
FigS6.3-06

CL

30 x 10 - 6 = 6.82 → W3 = W4 = 7µm (110x10 -6 )[2.5 − 2 − .85 + 0.55] 2

Next, we find that gm1 = (5x106)(2π)(3x10-12) = 94.25µS which gives gm12 (94.25)2 (W/L)1 = (W/L)2 = 2K’ I = 2·50·15 = 5.92 N 1 Calculating VSD5(sat) we get VDS5 = (−1) − (−2.5) − ∴ (W/L)5 = 30x10-6 - .85 = 0.203V 50x10-6·3 → W 5 = 29µm → W 1= W 2 = 6µm

2(30 x 10 - 6 ) = 29.1 (50 x 10 -6 )(0.203) 2

Next, we find gm4 ≈ 150µS which gives gm6 942.5 S6 = S4 g = 7· 150 = 43.4 ≈ 43 m4 The output stage current is, (942.5 x 10 - 6 ) 2 I6 = (2)(110 x 10-6)(43) = 93µA ∴  93µA  (W/L)7 = (W/L)520µA  = 29(93/30) = 89.9 → W7 = 90µm → W 6 = 43µm

The gain and power dissipation are identical with that in Ex. 6.3-1.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-20

Problem 6.3-07 For the p-channel input, CMOS op amp of Fig. P6.3-7, calculate the open-loop, lowfrequency differential gain, the output resistance, the power consumption, the powersupply rejection ratio at DC, the input common-mode range, the output-voltage swing, the slew rate, the common-mode rejection ratio, and the unity-gain bandwidth for a load capacitance of 20 pF. Assume the model parameters of Table 3.1-2. Design the W/L ratios of M9 and M10 to give a resistance of 1/gm6 and use the simulation program SPICE to find the phase margin and the 1% settling time for no load and for a 20 pF load. Solution Bias current calculation:
VT 8 + VON 8 + I8 .R S = V dd − V ss or, VT 8 +

2.I 8 / = 5 − I 8 .Rs . 3.K p

(1)

Solving for I 8 quadratically gives, I8 =_ 36µA , I5 =_ 36µA , and I7 =_ 60µA
/ Using the formula, g m = 2.K

gm2 gm6

W .I and g ds = λI we get, L = 60 µS , g ds 2 = 0.9µS , g ds 4 = 0.72µS = 363µS , g ds 6 = 3µS , g ds 7 = 2.4µS

(2) (3)

Small-signal open-loop gain: The small-signal voltage gain can be expressed as, − g m2 − g m6 = − 37 and AV 2 = = − 67 AV 1 = ( g ds 2 + g ds4 ) ( g ds6 + g ds7 ) Thus, total open-loop gain is, Output resistance:
Rout = 1 = 185KΩ ( g ds 6 + g ds 7 )

Av = Av1·Av2 = 2489V/V

(3)

(5)

Power dissipation: Pdiss = 5(36 + 36 + 60)µW = 660µW ICMR:
Vin ,max = 2.5 − VT 1 − V ON1 − VON 5 = 0.51V Vin ,min = − 2.5 − VT1 + VT 3 + VON 3 = − 2.21V

(6) (7) (8)

Output voltage swing: V 0,max = 2.5 − VON 7 = 1.81V Slew Rate:
I5 Slew rate under no load condition can be given as SR = C = 6V / µs C

(9)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.3-7 - Continued In presence of a load capacitor of 20 pF, slew rate would be, I 5 I7 SR = min C , C   c L CMRR:

Page 6-21

Under perfectly balanced condition where I1 = I 2 , if a small signal common-mode variation occurs at the two input terminals, the small signal currents i1 = i 2 = i 3 = i 4 and the differential output current at node (7) is zero. So, ideally, common-mode gain would be zero and the value for CMRR would be infinity. GBW: Let us design M9 and M10 first. Both these transistors would operate in triode region and will carry zero dc current. Thus, V ds9 = V ds10 ≅ 0 . The equation of drain current in triode region is given as, W I D ≅ K / (VGS − VT ).V DS . L The on resistance of the MOS transistor in triode region of operation would be, W RON = K / (VGS − VT ) . L 1 It is intended to make the effective resistance of M9 and M10 equal to . g m6 W 9  W 10 (11) So, K’ 9 L  (VGS9-VT9) + K’10 L  (VGS10-VT10) = gm6 9 10 V D 4 = V D 3 = − 2.5 + VT 3 + VON 3 = − 1.51V and VGS10 ≅ − 1V . Putting the appropriate values in (11), we can solve for the aspect ratios of M9 and M10. One of the solutions could be, W 10 W 9 1 and K’10 L  = very small (12) K’ 9 L  = 1  10  9 The dominant pole could be calculated as, − (g ds4 + g ds2 ) p1 = = −1.16 KHz. 2.π . AV 1 .C C And the load pole would be, − gm6 p2 = = − 2.8MHz. 2.π .C L Thus,
VGS 9 ≅ 4V

for a 20 pF load.

It can be noted that in this problem, the product of the open-loop gain and the dominant pole is approximately equal to the load pole. Thus, the gain bandwidth is approximately equal to 2.8 MHz and the phase margin would be close to 45 degrees.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-22

Problem 6.3-08 Design the values of W and L for each transistor of the CMOS op amp in Fig. P6.3-8 to achieve a differential voltage gain of 4000. Assume that K' N = 110 µA/V2, K' P = 50

µA/V2, VTN = −VTP = 0.7 V, and λN = λP = 0.01 V-1. Also, assume that the minimum device dimension is 2 µm and choose the smallest devices possible. Design Cc and R z to give GB = 1 MHz and to eliminate the influence of the RHP zero. How much load capacitance should this op amp be capable of driving without suffering a degradation in the phase margin? What is the slew rate of this op amp? Assume VDD = −VSS = 2.5V and RB = 100 kΩ.
Solution Given
Av = 4000 V/V GB = 1 MHz I8 = 40 µA

and

z1 = ∞

For I 5 = 50 µA , let us assume Thus, VGS 8 = 1 V or,
W  L W  L

2I 8 16 µm  ≅  = ’ 2 2 µm  8 K N (VGS 8 − VT 8 ) 5 W   =  5 4  L 20 µm   = 2 µm 8

or,

and,

40 µm W    = 2 µm  L 7

Also, let us assume that V SG3 = V SG 4 = 1.5 V or,
W  L 2I3 3 µm  W  =  =  = 2 ’ 2 µm 3  L 4 K ( P VSG 3 − VT 3 )

The aspect ratio of M 6 can be calculated as
W   W   L  W    = 2       L 6  L 7 W 5  L  4

→

12 µm W    = 2 µm  L 6

or,

g m6 = 245 µS RZ = 1 g m6 ≅ 4 KΩ

In order to eliminate the RHP zero Now,
Av = 2 g m1 g m6

I 5 I 7 (λ P + λ N )

2

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.3-08 - Continued or, or, or, g m1 = Av I5 I 7 (λ P + λ N )2 2 g m6 W  L   = 0.00145 1

Page 6-23

g m1 = 16 µS g m12 W    = ’  L 1 K N I 5 W  L  W  = 1  L

→

Let us assume a more realistic value as
2 µm   =  2 2 µm

This will give g m1 = 74.2 µS and Av = 9090 V/V g m1 = 74.2 pF Now, CC = GB The phase margin can be approximated as   GB  − 1 GB   PM = 180 o −  tan −1   p  + tan  p       2   1  Considering the worst-case phase margin to be 60 degrees   GB  60 o = 180o −  90o + tan − 1  p (min)    2   p2 (min) = 1.732GB = 1.732 MHz. or,

or,

C L (max) =

g m6 p2 (min)

= 141.5 pF

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-24

Problem 6.3-09 Use the electrical model parameters of the previous problem to design W 3 , L 3 , W 4 , L 4 , W5, L5, Cc, and Rz of Fig. P6.3-8 if the dc currents are increased by a factor of two and if W 1 = L1 = W 2 = L2 = 2 µm to obtain a low-frequency, differential-voltage gain of 5000 and a GB of 1 MHz. All devices should be in saturation under normal operating conditions and the effect of the RHP should be canceled. How much load capacitance should this op amp be able to drive before suffering a degradation in the phase margin? What is the slew rate of this op amp? Solution Given W1 = L1 = W 2 = L2 = 2 µm Referring to the solution of P6.3-8 gm1 = 104.8 µS g CC = m1 = 105 pF GB A I I ( λ + λN ) gm 6 = v 5 7 P = 190.8 µS 2 gm1 g 2 7.2 µm W  = m6 = '  L 6 KP I7 2 µm 1 RZ = ≅ 5.24 KΩ gm 6
2

or, Also,

or, and, Now,

W  W   W   L   W  2 µm = = 0.5 ≅  L 3  L 4  L  6  W  7  L  5 2 µm Assuming VGS 5 = 1 V 2I5 40 µm W  = ' 2 ≅  L  5 K (V − V ) 2 µm N GS 5 T5 Slew rate can be expressed as I SR = 5 ≅ 1 V / µs CC Considering the worst-case phase margin to be 60 degrees   GB  60 o = 180o −  90o + tan − 1  p (min)    2   or, or, p2 (min) = 1.732GB = 1.732 MHz.

CL (max) =

gm 6 = 110 pF p2 (min)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-25

Problem 6.3-10 +2.5V For the op amp shown in Fig. P6.3-10, assume all transistors are 10/1 10/1 M9 operating in the saturation region 10/1 M4 1/1 M3 and find (a.) the dc value of I5, I7 M6 vo and I8, (b.) the low frequency I8 differential voltage gain, Avd(0), Cc=5pF M1 M2 (c.) the GB in Hz, (d.) the I7 positive and negative slew rates, vin 10/1 10/1 20pF + (e.) the power dissipation, and (f.) I5 the phase margin assuming that the open-loop unity gain is 1MHz. M5 M8 M7 10/1 2/1 1/1 -2.5V Solution Figure P6.3-10 (a.) 2·I8 2·I8 1   1 5V = + 0.7 + K P ·1 K N ·1 + 0.7 ⇒ 3.6 = I8  25 + 55 ⇒ I8 = 10.75µA ∴ I 8 = 10.75µA, I 5 = 2I 8 = 21.5µA, and I 7 = 10I 8 = 107.5µA (b.) Av(0) = gm1(rds2||rds4)gm6(rds6||rds7) gm1 = 2·K N ·10·I8 = 153.8µS , gm6 = 2·K P ·10·I7 = 327.9µS , 25 rds2 = 10.75 = 2.33MΩ, 20 20 25 rds4 = 10.75 = 1.86MΩ, rds6 = 107.5 = 0.186MΩ , and rds7 = 107.5 = 0.233MΩ . ∴ A v (0) = (153.8µS)(1.034MΩ)(327.9µS)(0.1034MΩ) = 5395 V/V (c.) g m 1 153.8µS GB = C = 5pF = 30.76Mradians/sec = 4.90MHz c c I5 21.5µA (d.) Due to Cc: |SR| = C = 5pF = 4.3 V/µs I7-I5 86µA Due to CL: |SR| = C = 20pF = 4.3V/µs L (e.) ∴ |SR| = 4.3V/µs

Power Dissipation = 5(I 8 +I 5 +I 7 ) = 5(139.75µA) = 0.699mW GB GB GB (f.) Phase margin = 180° - tan-1 GB/A (0) - tan-1 p  - tan-1 z      2 v  gm6 gm6 p2 = C = 16.395x106 rads/sec and z = C = 65.6x106 rads/sec L c ∴ 6.28 6.28 Phase margin = 90° - tan -1  16.395 - tan -1  65.6 = 6 3 . 6 °    

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-26

Problem 6.3-11 +5V M4 A simple CMOS op amp is shown. Use 2/1 1/1 10/1 vo1 the following model parameters and find M3 M8 v out M1 10µA the numerical value of the small signal + 4/1 M2 10µA differential voltage gain, vout/vin, output 20µA v in 5pF 100µA 4/1 resistance, R out, the dominant pole, p 1, the unity-gainbandwidth, GB, the slew rate, SR, and the dc power dissipation. KN’=24µA/V2, KP’ = 8µA/V2, V TN = M7
1/1

M6

M5

1/1

5/1

-5V

VTP = 0.75V, λN = 0.01V-1 and λP = 0.02V-1. Solution Small signal differential voltage gain: By intuitive analysis methods, vo1 -0.5gm1 vout -gm4 vout 0.5gm1gm4 → vin = (gds1+gds3)(gds4+gds5) vin = g ds1 + g ds3 and vo1 = g ds4 + g ds5 gm1 = 2KNW1ID1 = 24·2·4·10 x10-6 = 43.82µS L1 gds3 = λPID3 = 0.02·10µA = 0.2µS

gds1 = λNID1 = 0.01·10µA = 0.1µS, gm4 =

2KPW4ID4 = 2·8·10·100 x10-6 = 126.5µS L4

gds4 = λPID4 = 0.02·100µA = 2µS, gds5 = λNID5 = 0.01·100µA = 1µS v out 0.5·43.82·126.5 ∴ vin = (0.1+0.2)(1+2) = 3,079V/V Output resistance: 1 106 R o u t = gds4+gds5 = 1+2 = 333kΩ Dominant pole, p1: 1 1 106 |p1| = R1C1 where R1 = gds1+gds3 = 0.1+0.2 = 3.33MΩ gm4 126.5 and C1 = Cc(1+|Av2|) = 5pF 1 + g +g  = 5 1+ 3  = 215.8pF  ds4 ds5   106 ∴ |p1| = 3.33·2.15.8 = 1,391 rads/sec → GB = |p 1 | = 1,391 rads/sec = 221Hz GB=4.382 Mrads/sec=0.697MHz

0.5·gm1 0.5·43.82x10-6 = = 4.382Mrads/s Cc 5x10-12

ID 6 1 0 µ A SR = C = 5pF = 2V/µs c

P diss = 10V(140µA) = 1.4mW

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-27

Problem 6.3-12 On a log-log plot with the vertical axis having a range of 10-3 to 10+3 and the horizontal axis having a range of 1 µA to 100 µA, plot the low-frequency gain A v(0), the unity-gain bandwidth GB, the power dissipation Pdiss, the slew rate SR, the output resistance R out, the magnitude of the dominant pole |p1|, and the magnitude of the RHP zero z, all normalized to their respective values at IB = 1 µA as a function of IB from 1 µA to 100 µA for the standard two-stage CMOS op amp. Assume the current in M5 is k1IB and the output current (M6) is k2IB. Solution gmI GB = C ∝ c IBias vin +

VDD M6 M3 M4 vout Pdiss = (VDD+|VSS|)(1+K1+K2)IBias ∝ Ibias K1IBias SR = C ∝ IBias c 1 1 ∝I Rout = Bias 2λK2IBias

M1

M2

IBias

K2IBias K1IBias M5 VSS M7
Fig. 6.3-04D

IBias2 1 |p1| = g R R C ∝ ∝ IBias1.5 IBias mII I II c gmII |z| = C ∝ IBias c Illustration of the Ibias dependence → Plot is done for normalized bias current.

103 102 101 100 10-1 10-2 10-3 1
Ao

Pdiss and SR

|p1|

GB

and z

and Rout

10 IBias IBias(ref)

100
Fig. 160-05

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-28

Problem 6.3-13 Develop the expression similar to Eq. (6.3-32) for the W/L ratio of M6A in Fig. P6.3-13 that will cause the right-half plane zero to cancel the output pole. Repeat Ex. 6.3-2 using the circuit of Fig. P6.3-13 using vin the values of the + transistors in Ex. 6.3-1.

VDD

M11
M3 M4

M10
M6A
vout

M6B
M1 M2

Cc
M7

CL
+ VBias M5 -

Solution RZ = 1 gm 6 B =

M8 M9 VSS Figure P6.3-13 Nulling resistor implemented by a MOS diode.
1 2K (W L) 6 B I 8
' P

Now, z1 = p2 or, −g −1 = m 6A CC ( RZ − 1 gm 6 A ) CL →
2

−g −1 = m 6A CC (1 gm 6 B − 1 gm 6 A ) CL (1)

W   W  I 8  CC + CL    = or,  L  6 A  L  6 A I 7  CC  Referring to Example 6.3-1 W  W  = = 94 and,  L 6A  L 6 From Equation (1) W  = 31.7 ≅ 32  L 6B or, gm 6 B = 218 µS gm 6 A = 945 µS RZ = z1 = 1 gm 6 B = 4.59 KΩ

I 8 = I 9 = I10 = I11 = 15 µA

−1 = −15 MHz. CC ( RZ − 1 gm 6 A ) −gm 6 A = −15 MHz. CL

p2 =

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-29

Problem 6.3-14 Use the intuitive approach presented in Sec. 5.2 to calculate the small-signal differential voltage gain of the two-stage op amp of Fig. 6.3-1. Solution Referring to the figure, the small-signal currents in the first stage can be given by id 4 = id 3 = id 1 = −gm1 and, So, or, id 2 = gm 2 v in 2 v in 2 v in 2

iout1 = id 4 − id 2 = −( gm1 + gm 2 ) iout1 = −( gm1 )v in gout1 = gds2 + gds4

The small-signal output conductance of the first stage is Thus, the small-signal gain of the first stage becomes Av1 = −gm1 (gds2 + gds4 ) −gm 6 (gds6 + gds7 ) gm1gm 6 (gds2 + gds4 )(gds6 + gds7 )

Considering the second gain stage, the gain can be given by Av 2 =

Thus, the overall small-signal voltage gain becomes Av = Av1 Av 2 =

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-30

Problem 6.3-15 A CMOS op amp capable of operating from 1.5V power supply is shown. All device lengths are 1µm and are to operate in the saturation region. Design all of the W values of every transistor of this op amp to meet the following specifications. Slew rate = ±10V/µs Vout(max) = 1.25V Vout(min) = 0.75V Vic(min) = 1V Vic(max) = 2V GB = 10MHz Phase margin = 60° when the output pole = 2GB and the RHP zero = 10GB. Keep the mirror pole ≥ 10GB (Cox = 0.5fF/µm2). Your design should meet or exceed these specifications. Ignore bulk effects in this problem and summarize your W values to the nearest micron, the value of Cc(pF), and I(µA) in the following table. Use the following model parameters: KN’=24µA/V2, KP’ = 8µA/V2, VTN = - VTP = 0.75V, λN = 0.01V-1 and λP = 0.02V-1. +1.5V M10 M9 1.5I I I v1 M1 I M8 M5 M3 M4 M6 1.5I M2 v2 I I Cc 10I M11 M12 M7 vout 10pF

Solution 1.) p2=2GB ⇒ gm6/CL=2gm1/Cc and z=10GB ⇒ gm6=10gm1. ∴ C c = C L /5 = 2pF 2.) I = Cc·SR = (2x10-11)·107 = 20µA ∴ I = 20µA 3.) GB = gm1/Cc ⇒ gm1 = 20πx106·2x10-12 = 40πx10-6 = 125.67µS W1 W2 gm12 (125.67x10-6)2 = L2 = 2KN(I/2) = = 32.9 ⇒ W1 = W 2 = 33µm L1 2·24x10-6·10x10-6 2·10 4.) Vic(min) = VDS5(sat.)+VGS1(10µA) = 1V→VDS5(sat.) = 1- 24·33 -0.75 = 0.0908 2·I 2·20 VDS5(sat) = 0.0908 = KNS5 → W5 = 24·(0.0908)2 = 201.9µm W 5 = 202µm 5.) Vic(max) = VDD-VSD11(sat)+VTN = 1.5-VSD11(sat)+0.75 = 2V→VSD11(sat) = 0.25V VSD11(sat) ≤ W11=W12≥120µm 2·1.5I K P·S11 → S11 = W11 ≥ 2·30 (0.25)2·8 = 120 →

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-31

Problem 6.3-15 - Continued 6.) Choose S3(S4) by satisfying Vic(max) specification then check mirror pole. 2·I Vic(max) ≥ VGS3(20µA) + VTN → VGS3(20µA) = 1.25V ≥ K N·S3 + 0.75V 2·20 = 6.67 ⇒ W 3 = W 4 = 7 µ m S 3 = S4 = (0.5)2·24 7.) Check mirror pole (p3 = gm3/CMirror). gm3 gm3 2·24·6.67·20x10-6 = 17.98x109 p3 = CMirror = 2·0.667·W3·L3·Cox = 2·0.667·6.67·0.5x10-15 which is much greater than 10GB (0.0628x109). Therefore, W3 and W4 are OK. 8.) gm6 = 10gm1 = 1256.7µS a.) gm6 = 2KNS610I ⇒ W6 = 164.5µm 2·10I b.) Vout(min) = 0.5 ⇒ VDS6(sat) = 0.5 = KNS6 ⇒ W6 = 66.67µm Therefore, use W 6 = 165µm I4 Note: For proper mirroring, S4 = I6 S6 = 8.25µm which is close enough to 7µm. 9.) Use the Vout(max) specification to design W7. Vout(max) = 0.25V ≥ VDS7(sat) = ∴ S7 ≥ 400µA ⇒ 8x10-6(0.25)2 2·200µA 8x10-6·S7

W 7 = 800µm

10.) Now to achieve the proper currents from the current source I gives, S7 S9 = S10 = 10 = 80 → W 9 = W 10 = 80µm and 1.5·S7 10 = 120 → W11 = W12 = 120µm. We saw in step 5 that W11 and W12 had to be greater than 120µm to satisfy Vic(max). ∴ W 11=W 12=120µm S11 = S12 = 11.) Pdiss = 15I·1.5V = 300µA·1.5V = 450µW I W1=W2 W3=W4 W5=W8 W6 W7 W9=W10 W11=W12 Pdiss Cc 2pF 20µA 33µm 7µm 202µm 165µm 800µm 80µm 120µm 450µW

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-32

Problem 6.3-16 A CMOS circuit used as an output buffer for an OTA is shown. Find the value of the small signal output resistance, Rout, and from this value estimate the -3dB bandwidth if a 50pF capacitor is attached to the output. What is the maximum and minimum output voltage if a 1kΩ resistor is attached to the output? What is the quiescent power dissipation of this circuit? Use the following model parameters: KN’=24µA/V2, KP’ = 8µA/V2, VTN = - VTP = 0.75V, λN = 0.01V-1 and λP = 0.02V-1.
M7
+ vin

20 VDD = 2.5V M9 10/1 M8 1/5 6 vin 1 +

vout

M5 8/1

16/1 2

vout

5
M1 M2

1.5V Cc 17 M10 1/1 20/1
M6

4/2 3 5/1

M3

M4

4/2 4 5/1

7

vout

t

30 VSS = -2.5V Figure P6.3-16

-1.5V

Solution Considering the Miller compensation path, the value of the nulling resistor implemented by M10 is given by 1 RZ = ' (1) K N (W L)10 (VDD − VS10 − VT 10 ) The zero created at the output is given by −1 z1 = (2) CC ( RZ − 1 gm 6 ) a.) When the output swings high, the voltage at the source of M10 goes low assuming the compensation capacitor tends to get short-circuited. Thus, (VDD − VS10 − VT 10 ) increases causing a decrease in the value of RZ . Also, as the voltage at the gate of M 6 goes down, the current in M 6 decreases causing a decrease in value of gm 6 . Referring to Equation (2), a decrease in both RZ and gm 6 would tend to place the zero in the right half plane and it would degrade the phase margin causing the op amp to oscillate. b.) When the output swings low, the voltage at the gate of M 6 and the source of M10 goes up. This decreases (VDD − VS10 − VT 10 ) causing an increase in RZ . Also, as the voltage at the gate of M 6 increases, the current through M 6 increases causing and increase in gm 6 . Thus, from Equation (2), an increase in RZ and gm 6 would create a LHP zero which would make the op amp more stable.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-33

Problem 6.4-01 Sketch the asymptotic frequency response of PSRR+ and PSRR- of the two-stage op amp designed in Example 6.3-1. Solution Referring to Example 6.3-1, for the positive PSRR, the poles and zeros are p1 =

(GB )g ds 6
Av (0)GII

= 361 Hz.

z1 = GB = 5 MHz. z2 = p 2 = 15 MHz.

For the negative PSRR, the poles and zeros are
= 71.6 KHz. g m1 z1 = GB = 5 MHz. z2 = p 2 = 15 MHz. p1 =

(GB )GI

The magnitude of the positive and negative PSRR is shown below. 80 60 Magnitude (dB) 40 20 0 -20 10 100 1000 PSRR+ PSRR-

10 4 10 5 10 6 Frequency (Hz)

10 7

10 8

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-34

Problem 6.4-02 Find the low frequency PSRR and all roots of the positive and negative power supply rejection ratio performance for the twostage op amp of Fig. P6.3-9.

+1.5V M9 1/1 I8 vin +

10/1 M3

10/1 M4

100/1 M6

vo

M1 10/1 I5 M8 1/1

Cc=5pF M2 I7 10/1 M5 2/1 -1.5V M7 10/1

20pF

Solution Referring to the figure
V DD − V SS = VT 8 + VT 9 +
’ K N ( L)8 W

Figure P6.3-10
2 I8 +
’ K P (W L )9

2I 8

or,

I8 = 60 µA

Now, g m1 = 363.3 µS , g ds2 = 2.4 µS , g ds4 = 3 µS , g m6 = 774.6 µS , g ds6 = 30 µS g ds7 = 24 µS and ∴
Av1 = 67.3 and Av 2 = 14.3

For the positive PSRR, the low frequency PSRR is A (0)GII PSRR + = v = 1737 g ds6 and poles and zeros are (GB )g ds 6 p1 = = 6.66 KHz, z1 = GB = 11.6 MHz. and z2 = p 2 = 6.2 MHz. Av (0)GII For the negative PSRR, the low frequency PSRR is given by A (0)GII PSRR − = v = 2171 g ds7 and the poles and zeros are (GB )GI = 172.4 p1 = KHz, z1 = GB = 11.6 MHz and z2 = p 2 = 6.2 MHz. g m1

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-35

Problem 6.4-03 Repeat the analysis of the positive PSRR of Fig. 6.4-2 if the Miller compensation circuitry of Fig. 6.2-15(a) is used. Compare the low frequency magnitude and roots with those of the positive PSRR for Fig. 6.4-2. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-36

Problem 6.4-04 In Fig. P6.4-4, find vout/vground and identify the low-frequency gain and the roots. This represents the case where a noisy ac ground can influence the noise performance of the two-stage op amp.

M6 M3 M4

VDD vout Cc

M1

M2

CL

vground

+ VBias -

M5
Figure P6.4-4

M7

VSS

Solution v ground and, v 5 be the small-signal ac voltage at the drain of M 5 . 2 Applying nodal analysis Let, v dd = −v ss =

(g (v m2 out

or, Now, m2 v5 =

(gm 2v out + gds2v dd + gm 5v ss ) (gm1 + gm 2 )

− v 5 ) + gm 5v ss + gds2 (v dd − v 5 ) − gm1v 5 + gds1 (v1 − v 5 ) rds5 = v 5 (1)

)

(g (v
C

out

or, Also,

(gm 2 + sCC )v out + (gds2 + gds3 )v dd = (gds1 + gds3 + sCC )v1
1

− v 5 ) + gds2 (v dd − v 5 ) + gm1v 5 + gds3 (v dd − v1 ) = gds1 (v1 − v 5 ) + sCC (v1 − v out )

) (

)
(2)

(sC (v

− v out ) + gm 7v ss = gds6 (v out − v dd ) + gds7 (v out − v ss ) + sCL v out + gm 6 (v1 − v dd )

) (

)

Using v dd = −v ss , we get

(gm 6 − gm 7 + gds6 − gds7 )v dd = (gds6 + gds7 + s(CC + CL ))v out + (gm 6 − sCC )v1 (3) v out v ground   2 gmI gmII =   GI ( gds6 − gds7 − gm 7 ) 
−1

Using Equations (2) and (3) gives the low frequency PSRR as

The zero is

GI ( gds6 − gds7 − gm 7 ) CC (GI + gm 6 − gm 7 + gds6 − gds7 ) The two poles are same as given by the zeros of Equation (6.4-14) in the text. z1 ≅ −

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.4-05 Repeat the analysis of Fig. 6.4-2 and Fig. 6.4-4 for the p-channel input, two-stage op amp shown in Fig. P6.45. Solution TBD

Page 6-37

+ VBias -

VDD M5 M7

M1

M2

Cc
M3 M4 M6 VSS Figure P6.4-5

vout

CL

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-38

Problem 6.5-01 Assume that in Fig. 6.5-1(a) that the currents in M1 and M2 are 50µA and the W/L values of the NMOS transistors are 10 and of the PMOS transistors are 5. What is the value of VBias that will cause the drain-source voltage of M1 and M2 to be equal to Vds(sat)? Design the value of R. to keep the source-drain voltage of M3 and M4 equal to Vsd(sat). Find an expression for the small-signal voltage gain of vo1/vin for Fig. 6.5-1(a). Solution
V BIAS = VT , MC1 + Vdsat, MC1 + Vdsat , M 1

or,

V BIAS = VT , MC1 +

2I 1 2 I1 + ’ W  ’ W KN  KN  L  C1 L

  1

Ignoring bulk effects V BIAS = 1.3V Now, VG , C3 = VT , C3 + Vdsat , C3 + Vdsat3 VG 3 = VT 3 + V dsat3 And, or,
IR = VG , C3 − VG3 = V dsat, C3

2 = 12.65kΩ ' W  IK P  L C 3 The output impedance is given by Rout = g m, C 4 rds, C 4 rds4 || g m, C 2 rds, C 2 rds2 R=

[

][

]

Rout = 19.38 MΩ

The small-signal voltage gain is given by Av = -gm,C2Rout = -6248 V/V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-39

Problem 6.5-02 If the W/L values of M1, M2, MC1 and MC2 in Fig. 6.5-1(b) are 10 and the currents in M1 and M2 are 50µA, find the W/L values of MB1 through MB5 that will cause the drainsource voltage of M1 and M2 to be equal to Vds(sat). Assume that MB3 = MB4 and the current through MB5 is 5µA. What will be the current flowing through M5? Solution Let, I B 5 = 5 µA VT , B5 + Vdsat, B 5 = VT , C1 + Vdsat , C1 + Vdsat1 2 I B5 2I1 VT , B5 + = VT , C1 + + or, ’ ’ K N (W L )B5 K N (W L)C1

2 I1 ’ K N ( L)1 W

Ignoring bulk effects, and assuming I1 = 50 µA 1 W    =  L B 5 4 The aspect ratios of the transistors MB1 through MB4 can be chosen (assumed) to be 1. The total current through M5 is 110 µA . Problem 6.5-03 In Fig. 6.5-1(a), find the small-signal impedance to ac ground looking into the sources of MC2 and MC4 assuming there is no capacitance attached to the output. Assume the capacitance to ground at these nodes is 0.2pF. What is the value of the poles at the sources of MC3 and MC4? Repeat if a capacitor of 10pF is attached to the output. Solution Let, C1 and C L be the capacitances at the source of MC2 (and MC4) and the output respectively. The impedance looking between the drain of M4 and Vdd (ac ground), Z4 , be 1 Z4 = (g ds4 + sC1 ) The impedance looking between the drain of MC4 and Vdd (ac ground), ZC 4 , be 1 ZC 4 =  (g ds 4 + sC1 )g ds, C 4  + sC L   g m, C 4     Thus, the impedance looking between the source of MC2 and Vdd (ac ground), Z S,C 2 , can be expressed as  rds, C 2 + Z C4   1  ZS , C 2 =   ||   1 + g m , C2 rds, C 2   sC1       1  ZC 4 ZS , C 2 ≅   ||   or, g m , C2 rds, C 2   sC1    

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.5-03 - Continued     1   ZS , C 2 = or,  g m, C2 (g ds 4 + sC1 )g ds, C 4  g m , C2 +s C L + sC1   g m, C 4 g ds , C2 g ds , C2    

Page 6-40

    or,   C1       Similarly, the impedance looking from the source of MC4 to ac ground, ZS ,C 4 , can be expressed as       1 ZS , C 4 =    g m, C 4  g m, C 4 g ds , C2     g m, C4 g ds2 g ds, C2 C1  + s C + 1 +    g ds, C 4 L  g m, C 2 g ds, C 4 g m, C 2 g ds , C4          Referring to problem 6.5-3, we have g m, C 4 = g m 4 = 158.1 µS g m, C 2 = g m 2 = 331.7 µS g ds, C 4 = g ds4 = 2.5 µS g ds, C 2 = g ds2 = 2 µS

   1 ZS , C 2 =   g m, C 2  g m, C 2 g ds , C4  g m, C2 g ds4 g ds, C4 C L + 1 + + s    g ds, C 2 g m, C 4 g ds , C2  g m, C 4 g ds, C 2   

When C L = 0
  1 ZS , C 2 =   Ω −6 −12  6.6 × 10 + s 0.72 × 10      1 ZS , C 4 =   Ω −6 −12  0.76 × 10 + s 0.27 × 10    When C L = 10 pF

(

)

(

)

  1 ZS , C 2 =   Ω −6 −12  6.6 × 10 + s 1659 × 10   

(

)

  1 ZS , C 4 =   Ω −6 −12  0.76 × 10 + s 632.7 × 10   

(

)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-41

Problem 6.5-04 Repeat Example 6.5-1 to find new values of W 1 and W 2 which will give a voltage gain of 10,000. Solution From Example 6.5-1
Rout = 25 MΩ

Thus, for Av = 10,000 A g m1 = v = 400 µS R out or,
2 g m1 14.5 W  W  =   =  = ’ 1  L 1  L  2 2K N I1

Problem 6.5-05 Find the differential-voltage gain of Fig. 6.5-1(a) where the output is taken at the drains of MC2 and MC4, W1/L1 = W2/L2 = 10 µm/1 µm, WC1/LC1 = WC2/LC2 = WC3/LC3 = WC4/LC4 = 1 µm/1 µm, W3/L3 = W4/L4 = 1 µm/1 µm, and I5 = 100 µA. Use the model parameters of Table 3.1-2 . Ignore the bulk effects. Solution I 5 = 100 µA g m1 = g m2 = 331.67 µS g m, C 2 = 104.8 µS g m, C 4 = 70.7 µS rds , C4 = rds4 = 400 KΩ rds , C2 = rds2 = 500 KΩ The output impedance is given by Rout = g m, C 2 rds, C 2 rds2 || g m, C 4 rds, C 4 rds4

[

][

]

or, So,

Rout = [26.2M ]|| [ .3M ] = 7.9MΩ 11

A = −gm 2 Rout = −2620V /V v CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-42

Problem 6.5-06 A CMOS op amp that uses a 5V power supply is shown. All transistor lengths are 1µm and operate in the saturation region. Design all of the W values of every transistor of this op amp to meet the following specifications. Use the following model parameters: KN’=110µA/V2, KP’=50µA/V2, VTN=0.7V, VTP=-0.7V, λN=0.04V-1 and λP=0.05V-1. Slew rate = ±10V/µs Vic(min) = 1.5V Vout(max) = 4V Vic(max) = 4V Vout(min) = 1V GB = 10MHz

Your design should meet or exceed these specifications. Ignore bulk effects and summarize your W values to the nearest micron, the bias current, I5(µA), the power dissipation, the differential voltage gain, A vd, and VBP and VBN in the following table. Assume that Vbias is whatever value necessary to give I5. W1=W2 W3=W4=W6 =W7=W8 89.75 40 W9=W10 W5 =W11 18.2 I5(µA) Avd VBP VBN Pdiss 2.5mW

13.75 250µA 17,338V/V 3.3V 1.7V

VDD = 5V M8 M3 M4 VBP v1 VBN M6 M7 I10 M11 M10
S01FEP2

v2 I9 VBias M9

M1 M2 I5 M5

vout 25pF

Solution Since W3 =W4 =W6 =W7 =W8 and W9 =W10 =W11, then I5 is the current available to charge the 25pF load capacitor. Therefore, dvOUT = 25pF(10V/µs) = 250µA I5 = C dt Note that normally, I10 = I9 = 125µA. However, for the following calculations we will use I6 or I10 equal to 250µA for the following vOUT(max/min) calculations. vOUT(max) = 4V ⇒ 0.5 = 2I5 K P '(W6/L6) = 2I5 K P '(W6/L6)

W 6 = W 7 = 40 = W 3 = W 4 = W 8

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-43

Problem 6.5-07 Verify Eqs. (6.5-4) through (6.5-8) of Sec. 6.5 for the two-stage op amp of Fig. 6.5-3 having a cascode second stage. If the second stage bias current is 50 µA and W6/L6 =W C6/LC6 = WC7/LC7 = W7/L7 = 1 µm/1 µm, what is the output resistance of this amplifier using the parameters of Table 3.1-2? Solution From intuitive analysis, it can be shown that gm1 Av1 = − (gds2 + gds4 ) For the second gain stage, the output resistance of the cascode stage can be given by RII = [gm ,C 6 rds,C 6 rds6 ] || [gm ,C 7 rds,C 7 rds7 ] or, Av 2 = −gm 6 RII Thus, Av = Av1 Av 2 = For, I 7 = 50 µA

(gds2 + gds4 ){[gm,C 6rds,C 6rds6 ] || [gm,C 7rds,C 7rds7 ]}

gm1gm 6

RII = [11.3 M ] || [26.2 M ] = 7.9MΩ

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-44

Problem 6.5-08 Verify Eqs. (6.5-9) through (6.5-11) of Sec. 6.5 assuming that M3 = M4 = M6 = M8 and M9 = M10 = M11 = M12 and give an expression for the overall differential-voltage gain of Fig. 6.5-4. Solution Solving the circuit intuitively The effective transconductance of the first stage gm1 2 The effective conductance of the first stage gmI = gI = gm 3 The effective transconductance of the second stage gmII = ( gm 6 + gm11 ) The effective conductance of the second stage gII = Now, Av1 = − Av 2 = − gm1 2 gm 3 gds6 gds7 gds11gds12 + gm 7 gm12

 gds6 gds7 gds11gds12  +  gm 7 gm12   

(gm 6 + gm11)

or,

Av =

gm1 ( gm 6 + gm11 ) g g g g  2 gm 3 ds6 ds7 + ds11 ds12  gm 7 gm12   

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-45

Problem 6.5-09 An internallycompensated, cascode op amp is shown in Fig. P6.5.-9. (a) Derive an expression for the common-mode input range. (b) Find 60/10 W 1/L 1, W 2/L 2, W 3/L 3, and W4/L4 when IBIAS is 80 µA and the input CMR is −3.5 V to 3.5 V. Use K'N = 25 µA/V2, K'p = 11 µA/V2 and |VT| = 0.8 60/10 to 1.0 V.

VDD = 5V M10 M8 M5 M11 M3 IBias vin + M1 M4 M2 M6

Cc vout CL

I7 M12

Solution The minimum input common-mode voltage can be given by Vin (min) = VSS + VT 1 (max) − Vdsat1 − Vdsat 7 Vin (min) = VSS + VT 1 (max) −

30/10 VSS = -5V Figure P6.5-9

M7

M9

I7 2I7 − ' K (W L)1 K N (W L) 7
' N

(1)

The maximum input common-mode voltage can be given by Vin (max) = VDD + VT 1 (min) − VT 5 (max) − Vdsat 3 − Vdsat 5 Vin (max) = VDD + VT 1 (min) − VT 5 (max) − The input common-mode range is given by ICMR = Vin (max) − Vin (min) which can be derived from Equations (1) and (2). Given I 7 = 40 µA, Vin (min) = −2.5 V and (W L) 7 = 3, from Equation (1)  W   W  64 µm = =  L 1  L  2 10 µm Also, for I 7 = 40 µA, Vin (max) = 3.5 V and assuming (W L) 5 = 6, from Equation (2)  W   W  135 µm = =  L  3  L  4 10 µm I7 I7 − ' K (W L) 3 K P (W L) 5
' P

(2)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-46

Problem 6.5-10 Develop an expression for the small-signal differentialvoltage gain and output resistance of the cascode op amp of Fig. P6.5-9.

VDD = 5V M10 M8 M5 M6

60/10

M11 M3 M4 M1 M2

Cc vout Solution The output resistance of the first gain stage is Rout1 ≅ rds 6 60/10 So,
Av1 = − g m1Rout1 = − g m1rds6

IBias vin +

CL

I7 M12

30/10 VSS = -5V Figure P6.5-9

M7

M9

The output resistance of the second gain stage is 1 Rout 2 = (g ds8 + g ds9 ) So, g m8 Av 2 = − g m8 Rout 2 = − (g ds8 + g ds 9 ) The overall small-signal gain is Av = Av1 Av 2 g m1 g m8 Av = or, g ds6 (g ds8 + g ds9 )
I 7 I 9 (λ P + λ N ) λ P The small-signal output resistance is given by 1 Rout = Rout 2 = (g ds8 + g ds9 )

or,

Av =

’ 8K ’ K P (W L)1 (W L )8 N 2 2

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-47

Problem 6.5-11 Verify the upper input common mode range of Ex. 6.5-2, step 6.) for the actual value of S 3 = S4 of 40. Solution The maximum input common-mode voltage is given by
Vin (max) = V DD + VT 1 (min) − VT 3 (max) − Vdsat3

or, or,

Vin (max) = V DD + VT 1 (min) − VT 3 (max) −

’ K P ( L)3 W

2I3

Vin (max) = 1.98V

Problem 6.5-12 Repeat Example 6.5-2 if the differential input pair are PMOS transistors (i.e. all NMOS transistors become PMOS and all PMOS transistors become NMOS and the power supplies are reversed).
VDD VBIAS M5 M10

M13 M6

M1

M2

M9 R1 R2

M7 Vout CL M14 M12

M4 M3 M8 M15 M11

VSS

Solution To satisfy the slew rate I 6 = I 7 = I12 = I11 = 250 µA The maximum output voltage is 1.5 V
V dsat6 = V dsat7 = 0.5 V

and let I 5 = 100 µA
S6 = S7 = S 9 = S10 = 40

→

Similarly, considering the minimum output voltage as –1.5 V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-48

Problem 6.5-12 - Continued
V dsat11 = Vdsat12 = 0.5 V

→

S11 = S12 = S14 = S15 = 18.2

The value of R1 and R2 can be calculated as V V dsat12 R1 = dsat7 = 2 KΩ = 2 KΩ and, R2 = I8 I15 Now, S6 2g m 3 Av g m1 = = 2.5 and RII ≅ 11 MΩ and, k = S4 kRII (g m6 + g m8 ) 2g m 3GB = 149 µS Thus, g m1 = 107.9 µS Also, g m1 = k (g m6 + g m8 )
S1 = S 2 = 4.4 So, let us choose g m1 = 149 µS . → But for this value of S1 = S 2 = 4.4 , from the expression of maximum input commonmode voltage, we will get V dsat5 = 0.025 V which is too small. So let us choose S1 = S 2 = 20 This, from the expression of Vin (max) , will give S5 = 27.7

Or,

S13 = 1.25S 5 = 34.6 and,

S8 = 2.5S 3 = 40

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-49

Problem 6.5-13 A CMOS op amp that uses a 5V VDD = 5V power supply is shown. All transistor lengths are 1µm and operate in the saturation region. M8 M6 M3 M4 Design all of the W values of every transistor of this op amp to meet the following VBP M7 specifications: Slew rate = vout v2 M2 v1 M1 ±10V/µs, Vout(max) = 4V, I10 Vout(min) = 1V, Vic(min) = I9 1.5V, Vic(max) = 4V and GB = I5 VBN M11 VBias 10MHz. 25pF M5 Your design should meet or exceed these M9 M10 specifications. Ignore bulk effects and summarize your W values to the nearest micron, the bias current, I5(µA), the power Figure P6.5-13 dissipation, the differential voltage gain, Avd, and VBP and VBN in the table shown. Solution 1.) I5 = CL·SR = 250µA W1 (1.570x10-3)2 2.) gm1 = GB·CL·= 20πx106·25pF = 1,570.8µS ⇒ L = = 90 1 2·110·125x10-6 2ID 2·250 3.) W3=W4=W6=W7=W8 = 2 = 50·0.25 = 40 (assumed ID of 250µA K’(VDS(sat)) worst case) 2ID 2·250 4.) W9=W10=W11 = = 110·0.25 = 18 (assumed ID of 250µA worst case) K’(VDS(sat))2 5.) Vicm(min) = VDS5(sat) + VGS1 → VDS5(sat) = 1.5 - (0.159+0.7) = 0.6411V 2ID 2·250 ∴ W5 = 2 = 110·0.64112 = 11 K’(VDS(sat)) gmN = 704µS, rdsN = 0.2MΩ, gmP = 707µS, rdsN = 0.16MΩ 6.) Avd = gm1Rout Rout ≈ gmN· rdsN2|| gmP· rdsP2 = 28.14MΩ||18.1ΜΩ = 11ΜΩ ∴ Avd = 1.57mS·11MΩ = 17,329V/V 7.) VBP = 5-VDSP(sat) + VGSP(sat) = 5-0.5+0.5+0.7 = 3.3V VBN = VDSP(sat) + VGSP(sat) = 0.5+0.5+0.7 = 1.7V 8.) Pdiss = 5(250µA + 250µA) = 2.5mW W1=W2 W3=W4=W6 =W7=W8 90 40 W9=W10 W5 I5(µA) Avd =W11 18 11 VBP VBN Pdiss 2.5mW

250µA 17,324V/V 3.3V 1.7V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-50

Problem 6.5-14 Repeat Example 6.5-3 if the differential input pair are PMOS transistors (i.e. all NMOS transistors become PMOS and all PMOS transistors become NMOS and the power supplies are reversed).
VDD VBIAS M3

M12 M10 M11

M1

M2 R1

M8 R2

M9 Vout CL M7

M13

M6

M14

M4

M5

VSS

Solution I 3 = 100 µA and, Given, Vout (max) = 2 V

I 4 = I5 = 125 µA V dsat9 = V dsat11 = 0.25 V → Considering worst-case peak sourcing current of 125 µA S8 = S 9 = S10 = S11 = 80 V dsat7 = V dsat5 = 0.25 V Given, Vout (min) = −2 V → Considering worst-case peak sinking current of 125 µA I 5 = 125 µA and I 7 = 25 µA S6 = S7 = S13 = 7.3

And,

S4 = S5 = S14 = 36.4 V R1 = dsat7 = 2 KΩ I14

and

V R2 = dsat9 = 2 KΩ I10

From gain-bandwidth 2 (GB )2 C L = 79 S1 = S 2 = ’ K P I3

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.5-14 - Continued Considering Vin (max) = 1 V
S3 = 21.6 V dsat 3 = 0.43 V → The minimum input common-mode voltage is Vin (min) = V SS − VT 1 (min) + V dsat4 = −2.8 V

Page 6-51

Finally, S12 = 1.25S 3 = 27 The small-signal gain is

(2 + k ) g R (2 + 2k ) mI II R (g + g ds 4 ) k = 9 ds2 (g m7 rds7 )
Av =

where, R9 = 55 MΩ g mI = 628.3 µS , g m7 = 347 µS , g ds7 = 3 µS , g ds4 = 5 µS , g ds2 = 2.5 µS

So,

k = 3.96 RII = 12 MΩ Av = 4364 V/V

or,

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-52

Problem 6.5-15 This problem deals +3V with the op amp M3 M4 shown in Fig. M14 P6.5-15. All 1.5I 1.5I device lengths are 1µm, the slew rate M15 M6 M7 is ±10V/µs, the GB is 10MHz, the 0.5I 0.5I I I maximum output I v1 M1 voltage is +2V, the M8 M9 minimum output v2 I M2 voltage is -2V, and the input common I I mode range is from M13 M10 M12 M5 M11 -1V to +2V. Design all W values of all transistors in -3V this op amp. Your Figure P6.5-15 design must meet or exceed the specifications. When calculating the maximum or minimum output voltages, divide the voltage drop across series transistors equally. Ignore bulk effects in this problem. When you have completed your design, find the value of the small signal differential voltage gain, Avd = vout/vid, where vid = v1-v2 and the small signal output resistance, Rout. Solution 1.) The slew rate will specify I. ∴ I = C·SR = 10-11·107 = 10-4 = 100µA.

vout 10pF

2.) Use GB to define W1 and W2. gm1 GB = C → gm1 = GB·C = 2πx107·10-11 = 628µS gm12 (628)2 ⇒ W 1 = W 2 = 36µm ∴ W1 = 2K (0.5I) = 2·110·50 = 35.85 N 3.) Design W15 to give VT+2VON bias for M6 and M7. VON = 0.5V will meet the desired maximum output voltage specification. Therefore, 2I VSG15 = VON15 + |VT| = 2(0.5V) + |VT| → VON15 = 1V = K PW 15 2I 2·100 ∴ W15 = = = 4µm ⇒ W 15 = 4µm KPVON152 50·12 4.) Design W3, W4, W6 and W7 to have a saturation voltage of 0.5V with 1.5I current. W3 =W 4 =W 6 =W 7 = 2(1.5I) 2·150 2 = 50·0.52 = 24µm KPVON ⇒ W 3 =W 4 =W 6 =W 7 = 24µm

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-53

Problem 6.5-15 – Continued 5.) Next design W8, W9, W10 and W11 to meet the minimum output voltage specification. Note that we have not taken advantage of smallest minimum output voltage because a normal cascode current mirror is used which has a minimum voltage across it of VT + 2V ON . Therefore, setting VT + 2VON = 1V gives VON = 0.15V. Using worst case current, we choose 1.5I. Therefore, 2(1.5I) 2·150 = = 121µm ⇒ W 8 =W 9 =W 10 =W 11 = W 8 =W 9 =W 10 =W 11 = K NV ON2 110·0.152 121µm 6.) Check the maximum ICM voltage. Vic(max) = VDD + VSD3(sat) + VTN = 3V – 0.5 + 0.7 = 3.2V which exceeds spec. 7.) Use the minimum ICM voltage to design W5. 2·50   Vic(min) = VSS + VDS5(sat) + VGS1 = -3 + VDS5(sat) +  110·36+0.7 = -1V 2I = 1.39µm = 1.4µm VDS5(sat) = 1.141 → W 5 = K N V DS5 (sat)2 Also, let W12 =W13 =W5 ⇒ W 12 =W 13 =W 5 = 1.4µm

∴

8.) W14 is designed as I14 I W 14 = W 3 I = 24µm 1.5I = 16µm 3 Now, calculate the op amp small-signal performance. Rout ≈ rds11gm9rds9||gm7rds7(rds2||rds4) gm9 = ⇒ W 14 = 16µm

25V 2KN·I·W9 = 1632µS, rds9 = rds11 = 100µA = 0.25MΩ, 20V 25V gm7 = 2KP·I·W7 = 490µS, rds7 = 100µA = 0.2MΩ, rd2 = 50µA = 0.5MΩ 20V rds4 = 150µA = 0.1333MΩ ∴ R out ≈ 102ΜΩ||10.31ΜΩ = 9.3682ΜΩ 102MΩ 2+k Avd =  2+2k gm1Rout, k = (r ||r )g r = 9.888, gm1 = K N ·I·W1 = 629µS   ds2 ds4 m7 ds7 ∴ Avd = (0.5459)(629µS)(9.3682MΩ) = 3,217V/V ⇒ A vd = 3,217V/V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-54

Problem 6.5-16 The small signal resistances looking into the sources of M6 and M7 of Fig. P6.5-15 will be different based on what we learned for the cascode amplifier of Chapter 5. Assume that the capacitance from each of these nodes (sources of M6 and M7) are identical and determine the influence of these poles on the small-signal differential frequency response. Solution The resistance looking from the output to Vss is
RD 9 ≅ g m9 rds9 rds11

The resistance looking at the source of M7 is
RB = RB

or,

(rds7 + R D9 ) ( + g m 7 rds7 ) 1 (g r r ) ≅ m 9 ds9 ds11 (g m 7 rds7 )
1 g m8 + 1 g m10

(1)

The resistance looking from the drain of M8 to Vss is RD 8 = The resistance looking at the source of M6 is (r + R D8 ) 1 R A = ds6 RB ≅ → ( + g m 6 rds6 ) 1 g m6 The poles at the sources of M6 and M7 are g 1 pA = − ≅ − m6 and RA C C
1 RB C

(2)

pB = −

≅−

1 rdsC

Both of these poles will appear as output poles in the overall voltage transfer function. Problem 6.6-01 How large could the offset voltage in Fig. 6.6-1 be before this method of measuring the open-loop response would be useless if the open-loop gain is 5000 V/V and the power supplies are ±2.5V? Solution Given, V DD − V SS = 5 V, and Av = 5000 V/V Therefore, the offset voltage should be less than ( −V SS ) V Vos < DD Av or,
Vos < 1 mV

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-55

Problem 6.6-02 Develop the closed-loop frequency response for op amp circuit shown which is used to measure the open-loop frequency reasponse. Sketch the closed-loop frequency response of the magnitude of Vout/Vin if the low frequency gain is 4000 V/V, the GB = 1MHz, R = 10MΩ, and C = 10µF. (Ignore RL and CL)

vIN CL C R RL

vOUT

VDD

VSS
S01E2P2

Solution The open-loop transfer function of the op amp is, 2πx106 GB Av(s) = s +(GB/A (0)) = v s +500π The closed-loop transfer function of the op amp can be expressed as,   -1/sC     -1/RC   vOUT = Av(s) R+(1/sC) v OUT +v IN  = A v(s) s+(1/RC) v OUT +v IN  ∴ vOUT -[s +(1/RC)]A v(s) -[s +(1/RC)] -(s+0.01) = s +(1/RC)+A (s)/RC = s +(1/RC) = s +0.01 vI N v A v(s) +1/R C A v(s) + 0 . 0 1 Substituting, Av(s) gives, vOUT -2πx106s -2πx104 -2πx106s -2πx104 -2πx10 6(s +0.01) = = 2 = (s+41.07)(s+1529.72) v I N (s+0.01)(s+500π)+2πx104 s +500πs +2πx104 The magnitude of the closed-loop frequency response is plotted below. 80 Magnitude, dB 60 40 20 0 -20 0.001 0.1 10 1000 105 Radian Frequency (radians/sec) 107
S01E2S2

|Av(jω)|

Vout(jω) Vin(jω)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-56

Problem 6.6-03 Show how to modify Fig. 6.6-6 in order to measure the open-loop frequency response of the op amp under test and describe the procedure to be followed. Solution From the figure, let us change the v SET associated with the top op amp. Change in this voltage would cause a change in v I at the input of the DUT. Let, for v SET 1 v v I 1 = out1 AV And, for v SET 2 v v I 2 = out2 AV ∆v (v − v ) (v − v out 2 ) = 1000 out AV = out1 out 2 = 1000 out1 or, ∆v os (v I 1 − v I 2 ) (v os1 − v os2 ) Thus, by measuring the values of ∆ vout and ∆ vos while changing v SET can help in finding the value of the open-loop gain. Problem 6.6-04 A circuit is shown which is used to measure the CMRR and PSRR of an vos op amp. Prove that the CMRR can be given as 1000 vicm 10kΩ CMRR = vos

100kΩ 100kΩ vicm

Solution vOUT The definition of the common-mode + rejection ratio is 10Ω vi vout CL RL  Avd  v id CMRR = A  = v out  cm vicm However, in the above circuit the value of vout is the same so that we get vicm CMRR = v id vos But vid = vi and vos ≈ 1000vi = 1000vid ⇒ vid = 1000 vicm 1000 vicm Substituting in the previous expression gives, CMRR = v = vos os 1000

+ -

VDD vicm VSS
S99FEP7

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-57

Problem 6.6-05 Sketch a circuit configuration suitable for simulating the following op amp characteristics: (a) slew rate, (b) transient response, (c) input CMR, (d) output voltage swing. Repeat for the measurement of the above op amp characteristics. What changes are made and why? Solution
VDD Vin Vout VSS CL RL

Slew rate, Transient response, and ICMR measurements VDD Vin Vout VSS CL RL

Output voltage swing measurement

The measurement of ICMR, Slew rate, and large-signal transient response can be measured using the buffer configuration as shown in the figure. The input applied is a railto-rail step signal, which can be used to measure the maximum and minimum input swing, the slew rate, rise and settling time. The same configuration can be used to measure the performance in simulation. This buffer configuration can also be used to measure the smallsignal transient performance. The applied input should be a small signal applied over the nominal input common-mode bias voltage, and it can be used to measure the overshoot. The maximum and minimum output voltage swing can be measured using the open-loop configuration of the op amp as shown in the figure. The input applied is a rail-to-rail step signal, which will overdrive the output to its maximum and minimum swing voltage levels.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-58

Problem 6.6-06 Using two identical op amps, show how to use SPICE in order to obtain a voltage which is proportional to CMRR rather than the inverse relationship given in Sec. 6.6. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-07 Repeat the above problem for PSRR. Solution TBD

Page 6-59

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-60

Problem 6.6-08 Use SPICE to simulate the op amp of Example 6.5-2. The differential-frequency response, power dissipation, phase margin, common-mode input range, output-voltage range, slew rate, and settling time are to be simulated with a load capacitance of 20 pF. Use the model parameters of Table 3.1-2. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-61

Problem 6.6-09 Use SPICE to simulate the op amp of Example 6.5-3. The differential frequency response, power dissipation, phase margin, input common-mode range, output-voltage range, slew rate, and settling time are to be simulated with a load capacitance of 20pF. Use the model parameters of Table 3.1-2. Solution
VDD
3

M14M4
10 8

M5
9

11 1 2

vin +

M1

6

M2
12

M15 M6 13 R1
R2
14

M7

5

vout

CL
M9
16

+ VBias7 -

M8 M3 M10 VSS
4 15

M11

Figure 6.5-7 (b) The following is the SPICE source file for figure 6.5-7. * Problem 6.6-9 SPICE simulation * *Voltage gain and phase margin *VDD 3 0 DC 2.5 *VSS 0 4 DC 2.5 *VIN 30 0 DC 0 AC 1.0 *EIN+ 1 0 30 0 1 *EIN- 2 0 30 0 -1 *Output voltage swing *VDD 3 0 DC 2.5 *VSS 0 4 DC 2.5 *VIN+ 40 0 DC 0 AC 1.0 *VIN- 2 0 0 *Reg1 40 1 10K *Reg2 5 1 100K

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-09 - Continued *ICMR *VDD 3 0 DC 2.5 *VSS 0 4 DC 2.5 *VIN+ 1 0 DC 0 AC 1.0 *PSRR+ *VDD 3 0 DC 2.5 AC 1.0 *VSS 0 4 DC 2.5 *PSRRVDD 3 0 DC 2.5 VSS 0 4 DC 2.5 AC 1.0 VIN+ 1 0 DC 0

Page 6-62

*Slew Rate *VDD 3 0 DC 2.5 *VSS 0 4 DC 2.5 *VIN+ 1 0 PWL(0 -1 10N -1 20N 1 2U 1 2.0001U -1 4U -1 4.0001U 1 6U 1 6.0001u + -1 8U -1 8.0001U 1 10U 1) *General *X1 1 2 3 4 5 OPAMP *Unity gain configuration X1 1 5 3 4 5 OPAMP .SUBCKT OPAMP 1 2 3 4 5 M1 8 1 6 4 NPN W=35.9u L=1u M2 9 2 6 4 NPN W=35.9u L=1u M3 6 7 4 4 NPN W=20u L=1u M4 8 11 3 3 PNP W=80u L=1u M5 9 11 3 3 PNP W=80u L=1u M6 13 12 8 8 PNP W=80u L=1u M7 5 12 9 9 PNP W=80u L=1u M8 14 13 15 4 NPN W=36.36u L=1u M9 5 13 16 4 NPN W=36.36u L=1u M10 15 14 4 4 NPN W=36.36u L=1u M11 16 14 4 4 NPN W=36.36u L=1u M12 12 7 4 4 NPN W=25u L=1u M13 11 12 10 10 PNP W=80u L=1u M14 10 11 3 3 PNP W=80u L=1u R1 11 12 2K R2 13 14 2K VBIAS 0 7 1.29 .MODEL NPN NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 .MODEL PNP PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 .ENDS *Load cap CL 5 0 20PF .OP .OPTION GMIN=1e-6

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-09 - Continued .DC VIN+ -2.5 2.5 0.1 .PRINT DC V(5) .TRAN 0.05u 10u .PRINT TRAN V(5) V(1) .AC DEC 10 1 100MEG .PRINT AC VDB(5) VP(5) .PROBE .END The simulation results are shown.

Page 6-63

Result 1. Voltage gain and phase margin

Result 2. Output voltage swing range

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-09 - Continued

Page 6-64

Result 3. Input common-mode range

Result 4. Positive power supply rejection ratio

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-09 - Continued

Page 6-65

Result 5. Negative power supply rejection ratio

Result 6. Slew rate

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-09 - Continued

Page 6-66

Result 7. Settling time From the output file of the SPICE simulation, total power dissipation is 6mW. The following is a part of the output file. NODE VOLTAGE ( 1) -1.0000 ( 3) NODE VOLTAGE 2.5000 ( NODE VOLTAGE 5) -1.0004 1.5874 -.9291 NODE VOLTAGE

4) -2.5000 (

( X1.6) -2.0477 ( X1.7) -1.2900 ( X1.8) (X1.10) 1.7094 (X1.11) 1.3594 (X1.12)

1.5876 ( X1.9) .5508 (X1.13)

(X1.14) -1.4451 (X1.15) -2.0731 (X1.16) -2.0706

VOLTAGE SOURCE CURRENTS NAME CURRENT VDD -1.218E-03 VSS -1.218E-03 VIN+ 0.000E+00 X1.VBIAS 0.000E+00 TOTAL POWER DISSIPATION 6.09E-03 WATTS

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 6.6-10 A possible scheme for simulating the CMRR of an op amp is shown. Find the value of Vout/Vin and show that it is approximately equal to 1/CMRR. What problems might result in the actual implementation of this circuit to measure CMRR? Solution The model for this circuit is shown. We can write that Vout = Avd(V1-V2) + AcmVcm = -AvdVout + AcmVcm Thus, Vout(1+Avd) = AcmVcm or Acm Vout A cm 1 = 1+A ≈ A = CMRR V cm vd vd
S02E2S4A

Page 6-67

V1

S02E2P4

The potential problem with this method is that PSRR+ is not equal to PSRR -. This can be seen by moving the Vcm through the power supplies so it appears as power supply ripple as shown below. This method depends on the fact that the positive and negative power supply ripple will cancel each other.

Vcm

V1

S02E2S4B

+

-

V2

vout

VDD Vcm VSS

+

-

V2

vout

VDD VSS Vcm
Vout

V2
Avd(V1-V2)

V1
AcmVcm

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-68

Problem 6.6-11 Explain why the positive overshoot of the simulated positive step response of the op amp shown in Fig. 6.6-20(b) is smaller than the negative overshoot for the negative step response. Use the op amp values given in Ex. 6.3-1 and the information given in Tables 6.6-1 and 6.6-3. Solution Consider the following circuit and waveform: VDD = 2.5V 94/1 M6 i6 iCc iCL 0.1V

Cc 95µA VBias
VSS = -2.5V M7

vout

t

CL
-0.1V 0.1µs 0.1µs
Fig. 6.6-22

During the rise time, iCL = CL(dvout/dt )= 10pF(0.2V/0.1µs) = 20µA and iCc = 3pf(2V/µs) = 6µA ∴ i6 = 95µA + 20µA + 6µA = 121µA ⇒ gm6 = 1066µS (nominal was 942.5µS) During the fall time, iCL = CL(-dvout/dt )= 10pF(-0.2V/0.1µs) = -20µA and iCc = -3pf(2V/µs) = -6µA ∴ i6 = 95µA - 20µA - 6µA = 69µA ⇒ gm6 = 805µS The dominant pole is p1 ≈ (RIgm6RIICc)-1 where RI = 0.694MΩ, RII = 122.5kΩ and Cc = 3pF. ∴ p1(95µA) = 4,160 rads/sec, p1(121µA) = 3,678 rads/sec, and p1(69µA) = 4,870 rads/sec. Thus, the phase margin is less during the fall time than the rise time.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-69

Problem 6.7-01 Develop a macromodel for the op amp of Fig. 6.1-2 which models the low frequency gain Av(0), the unity-gain bandwidth GB, the output resistance Rout, and the output-voltage swing limits VOH and VOL. Your macromodel should be compatible with SPICE and should contain only resistors, capacitors, controlled sources, independent sources, and diodes. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-70

Problem 6.7-02 Develop a macromodel for the op amp of Fig. 6.1-2 that models the low-frequency gain Av(0), the unity-gain bandwidth GB, the output resistance Rout, and the slew rate SR. Your macromodel should be compatible with SPICE and should contain only resistors, capacitors, controlled sources, independent sources, and diodes. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-71

Problem 6.7-03 Develop a macromodel for the op amp shown in Fig. P6.7-3 that has the following properties: iO s  1 Avd(0)z1 - 1 3 vO 2 a.) Avd(s) = s   s  Figure P6.7-3  p1 + 1  p2 + 1 where Avd(0) = 104,z1 = 106 rads/sec., p1 = 102 rads/sec, and p2 = 107 rads/sec. b.) Rid = 1MΩ. c.) Ro = 100Ω. d.) CMRR(0) = 80dB. Show a schematic diagram of your macromodel and identify the elements that define the model parameters Avd(0), z1, p1, p2, Rid, R o, and CMRR(0). Your macromodel should have a minimum number of nodes. Solution The following macromodel is used to solve this problem.
1 5

0.5Rid
2

kAvd(0) (V1-V2) R2
4

V4 R1

R2

C2

0.5Rid Avd(0) (V -V ) R1 1 2
Fig. S6.7-03

R1

C1

V5 Ro

V1 2Ro

V2 2Ro

Verifying the macromodel by solving for V3 gives, R2 V 4 kA vd (0)  V3 = V5 + 0.5(V1+V2) =  sR C +1  R R 2 (V 1 -V 2 )  + Vicm  2 2  2 Avd(0) Vid Avd(0) =  sR C +1  sR C +1 - k V i d + Vicm= ( sR C +1)(sR C +1) (1-ksR1C1-k)Vid +  2 2  1 1  1 1 2 2 V icm Choose R1 = 10kΩ → C1=1µF, R2 = 1Ω → C1=0.1µF, Ro = 100Ω, and Rid = 1MΩ and solve for k. (note that the polarity of k was defined in the above macromodel to make k positive). 1 1 1 z = R C  k - 1 → 106 = 102(k -1) → k ≈10-4   1 1 With these choices, the transconductance values of all controlled sources are unity except for the ones connected to the output node, node 3. 1-ksR1C1-k = 0 →

+

3

Ro

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 6-72

Problem 6.7-04 Develop a macromodel suitable for SPICE of a differential, current amplifier of Fig. P6.7-4 having the following specifications: iOUT = Ai(s)[i1 - i2] where GB Ai(s) = = ω s+ω a s+100 R in1 = R in2 = 10Ω Rout = 100kΩ and Max|diOUT/dt| = 10A/µs. Your macromodel may use only passive components, dependent and independent sources, and diodes (i.e., no switches). Give a schematic for your macromodel and relate each component to the parameters of the macromodel. (The parameters are in bold.) Minimize the number of nodes where possible. Solution A realization is shown below along with the pertinent relationships. i1 1 4

106

Rin1 i1

Rout iOUT Current Amplifier

Rin2 i2 Figure P6.7-4

VI1=0V
6

D1 C1
7

8

D1 ISR D2 V6,7 Ro

iOUT
3

Rin1=10Ω i2
2 5

104 I 104 I VI1 VI2 R1 R1 VI2=0V

D2
9

R1

Ro= 100kΩ

Rin2=10Ω
Fig. S6.7-04

dv6,7 iC1 = dt C1 → ISR = 107 C1 1 Therefore, R C = 100 1 1 →

Choose C1 = 0.1µF ⇒

IS R = 1A

1 107 R1 = 100·C = 2 = 100kΩ → R 1 = 100kΩ 1 10 Note that the voltage rate limit becomes a current rate limit because iOUT = v6,7

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-1

CHAPTER 7 – HOMEWORK SOLUTIONS
Problem 7.1-01 Assume that VDD = -V SS and I17 and I20 in Fig. 7.1-2 are 100µA. Design W18/L18 and W19/L19 to get VSG18 = VGS19 = 1.5V. Design W21/L21 and W22/L22 so that the quiescent current in M21 and M22 is also 100µA. Solution Assuming V DD = −VSS = 2.5 V, and Vo = 0 V Due to bulk effects,
VT = VT 0 + γ

( 2φ + VSB −

2φ

)

Thus, VT 19 = 0.89 V, and VT 18 = 0.95 V Now,
V SG18 = VT 18 + 2 I18 ’ K P ( L)18 W

or,

W  L

  = 13.5 18
’ K N (W L )19

And, V SG19 = VT 19 + or,
W    = 4 .9  L 19

2I 19

Since Vo = 0 V, VT 21 = 1.08 V, and VT 22 = 1.23 V
V SG 21 = VT 21 + W    = 10.3  L  21 2I 22 ’ K P (W L )22 2I 21 ’ K N ( L)21 W

or,

And, V SG 22 = VT 22 +
W  L   = 55  22

or,

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-2

Problem 7.1-02 Calculate the value of VA and VB in Fig. 7.1-2 and therefore the value of VC. Solution The first trip point V A is defined as the input for which M 5 trips (or turns on). If it is assumed that the small-signal gain of the inverters (M1 − M 3 and M 2 − M 4 ) is large, then it can be assumed that M 5 will trip when M1 − M 3 are in saturation. Thus, β3 V A = VGS1 = VT 1 + ( SG3 − VT 3 ) V → V A = 0.9 V β1 Similarly, it can be assumed that M 6 will trip when M 2 − M 4 are in saturation. Thus, β4 V B = VGS 2 = VT 2 + ( SG 4 − VT 4 ) V β2 or, V A = 1.0 V So, VC = VB − VA = 0.1V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-3

Problem 7.1-03 Assume that K'N = 47 µA/V2, K'P = 17 µA/V2, V TN = 0.7 V, VTP = −0.9 V, γN = 0.85 V1/2, γP = 0.25 V1/2, 2|φF| = 0.62 V, λN = 0.05 V-1, and λP = 0.04 V-1. Use SPICE to simulate Fig. 7.1-2 and obtain the simulated equivalent of Fig. 7.1-3. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-4

Problem 7.1-04 Use SPICE to plot the total harmonic distortion (THD) of the output stage of Fig. 7.1-5 as a function of the RMS output voltage at 1 kHz for an input-stage bias current of 20 µA. Use the SPICE model parameters given in the previous problem. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-5

Problem 7.1-05 An MOS output stage is shown in Fig. P7.1-5. Draw a small-signal model and calculate the ac voltage gain at low frequency. Assume that bulk effects can be neglected. Solution Referring to the figure v gs 2 = v out , and v gs1 = v in Applying nodal analysis

VDD M2 M6 vout

(g ds 2 + g ds1 )v gs4 + g m1vin + g m 2v out
And,
g m 4v gs 4 + (g m3 + g ds4 )v out = 0

=0

(1) (2)

vin

M5 M1 VSS
Figure P7.1-5

From Equations (1) and (2) v out − g m1 g m4 = vin (g m2 g m4 − (g m 3 + g ds4 )(g ds1 + g ds 2 )) + vgs1=vin - gm1vgs1 + vgs4 - gm4vgs4

rds1

rds2 gm2vgs2

rds4

1/gm3

+ vout = vgs4 -

Fig. S7.1-05A

Problem 7.1-06 Find the value of the small-signal output resistance of Fig. 7.1-9 if the W values of M1 and M2 are increased from 10µm to 10µm. Use the model parameters of Table 3.1-2. What is the -3dB frequency of this buffer if CL = 10pF? Solution The loop-gain of the negative feedback loop is given by g (g + g m8 ) LG = − m 2 m 6 2g m 4 (g ds6 + g ds7 )
LG = − 164 or, The output resistance can be expressed as Rout =

(g ds6 + g ds7 )− 1
1 − LG

or,

Rout = 67.3 Ω

The –3 dB frequency point is 1 f − 3dB = 2π Rout C L or, f-3dB = 236 MHz

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-6

Problem 7.1-07 A CMOS circuit used as an output buffer for an OTA is shown. Find the value of the small signal output resistance, R out, and from this value estimate the -3dB bandwidth if a 50pF capacitor is attached to the output. What is the maximum and minimum output voltage if a 1kΩ resistor is attached to the output? What is the quiescent power dissipation of this circuit? Use the following model parameters: KN’=110µA/V2, KP’ = 50µA/V2, V TN = -VTP = 0.7V, λN = 0.04V-1 and λP = 0.05V-1. Solution Use feedback concepts to calculate the output resistance, Rout. Ro Rout = 1-LG where Ro is the output resistance with the feedback open and LG is the loop gain. 1 1 106 = = 0.09·500 = 22.22kΩ ds6+gds7 (λN+λP)I6 The loop gain is, vout’ 1 gm2gm6 g m 1 g m 9  LG = v = - 2 g  m4 + gm7  Ro out Ro = g gm1 = gm2 = 2·110·50·10 = 331.67µS, gm3 = gm4 = 2·50·50·10 = 223.6µS,

gm6 = 2·50·100·500 = 2236µS and gm7 = 2·110·500·100 = 3316.7µS vout’ 1 -331.67·2236 -331.67·3316.7 LG = v = - 2 + 223.6 331.67   = -73.68V/V out Ro 22.22kΩ Rout = 1-LG = 1+73.68 = 294.5Ω 1 1 f-3dB = = = 10.81MHz 2π·R out·50pF 2π·294.5·50pF To get the maximum swing, we must check two limits. First, the saturation voltages of M6 and M7. 2·1000 2·1000 Vds6(sat) = 50·100 = 0.6325V and Vds7(sat) = 110·100 = 0.4264V ∴ Second, the maximum current available to the 1kΩ resistor is ±1mA which means that the output swing can only be ±1V. Therefore, maximum/minimum output = ±1V. Pdiss = 6V(650µA) = 3.9mW

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-7

Problem 7.1-08 What type of BJT is available with a bulk CMOS p-well technology? A bulk CMOS n-well technology? Solution In a bulk CMOS p-well technology, n-p-n BJTs (both substrate and lateral) are available. In a bulk CMOS n-well technology, p-n-p BJTs (both substrate and lateral) are available. Problem 7.1-09 Assume that Q10 of Fig. 7.1-11 is connected directly to the drains of M6 and M7 and that M8 and M9 are not present. Give an expression for the small-signal output resistance and compare this with Eq. (9). If the current in Q10-M11 is 500µA, the current in M6 and M7 is 100µA, and ßF = 100, use the parameters of Table 3.1-2 assuming 1µm channel lengths and calculate this resistance at room temperature. Solution
Vdd

M7

Cc

Q10

Vout M6 RL CL

M11

Vss

The output resistance is 1 1 Rout ≅ + g m10 ( + β F )(g ds6 + g ds7 ) 1 From Equation (7.1-9) 1 1 Rout ≅ + g m10 ( + β F )g m 9 1 Here, g m10 = 19.23 µS and g ds6 + g ds7 = 9 µS

Thus, R out = 1152 Ω

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-8

Problem 7.1-10 Find the dominant roots of the MOS follower and the BJT follower for the buffered, classA op amp of Ex. 7.1-2. Use the capacitances of Table 3.2-1. Compare these root locations with the fact that GB = 5MHz? Assume the capacitances of the BJT are Cπ = 10pf and Cµ = 1pF. Solution The model of just the output buffer of Ex. 7.1-2 is shown.
VDD
100µA 146/1 10µA M8 vi 10/1 M9 90µA 1467/1 VSS M11 CL Q10 vo g (V -V ) m9 i 1 RL R1 C1 1000µA V1 Cπ rπ gm10(V1-Vo) R2 C2 Vo

R1 = rds8||rds9

R2 = rds11||ro10||RL C2 = C L
Fig. S7.1-10

100pF 500Ω

C1 = Cgd8+Cbd8+Cgs9+Cbs9+Cµ10

The nodal equations can be written as, gm9Vi = (gm9 + G1 + gπ10 + sCπ10 + sC1)V1 – (gπ10 + sCπ10)Vo 0 = –( gm10 + gπ10 + sCπ10)V1 + (gm10 + G2 + gπ10 + sCπ10 + sC2)Vo Solving for Vo/Vi gives, Vo Vi = g m9 (g m10 + gπ 10 + sC π 10 ) (g π 10 + sC π 10 )(g m 9 + G 1 + G 2 + sC 1 + sC 2 ) + (g m 10 + G 2 + sC 2 )(g m 9 + G 1 + sC 1 ) V o g m9(g m10+ gπ 10+ sC π 10) Vi = a + sa + s 2 a where a0 = g m9g π10 + g π10G 1 + g π 1 0 G 2 + g m9g m1 0 + g m10G 1 + g m9G 2 + G 1G 2 1 a1 = gm9C π10+G 1C π10+G 2C π 1 0 +gπ10C 1+gπ 1 0 C 2+gm10C 1+G 2C 1+gm9C 2 +G 1C 2 a2 = Cπ10C1 + Cπ 1 0 C2 + C1C2 The numerical value of the small signal parameters are: 1mA gm10 = 25.9mV = 38.6mS, G2 = 2mS, gπ10 = 386µS, gm9 = 300µS, G1 = gds8 + gds9 = 0.05·100µA + 0.05·90µA = 9.5µS Cgs9 = Cov +0.667CoxW9L9 = (220x10-12)(10x10-6) +0.667(24.7x10-4)(10x10-12) = 18.7fF
0 1 2

2·50·10·90 =

C2 = 100pF, Cπ10 = 10pF, C1 = Cgs9 + Cbs9 + Cbd8 + Cgd8 + Cµ10

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-9

Problem 7.1-10 – Continued Cbs9 = 560x10-6(30x10-12)+350x10-12(26x10-6) = 25.9fF (Assumed area=3µmx10µm = 30µm and perimeter is 3µm+10µm+3µm+10µm = 26µm) Cbd8 = 560x10-6(438x10-12)+350x10-12(298x10-6) = 349fF Cgd8 = Cov = (220x10-12)(146x10-6) = 32.1fF ∴ C1 = 18.7fF + 25.9fF + 349fF + 32.1fF + 1000fF = 1.43pF (We have ignored any reverse bias influence on pn junction capacitors.) The dominant terms of a0 , a1, and a2 based on these values are shown in boldface above. Vo g m9 (g m10 + gπ 10 + sC π 10 ) ∴V ≈ i gm9gm10+ gπ10G2+s(G2Cπ10+gπ10C2+gm10C1+gm9C2)+s2C2Cπ10 gm9gm10 Vo =g g Vi m9 m10 + gπ 10 G 2 sC π 1 0   1+ g m10   G2Cπ10+gπ10C2+gm10C1+gm9C2 C2Cπ10 1 + s   2  g m9g m10+ gπ10G 2   + s g m9g m10+ gπ10G 2 Assuming negative real axis roots widely spaced gives, -(gm9gm10+ gπ10G 2) 1 1.235x10-5 p1 = - a = G C +g C +g C +g C = = -84.3 x106 rads/sec. 2 π10 π10 2 m10 1 m9 2 1.465 x10-13 = -13.4MHz a -(G2Cπ10+gπ10C2+gm10C1+gm9C2) 1.465 x10-13 p2 = - b = =C2Cπ10 100x10-12·10x10-12 = -146.5 x106 rads/sec. → -23.32MHz gm10 38.6x10-3 9 z1 = - C =-12 = -3.86 x10 rads/sec. → -614MHz π10 10 x10 We see that neither p1 or p2 is greater than 10GB if GB = 5MHz so they will deteriorate the phase margin of the amplifier of Ex. 7.1-2.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-10

Problem 7.1-11 Given the op amp in Fig. P7.111, find the quiescent currents flowing in the op amp, the smallsignal voltage gain, ignoring any loading produced by the output stage and the small-signal output resistance. Assume K' N = 25 µA/V2 and K' P = 10 µA/V2 and λ = 0.04 V-1 for both types of MOSFETs.

VDD
10 20µA 2 60µA M1 vin M8 + 10 2 14 2 2µA Q1 Q2 vout 200µA 4 M9 2 20 M7 2

M3
8 2

M4

M6
40µA

60µA M2 8 2

2 2

120µA 12 2 All W/L values in microns VSS Figure P7.1-11 - Solution

M5

Assume the the BJT has a current gain of βF = 100.

Solution The quiescent currents flowing in the op amp are shown on the above schematic. The small-signal model parameters for the MOSFETs are: gm1 = gm2 = 2·25·4·60 = 109.5µS rds2 = rds4 = and gm6 = 2·10·7·40 = 74.8µS

25x106 25x106 = 0.4167MΩ, rds6 = rds7 = 40 = 0.625MΩ 60 For the two BJT’s,gm1 = 2x10-6 = 7.7µS, 26x10-3

25x106 and rds9 = 200 = 0.125MΩ

101 200x10-6 rπ1 = 7.7µS = 1.308MΩ, gm2 = = 7.7mS 26x10-3

101 and rπ2 = 7.7mS = 13.08kΩ

The small-signal voltage gain is Av = gm1RI gm6RII Abuff where RI = 0.4167MΩ||0.4167MΩ 0.2083ΜΩ and RII = 0.625MΩ||0.615MΩ = 0.3125MΩ. 10120.125MΩ = = 0.998 Abuff = rπ1+(1+βF)[rπ2+(1+βF)rds9] 1.3MΩ+101[13.08kΩ+101·0.125MΩ] ∴ Av = 109.5µS·0.2083MΩ·74.8µS·0.3125MΩ·0.998 = 532.2V/V (1+βF)2rds9

 (rπ1+RII)/(1+βF)+rπ2  (0.3125MΩ+1.208MΩ)/101+13.08kΩ Rout = rds9||  = 0.125MΩ||  101 1+βF   = 0.125MΩ||288 = 287.4Ω

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-11

Problem 7.2-1 Find the GB of a two-stage op amp using Miller compensation using a nulling resistor that has 60° phase margin where the second pole is -10x106 rads/sec and two higher poles both at -100x106 rads/sec. Assume that the RHP zero is used to cancel the second pole and that the load capacitance stays constant. If the input transconductance is 500µA/V, what is the value of Cc? Solution The resulting higher-order poles are two at -100x106 radians/sec. The resulting phase margin expression is, GB GB PM = 180° - tan-1(Av(0)) - 2tan-1 7 = 90° - 2tan-1 7 = 60° 10  10  GB ∴ 30° = 2tan-1 7 → 10   GB = tan(15°) = 0.2679  107 → Cc = 500x10-6 = 18.66pF 26.79x107

gm1 GB = 2.679x107 = C c

Problem 7.2-02 For an op amp where the second pole is smaller than any larger poles by a factor of 10, we can set the second pole at 2.2GB to get 60° phase margin. Use the pole locations determined in Example 7.2-2 and find the constant multiplying GB if p6 for 60° phase margin. Solution Referring to Example (7.2-2) p6 = − 0.966 Grad/sec p A = − 1.346 Grad/sec p B = − 1.346 Grad/sec p8 = − 3.149 Grad/sec p9 = − 3.149 Grad/sec p10 = −3.5 Grad/sec

For a phase margin of 60 , the contributions due to all the poles on the phase margin can be given as  GB  − 1 GB  − 1 GB  − 1 GB  o tan− 1   p  + 2 tan  p  + 2 tan  p  + tan  p  = 30         6  A  8  10  Solving for the value of gain-bandwidth, we get GB ≅ 0.23 p 6 = 35 MHz.

o

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-12

Problem 7.2-03 What will be the phase margin of Ex. 7.2-2 if CL = 10pF? Solution The value of the output resistance from Example (7.2-2) is
Rout = 19.4 MΩ

Thus, the dominant pole is p1 = −1 = 8.2 KHz. Rout C L

The gain-bandwidth is given by
GB = Av (0) p1 = (7464)(8.2 K ) = 61 MHz.

Considering the location of the various poles from Example (7.2-2), the phase margin becomes
   GB   GB   GB   GB      + 2 tan −1   + 2 tan −1   + tan −1  PM = 180 o − 90 o − tan −1  p  p  p   p      6  A  8   10      

or, or,

PM = 180 o − 90o − 21.7o + 32 o + 14 o + 6.2o PM = 16 o

[ {

} ]

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-13

Problem 7.2-04 Use the technique of Ex. 7.2-2 to extend the GB of the cascode op amp of Ex. 6.5-2 as much as possible that will maintain 60° phase margin. What is the minimum value of CL for the maximum GB? Solution Assuming all channel lengths to be 1 µm , the total capacitance at the source of M7 is C7 = C gs 7 + Cbd 7 + C gd 6 + Cbd 6 C7 = 75 + 51 + 9 + 51 = 186 fF → g m7 = 707 µS Thus, the pole at the source of M7 is g pS 7 = − m7 = −605 MHz. C7 The total capacitance at the source of M12 is C12 = C gs12 + C bd12 + C gd11 + Cbd11 → C12 = 34 + 29 + 4 + 29 = 96 fF g m12 = 707 µS Thus, the pole at the source of M12 is g pS 12 = − m12 = −1170 MHz. C12 The total capacitance at the drain of M4 is C 4 = C gs 4 + C gs6 + Cbd 4 + C gd 2 + Cbd 2 → C 4 = 43 + 75 + 21 + 3 + 19 = 161 fF g m 4 = 283 µS Thus, the pole at the drain of M4 is g p D4 = − m4 = −280 MHz. C4 The total capacitance at the drain of M8 is C8 = C gd 8 + C bd8 + C gs10 + C gs12
R2 + 1 g m10 = 3 .4 K Ω

→

C8 = 9 + 51 + 34 + 34 = 128 fF

Thus, the pole at the drain of M8 is 1 = − 366 MHz. p D8 = −  1   C8  R2 +  g m10    For a phase margin of 60 , we have    GB   GB   GB   GB      + tan − 1  + tan − 1  + tan − 1 PM = 180 o − 90 o − tan −1  p  p  p   p      S7   S12   D4   D 8       Solving the above equation GB ≅ 65 MHz and Av = 6925 V/V Thus, p1 = 9.39 KHz, and CL ≥ 1.54 pF o CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-14

Problem 7.2-05 For the voltage amplifier using a current mirror shown in Fig. 7.2-11, design the currents in M1, M2, M5 and M6 and the W/L ratios to give an output resistance which is at least 1MΩ and an input resistance which is less than 1kΩ. (This would allow a voltage gain of 10 to be achieved using R1 = 10kΩ and R2 = 1MΩ. Solution
1 (g ds6 + g ds2 ) I 2 = I 6 = 10 µA Let, 1 Rout = = 1.1 MΩ or, (g ds6 + g ds2 ) R1 = 10 KΩ , R2 = 1000 KΩ , and Av = − 10 Given, R 2 A0 And, Av = − R1 ( + A0 ) 1 Rout = I2 1 = Thus, A0 = I1 9 I 2 = I 6 = 10 µA and I1 = I 5 = 90 µA or, 1 Rin = = 1 KΩ g m1

or, and,

W  W    = 50.5 , and   = 5.6  L 1  L 2 W  L  W   = 50.5 , and   = 5.6 5  L 6

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-15

Problem 7.2-06 In Ex. 7.2-3, calculate the value of the input pole of the current amplifier and compare with the magnitude of the output pole. Solution Assuming all channel lengths to be 1 µm . In this problem, A0 = 0.1 , S2 = 20 , S1 = 200 , I 2 = 100 µA , and I1 = 1000 µA g m1 = 6.63 mS 1 = 451 Ω Thus, Rin = R3 + g m1 The input capacitance is
Cin = C gd 5 + Cbd 5 + C gs3 + C gs 4 + C gd 3 + C gd 4

or,

Cin = 44 + 253 + 375 + 38 + 44 + 4.4 = 758 fF 1 = − 466 MHz which is compared to 50 MHz for the output pole. RinC in

The input pole is given by pin = −

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-16

Problem 7.2-07 Add a second input to the voltage amplifier of Fig. 7.2-12 using another R 1 resistor connected from this input to the input of the current amplifier. Using the configuration of Fig. P7.2-7, calculate the input resistance, output resistance, and -3dB frequency of this circuit. Assume the values for Fig. 7.2-12 as developed in Ex. 7.2-3 but let the twoR1 resistors each be 1000Ω. Solution
R1

Vin

R1

Vout

-Av

Vin

R1
-Av

Vout

R1/(1-Av)

R1(Av-1)/Av

Referring to the figure, the Miller resistance, R1 , between the input and the output can be broken as shown. Here, R1 = 1 KΩ , R2 = 110 KΩ , and R3 = 0.3 KΩ The input resistance can be written as
 R   1   Rin = R1 +  1  ||   R3 +  g m1    1 − Av      1   1K    → Rin = 1K +  1 + 10  ||   300 + 6.63m      

or,

Rin = 1076 Ω

The output resistance can be written as R (A − 1) 1 || 1 v Rout = → g m12 Av

Rout = 636 Ω

The –3 dB frequency, the pole created at the drains of M4 and M6, is given by f −3dB = 1 2πR2Co

where, R2 = 110 KΩ , and Co = 105 pF. So, f-3dB = 13.87 MHz.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-17

Problem 7.2-08 Replace R1 in Fig. 7.2-12 with a differential amplifier using a current mirror load. Design the differential transconductance, gm, so that it is equal to 1/R1. Solution
Vdd M7 M15 M16 M5 i1 R2

Vin

M13

M14

R3

M3 VBIAS

M17

M1

VSS

Referring to the figure, the output current of the input transconductor, i1 , is given by i1 = g m13v in vin Comparing with the expression i1 = R , we get 1 1 R1 = g m13

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-18

Problem 7.3-01 Compare the differential output op amps of Fig. 7.3-3, 7.3-5, 7.3-6, 7.3-7, 7.3-8 and 7.310 from the viewpoint of (a.) noise, (b.) PSRR, (c.) ICMR [Vic(max) and Vic(min)], (d.) OCMR [Vo)max) and Vo(min)], (e.) SR assuming all input differential currents are identical, and (f.) power dissipation if all current of the input differential amplifiers are identical and power supplies are equal. Solution Assume that all differential amplifiers have the same bias current of ISS.
VDD
VDD + VBP -

M4
M6 M4

M15

M14 M13

M5 M7
R1

M7

Cc vo1 vi1

Rz

M3

Rz

Cc vi2 M6 vo2 vo2
M1 M5 M2

vi1

M1

M2

vi2

vo1

M9

+ VBN -

M8

R2 M16 M8 M10 M17

M3 VBias
VSS

M12 M9 M11

VSS Figure 7.3-3 Two-stage, Miller, differential-in, differential-out op amp.

Figure 7.3-5 Differential output, folded-cascode op amp.
VDD + VBP -

M3
M13

M4 M6
M14

VDD
M12

M4 M6

M20 M19

M7 vo1

M5

M13 M15 M11

Cc

Rz vi1 Rz Cc
M1 M5 M2 vi2 vo2

M14 M10

M7
R1

M9

M10

VSS Figure 7.3-6 Two-stage, Miller, differential-in, differential-out op amp with a push-pull output stage.

+ VBN -

M12

M8

vo2
M16

Rz

Cc

vi1

M1

M2

vi2
M18

Rz

Cc

vo1
M17

M8

M3

VBias

M9

VSS Figure 7.3-7 Two-stage, differential output, folded-cascode op amp.

VDD
M7 M21 M9 M5 M3 M4 M6 M20
M13

VDD

M8

M9 M26

M7 M8
M25 vi1 vi2 M24 R1

M10

M10 R2

M1 M2

vo1
M15

vi1
M22

M1 M2

vi2

M19 R1

vo2
M16

vo1

M21 M19
R2 M27 M28 + VBias -

M22
M3 M4

M14 vo2

M15

M20 M16

M17 M23

VBias
M12 M11

M18
M11

M17

M18

M23

M13

M14

VSS Figure 7.3-8 Unfolded cascode op amp with differential-outputs.

M12 M6 VSS Figure 7.3-10 Class AB, differential output op amp using a cross-coupled differential input stage.
M5

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Problem 7.3-01 – Continued Fig. 7.3-3 Noise PSRR Good Poor Fig. 7.3-5 Poor Good VDD+VT V SS + 2VON+VT VDD-2VON V SS+2V ON ISS/C L Fig. 7.3-6 Good Poor VDD-VON V SS + 2VON+VT VDD-VON V SS +V O N ISS/Cc Fig. 7.3-7 Poor Good VDD+VT V SS + 2VON+VT VDD-VON V SS +V O N ISS/C L Fig. 7.3-8 Okay Good VDD-VON V SS + 2VON+VT VDD-2VON V SS+2V ON ISS/C L

Page 7-19

Fig. 7.3-10 Poor Good VDD-VON VSS+ 3VON+2VT VDD-2VON V SS+2V ON ISS/C L

ICMR Vic(max) VDD-VON VSS+ Vic(min) 2VON+VT OCMR Vo(max) Vo(min) SR VDD-VON V SS +V O N ISS/Cc

Problem 7.3-02 Prove that the load seen by the differential outputs of the op amps in Fig. 7.3-4 are identical. What would be the single-ended equivalent loads if CL was replaced with a resistor, RL? Solution
2CL vin CL + vin + RL vod vin + + 2CL 2CL vin vod 2CL RL/2 vod vin + vod RL/2 vod

Referring to the figure, when a capacitive load of C L is driven differentially, the load capacitor can be broken into two capacitors in series, each with a magnitude of 2C L . The mid point of the connection of these two capacitors is ac ground as the output signal swings differentially. In case of a resistive load RL , it can be broken into two resistive loads in series, each resistor being RL / 2 .

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-20

Problem 7.3-03 Two differential output op amps are shown in Fig. P7.3-3. (a.) Show how to compensate these op amps. (b.) If all dc currents through all transistors is 50µA and all W/L values are 10µm/1µm, use the parameters of Table 3.1-2 and find the differential-in, differentialout small-signal voltage gain.
+ VBias -

VDD
M8

M3

M4
Rz M6 M7
+ -

+ VBias Rz vout+ vout Cc vin+

VDD

Rz Cc vinvout-

vin -

+

M1 Cc M2

Rz M9

Cc + VBias -

M5 VSS (a.)

M10

+ VBias -

VSS (b.)

Fig. S7.3-3

Solution a) The compensation of both the op amps are shown in the figure. b) The small-signal voltage gain of Figure P7.3-3(a) is given by g m1 g m6 Av = (g ds1 + g ds 3 )(g ds6 + g ds9 ) or, or,
Av =

(332 µ )(224µ ) (4.5µ )(4.5µ )

A v = 3673 V/V

The small-signal voltage gain of Figure P7.3-3(b) is given by g m1 (g m6 + g m9 ) Av = (g ds1 + g ds 3 )(g ds6 + g ds9 ) or, or,
Av =

(332 µ )(556 µ ) (4.5 µ )(4.5µ )

A v = 9117 V/V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-21

Problem 7.3-04 Comparatively evaluate the performance of the two differential output op amps of Fig. P7.3-3 with the differential output op amps of Fig. 7.3-3, 7.3-5, 7.3-6, 7.3-7, 7.3-8 and 7.3-10. Include the differential-in, differential-out voltage gain, the noise, and the PSRR. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-22

Problem 7.3-05 Fig. P7.3-5 shows a differential-in, differential-out op amp. Develop an expression for the small-signal, differential-in, differential-out voltage gain and the small-signal output resistance.

VDD
M8

M6

Cc
+ vin + VBias M9

M3

M4

Cc
+

M1

M2

vout -

M5 VSS Figure P7.3-5

M7

Solution The small-signal differential voltage gain can be found by simply connecting the sources of M1 and M2 to ac ground and solving for the single-ended output assuming the full input is applied single-ended. gm1 gm8  1 1 Rout =  g +g + g +g  ∴ Avdd = g  g +g   ds8 ds9 m3 ds8 ds9 ds6 ds7

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-23

Problem 7.3-06 Use the common-mode output stabilization circuit of Fig. 7.3-13 to stabilize the differential output op amp of Fig. 7.3-3 to ground assuming that the power supplies are split around ground (VDD = |VSS|). Design a correction circuit that will function properly. Solution VDD Vo1 M1 M2 Vo2 M3 M4 VBP M11 M12

VBN M9 Vocm M5 VSS M6 M7

M10

M8

M7
+ - vo1

VDD + VBP -

M6 M4

Cc vi1 Rz

M3

Rz

Cc vi2 vo2

M1 M5 VBN VSS

M2

M9

M8

Referring to the figure of the common-mode stabilizing circuit, the common-mode voltage at the output nodes vo1 and vo2 will be held close to the common-mode voltage Vocm due to negative feedback. If these two output nodes swing differential, the drain of M5 will not change and thus, the common-mode feedback circuit is non-functional. When the commonmode voltage at these two output nodes tend to change in the same direction, the negative feedback loop of M1-M5-M6-M7-M9 and M2-M5-M6-M8-M10 will reduce the variations at vo1 and vo2, respectively.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-24

Problem 7.3-07 (a.) If all transistors in Fig. 7.3-12 have a dc current of 50µA and a W/L of 10µm/1µm, find the gain of the common mode feedback loop. (b.) If the output of this amplifier is cascoded, then repeat part (a.). Solution

M10

VDD + VBP
-

M11

M7

M6 M4

Cc vo1 vi1

Rz

M3

Rz

Cc vi2 vo2

M1 M5

M2

M9

+ VBN -

M8

VSS Figure 7.3-12 Two-stage, Miller, differential-in, differential-out op amp with common-mode stabilization.
The loop gain of the common-mode feedback loop is, gm11 gm10 = -gm10rds9 or - g = -gm11rds8 CMFB Loop gain ≈ - g ds9 ds8 2KP’WID With ID = 50µA and W/L = 10µm/1µm, gm10 = = 2·50·10·50) L = 223.6µS, 1 25 1 20 rdsN = = 50µA = 0.5MΩ and rdsP = = 50µA = 0.4MΩ λ N ID λPID ∴ CMFB Loop gain ≈ −g m10 r ds9 = -223.6(0.5) = -111.8V/V gm10 gm(cascode)rds(cascode) CMFB Loop gain with cascoding ≈ − g ds9 If the output is cascoded, the gain becomes,

= -gm10{[rds9 gm(cascode)rds(cascode)]||[gm7rds7 (rds10||rds10]} gmP = 2K N’WID = 2·110·10·50) = 331.67µS L

= -(223.6)[(0.5·331.67·0.5)||(223.6)(0.4)(0.2)] = 223.6(14.7) = -3,290 V/V ∴ CMFB Loop gain with cascoding ≈ -3.290V/V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-25

Problem 7.3-08 Show how to use the common feedback circuit of Fig. 5.2-15 to stabilize the common mode output voltage of Fig. 7.3-5. What would be the approximate gain of the common mode feedback loop (in terms of gm and rds) and how would you compensate the common mode feedback loop? Solution
VDD MC5 MC3 R1 MC6 MC4 R1 RCM1 RCM2 MC1 VICM MC7 MC2 M8 M10 VSS vo2 VB2 M3 M9 VB1 M11 M6 vi1 M1 M2 M4

M5

M7 vi2 vo1

Referring to the figure, the loop gain of the common-mode feedback loop can be given by LG = gm ,C 2 gm 4 g g g g  2 gm ,C 5  ds4 ds6 + ds8 ds10  gm10   gm 4

The compensation of the common-mode feedback loop can be done using the output load capacitor (single-ended load capacitors to ac ground). The dominant pole of this loop would be caused at the output nodes by the large output resistance given by Rout = 1  gds4 gds6 gds8 gds10  +   gm10   gm 4

Considering the differential output load capacitance to be C L , the dominant pole of the common-mode feedback loop can be expressed as p1 = 1 Rout (2CL )

The other poles, at the source and drain of MC3, and the source of M6, can be assumed to be large as these nodes are low impedance nodes.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-26

Problem 7.4-01 Calculate the gain, GB, SR and Pdiss for the folded cascode op amp of Fig. 6.5-7b if VDD = -VSS = 1.5V, the current in the differential amplifier pair is 50nA each and the current in the sources, M4 and M5, is 150nA. Assume the transistors are all 10µm/1µm, the load capacitor is 2pF and that n1 is 2.5 for NMOS and 1.5 for PMOS.
VDD VDD
M14 M4 I4 M5 I5 A B RB RA

M6

M7 VB

I1
+ vin -

I2

I1 vout + vin -

I2
M13 M6 I6 M7 I7 R1 R2 vout

M1 M2

M1 M2

R9
M9 M11

CL

Cascode Current Mirror

I3
+ VBias -

M8

M3

M12 M10

VSS VSS (b) (a) Figure 6.5-7 (a) Simplified version of an N-channel input, folded cascode op amp. (b) Practical version (a).

Solution ID 50nA 1 = 500MΩ gm1 = gm2 = n (kT/q) = 2.5·25.9mV = 0.772µS and rds1 = rds2 = 1 ID λ N ID 150nA 1 gm4 = gm5 = n (kT/q) = 1.5·25.9mV = 3.861µS and rds4 = rds5 = = 133MΩ 1 ID λ N ID 100nA 1 gm6 = gm7 = n (kT/q) = 1.5·25.9mV = 2.574µS and rds6 = rds5 = = 200MΩ 1 ID λ N ID 100nA gm8 = gm9 = gm10 = gm11 = n (kT/q) = 2.5·25.9mV = 1.544µS 1 1 and rds8 = rds9 = rds10 = rds11 = = 250MΩ ID λ N Gain: A v(0) = gm1R out, Rout ≈ rds11gm9rds9||[gm7rds7(rds5||rds2)] = 96.5GΩ||34.23GΩ = 25.269GΩ ∴ Av(0) = 0.772µS·25.269GΩ = 19,508 V/V GB which is the case if CL makes RB approximately the same as RA at ω = GB.) SR = 100nA/2pF = 0.05V/µs Pdiss = 3V·(3·150nA) =1.35µW

GB = gm1/CL = 386krads/sec = 61.43kHz (this assumes all other poles are greater than

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-27

Problem 7.4-02 Calculate the gain, GB, SR and Pdiss for the op amp of Fig. 7.4-3 where I5 = 100nA, all transistor widths (M1-M11) are 10µm and lengths 1µm, and VDD = -VSS = 1.5V. If the saturation voltage is 0.1V, design the W/L values of M12-M15 that achieves maximum and minimum output swing assuming the transistors M12 and M15 have 50nA. Assume that IDO = 2nA, np = 1.5, nn = 2.5 and Vt = 25mV. Solution (Solution incomplete) The small-signal gain can be expressed as Av = or,  gm1  gm 8     g gm 7 + gm 6 Rout 2 gm 3  m 9 

Av = gm1Rout  gm10   gm11  ||  gds10 gds6   gds11gds7     

The output resistance is given by Rout = or, Thus, Av = gm1Rout = 73, 846 V/V Assuming Cc = 1 pF The dominant pole is p1 = − 1 = 1.66 Hz. Rout Cc GB = Av (0) p1 = 122.5 KHz. The power dissipation is 0.9 µW .   I10 VSG10 = Vdsat 6 + Vdsat10 + n pVt ln  = 0.236 V  (W L)10 I D 0    I11 VGS11 = Vdsat 7 + Vdsat11 + n nVt ln  = 0.26 V  (W L)11 I D 0 

Rout = 96 GΩ

Thus, the gain-bandwidth becomes

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-28

Problem 7.4-03 Derive Eq. (17). If A = 2, at what value of vin/nVt will iout = 5I5 or 5Ib if b=1 ? Solution Start with the following relationships: i1 + i2 = I5 + A(i2 - i1) and i2 v in = exp nV  i1  t v in v in i1 + i1 exp nV  = I5 + Ai1 exp nV  - Ai1  t  t or v in i1[(1+A) +(1-A) exp nV  ] = I5   t Eq. (15) Eq. (16)

Defining iout = b(i2 - i1) solve for i2 and I1.

→

i1 =

I5 v in (1+A) +(1-A) exp nV   t

Similarly for i2, v in I5 exp  nV    t i1 =

 v in (1+A) +(1-A) exp  nV  t

∴ (17)

  v in   I 5  expnV  -1 t iout = b(i2 - I1) = iout = (i2 - I1) =  v in (1+A) +(1-A) exp  nV  t

Eq.

v in Setting iout = 5I5 and solving for nV gives, t v in  v in  5[3- exp nV  ] = expnV  -1   t t

→

v in 16 = 6 exp nV    t →

v in exp nV  =  t

2.667 ∴ v in nV t = ln(2.667) = 0.9808

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-29

Problem 7.4-04 Design the current boosting mirror of Fig. 7.4-6a to achieve 100µA output when M2 is saturated. Assume that i1 = 10µA and W1/L1 = 10. Find W2/L2 and the value of VDS2 where i2 = 10µA. Solution Given, S1 =10, I1 = 10 µA, and I1 = 100 µA when M2 is saturated. Thus, S2 =100 And, Vdsat1 = Vdsat2 = 0.135 V Now, in the active region of operation for M2
2  Vds  ' S V I D = K N 2  dsat 2Vds − 2   

or, or,

 V2  10 µ = (100 µ )100 0.135Vds − ds  2   Vds ≅ 7 mV

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-30

Problem 7.4-05 In the op amp of Fig. 7.4-7, the current boosting idea illustrated in Fig. 7.4-6 suffers from the problem that as the gate of M15 or M16 is increased to achieve current boosting, the gate-source drop of these transistors increases and prevents the v DS of the boosting transistor (M11 and M12) from reaching saturation. Show how to solve this problem and confirm your solution with simulation. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-31

Problem 7.5-01 For the transistor amplifier in Fig. P7.5-1, what is the equivalent inputnoise voltage due to thermal noise? Assume the transistor has a dc drain current of 20 µA, W/L = 150 µm/10 µm, K' N = 25 µA/V2, and RD is 100 Kilohms. Solution g m = 122 µS and,
Av ≅ − g m R D = −12.2 8KT 4 KTRD 2 e eq = + 2 3gm Av

VDD
RD 20µA

The equivalent input thermal noise is

Figure P7.5-1

or, or,

2 e eq = 102.1 × 10 −18 V 2 / Hz

Veq(rms) ≈ 10nV/ Hz

Problem 7.5-02 Repeat Ex. 7.5-1 with W1 = W2 = 500µm and L1 = L2 = 0.5µm to decrease the noise by a factor of 10. Solution S1 = 500 / 0.5 , S3 = 100 / 20 Flicker noise B N = 7.36 × 10 − 22 (Vm)2 e 21 = n

and

BP = 2.02 × 10 −22 (Vm)2

8.08 × 10 −13 BP = V 2 / Hz fW1 L1 f  L  2   1    L3     

So,

  K’ B 2 e 2 = 2en1 1 +  N N eq   K ’ BP   P

→

e2 = eq

1.624 × 10 −12 V 2 / Hz f

Thermal noise 8KT e 21 = = 0.49 × 10 − 17 V 2 / Hz n 3 g m1
K ’ W3 L1  N  ’  K PW1 L3    The corner frequency, f c = 150.4 KHz
2 e 2 = 2en1 1 + eq



→

2 e eq = 1.08 × 10 −17 V 2 / Hz

Considering a 100 KHz. Bandwidth 2 Veq (rms) = 1.624 × 10 −12 ln 10 5 + 1.08 × 10 − 17 105

( )

( )

→ Veq (rms) = 4.45 µV

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-32

Problem 7.5-03 Interchange all n-channel and p-channel transistors in Fig. 7.5-1 and using the W/L values designed in Example 7.5-1, find the input equivalent 1/f noise, the input equivalent thermal noise, the noise corner frequency and the rms noise in a 1Hz to 100kHz bandwidth. Solution The flicker noise is B N = 7.36 × 10 − 22 (Vm)2 BP = 2.02 × 10 −22 (Vm)2 and e 21 = n BN fW1 L1 = 7.36 × 10 − 12 2 V / Hz f  L  2   1    L3     

So,

  ’ 2 2   K P BP e eq = 2en1 1 + ’   K N BN  

→

e2 = eq

14.72 × 10 −12 V 2 / Hz f

The thermal noise is e 21 = n 8KT = 1.05 × 10 −17 V 2 / Hz 3 g m1
’ K PW3 L1   ’ K NW1 L3  

 2 e 2 = 2en1 1 + eq  

→

2 eeq = 2.42x10-17 V2/Hz

The corner frequency is fc = 608 KHz. Considering a 100 KHz. Bandwidth
2 Veq (rms) = 14.72x10-12 ln(105) + 2.42x10-17 ln(105) → Veq(rms) = 13.1 nV/ Hz

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-33

Problem 7.5-04 Find the input equivalent rms noise voltage of the op amp designed in Ex. 6.3-1 of a bandwidth of 1Hz to 100kHz. Solution The input referred noise is given by 2 2    1  2  2 2 g 2  2en1 +  m3  2en3 +   e eq = g   A  e n6     m1   v1    Flicker noise 2   K ’ B  L  2  1  2  2 2  2en1 +  P P  1  2e 23 +   e eq = n  A  en6    K ’ B  L3    v1   N N     e 21 = n e 23 = n e 26 = n 2.45 × 10 −10 V 2 / Hz f 1.35 × 10 −11 V 2 / Hz f

2.15 × 10 −12 V 2 / Hz f Av1 = − 68.5 4.9 × 10 − 10 V 2 / Hz f

2 Thus, e eq =

Thermal noise 2 e n1 = 1.11 × 10 −16 V 2 / Hz e 23 = 7.395 × 10 − 17 V 2 / Hz n
2 e n6 = 1.17 × 10 −17 V 2 / Hz 2 e eq = 5.58 × 10 −16 V 2 / Hz

or,

The corner frequency is f c = 884 KHz Considering a 100 KHz bandwidth
2 Veq (rms) = 4.9 × 10 −10 ln 10 5 + 5.58 × 10− 16 105

( )

( )

→Veq(rms) = 75.5 µV/ Hz

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-34

Problem 7.5-05 Find the equivalent rms noise voltage of the op amp designed in Example 6.5-2 over a bandwidth of 1Hz to 100kHz. Use the values for KF of Example 7.5-1. Solution VDD The circuit for this amplifier is shown. M6 M4 The W/L ratios in M15 microns are: M8 M3 S1 = S2 = 12/1 M14 M7 S3 = S4 = 16/1 S5 = 7/1 S5 = 8.75/1 S6 = S7 = S8 = S14 = S15 = 40/1 S9 = S10 = S11 = S12 = 18.2/1 Find the short
2

M1
2 eeq *

M2

R1 M9 M10

R2

2 ito

M12 M5
+ VBias -

M11

M13
VSS
Fig. S7.5-05

circuit noise current at the output, i to , due to each noise-contributing transistor in the circuit (we will not includeM7, M9, M12 and M14 because they are cascodes and their effective gm is small. The result is, g 2  2 2 2 m8 2 2 2 2 2 2 i to = 2gm1en1 2  + 2gm8en3 + 2gm8en8 + + 2gm11en10 gm3  where we have assumed that gm1=gm2, gm3=gm4, gm6=gm8, and gm10=gm11 and en1=en2, en3=en4, en6=en8, and en10=en11. Dividing i to by the transconductance gain gives
2 eeq = 2

g 2  g 2  g 2 g 2  2 + 2 m3  e 2 + 2 m3  e 2 + 2 m3 m11 e 2 n10 2 2 2 = 2en1 2 n3 2 n8 2 2 gm1gm8/gm3 gm1 gm1  gm1gm8 
2 ito

The values of the various parameters are: gm1 = 251µS, gm3 = 282.5µS, gm8 = 707µS, and gm11 = 707µS. ∴
2 eeq

 en3 2 = 2en11 + 1.266  2 +   en1
2

e n8

2

2 + 2 en1 en1

e n10
2

 

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-35

Problem 7.5-05 – Continued 1/f Noise: Using the results of Ex. 7.5-1 we get BN = 7.36x10-22(V·m)2 and Bp = 2.02x10-22(V·m)2 BN 7.36x10-22 6.133x10-11 2 2 en1 = fW L = = V /Hz f 1 1 f·12x10-12 B P ·f·W 1 L 1 B P·W 1L1 2.02·12 = B ·f·W L = B ·W L = 7.36·16 = 0.2058 2 N 3 3 N 3 3 en1
2 en8 2 en3

B P ·f·W 1 L 1 B P·W 1L1 2.02·12 = B ·f·W L = B ·W L = 7.36·40 = 0.0823 2 N 8 3 N 3 3 en1
2 en1

2 en10

B N ·f·W 1 L 1 = B ·f·W L
N

B P·W 1L1 12 = B ·W L = 18.2 = 0.6593 10 10 N 3 3

∴

2 eeq = 2 2 eeq =

6.133x10-11 6.133x10-11 [1+1.266(0.2058+0.0823+0.6593)] = 2 2.1995 f f

2.1995x10-10 2 V /Hz f Thermal noise:
-23 2 = 8kT = 8·1.38x10 ·300 = 4.398x10-17 V2/Hz en1 3g m1 3·251x10-6 2 en3

gm1 251 =g = 282.4 = 0.8888 and 2 m3 en1

2 en8

2 en10 gm1 251 = 2 =g = 707 = 0.0.355 2 m8 en1 en1

The corner frequency is fc = 2.698x10-10/2.66x10-16 = 1.01x106 Hz. Therefore in a 1Hz to 100kHz band, the noise is 1/f. Solving for the rms value gives,
100,000 2 V eq (rms) =

⌠2.698x10-10 df = 2.698x10-10[ln(100,000) – ln(1)] ⌡ f
1

= 3.1062x10-9 V2(rms) ∴ Veq(rms) = 55.73µV( rms)

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-36

Problem 7.6-01 If the W and L of all transistor in Fig. 7.6-3 are 100µm and 1µm, respectively, find the lowest supply voltage that gives a zero value of ICMR if the dc current in M5 is 100µA. Solution W I 5 = 100 µA, and   = 100 L VIC (max) = VDD + VT 1 (min) − Vdsat 3 and, VIC (min) = Vdsat1 + VT 1 (max) + Vdsat 5 ICMR = VIC (max) − VIC (min) For ICMR=0 VDD = Vdsat1 + Vdsat 5 + Vdsat 3 + VT 1 (max) − VT 1 (min) or, VDD = 2 I1 2I5 2I3 + + + VT 1 (max) − VT 1 (min) ' ' ' K N S1 K N S5 K P S3 → VDD = 0.671 V The input common-mode range is

Problem 7.6-02 Repeat Problem 1 if M1 and M2 are natural MOSFETs with a V T = 0.1V and the other MOSFET parameters are given in Table 3.1-2. Solution
VT 1 = 0.1 V, I 5 = 100 µA, and  W  = 100 L

Let, the variation in the threshold voltage be ± 20% ∆ VT 1 = ± 0.02 V or, VIC (max) = VDD + VT 1 (min) − Vdsat 3 and, VIC (min) = Vdsat1 + VT 1 (max) + Vdsat 5 ICMR = VIC (max) − VIC (min) For ICMR=0 VDD = Vdsat1 + Vdsat 5 + Vdsat 3 + VT 1 (max) − VT 1 (min) or, VDD = 2 I1 2I5 2I3 + + + VT 1 (max) − VT 1 (min) → ' ' ' K N S1 K N S5 K P S3 VDD = 0.411 V The input common-mode range is

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-37

Problem 7.6-03 Repeat Problem 1 if M1 and M2 are depletion MOSFETs with a V T = -1V and the other MOSFET parameters are given in Table 3.1-2. Solution W VT 1 = −1 V, I 5 = 100 µA, and   = 100 L Let, the variation in the threshold voltage be ± 20% or,
∆ VT 1 = m0.2 V

VIC (max) = VDD + VT 1 (min) − Vdsat 3 and, VIC (min) = Vdsat1 + VT 1 (max) + Vdsat 5 ICMR = VIC (max) − VIC (min) For ICMR=0 VDD = Vdsat1 + Vdsat 5 + Vdsat 3 + VT 1 (max) − VT 1 (min) or, VDD = 2 I1 2I5 2I3 + + + VT 1 (max) − VT 1 (min) → VDD = 0.711 V ' ' ' K N S1 K N S5 K P S3 The input common-mode range is

Problem 7.6-04 Find the values of Vonn and Vonp of Fig. 7.6-4 if the W and L values of all transistors are 10µm and 1µm, respectively and the bias currents in MN5 and MP5 are 100µA each. Solution Vonn = V dsat, N 5 + VTN 1 (max) + Vdsat, N1 or,
Vonn = 0.426 + 0.85 + 0.302

→

Vonn = 1.578 V

Let us assume that V DD = 2.5 V
Vonp = V DD − Vdsat, P1 − Vdsat, P 5 − VT , P1 (max) → V onp = 0.57 V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-38

Problem 7.6-05 Two n-channel source-coupled pairs, one using regular transistors and the other with depletion transistors having a V T = -1Vare connected with their gates common and the sources taken to individual current sinks. The transistors are modeled by Table 3.1-2 except the threshold is -1V for the depeletion transistors. Design the combined sourcecoupled pairs to achieve rail-to-rail for a 0V to 2V power supply. Try to keep the equivalent input transconductance constant over the ICMR. Show how to recombine the drain currents from each source-coupled pair in order to drive a second-stage single-ended. Solution
VDD VBP M3 M4 MD3 MD4

+

M1 VT=0.7 M5

M2

-

-

MD1

MD2 VT=-1.0 MD5

+

VBN

VSS VDD VBP M3 M4

+

M1 VBN

M2 VT=0.7 M5

-

MD1 MD2 VT=-1.0 MD5

+

VSS

Considering the differential amplifier consisting of M1-M5, the range of the input common mode can be given by VIC (max) = VDD + VT 1 − Vdsat 3 and VIC (min) = VSS + VT 1 + Vdsat1 + Vdsat 5 (1) Now, considering the differential amplifier consisting of MD1-MD5, the range of the input common mode can be given by VIC (max) = VDD + VT ,D1 − Vdsat ,D 3 and VIC (min) = VSS + VT ,D1 + Vdsat ,D1 + Vdsat ,D 5 (2) Let us assume that the saturation voltage (Vdsat ) of each of the transistors is equal to 0.1 V, and let VDD = 2 V Then, from Equation (1), for the transistors M1-M5 VIC (max) = 2.6 V and VIC (min) = 0.9 V From Equation (2), for the transistors MD1-MD5 Vic(max) = 0.9 V and Vic(min) = -0.8 V Since, the common-mode input range of both stages overlap, they can be joined as shown in the figure and will provide a constant gm across the rail-to-rail input range of 0-2 V.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-39

Problem 7.6-06 Show how to create current mirrors by appropriately modifying the circuits in Sec. 4.4 that will have excellent matching and a VMIN(in) = VON and VMIN(out) = VON. Solution
VDD VDD

I1-IB iin

IB

IB

I2 iout iin

I1

IB1

IB2

IB1

I2 iout

M3

M4 M6

M7

M3 or M7 M4 M6 M5

M1 M5

M2

M1 IB2 M2
Fig. 7.6-13A

Problem 7.6-07 Show how to modify Fig. 7.6-16 to compensate for the temperature range to the left of where the two characteristics cross. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-40

Problem 7.6-08 For the op amp of Ex. 7.6-1, find the output and higher order poles and increase the GB as much as possible and still maintain 60° phase margin. Assume that L1+L2+L3 = 2µm in order to calculate the bulk-source/drain depletion capacitors (assume zero voltage bias). What is the new value of GB and the value of Cc? Solution Referring to the Figure 7.6-17 and Example 7.6-1, the dominant pole is caused at the drain of M9. The second pole ( p2 ) is caused at the output by the load capacitor. The magnitude of this pole is given by p2 = −gm14 = −20 MHz. CL

To increase the gain bandwidth, let us design the nulling resistor ( RZ ) in such a way that the LHP zero created by this resistor will cancel the load pole. The value of Cc = 2 pF. Thus, RZ = 1 gm14 + 1 = 4.77 KΩ 2πCc p2

We can see that the pole at the source of M6 is p6 = −1.2 GHz. The third pole ( p3 ) at the output is caused by the nulling resistor and is given by p3 ≅ −1 = −101 MHz. 2πRZ Cgs14

In order to maintain a phase margin of 60 o, the gain bandwidth can be calculated as  GB   = 30 o tan −1  p3  or, → GB = 58 MHz. → W  W  = = 241.6  L 1  L  2

gm1 = (GB)Cc = 729 µS

Considering the minimum input common-mode range Vdsat 5 = 0.22 V → W  = 7.5  L 5

Considering the maximum input common-mode range W  W  = = 19.2  L 3  L 4 Rest of the transistor sizes are the same as calculated in Example 7.6-1. But, the smallsignal voltage gain is 18,000 V/V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 7-41

Problem 7.6-09 Replace M8 and M9 of Fig. 7.6-17 with a high swing cascode current mirror of Fig. 4.3-7 and repeat Ex. 7.6-1. Solution Referring to the figure and Example 7.6-1 VGS 8 = 1.5 V → Vdsat 8 = 0.8 V → W  W  = = 0.57 ≅ 1  L 8  L 9

Let us assume VBIAS = 2 V. Then, Vdsat17 = 0.5 V → W  W  + = 1.45  L 17  L 18

The output resistance seen at the drain of M7 is Rout1 =  gds18 gds9 gds7 ( gds4 + gds2 )  +   gm 7  gm18  1 = 50 MΩ

Thus, the overall small-signal gain becomes 2.8 × 10 5 V/V. The gain bandwidth is 10 MHz. The load pole is at 20 MHz. Referring to the figure, the extra pole that would affect the phase margin the most is created at the source of M18. The resistance seen at the source of M18 can be given by   gm 7  rds18 +   gds7 ( gds4 + gds2 )    RS18 =   || [rds9 ] → RS18 = [844 K ] || [1.25 M ] = 504 KΩ (1 + gm18rds18 )       The pole at the source of M18 is p18 = RS18 Cgs18 + Cbd 18 + Cgd 9 + Cbd 9

(

−1

)

→

p18 =

−1 = −35 MHz (504K )(9 × 10 −15 )

It can be seen that this pole p18 would degrade the phase margin by 16 o. Thus to maintain a 60 o phase margin with a gain bandwidth of 10 MHz, let us use nulling resistor compensation to cancel this pole. The value of Rz can be given by RZ = 1 gm14 + 1 = 3.07 KΩ 2πCc p18

The pole due to the introduction of Rz is p4 = −1 = −157 MHz RZ Cgs14

This pole is large enough to affect the phase margin. Though the pole at the source of M18 has been eliminated using the nulling resistor compensation technique, the pole at the source of M7 could be dominant enough to degrade the phase margin.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 8-1

CHAPTER 8 – HOMEWORK SOLUTIONS
Problem 8.1-01 Give the equivalent figures for Figs. 8.1-2, 8.1-4, 8.1-6 and 8.1-9 for an inverting comparator. Solution The figures for the inverting comparator are shown below.
Vo VOH VOH Vo VOH Vo

VIL vp-vn VOL

VIH vp-vn VOL

VIL VOS

VIH vp-vn VOL

Vo VOH

t tp VOL

Vin VIH

t VIL

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 8-2

Problem 8.1-02 Use the macromodel techniques of Sec. 6.6 to model a comparator having a dc gain of 10,000 V/V, and offset voltage of 10mV, VOH = 1V, VOL = 0V, a dominant pole at -1000 radians/sec. and a slew rate of 1V/µs. Verify your macromodel by using it to simulate Ex. 8.1-1. Solution TBD

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 8-3

Problem 8.1-03 Draw the first-order time response of an inverting comparator with a 20 µs propagation delay. The input is described by the following equation vin = 0 for t < 5 µs vin = 5(t − 5 µs) for 5 µs < t < 7 µs vin = 10 for t > 7 µs Solution The input and the output response of the inverting comparator are shown in the figure. VOH Vo

0.5(VOH+VOL) VOL tp=20 t Vin VIH=10

0.5(VIH+VIL) VIL=0 5 6 7 t

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 8-4

Problem 8.1-04 Repeat Ex. 8.1-1 if the pole of the comparator is -105 radians/sec rather than -103 radians/sec. Solution The pole location is

ω c = −100 Krad/s k= Vin Vin (min) = 10m = 100 0.1m

The propagation delay is given by tp = 1  2k  ln  ω c  2k − 1 

or,

t p = 50.1 ns

(1)

Considering the maximum slew rate, the propagation delay can be expressed as V − V OL t ’ = OH p 2 SR or, t ’ = 500 ns p

(2)

From Equations (1) and (2), the propagation delay is tp = 500 ns Problem 8.1-05 What value of Vin in Ex. 8.1-1 will give a slewing response? Solution The comparator will start to slew when the propagation delay of the comparator is dominated by its maximum slew rate (and not by the comparator’s small-signal propagation delay). VOH − VOL 1  2k  > ln   ω c  2k − 1  2SR or,
 2k  ω c (VOH − VOL ) ln  < 2SR  2k − 1 

Solving for k, we get k > 1000.5 or, Vin > 100.05 mV

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 8-5

Problem 8.2-01 Repeat Ex. 8.2-1 for the two-stage comparator of Fig. 8.2-5. Solution The output swing levels are
  2I7 1 − 1 −  VOH = V DD − ( DD − VG 6 (min) − VTP ) V 2   β 6 ( DD − VG 6 (min) − VTP )  V 

or, or,

  2(234)  VOH = 2.5 − (2.5 − 0 − 0.7)1 − 1 − 2  (50)(38)(2.5 − 0 − 0.7 )   

VOH = 2.43 V V OL = -V SS = -2.5 V

The minimum input resolution is V − VOL Vin (min) = OH Av and, or,
Av = I1 I 6 (λ P g m1 g m 2
2 + λN )

= 3300

Vin(min) = 1.5 mV

The pole locations are g ds2 + gds4 = 1.074 MHz p1 = CI p2 = g ds6 + gds7 = 0.67 MHz CII

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 8-6

Problem 8.2-02 If the poles of a two-stage comparator are both equal to -107 radians/sec., find the maximum slope and the time it occurs if the magnitude of the input step is 10Vin(min) and VOH -VOL = 1V. What must be the SR of this comparator to avoid slewing? Solution The response to a step response to the above comparator can be written as, vout where vout’ = A (0)V and tn = tp1 vout’ = 1 – e-tn –tne-tn v in To find the maximum slope, differentiate twice and set to zero. dvout’ -t -t -t -t dtn = e n + tne n - e n = tne n d2vout’ dtn2 ∴ = -tne-tn + e-tn = 0 ⇒ (1-tn)e-tn = 0 ⇒ tn(max) = tp1 = 1

tn 1 and t(max) = |p | = 7 = 0.1µs 1 10 dvout’(max) dvout’(max) = e-1 = 0.3679 V/sec or = 3.679V/µs dtn dtn

tn(max) = 1sec

dvout’(max) dvout’(max) = 10(VOH-VOL)· = 36.79V/µs dt dtn ∴ Therefore, the slew rate of the comparator should be greater than 36.79V/µs to avoid slewing.

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 8-7

Problem 8.2-03 Repeat Ex. 8.2-3 if p1 = -5x106 radians/sec. and p2 = 10x106 radians/sec. Solution Given p1 = −5 Mrad/s, and p2 = −10 Mrad/s So, m= p2 =2 p1

When Vin = 10m k= Vin Vin (min) = 15.576

and,

tp =

1 p1 mk

= 35.8 ns

When Vin = 100m (assuming no slewing) k= Vin Vin (min) = 155.76

and,

tp =

1 p1 mk

= 11.3 ns

When Vin = 1 (assuming no slewing) k= Vin Vin (min) = 1557.6

and,

tp =

1 p1 mk

= 3.58 ns

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions

Page 8-8

Problem 8.2-04 For Fig. 8.2-5, find all of the possible initial states listed in Table 8.2-1 of the first stage output voltage and the comparator output voltage. Solution Condition: VG1 > VG 2 , I1 < I SS , I 2 > 0
2.1315 < Vo1 < 2.5 , and Vo 2 = − 2.5

Condition: VG1 >> VG 2 , I1 = I SS , I 2 = 0
Vo1 = 2.5 , and Vo 2 = − 2.5

Condition: VG1 < V G 2 , I1 > 0, I 2 < I SS
V S 2 < Vo1 < V S 2 + 0.3 , and Vo 2 = 2.5 − 0.123 (2.5 − Vo1 − 0.7 )

Condition: VG1 V G1 , I1 > 0, I 2 < I SS
V S 2 < Vo1 < V S 2 + 0.3 , and Vo 2 = 2.5 − 0.123 (2.5 − Vo1 − 0.7 )

Condition: VG 2 >> VG1 , I1 = 0, I 2 = I SS
Vo1 = − 2.5 , and Vo 2 = 2.47

Condition: VG 2 < VG1 , I1 < I SS , I 2 > 0
2.1315 < Vo1 < 2.5 , and Vo 2 = − 2.5

Condition: VG 2